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The e5500 MMU cannot be disabled. However you can program the L2 TLB1 to cover all available physical address space statically. The L1 TLBs are transparent for your software you should not care of it. The L1 TLBs is loaded form the L2 TLBs by the core hardware. The simplest way is using L2 TLB1 which has 64 entries, each entry support variable size page up to 4 GBytes. When the core comes out of reset, its MMU has one 4 KB page defined at 0x0_FFFF_Fnnn. When the core executes code from that page it can program L2 TLB1 to cover all required physical memories at once. For example U-boot programs the MMU in this way. Of course software can set effective address of page equal to the physical address and we get “real” mode.
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