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********************************************************************************  Detailed Description:  Example shows how to use FlexCAN 0 Pretended networking mode to allow FlexCAN  module to wake up MCU from STOP mode.  Wake up by Timeout and wake up by Match events are enabled.  Also pin interrupt can be used to exit STOP mode.  So MCU enters STOP mode by pressing SW3 button.  MCU exits STOP mode when one of following happens:  - no CAN message comes in 8sec (CAN PN timeout event)  - message with standard ID 0x554 or 0x555 comes (CAN PN match event)  - SW2 button is pressed (PTC12 interrupt)  In run mode blue LED is dimming and the rate is different for each wakeup event  ------------------------------------------------------------------------------  Test HW: S32K144 EVB-Q100  MCU: FS32K144UAVLL 0N57U  Fsys: 160MHz  Debugger: Lauterbach, OpenSDA  Target: internal_FLASH ********************************************************************************
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I write a doc and a demo about LPUART hardware flow control, runs on s32k144 evb board with RTM 3.0.0, the flow control function work normally. If you have any question please contact me. 
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Using S32k144 ISELD SDK driver and adding Touch Sensor software, a demo is created to show different light combinations when electrodes of S32K144 EVB are touched. ADK ISELED board is attached to S32K144 EVB.
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An example implementation of SENT protocol receiver with S32K118 evaluation board. The input is expected in J106, TICK duration is 2,75us. CRC is calculated and check, the decoded output is printed into terminal via UART (ASCII)
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Often we need to implement a SENT receiver in order to read the information sent by some sensors. It is useful to have the possibility of transmitting different message patterns in order to test your implementation. With this project you can transmit via a computer terminal a group of messages (up to 64). The project runs on a S32K144 EVB board, the output signal goes through J206 pin.
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Example of usage of AIPS-lite, Protects the access to GPIO port. This example can be used with UART terminal, 115200 bps. The interface menu shows like this: AIPS example has started Please press 0 + enter to set red LED in GPIO port Please press 1 + enter to set red LED in GPIO port Please press 2: GPIO peripheral will only accept accesses from trusted master, M0 (Core) is set as untrusted when a write access, AIPS cannot longer be modified from core and a reset will occur in the next GPIO access Please press 3: GPIO access is write protected, any write access to GPIO will produce a hard fault
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You can find here a reference code for a march c software test in order to test RAM memories
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******************************************************************************** * Detailed Description: * RAM self-test is performed after reset in startup_S32K144.s file. * The RAM self-test should be executed right after reset, so it does not destroy * data loaded to RAM by init functions. The code is inserted after * initialization of core registers. RAM initialization is commented out because * the same operation is done by the self-test. * The test flow is: * 1. Write pattern 0x55AA55AA to first word in RAM * 2. Read the data back * 3. Compare the data and increment error counter if not equal * 4. Write inverse pattern 0xAA55AA55 to first word in RAM * 5. Read the data back * 6. Compare the data and increment error counter if not equal * 7. Clear the first word in RAM to leave whole RAM erased to ‘0’ at the end of test * This procedure is repeated for whole RAM. * If the error counter is different from zero at the end, the program stays in * endless loop until watchdog reset. * * ------------------------------------------------------------------------------ * Test HW:         S32K144EVB-Q100 * MCU:             FS32K144UAVLL 0N57U * Fsys:            Default * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * ********************************************************************************
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******************************************************************************************************** Detailed Description: On WDOG timeout, the WDOG module requests reset in the Reset Control Module (RCM). The reset request to RCM can be delayed by 128 bus clock cycles if the WDOG interrupt is enabled (WDOG_CS[INT] = 1). If enabled, the WDOG interrupt vector is fetched or it becomes pending in NVIC. After the delay, the reset is requested in RCM. Independently of the WDOG interrupt, the RCM can again delay the reset by up to 514 LPO additional clock cycles if the corresponding RCM_WDOG interrupt is enabled (RCM_SRIE[GIE, WDOG] = 1). If so, instead of forcing reset immediately, the module requests the RCM interrupt in NVIC and forces the reset after the additional delay (RCM_SRIE[DELAY]). Either way, the reset is forced, it can’t be stopped only delayed. This example enables the WDOG interrupt in the WDOG_CS register but leaves this interrupt disabled in NVIC. That means that this interrupt becomes pending in NVIC on the WDOG timeout, it sets the WDOG_CS_FLG, but the vector doesn’t get fetched. The RCM interrupt is enabled and it gets asserted in NVIC after the WDOG interrupt delay (2.67us (48MHz BUS CLK)). The WDOG flag (WDOG_CS_FLG) is read in the RCM ISR instead. The execution stays in an infinite loop for 514 LPO (128kHz) cycles (~ 4ms) until the reset is forced. ------------------------------------------------------------------------------------------------------------------------- Test HW: S32K144EVB-Q100 MCU: S32K144 0N57U Debugger: S32DSR1 OpenSDA Target: internal_FLASH ********************************************************************************************************
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Dear all, I'd like to share some useful tips about S32DS for ARM v2018.R1 IDE and S32K1xx development  in Chinese as below: 《S32DS使用Tips--SDK使用常见问题(FAQ)答疑》; 《S32K SDK使用详解之S32 SDK软件编程思想详解》; 《S32K SDK使用详解之S32 SDK软件架构详解》; 《 S32K1xx系列MCU使用Tips--功能介绍及软件开发和硬件设计FAQ》; 《 S32K1xx系列MCU使用Tips--Flash加密后不断复位无法连接调试器的问题解决》; 《S32DS使用Tips--S32DS for Power V1.2 链接文件和启动过程详解》; 《S32K1xx系列MCU使用Tips之SDK软件架构和使用详解》; 《S32DS使用Tips--SDK使用常见问题(FAQ)答疑》; 《S32DS IDE使用Tips--应用工程调试常见问题(FAQ)答疑》; 《 S32DS 使用Tips之S32DS for Power不同版本之间的GNU工具链差异与外设寄存器位域访问问题总结》; 《 S32DS使用Tips之S32DS for Power v1.1应用工程升级到v1.2重新编译运行程序跑飞问题解决》; 《S32DS 使用tips--S32DS for ARM v1.3工程到S32DS for ARM V2.0迁移升级方法和注意事项》; 《  S32DS 使用 tips--工程属性配置(编译选项和C编译器、汇编器及链接器设置)》; 《 S32DS使用Tips--如何编译生成和调用静态库》; 《S32DS使用Tips--如何通过创建新的编译目标(Build Target)在同一个S32DS工程中同时编译静态库和应用程序》; 《 S32DS使用Tips--如何配置和使能Attach功能定位软件程序bug和完成bootloader与应用程序工程的联合调试》; 《 CodeWarrior与S32DS IDE使用 Tips之如何在应用工程中保留定义但未使用的全局常量、变量(用于参数标定)》; 《 S32DS 使用 tips--使用Flash from file下载S19或elf文件》; 《S32DS for ARM v2018.R1安装IAR Eclipse插件调用IAR工具链开发S32K系列MCU应用程序详解》 For more contents, please follow below link: “汽车电子expert成长之路”微信公众号最新最全原创技术分享文章列表 ; Hope this can help you and have a nice day~! Best regard, Enwei Hu(胡恩伟)
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******************************************************************************** Detailed Description: This example shows SRAM ECC injection. By default, a double-bit ECC error is injected on read access of a location in SRAM_U region. This can be changed with the SRAM_U and DOUBLE_BIT macros. The errors can be detected by both the ERM and MCM modules and the corresponding interrupts can be called. Although only ERM is needed, for demonstration purposes, the MCM interrupt is enabled as well with a lower priority than the ERM interrupts. The ERM interrupts that are called first disable the injection mechanism so that subsequent errors can not be detected during a stack read access. The default S32 Design Studio start_up file copies the vector table to the SRAM_L region. To be able to inject ECC errors in this SRAM region and call the interrupts, the copying is disabled by __flash_vector_table__ symbol  declared in the start_up.h file and defined in the S32K144_64_flash linker file. -------------------------------------------------------------------------------------------- Test HW: S32K144EVB-Q100 MCU: S32K144 0N57U Debugger: S32DSR1 Target: internal_FLASH ********************************************************************************
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******************************************************************************** Detailed Description: This example shows the use of SRAM retention after SW reset. The SW reset is triggered by pressing the SW3 button on the S32K144 EVB The reset is delayed in RCM module: 514 LPO cycles. In the RCM interrupt, SRAMU_RETEN and SRAML_RETEN are cleared allowing to retain SRAM data during the reset. After software reset, SRAMU_RETEN and SRAML_RETEN are set to1 to allow accesses to SRAM.  During software initialization in the startup_S32K144.S, ECC RAM initialization is skipped.  After that, we can check the written data before reset are still placed in the SRAM.  ------------------------------------------------------------------------------ Test HW: S32K144EVB-Q100 MCU: S32K 0N57U Debugger: S32DSR1 ********************************************************************************
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************************************************************************************************ Detailed Description: WDOG tested in SystemInit() function (system_S32K116.c) after POR. For debugging purposes: - WDOG counter reference clock is pre-scaled to slow the test (CS_PRES = 1). - During CNT_LOW test, BLUE LED (PTE8) ON. - During CNT_HIGH test, RED LED (PTD16) ON. - Once both tests have passed, GREEN LED (PTD15) ON. If either of the test fails, WDOG will stay in its default configuration and rest the MCU. ---------------------------------------------------------------------------------------------------------------- Test HW: S32K116EVB-Q048 REV.B MCU: S32K116 0N96V Debugger: S32DSR1, OpenSDA Target: internal_FLASH ************************************************************************************************
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**************************************************************************************** Detailed Description: This is a rather simple example that shows LPI2C0 in Master mode. MPL3115A2 sensor is used as a slave device. I2C bus at PTA2 SDA, PTA3 SCL (2-pin open drain mode), external pull-up resistors on BRKTSTBC-P3115 board. BRKTSTBC-P3115 supplied from P3V3 (J3.7). Baud rate 400kHz, source SIRCDIV2 8MHz. The master reads periodically MPL3115A2 status register (every 200ms) and temperature / altitude data once they are ready. ------------------------------------------------------------------------------------------------------- Test HW: S32K144EVB-Q100, BRKTSTBC-P3115 MCU: S32K144 0N57U IDE: S32DSR1, OpenSDA Target: internal_FLASH ****************************************************************************************
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******************************************************************************************************************************************** Detailed Description: This example shows use of RTC in VLPS mode. The MCU is put into the VLPS mode (Sleep-On-Exit). RTC alarm interrupt brings it to VLPR every 3s and toggles BLUE LED (PTD0). Since it works in the Sleep-On-Exit mode, after the ISR, the MCU goes to VLPS again without calling the WFI instruction. When BTN0 (S32K144 EVB) is pressed, the power mode switch from VLPS to VLPR and other way round. Interrupt is triggered on rising edge (PTC12), filtered by digital filter (clocked from LPO). In VLPR, RTC seconds interrupt is enabled as well and toggles RED LED (PTD15) in the ISR. RTC_CLKOUT (1Hz) and CLKOUT (bus_clk) can be monitored at PTD13 and PTD14 respectively. CLKOUT is not available in VLPS. The MCU needs to be power-cycled and run stand-alone. -------------------------------------------------------------------------------------------------------------------------------------------------------------------- Test HW: S32K144EVB-Q100 MCU: S32K 0N57U Debugger: S32DS_ARM_2.2, OpenSDA Target: internal_FLASH ********************************************************************************************************************************************
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Hi,     I would like to share with you the follow solution for S32K14x which could be attached while couldn't be re-programmed and stopped at RAM initializing.     If you met the issue as title, please check the SIM_CHIPCTL's value in IDE with attach function. Maybe you can find that the value is 0x0, which is not as default value after reset which is 0x0030_0000.     If you check the meaning on SIM_CHIPCTL, you can find that SRAMU and SRAML are retained across resets.  To solute the issue, you should add 'WRITE_LONG=00300000/40048004/ ;' in front of it the algorithm (it's better after reset) of freescale_s32k144f512m15_pflash_dflash_eeprom.arp which is at  'C:\NXP\S32DS_ARM_v20\eclipse\plugins\com.pemicro.debug.gdbjtag.pne_3.3.3.201712132114\win32\gdi\P&E\supportFiles_ARM\NXP\S32K1xx' After that, you can download your project as normal. Cheers! Oliver
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****************************************************************************************************************** Detailed Description: The example code shows CMP in Round-robin mode. CMP is clocked (125kHz) and triggered (80ms) by LPTMR, operates in VLPS. Input channels are CMP0_IN1 (PTA1), CMP0_IN2 (PTC4), CMP0_IN3 (PTE8), CMP0_IN4 (PTC3). The initial state of CMP outputs is 0 (Input analog pins < DAC input (Vin1/2)) The input pins are pulled down internally for debugging purposes. CPM will wake up the MCU if an input has changed. BLUE LED flashes 1x if CMP_IN1 has changed, 2x CMP0_IN2, 3x CMP0_IN3, 4x CMP0_IN4. After that, the MCU goes back to VLPS. ------------------------------------------------------------------------------------------------------------------------------------- Test HW: S32144EVB-Q100X MCU: S32K144 (0N47T) Debugger: S32DS2.0, OpenSDA Target: internal_FLASH ******************************************************************************************************************
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******************************************************************************** Detailed Description: The S32K144 MCU is secure if SEC bits are set to non 0b10 value in Flash Secure Register (FSEC). And can be unsecure using either Mass Erase or Verify Backdoor Access Key command provided they are enabled, again indicated by bits KEYEN and MEEM in the FSEC register. The FSEC register is a read-only register and is loaded with the content of the flash security byte in the Flash Configuration Field located in program flash memory during the reset sequence. The configuration field holds the Backdoor comparison key as well and is configurable in startup_S32K144.S file. The attached example code shows use of Verify Backdoor Access Key flash command. The MCU is secured in the Flash configuration field and therefore once the application has been loaded the debugger does not have access to the MCU which must be run stand-alone. The state of the SEC bits is indicated by LEDs. The RED LED indicates the MCU is secure (SEC != 0b10) after reset. After a delay loop, the Verify Backdoor key command is executed which will unsecure the device and the LED will turn BLUE (SEC = 0b10). NOTE: The Verify Backdoor key command is executed from RAM to avoid simultaneous access to the PFlash block. -------------------------------------------------------------------------------------------- Test HW:      S32144EVB-Q100 MCU:           S32K144 0N47T Debugger:    S32DS1.3, OpenSDA Target:          internal_FLASH ******************************************************************************** 2.0     Sep-30-2017     Daniel ********************************************************************************
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******************************************************************************** Detailed Description: Configures the FlexCAN 0 to transmit and receive message into RXFIFO. LOOPBACK mode is enabled. Two IDs are set into RXFIFO ID table. DMA is configured to read the message from RXFIFO. Within DMA major interrupt the new message is send according to which Identifier Acceptance Filter was hit. ------------------------------------------------------------------------------  Test HW:         S32K144 EVB-Q100  MCU:             PS32K144HFVLL 0N77P  Fsys:            160MHz  Debugger:        Lauterbach  Target:          internal_FLASH ******************************************************************************** Revision History: 1.0     Sep-4-2017     Petr Stancik    Initial Version *******************************************************************************
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Greetings, if you want to use the open source EmbSysRegView plugin in your Eclipse environment: this article describes how to add the S32K CMSIS-SVD files to it: Adding CMSIS-SVD Files to EmbSysRegView 0.2.6.r192 and Eclipse Happy SVDing 🙂 Erich
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