Example S32K144 RAM Retention S32DS.R1

[#1]

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Detailed Description:

This example shows the use of SRAM retention after SW reset.
The SW reset is triggered by pressing the SW3 button on the S32K144 EVB

The reset is delayed in RCM module: 514 LPO cycles.

In the RCM interrupt, SRAMU_RETEN and SRAML_RETEN are cleared allowing to retain SRAM data during the reset.

After software reset, SRAMU_RETEN and SRAML_RETEN are set to1 to allow accesses to SRAM. 

During software initialization in the startup_S32K144.S, ECC RAM initialization is skipped. 

After that, we can check the written data before reset are still placed in the SRAM.
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Test HW: S32K144EVB-Q100
MCU: S32K 0N57U
Debugger: S32DSR1
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[Catosh]

Hello Diana, 

I have a question on the RAMRetention function from startup_S32k144.s - assuming no optimization in the compiler is provided (-O0) and on a smaller microcontroller (the CM0+). 

After initializing the registers, I can see a blx to RAMRetention function. 

Does the blx trigger a push operation in ram memory? What happens if there is a write access to the SRAM?

Shall I use the __n_a_k_e_d__ attribute to get rid of the push operations?

The local variable in RAMRetention is placed on the stack, does this trigger a new access to the SRAM hence an error?

I'm wondering if my questions have some rationale beyond or if  I am just overthinking. 

Generally speaking, how does the SRAM_U behave in this scenarios, where no other SRAM can be used for safety purposes?

Best regards, 

L. 

[dianabatrlova]

Hello Luca,

Firstly, I'm very sorry for a huge delay. I did not notify you that I have updated the code for the S32K144 device and now there is no RAMRetention function nor blx instruction.  Unfortunately, I have not tested it on the CM0+ yet.

Thank you for pointing this out and again sorry.

Best Regards,

Diana