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Linux 中的监管域和 Wi-Fi 发射功率级别管理(国家监管设置) 默认初始化情况 默认情况下,如果未定义国家/地区监管设置,我们会使用 WW(全球安全设置,即我们只在全球允许的频段上传输,发射功率符合所有国家/地区的法规要求)。   设置国家/地区 1/ 在 AP 模式下运行时: - 我们通常在 hostapd.conf 中设置国家/地区代码(例如:country_code=JP)来定义国家 / 地区。 - 如果在 hostpad.conf 中设置了 ieee80211d=1,则此国家定义将被通告给所有连接的 STA - 也可以使用 “iw reg set” 命令设置国家/地区。   2/ 在 STA 模式下操作时 - 可以使用 “iw reg set” 命令或在 wpa_supplicant.conf 中设置国家 / 地区代码(例如:country=jp)。 - 一旦连接到启用了 80211d 的 AP,STA 将切换到 AP 的国家 / 地区设置(可通过添加 country_ie_ignore=1 驱动参数禁用此行为)。   设置国家/地区后: - 我们只会在该国家/地区允许的信道上传输 - 发射功率不超过该国家/地区的最大限制 - 我对于国家/地区声明为 DFS 信道的信道,我们可能会使用 DFS 功能。   TX功率设置   1/ 默认情况下,使用 Linux 监管设置(/lib/firmware/regulatory.db,由 db.txt 生成) 这些设置基于国家/地区定义了允许的信道、DFS 标志和最大发射功率。 详见下文 “Regulatory db” 部分。   2/ Linux 监管设置可通过以下方式覆盖: a. cntry_txpwr=0 和 txpwrlimit_cfg=nxp/txpower.bin 驱动参数(由 txpower.conf(信道 / MCS-> 发射功率)生成,参见 AN13009) 所有国家/地区使用相同设置(静态)。 使用 db.txt 中的信道/标志,发射功率取 db.txt 与 txpower.bin/rgpower.bin 中的最小值。 b. cntry_txpwr=1(查找 nxp/txpower_XX.bin 文件(由 txpower.conf(信道 / MCS-> 发射功率)生成,参见 AN13009) 每个国家/地区 XX 需要一个 txpower_XX.bin 文件(动态加载,例如通过 iw reg set XX)。 使用 db.txt 中的通道/标志,以及 db.txt 和 txpower_XX.bin 之间的最小 TX 功率   cntry_txpwr txpwrlimit_cfg TX功率限制 方法 0 nxp/txpower.bin nxp/txpower.bin(静态) V1 1 - nxp/txpower_XX.bin(动态) V1 cfg     我们有默认的 TX 功率表,但客户可以根据他们的硬件调整这些 TX 功率设置。 请参考《AN13009 Linux 中的 Wi-Fi 发射功率管理》。       Regulatory db   来源https://wireless.wiki.kernel.org/en/developers/Regulatory/wireless-regdb   Wi-Fi 监管设置(允许的信道等)定义在 db.txt 中,然后转换为 regulatory.db(存储在 /lib/firmware 中)。 我们可以从这里获取官方的 db.txt 文件,并使用以下命令构建 regulatory.db:   git clone git://git.kernel.org/pub/scm/linux/kernel/git/wens/wireless-regdb.git make   Linux 内核会检查 regulatory.db 的完整性。 通过以下内核配置禁用 REGDB 签名检查: CONFIG_EXPERT=y CONFIG_CFG80211_CERTIFICATION_ONUS=y # CONFIG_CFG80211_REQUIRE_SIGNED_REGDB 未设置   重新构建内核并烧写: scp Image [email protected]:/run/media/mmcblk0p1/     iw reg 命令示例和其他注释   root@imx8mqevk:~# iw reg get global country 00: DFS-UNSET         (2402 - 2472 @ 40), (N/A, 20), (N/A)         (2457 - 2482 @ 20), (N/A, 20), (N/A), AUTO-BW, PASSIVE-SCAN         (2474 - 2494 @ 20), (N/A, 20), (N/A), NO-OFDM, PASSIVE-SCAN         (5170 - 5250 @ 80), (N/A, 20), (N/A), AUTO-BW, PASSIVE-SCAN         (5250 - 5330 @ 80), (N/A, 20), (0 ms), DFS, AUTO-BW, PASSIVE-SCAN         (5490 - 5730 @ 160), (N/A, 20), (0 ms), DFS, PASSIVE-SCAN         (5735 - 5835 @ 80), (N/A, 20), (N/A), PASSIVE-SCAN         (57240 - 63720 @ 2160), (N/A, 0), (N/A) root@imx8mqevk:~# iw reg get global country FR: DFS-ETSI         (2400 - 2483 @ 40), (N/A, 20), (N/A)         (5150 - 5250 @ 80), (N/A, 23), (N/A), NO-OUTDOOR, AUTO-BW         (5250 - 5350 @ 80), (N/A, 20), (0 ms), NO-OUTDOOR, DFS, AUTO-BW         (5470 - 5725 @ 160), (N/A, 26), (0 ms), DFS         (5725 - 5875 @ 80), (N/A, 13), (N/A)         (57000 - 66000 @ 2160), (N/A, 40), (N/A) 默认情况下(如果未设置国家/地区),我们使用全球域,这是限制最严格的。 你可以设置国家/地区(使用驱动模块参数、wpa_supplicant.conf 等),或者自动获取接入点提供的国家 / 地区信息 (80211d)。这将更新监管域,即允许的信道等。 你可以使用 “iw reg get” 命令检查国家/地区设置。 与您在 wpa_supplicant.conf 中设置的频道列表相比,监管域具有优先权。 OS LINUX 产品:WiFi 88MW32X 产品:WiFi 88W8801 产品:WiFi 88W8897 产品:WiFi 88W8987 产品:WiFi 88W8997 产品:WiFi 88X9098 产品:WiFi IW416 产品:WiFi IW6XX 产品:WiFi RW6XX 协议:Wi-Fi
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i.MX93 M33 コア: カスタム ボード上の micro-ROS のシステム稼働時間 (秒/ナノ秒) を取得するにはどうすればよいですか? こんにちは、皆さん 現在、カスタム SOM と MCUXpresso SDK (v25.06.00) を使用して、micro-ROS を i.MX93 (MIMX9352) の Cortex-M33 コアに移植しています。 UART トランスポートを確立し、 micro-ROS エージェントにコネクテッド。ノードとトピックは作成されましたが、公開されたデータは空または無効のようです。デバッグ後、ROS 2 エコシステムと同期するには、micro-ROS クライアントに高解像度のタイムスタンプ (秒とナノ秒) を提供する必要があることに気付きました。 スクリーンショット、デバッグ端末出力、コードを以下に添付します。 マイクロロスエージェント接続 Micro-ros agent connectionMicro-ros agent connectionマイクロロスエージェント接続 ROS トピック一覧 (トピックが空です (データは公開されていません)) ROS Topic listing (But topic is empty)ROS Topic listing (But topic is empty)ROS トピック一覧(ただしトピックは空です) デバッグ端末出力: デバッグコンソールの初期化が完了しました 過去のlpuart initとカスタム転送オープン 過去のrclcサポート、ノード、パブリッシャーの初期化 過去のrclcタイマー初期化 過去のrclcエグゼキュータinit、add_timer whileループ内 RCSOFTCHECK 失敗: rclc_executor_spin_some(&executor, RCL_MS_TO_NS(100)) | Lin0 執行者のスピン後 whileループ内 RCSOFTCHECK 失敗: rclc_executor_spin_some(&executor, RCL_MS_TO_NS(100)) | Lin0 執行者のスピン後 whileループ内 RCSOFTCHECK 失敗: rclc_executor_spin_some(&executor, RCL_MS_TO_NS(100)) | Lin0 執行者のスピン後 問題: rmw_publisher_publish に必要な精度を提供する、信頼性の高い「システム稼働時間」または「ティック」関数を SDKs で見つけるのに苦労しています。 lptmrドライバの例を使用しようとしましたが、LPTMR_Init()中にコードがハングします 私の質問: i.MX93 M33 の起動以降の高解像度 (nsec) モノトニック タイムスタンプを取得するための推奨 SDK API はありますか? i.MX9 シリーズに micro-ROS を実装した方: 専用のハードウェア タイマーを使用しましたか、それとも代わりに使用すべき標準の CMSIS/SDKs「GetTime」関数がありますか? 環境の詳細: ハードウェア: カスタム i.MX93 SOM + EVB ベースボード コア: Cortex-M331 SDK: 25.06.00 ツールチェーン:MCUXpresso IDE / VS Code Extension2 このプラットフォームでの 64 ビットナノ秒カウンター実装に関する洞察やコードスニペットがあれば、ぜひお知らせください。 よろしくお願いいたします。 アナンド Re: i.MX93 M33 Core: How to get System Uptime (sec/nsec) for micro-ROS on Custom Board? こんにちは、 tstmr.cを試してみましたSDK の例のデモ プログラム。期待通りに動作しません。カスタム ボードと avnet osm93 の 2 つの異なるボードで試しましたが、どちらもターミナルに出力がありませんでした。 デバッグすると、TSTMR 関連の関数が動作せず、プログラムは「TSTMR_ReadTimeStamp()」を超えません。 使用したSDK:MCUXpresso SDK(v25.06.00)。
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A1006 Write permsiions in "Authentication Operation" mode I’m a little confused about the write operation of the NXP A1006 when it is in “Authentication Operation” mode.   In “sd276413 - Objective short data sheet A1006, Secure Authentication IC (1.3).pdf” section 9.3.1 it is states that “Depending on the IC life cycle status the memory write operation is restricted to some specific memory areas and arbitrary data write operations are not possible but only non-reversible write operations are possible.”   Both “sd276413 - Objective short data sheet A1006, Secure Authentication IC (1.3).pdf” and “ds374620 - A1006 Secure Authenticator IC (2.0).pdf” state that in “Authentication Operation” “Only write operations to the user memory possible, for example transactional “usage data” updates” are possible but there is no exact definition of “transactional “usage data” updates”.   The problem is that “ds374620 - A1006 Secure Authenticator IC (2.0).pdf” states in Fig 16 that during “Authentication Operation” “Write arbitrary data to User Memory and read operation allowed”.   The A1006 does not have a counter like the Infineon SLE95250 or the NXP A1007. I had planned to implement a counter using 1 bit per count in “Authentication Operation" mode because I thought that “only non-reversible write operations are possible” in this mode. But if one can “Write arbitrary data to User Memory ” in “Authentication Operation" mode, then I cannot make a tamper-proof counter in the A1006.   Can anyone clarify the write permissions for the A1006 in "Authentication Operation" mode? 回复: A1006 Write permsiions in "Authentication Operation" mode I need A1006 technical support. If you have done it before, please contact me on FB 13922881086 Re: A1006 Write permsiions in "Authentication Operation" mode Hello,  Sorry for the inconvenience this might cause you but as the information of this product it's under NDA (Non-Disclosure Agreement) the information it's not public, this is not a secure channel to share any information of this device and currently, you are providing information which it's under NDA in a public way.  Could you please contact the person that helped you with getting the information (sales or distributor) for further details on your request?  Regards,  Estephania 
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MCXA346 - cannot locate the demo code for AN14822 Specifically: 2. Import a project from the GitHub repository. 3. Locate and open the an-mcxa346-spi-interface-implemented-by-smartdm project. Bought the board, now raring to go 🙂 MCXA Re: MCXA346 - cannot locate the demo code for AN14822 Hello, I apologize for the inconvenience, but AN14822 project is in the process of being published in Application Code Hub page I would recommend staying updated on the page. Best Regards, Luis
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OM13589 for A1006 Secure Authenticator Solutions Hi, It is possible that I erase the FW of OM13589 Demonstration Kit by MCUXpresso. However, I cannot find the FW or image from the website https://www.nxp.com/pages/demonstration-kit-for-a1006-secure-authenticator-solutions:OM13589 . Where can I get the FW or image for the A1006 Demo Kit solution? I want to test it with A1006 Demo Utility. Thank you. Demonstration Kit  Demonstration Kit  LPC17xx Re: OM13589 for A1006 Secure Authenticator Solutions Where can I get the FW or image for the A1006 Demo Kit solution? I want to test it with A1006 Demo Utility. v jesssaid fb 13922881086 Thank you. Re: OM13589 for A1006 Secure Authenticator Solutions HI Jerome, I am not sure if the demo project is available to public site. I would suggest you create a private case to request it. How to submit a new question for NXP Support  Have a great day, Jun Zhang ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: OM13589 for A1006 Secure Authenticator Solutions Hi Jun, Where can I download the example code for A1006 (Rapid IoT Kit Out Of Box Demo)? Thank you, Jerome Re: OM13589 for A1006 Secure Authenticator Solutions Hi Jerome 1. yes, it does. see Example code for A1006 in IOT Studio?  2. I currently don't have this board, I suggest you create a new thread to consult IoT box Rapid IoT  Have a great day, Jun Zhang ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: OM13589 for A1006 Secure Authenticator Solutions Hi Jun, Thanks for your support. But I have some questions, 1. Does the FW "Rapid IoT Kit Out Of Box Demo.atmo" support A1006 solution? 2. How to flash the FW to my OM13589 EV-kit? Is there any development guide?  Thank you, Jerome Re: OM13589 for A1006 Secure Authenticator Solutions Hi YUNFENG TSAI We have out of box example, and you can download it here: https://rapid-iot-studio.nxp.com/ Have a great day, Jun Zhang ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: OM13589 for A1006 Secure Authenticator Solutions How to get Chinese support?
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如何提出客户投诉? 任何受到伤害的消费者都可以拨打免费电话 07699-595-414 与代理交谈或自己注册,以登记他/她的申诉 ... 电源解决方案 Re: How do you raise a customer complaint? 任何受到伤害的消费者都可以拨打免费电话 07699-595-414 与代理交谈或自己注册,以登记他/她的申诉 ... Re: How do you raise a customer complaint? 任何受到伤害的消费者都可以拨打免费电话 07699-595-414 与代理交谈或自己注册,以登记他/她的申诉 ...
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間違った取引を返金する方法 間違った取引があった場合、電話で払い戻しを受けるにはどうすればよいですか?076995-95414- 電話で間違った番号に誤って送金した場合、通常は... 機能安全
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Using correct ENV Variable with nx_personalization demo for A30 I'm currently trying things out with the new A30 and I can't get the nx_personalization demo to work for the SIGMA-I authentication. I changed the ENV variable accordingly but still get an error. My output is as follows: nx_mw :INFO :Session Open Succeed nx_mw :INFO :Nx provision start nx_mw :INFO :******************************* NOTE ******************************************** nx_mw :INFO :Default top level certificate directory is: /tmp/configuration/a30_hostcert_depth2_x509_rev3_nistp/ nx_mw :INFO :To override this directory path, you need to set env variable as follows: nx_mw :INFO :NX_AUTH_CERT_DIR=..\nx-mw-top\binaries\configuration\cert_depth3_PKCS7_rev1 nx_mw :INFO :********************************************************************************* nx_mw :INFO :Using certificate/key from:'..\nx-mw-top\binaries\configuration\cert_depth3_PKCS7_rev1' (ENV=NX_AUTH_CERT_DIR) nx_mw :WARN :Potential directory traversal nx_mw :WARN :host_root_certificates is not found. Use leaf certificate which is assumed to be self signed nx_mw :INFO :Using certificate/key from:'..\nx-mw-top\binaries\configuration\cert_depth3_PKCS7_rev1' (ENV=NX_AUTH_CERT_DIR) nx_mw :WARN :Potential directory traversal nx_mw :WARN :nxEnsure:'status == kStatus_SSS_Success' failed. At Line:741 Function:nx_load_host_root_CA_pubkey nx_mw :WARN :nxEnsure:'status == kStatus_SSS_Success' failed. At Line:976 Function:ex_sss_entry nx_mw :ERROR:nx_Personalization Example Failed !!!... nx_mw :INFO :ex_sss Finished nx_mw :ERROR:ex_sss_entry Failed nx_mw :ERROR:!ERROR! ret != 0. Re: Using correct ENV Variable with nx_personalization demo for A30 Hello, I need to develop A1006UK , experienced help me out , thanks! Re: Using correct ENV Variable with nx_personalization demo for A30 Hi @Jansch , Thanks for the info! Actually A30 can only be personalized once, I am not sure how you configure nxMW for the first personalization, but please keep align with the first configuration when you do the first personalization,  I think it should also be done by yourself , right? if you personalize the chip with the keys and certs in folder A but run demos with ENV to folder B , there would be issues for sure. BTW, Is it possible to share your current nxMW cmake options for a review? Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: Using correct ENV Variable with nx_personalization demo for A30 Hello @Kan_Li  You are absolutely right, I didn't realise that was the issue with the nx_Personalization, as I don't have the chip first hand. I also wanted to apologize for the formatting, if I only use quick reply, it doesn't format properly. When running the Minimal example using SIGMA-I I receive this error still though. Is this the wrong directory?  nx_mw :INFO :Read file from /home/pi/a30mw/nxmw-main/binaries/configuration/cert_depth3_PKCS7_rev1/cert_and_key/nist_p/device_root_certificate.der nx_mw :WARN :nxEnsure:'status == kStatus_SSS_Success' failed. At Line:1963 Function:nx_verify_leaf_cert_hash_signature nx_mw :WARN :nxEnsure:'status == kStatus_SSS_Success' failed. At Line:3512 Function:nx_sigma_i_authenticate_channel nx_mw :ERROR:Could not set SIGMA-I Verifier Secure Channel nx_mw :WARN :nxEnsure:'kStatus_SSS_Success == status' failed. At Line:174 Function:ex_sss_boot_nx_open nx_mw :ERROR:ex_sss_session_open Failed nx_mw :ERROR:!ERROR! ret != 0. Re: Using correct ENV Variable with nx_personalization demo for A30 Hi @Jansch , Thanks for the info! We noticed the 91 DE error in the error log which indicates it's already personalized, so it can not be personalized any more. and as you mentioned , All example are working but nx_Personalization is failed. Question 1) Have you played with all example works with Symmetric authentication? I understand you didn't try with Sigma-I-Authentication, right? Please kindly clarify. Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: Using correct ENV Variable with nx_personalization demo for A30 Hey @Kan_Li  I wrote the wrong directory in the last message, this is the correct one: nx_mw :INFO :Using certificate/key from:'/home/pi/a30mw/nxmw-main/binaries/configuration/cert_depth3_PKCS7_rev1' (ENV=NX_AUTH_CERT_DIR) nx_mw :INFO :Read file from /home/pi/a30mw/nxmw-main/binaries/configuration/cert_depth3_PKCS7_rev1/cert_and_key/nist_p/host_root_certificate.der nx_mw :INFO :Read file from /home/pi/a30mw/nxmw-main/binaries/configuration/cert_depth3_PKCS7_rev1/cert_and_key/nist_p/device_leaf_certificate.der nx_mw :INFO :Read file from /home/pi/a30mw/nxmw-main/binaries/configuration/cert_depth3_PKCS7_rev1/cert_and_key/nist_p/device_leaf_keypair.der  The output for verbose logs is long, as following: nx_mw :INFO :Session Open Succeed nx_mw :INFO :Nx provision start nx_mw :INFO :******************************* NOTE ******************************************** nx_mw :INFO :Default top level certificate directory is: /tmp/configuration/a30_hostcert_depth2_x509_rev3_nistp/ nx_mw :INFO :To override this directory path, you need to set env variable as follows: nx_mw :INFO :NX_AUTH_CERT_DIR=..\nx-mw-top\binaries\configuration\cert_depth3_PKCS7_rev1 nx_mw :INFO :********************************************************************************* nx_mw :INFO :Using certificate/key from:'/home/pi/a30mw/nxmw-main/binaries/configuration/cert_depth3_PKCS7_rev1' (ENV=NX_AUTH_CERT_DIR) nx_mw :DEBUG:Number of characters read = 523 nx_mw :INFO :Read file from /home/pi/a30mw/nxmw-main/binaries/configuration/cert_depth3_PKCS7_rev1/cert_and_key/nist_p/host_root_certificate.der nx_mw :DEBUG:openssl parse certificates failed. It maybe PKCS#7 certificate APDU :DEBUG:GetKeySettings [CARootKeyList] APDU :DEBUG: [Option] = 0x2 nx_mw :DEBUG: Input:Native Command code (Len=1) 45 nx_mw :DEBUG: Input:Native Command Header (Len=1) 02 nx_mw :DEBUG:FN: nx_AES_EV2_MAC_CommandAPDU nx_mw :DEBUG:Command counter = 1 nx_mw :DEBUG:APDU Tx> (Len=15) 90 45 00 00 09 02 69 8F 94 02 2C AD 68 40 00 nx_mw :DEBUG:Enter phNxpEseProto7816_Transceive nx_mw :DEBUG:Transceive data ptr 0x0x7ffff91e9870 len:15 nx_mw :DEBUG:I-Frame Data Len: 15 Seq. no:1 nx_mw :DEBUG:TransceiveProcess nextTransceiveState 1 nx_mw :DEBUG:phNxpEse_WriteFrame Enter .. nx_mw :DEBUG:TX (axI2CWrite) > (Len=21) 21 40 00 0F 90 45 00 00 09 02 69 8F 94 02 2C AD 68 40 00 66 0A nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RAW Tx> (Len=21) 21 40 00 0F 90 45 00 00 09 02 69 8F 94 02 2C AD 68 40 00 66 0A nx_mw :DEBUG:phNxpEse_read Enter .. nx_mw :DEBUG:phPalEse_i2c_read Read Requested 2 bytes nx_mw :DEBUG:Done with rv = 0d nx_mw :DEBUG:RX (axI2CRead): (Len=2) 00 00 nx_mw :DEBUG:_i2c_read() error : 13 nx_mw :DEBUG:_i2c_read() failed. Going to retry, counter:1 ! nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RX (axI2CRead): (Len=2) 12 40 nx_mw :DEBUG:phNxpEse_readPacket Read HDR nx_mw :DEBUG:phNxpEse_readPacket SOF FOUND nx_mw :DEBUG:phPalEse_i2c_read Read Requested 2 bytes nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RX (axI2CRead): (Len=2) 00 12 nx_mw :DEBUG:poll_sof_chained_delay value is 0 nx_mw :DEBUG:phPalEse_i2c_read Read Requested 20 bytes nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RX (axI2CRead): (Len=20) 01 00 0C FF 3F 30 3F 00 7A 0B 9B FC 58 3F DC CD 91 00 90 5D nx_mw :DEBUG:RAW Rx< (Len=24) 12 40 00 12 01 00 0C FF 3F 30 3F 00 7A 0B 9B FC 58 3F DC CD 91 00 90 5D nx_mw :DEBUG:phNxpEseProto7816_ProcessResponse p_data ----> 0x55562b33cab0 len ----> 0x18 nx_mw :DEBUG:Received CRC:0x905d Calculated CRC:0x905d nx_mw :DEBUG:Retry Counter = 0 nx_mw :DEBUG:phNxpEseProto7816_DecodeFrame I-Frame Received nx_mw :DEBUG:phNxpEseProto7816_DecodeFrame I-Frame lastRcvdIframeInfo.seqNo:0x1 nx_mw :DEBUG:Data[0]=0x1 len=18 Data[17]=0x91 Data[18]=0x0 nx_mw :DEBUG: phNxpEse_Transceive Exit status 0x0 nx_mw :DEBUG:APDU Rx< (Len=18) 01 00 0C FF 3F 30 3F 00 7A 0B 9B FC 58 3F DC CD 91 00 nx_mw :DEBUG:FN: nx_DeCrypt nx_mw :DEBUG: Input:rspBuf (Len=18) 01 00 0C FF 3F 30 3F 00 7A 0B 9B FC 58 3F DC CD 91 00 nx_mw :DEBUG:Mac verified : (Len=16) 09 7A 96 0B 06 9B E5 FC 5B 58 13 3F CD DC 18 CD nx_mw :DEBUG:Decrypted the response (Len=10) 01 00 0C FF 3F 30 3F 00 91 00 APDU :DEBUG:ManageCARootKey [] APDU :DEBUG: [KeyNo] = 0x0 APDU :DEBUG: [curveID] = 0xC APDU :DEBUG: [accessRight(LSB)] = 0x3FFF APDU :DEBUG: [writeAccessCond] = 0x30 APDU :DEBUG: [readAccessCond] = 0x3F APDU :DEBUG: [Reserved] = 0x0 APDU :DEBUG: [Public key] (Len=65) 04 C2 3A B7 F3 EB 7E CD F9 4E 1C 43 B2 8B 0C 2F 49 C9 61 35 A1 4A E0 58 BC A9 FE F9 4D 18 D4 46 28 C1 2F 8D 00 5B C4 8C C4 02 74 86 90 42 75 AE 55 96 0B 23 C7 6E 96 EF 96 80 27 04 2A 16 7D E5 AD APDU :DEBUG: [CA Subject Name Len] = 0x64 APDU :DEBUG: [CA Issuer Name] (Len=100) 30 62 31 0B 30 09 06 03 55 04 06 13 02 4E 4C 31 12 30 10 06 03 55 04 08 0C 09 45 69 6E 64 68 6F 76 65 6E 31 12 30 10 06 03 55 04 07 0C 09 45 69 6E 64 68 6F 76 65 6E 31 0C 30 0A 06 03 55 04 0A 0C 03 4E 58 50 31 1D 30 1B 06 03 55 04 03 0C 14 4E 58 50 20 41 75 74 68 20 52 6F 6F 74 43 41 76 45 32 30 31 nx_mw :DEBUG: Input:Native Command code (Len=1) 48 nx_mw :DEBUG: Input:Native Command Header (Len=7) 00 0C FF 3F 30 3F 00 nx_mw :DEBUG: Input:Native Command Data (Len=166) 04 C2 3A B7 F3 EB 7E CD F9 4E 1C 43 B2 8B 0C 2F 49 C9 61 35 A1 4A E0 58 BC A9 FE F9 4D 18 D4 46 28 C1 2F 8D 00 5B C4 8C C4 02 74 86 90 42 75 AE 55 96 0B 23 C7 6E 96 EF 96 80 27 04 2A 16 7D E5 AD 64 30 62 31 0B 30 09 06 03 55 04 06 13 02 4E 4C 31 12 30 10 06 03 55 04 08 0C 09 45 69 6E 64 68 6F 76 65 6E 31 12 30 10 06 03 55 04 07 0C 09 45 69 6E 64 68 6F 76 65 6E 31 0C 30 0A 06 03 55 04 0A 0C 03 4E 58 50 31 1D 30 1B 06 03 55 04 03 0C 14 4E 58 50 20 41 75 74 68 20 52 6F 6F 74 43 41 76 45 32 30 31 nx_mw :DEBUG:FN: nx_AES_EV2_Encrypt_CommandAPDU nx_mw :DEBUG:FN: nx_PadCommandAPDU nx_mw :DEBUG:Input: cmdApduBuf (Len=176) 04 C2 3A B7 F3 EB 7E CD F9 4E 1C 43 B2 8B 0C 2F 49 C9 61 35 A1 4A E0 58 BC A9 FE F9 4D 18 D4 46 28 C1 2F 8D 00 5B C4 8C C4 02 74 86 90 42 75 AE 55 96 0B 23 C7 6E 96 EF 96 80 27 04 2A 16 7D E5 AD 64 30 62 31 0B 30 09 06 03 55 04 06 13 02 4E 4C 31 12 30 10 06 03 55 04 08 0C 09 45 69 6E 64 68 6F 76 65 6E 31 12 30 10 06 03 55 04 07 0C 09 45 69 6E 64 68 6F 76 65 6E 31 0C 30 0A 06 03 55 04 0A 0C 03 4E 58 50 31 1D 30 1B 06 03 55 04 03 0C 14 4E 58 50 20 41 75 74 68 20 52 6F 6F 74 43 41 76 45 32 30 31 80 00 00 00 00 00 00 00 00 00 nx_mw :DEBUG:FN: nx_AES_EV2_MAC_CommandAPDU nx_mw :DEBUG:Command counter = 2 nx_mw :DEBUG:APDU Tx> (Len=197) 90 48 00 00 BF 00 0C FF 3F 30 3F 00 F5 AE 1D 20 C9 3C EA 4A A7 6D 67 3E 1D E5 79 6B D7 C1 91 23 04 9E 00 52 0A F5 DA 93 8F 83 D0 1E EC 98 3B 07 30 BE 85 97 47 5A 8A CF CF 52 79 8F CC A0 47 06 F8 6E 3B B9 A9 E5 FB 84 FC F9 F0 19 0E 2A F4 00 C4 F4 C4 BD 56 B9 21 03 AC 10 90 C8 A1 A3 3C 9C 75 4E 10 5A BD F8 AA 2D 8E BA CB 89 CE 04 50 F9 CB 4E CF 56 45 E2 E4 BF D9 FF D4 AA 35 81 2A 32 F4 CB B3 B3 EE E1 F0 AB 47 A5 DF 95 8D 43 CA 6F 05 14 36 AE 13 73 1C 29 E7 CE EB 38 3E 37 20 41 95 B1 AD 15 5A 1A D8 89 29 4F 9A 48 9F AE 13 F8 38 03 D3 DB 16 99 E3 0B 7F 24 E8 C0 2E E1 98 E2 D7 11 C7 FB 00 nx_mw :DEBUG:Enter phNxpEseProto7816_Transceive nx_mw :DEBUG:Transceive data ptr 0x0x7ffff91ea760 len:197 nx_mw :DEBUG:I-Frame Data Len: 197 Seq. no:0 nx_mw :DEBUG:TransceiveProcess nextTransceiveState 1 nx_mw :DEBUG:phNxpEse_WriteFrame Enter .. nx_mw :DEBUG:TX (axI2CWrite) > (Len=203) 21 00 00 C5 90 48 00 00 BF 00 0C FF 3F 30 3F 00 F5 AE 1D 20 C9 3C EA 4A A7 6D 67 3E 1D E5 79 6B D7 C1 91 23 04 9E 00 52 0A F5 DA 93 8F 83 D0 1E EC 98 3B 07 30 BE 85 97 47 5A 8A CF CF 52 79 8F CC A0 47 06 F8 6E 3B B9 A9 E5 FB 84 FC F9 F0 19 0E 2A F4 00 C4 F4 C4 BD 56 B9 21 03 AC 10 90 C8 A1 A3 3C 9C 75 4E 10 5A BD F8 AA 2D 8E BA CB 89 CE 04 50 F9 CB 4E CF 56 45 E2 E4 BF D9 FF D4 AA 35 81 2A 32 F4 CB B3 B3 EE E1 F0 AB 47 A5 DF 95 8D 43 CA 6F 05 14 36 AE 13 73 1C 29 E7 CE EB 38 3E 37 20 41 95 B1 AD 15 5A 1A D8 89 29 4F 9A 48 9F AE 13 F8 38 03 D3 DB 16 99 E3 0B 7F 24 E8 C0 2E E1 98 E2 D7 11 C7 FB 00 D3 7A nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RAW Tx> (Len=203) 21 00 00 C5 90 48 00 00 BF 00 0C FF 3F 30 3F 00 F5 AE 1D 20 C9 3C EA 4A A7 6D 67 3E 1D E5 79 6B D7 C1 91 23 04 9E 00 52 0A F5 DA 93 8F 83 D0 1E EC 98 3B 07 30 BE 85 97 47 5A 8A CF CF 52 79 8F CC A0 47 06 F8 6E 3B B9 A9 E5 FB 84 FC F9 F0 19 0E 2A F4 00 C4 F4 C4 BD 56 B9 21 03 AC 10 90 C8 A1 A3 3C 9C 75 4E 10 5A BD F8 AA 2D 8E BA CB 89 CE 04 50 F9 CB 4E CF 56 45 E2 E4 BF D9 FF D4 AA 35 81 2A 32 F4 CB B3 B3 EE E1 F0 AB 47 A5 DF 95 8D 43 CA 6F 05 14 36 AE 13 73 1C 29 E7 CE EB 38 3E 37 20 41 95 B1 AD 15 5A 1A D8 89 29 4F 9A 48 9F AE 13 F8 38 03 D3 DB 16 99 E3 0B 7F 24 E8 C0 2E E1 98 E2 D7 11 C7 FB 00 D3 7A nx_mw :DEBUG:phNxpEse_read Enter .. nx_mw :DEBUG:phPalEse_i2c_read Read Requested 2 bytes nx_mw :DEBUG:Done with rv = 0d nx_mw :DEBUG:RX (axI2CRead): (Len=2) 00 00 nx_mw :DEBUG:_i2c_read() error : 13 nx_mw :DEBUG:_i2c_read() failed. Going to retry, counter:1 ! nx_mw :DEBUG:Done with rv = 0d nx_mw :DEBUG:RX (axI2CRead): (Len=2) 00 00 nx_mw :DEBUG:_i2c_read() error : 13 nx_mw :DEBUG:_i2c_read() failed. Going to retry, counter:2 ! nx_mw :DEBUG:Done with rv = 0d nx_mw :DEBUG:RX (axI2CRead): (Len=2) 00 00 nx_mw :DEBUG:_i2c_read() error : 13 nx_mw :DEBUG:_i2c_read() failed. Going to retry, counter:3 ! nx_mw :DEBUG:Done with rv = 0d nx_mw :DEBUG:RX (axI2CRead): (Len=2) 00 00 nx_mw :DEBUG:_i2c_read() error : 13 nx_mw :DEBUG:_i2c_read() failed. Going to retry, counter:4 ! nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RX (axI2CRead): (Len=2) 12 00 nx_mw :DEBUG:phNxpEse_readPacket Read HDR nx_mw :DEBUG:phNxpEse_readPacket SOF FOUND nx_mw :DEBUG:phPalEse_i2c_read Read Requested 2 bytes nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RX (axI2CRead): (Len=2) 00 0A nx_mw :DEBUG:poll_sof_chained_delay value is 0 nx_mw :DEBUG:phPalEse_i2c_read Read Requested 12 bytes nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RX (axI2CRead): (Len=12) 05 98 F4 58 9A 1B FB D3 91 00 FE D5 nx_mw :DEBUG:RAW Rx< (Len=16) 12 00 00 0A 05 98 F4 58 9A 1B FB D3 91 00 FE D5 nx_mw :DEBUG:phNxpEseProto7816_ProcessResponse p_data ----> 0x55562b33cab0 len ----> 0x10 nx_mw :DEBUG:Received CRC:0xfed5 Calculated CRC:0xfed5 nx_mw :DEBUG:Retry Counter = 0 nx_mw :DEBUG:phNxpEseProto7816_DecodeFrame I-Frame Received nx_mw :DEBUG:phNxpEseProto7816_DecodeFrame I-Frame lastRcvdIframeInfo.seqNo:0x0 nx_mw :DEBUG:Data[0]=0x5 len=10 Data[9]=0x91 Data[10]=0x0 nx_mw :DEBUG: phNxpEse_Transceive Exit status 0x0 nx_mw :DEBUG:APDU Rx< (Len=10) 05 98 F4 58 9A 1B FB D3 91 00 nx_mw :DEBUG:FN: nx_DeCrypt nx_mw :DEBUG: Input:rspBuf (Len=10) 05 98 F4 58 9A 1B FB D3 91 00 nx_mw :DEBUG:Mac verified : (Len=16) 43 05 90 98 C4 F4 1B 58 42 9A 1F 1B 62 FB EE D3 nx_mw :DEBUG:Decrypted the response (Len=2) 91 00 nx_mw :DEBUG:Using certificate/key from:'/home/pi/a30mw/nxmw-main/binaries/configuration/cert_depth3_PKCS7_rev1' (ENV=NX_AUTH_CERT_DIR) nx_mw :DEBUG:Number of characters read = 500 nx_mw :INFO :Read file from /home/pi/a30mw/nxmw-main/binaries/configuration/cert_depth3_PKCS7_rev1/cert_and_key/nist_p/device_leaf_certificate.der nx_mw :DEBUG:Using certificate/key from:'/home/pi/a30mw/nxmw-main/binaries/configuration/cert_depth3_PKCS7_rev1' (ENV=NX_AUTH_CERT_DIR) nx_mw :DEBUG:Number of characters read = 121 nx_mw :INFO :Read file from /home/pi/a30mw/nxmw-main/binaries/configuration/cert_depth3_PKCS7_rev1/cert_and_key/nist_p/device_leaf_keypair.der APDU :DEBUG:GetKeySettings [ECCPrivateKeyList] APDU :DEBUG: [Option] = 0x1 nx_mw :DEBUG: Input:Native Command code (Len=1) 45 nx_mw :DEBUG: Input:Native Command Header (Len=1) 01 nx_mw :DEBUG:FN: nx_AES_EV2_MAC_CommandAPDU nx_mw :DEBUG:Command counter = 3 nx_mw :DEBUG:APDU Tx> (Len=15) 90 45 00 00 09 01 63 3C E6 71 4F 32 9A AE 00 nx_mw :DEBUG:Enter phNxpEseProto7816_Transceive nx_mw :DEBUG:Transceive data ptr 0x0x7ffff91e97f0 len:15 nx_mw :DEBUG:I-Frame Data Len: 15 Seq. no:1 nx_mw :DEBUG:TransceiveProcess nextTransceiveState 1 nx_mw :DEBUG:phNxpEse_WriteFrame Enter .. nx_mw :DEBUG:TX (axI2CWrite) > (Len=21) 21 40 00 0F 90 45 00 00 09 01 63 3C E6 71 4F 32 9A AE 00 1F 2E nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RAW Tx> (Len=21) 21 40 00 0F 90 45 00 00 09 01 63 3C E6 71 4F 32 9A AE 00 1F 2E nx_mw :DEBUG:phNxpEse_read Enter .. nx_mw :DEBUG:phPalEse_i2c_read Read Requested 2 bytes nx_mw :DEBUG:Done with rv = 0d nx_mw :DEBUG:RX (axI2CRead): (Len=2) 00 00 nx_mw :DEBUG:_i2c_read() error : 13 nx_mw :DEBUG:_i2c_read() failed. Going to retry, counter:1 ! nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RX (axI2CRead): (Len=2) 12 40 nx_mw :DEBUG:phNxpEse_readPacket Read HDR nx_mw :DEBUG:phNxpEse_readPacket SOF FOUND nx_mw :DEBUG:phPalEse_i2c_read Read Requested 2 bytes nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RX (axI2CRead): (Len=2) 00 3F nx_mw :DEBUG:poll_sof_chained_delay value is 0 nx_mw :DEBUG:phPalEse_i2c_read Read Requested 65 bytes nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RX (axI2CRead): (Len=65) 04 00 0C 04 00 30 00 00 00 00 00 00 00 00 02 0C 30 00 30 00 00 00 00 00 00 00 00 03 0D 04 00 30 00 00 00 00 00 00 00 00 04 0C 08 00 30 00 00 00 00 00 00 00 00 94 8F 21 C9 D4 42 97 1C 91 00 61 71 nx_mw :DEBUG:RAW Rx< (Len=69) 12 40 00 3F 04 00 0C 04 00 30 00 00 00 00 00 00 00 00 02 0C 30 00 30 00 00 00 00 00 00 00 00 03 0D 04 00 30 00 00 00 00 00 00 00 00 04 0C 08 00 30 00 00 00 00 00 00 00 00 94 8F 21 C9 D4 42 97 1C 91 00 61 71 nx_mw :DEBUG:phNxpEseProto7816_ProcessResponse p_data ----> 0x55562b33cab0 len ----> 0x45 nx_mw :DEBUG:Received CRC:0x6171 Calculated CRC:0x6171 nx_mw :DEBUG:Retry Counter = 0 nx_mw :DEBUG:phNxpEseProto7816_DecodeFrame I-Frame Received nx_mw :DEBUG:phNxpEseProto7816_DecodeFrame I-Frame lastRcvdIframeInfo.seqNo:0x1 nx_mw :DEBUG:Data[0]=0x4 len=63 Data[62]=0x91 Data[63]=0x0 nx_mw :DEBUG: phNxpEse_Transceive Exit status 0x0 nx_mw :DEBUG:APDU Rx< (Len=63) 04 00 0C 04 00 30 00 00 00 00 00 00 00 00 02 0C 30 00 30 00 00 00 00 00 00 00 00 03 0D 04 00 30 00 00 00 00 00 00 00 00 04 0C 08 00 30 00 00 00 00 00 00 00 00 94 8F 21 C9 D4 42 97 1C 91 00 nx_mw :DEBUG:FN: nx_DeCrypt nx_mw :DEBUG: Input:rspBuf (Len=63) 04 00 0C 04 00 30 00 00 00 00 00 00 00 00 02 0C 30 00 30 00 00 00 00 00 00 00 00 03 0D 04 00 30 00 00 00 00 00 00 00 00 04 0C 08 00 30 00 00 00 00 00 00 00 00 94 8F 21 C9 D4 42 97 1C 91 00 nx_mw :DEBUG:Mac verified : (Len=16) D0 94 C2 8F 88 21 4F C9 10 D4 FE 42 1B 97 B9 1C nx_mw :DEBUG:Decrypted the response (Len=55) 04 00 0C 04 00 30 00 00 00 00 00 00 00 00 02 0C 30 00 30 00 00 00 00 00 00 00 00 03 0D 04 00 30 00 00 00 00 00 00 00 00 04 0C 08 00 30 00 00 00 00 00 00 00 00 91 00 APDU :DEBUG:ManageKeyPair [] APDU :DEBUG: [KeyNo] = 0x0 APDU :DEBUG: [Option] = 0x1 APDU :DEBUG: [curveID] = 0xC APDU :DEBUG: [KeyPolicy(LSB)] = 0x4 APDU :DEBUG: [writeAccessCond] = 0x30 APDU :DEBUG: [KUCLimit(LSB)] = 0x0 APDU :DEBUG: [Private key] (Len=32) 2F 0A 6C 8F AC A9 E6 E3 B2 8D C1 24 F6 39 D3 9F E2 83 27 C6 6B 25 0C 18 75 F0 2C 94 8B 15 CC 47 nx_mw :DEBUG: Input:Native Command code (Len=1) 46 nx_mw :DEBUG: Input:Native Command Header (Len=10) 00 01 0C 04 00 30 00 00 00 00 nx_mw :DEBUG: Input:Native Command Data (Len=32) 2F 0A 6C 8F AC A9 E6 E3 B2 8D C1 24 F6 39 D3 9F E2 83 27 C6 6B 25 0C 18 75 F0 2C 94 8B 15 CC 47 nx_mw :DEBUG:FN: nx_AES_EV2_Encrypt_CommandAPDU nx_mw :DEBUG:FN: nx_PadCommandAPDU nx_mw :DEBUG:Input: cmdApduBuf (Len=48) 2F 0A 6C 8F AC A9 E6 E3 B2 8D C1 24 F6 39 D3 9F E2 83 27 C6 6B 25 0C 18 75 F0 2C 94 8B 15 CC 47 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 nx_mw :DEBUG:FN: nx_AES_EV2_MAC_CommandAPDU nx_mw :DEBUG:Command counter = 4 nx_mw :DEBUG:APDU Tx> (Len=72) 90 46 00 00 42 00 01 0C 04 00 30 00 00 00 00 A2 B1 30 6A AE CF 30 47 D5 96 D7 EB 69 EF DB A3 66 8D F0 B1 0F FD 3D FE 42 98 DF 73 71 EA 7D 82 98 B6 31 9E CE F0 FF 8C D6 14 53 D5 22 03 CD 78 C9 ED 69 98 30 1A BF DA 00 nx_mw :DEBUG:Enter phNxpEseProto7816_Transceive nx_mw :DEBUG:Transceive data ptr 0x0x7ffff91ea740 len:72 nx_mw :DEBUG:I-Frame Data Len: 72 Seq. no:0 nx_mw :DEBUG:TransceiveProcess nextTransceiveState 1 nx_mw :DEBUG:phNxpEse_WriteFrame Enter .. nx_mw :DEBUG:TX (axI2CWrite) > (Len=78) 21 00 00 48 90 46 00 00 42 00 01 0C 04 00 30 00 00 00 00 A2 B1 30 6A AE CF 30 47 D5 96 D7 EB 69 EF DB A3 66 8D F0 B1 0F FD 3D FE 42 98 DF 73 71 EA 7D 82 98 B6 31 9E CE F0 FF 8C D6 14 53 D5 22 03 CD 78 C9 ED 69 98 30 1A BF DA 00 68 F3 nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RAW Tx> (Len=78) 21 00 00 48 90 46 00 00 42 00 01 0C 04 00 30 00 00 00 00 A2 B1 30 6A AE CF 30 47 D5 96 D7 EB 69 EF DB A3 66 8D F0 B1 0F FD 3D FE 42 98 DF 73 71 EA 7D 82 98 B6 31 9E CE F0 FF 8C D6 14 53 D5 22 03 CD 78 C9 ED 69 98 30 1A BF DA 00 68 F3 nx_mw :DEBUG:phNxpEse_read Enter .. nx_mw :DEBUG:phPalEse_i2c_read Read Requested 2 bytes nx_mw :DEBUG:Done with rv = 0d nx_mw :DEBUG:RX (axI2CRead): (Len=2) 00 00 nx_mw :DEBUG:_i2c_read() error : 13 nx_mw :DEBUG:_i2c_read() failed. Going to retry, counter:1 ! nx_mw :DEBUG:Done with rv = 0d nx_mw :DEBUG:RX (axI2CRead): (Len=2) 00 00 nx_mw :DEBUG:_i2c_read() error : 13 nx_mw :DEBUG:_i2c_read() failed. Going to retry, counter:2 ! nx_mw :DEBUG:Done with rv = 0d nx_mw :DEBUG:RX (axI2CRead): (Len=2) 00 00 nx_mw :DEBUG:_i2c_read() error : 13 nx_mw :DEBUG:_i2c_read() failed. Going to retry, counter:3 ! nx_mw :DEBUG:Done with rv = 0d nx_mw :DEBUG:RX (axI2CRead): (Len=2) 00 00 nx_mw :DEBUG:_i2c_read() error : 13 nx_mw :DEBUG:_i2c_read() failed. Going to retry, counter:4 ! nx_mw :DEBUG:Done with rv = 0d nx_mw :DEBUG:RX (axI2CRead): (Len=2) 00 00 nx_mw :DEBUG:_i2c_read() error : 13 nx_mw :DEBUG:_i2c_read() failed. Going to retry, counter:5 ! nx_mw :DEBUG:Done with rv = 0d nx_mw :DEBUG:RX (axI2CRead): (Len=2) 00 00 nx_mw :DEBUG:_i2c_read() error : 13 nx_mw :DEBUG:_i2c_read() failed. Going to retry, counter:6 ! nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RX (axI2CRead): (Len=2) 12 00 nx_mw :DEBUG:phNxpEse_readPacket Read HDR nx_mw :DEBUG:phNxpEse_readPacket SOF FOUND nx_mw :DEBUG:phPalEse_i2c_read Read Requested 2 bytes nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RX (axI2CRead): (Len=2) 00 0A nx_mw :DEBUG:poll_sof_chained_delay value is 0 nx_mw :DEBUG:phPalEse_i2c_read Read Requested 12 bytes nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RX (axI2CRead): (Len=12) 7F 8B 20 25 EA 16 35 E6 91 00 86 F6 nx_mw :DEBUG:RAW Rx< (Len=16) 12 00 00 0A 7F 8B 20 25 EA 16 35 E6 91 00 86 F6 nx_mw :DEBUG:phNxpEseProto7816_ProcessResponse p_data ----> 0x55562b33cab0 len ----> 0x10 nx_mw :DEBUG:Received CRC:0x86f6 Calculated CRC:0x86f6 nx_mw :DEBUG:Retry Counter = 0 nx_mw :DEBUG:phNxpEseProto7816_DecodeFrame I-Frame Received nx_mw :DEBUG:phNxpEseProto7816_DecodeFrame I-Frame lastRcvdIframeInfo.seqNo:0x0 nx_mw :DEBUG:Data[0]=0x7f len=10 Data[9]=0x91 Data[10]=0x0 nx_mw :DEBUG: phNxpEse_Transceive Exit status 0x0 nx_mw :DEBUG:APDU Rx< (Len=10) 7F 8B 20 25 EA 16 35 E6 91 00 nx_mw :DEBUG:FN: nx_DeCrypt nx_mw :DEBUG: Input:rspBuf (Len=10) 7F 8B 20 25 EA 16 35 E6 91 00 nx_mw :DEBUG:Mac verified : (Len=16) 28 7F 86 8B E1 20 6F 25 BE EA C1 16 1B 35 B5 E6 nx_mw :DEBUG:Decrypted the response (Len=2) 91 00 APDU :DEBUG:GetConfiguration [Certificate Management] APDU :DEBUG: [Option] = 0x13 nx_mw :DEBUG: Input:Native Command code (Len=1) 65 nx_mw :DEBUG: Input:Native Command Header (Len=1) 13 nx_mw :DEBUG:FN: nx_AES_EV2_MAC_CommandAPDU nx_mw :DEBUG:Command counter = 5 nx_mw :DEBUG:APDU Tx> (Len=15) 90 65 00 00 09 13 A2 19 25 9F 28 A9 67 A0 00 nx_mw :DEBUG:Enter phNxpEseProto7816_Transceive nx_mw :DEBUG:Transceive data ptr 0x0x7ffff91ea0c0 len:15 nx_mw :DEBUG:I-Frame Data Len: 15 Seq. no:1 nx_mw :DEBUG:TransceiveProcess nextTransceiveState 1 nx_mw :DEBUG:phNxpEse_WriteFrame Enter .. nx_mw :DEBUG:TX (axI2CWrite) > (Len=21) 21 40 00 0F 90 65 00 00 09 13 A2 19 25 9F 28 A9 67 A0 00 7A 7F nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RAW Tx> (Len=21) 21 40 00 0F 90 65 00 00 09 13 A2 19 25 9F 28 A9 67 A0 00 7A 7F nx_mw :DEBUG:phNxpEse_read Enter .. nx_mw :DEBUG:phPalEse_i2c_read Read Requested 2 bytes nx_mw :DEBUG:Done with rv = 0d nx_mw :DEBUG:RX (axI2CRead): (Len=2) 00 00 nx_mw :DEBUG:_i2c_read() error : 13 nx_mw :DEBUG:_i2c_read() failed. Going to retry, counter:1 ! nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RX (axI2CRead): (Len=2) 12 40 nx_mw :DEBUG:phNxpEse_readPacket Read HDR nx_mw :DEBUG:phNxpEse_readPacket SOF FOUND nx_mw :DEBUG:phPalEse_i2c_read Read Requested 2 bytes nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RX (axI2CRead): (Len=2) 00 1A nx_mw :DEBUG:poll_sof_chained_delay value is 0 nx_mw :DEBUG:phPalEse_i2c_read Read Requested 28 bytes nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RX (axI2CRead): (Len=28) 2E 7F BE 71 08 3B 2B FF 46 F0 2B E5 66 16 DA 32 F7 34 39 B6 4D EA C7 D7 91 00 BB AF nx_mw :DEBUG:RAW Rx< (Len=32) 12 40 00 1A 2E 7F BE 71 08 3B 2B FF 46 F0 2B E5 66 16 DA 32 F7 34 39 B6 4D EA C7 D7 91 00 BB AF nx_mw :DEBUG:phNxpEseProto7816_ProcessResponse p_data ----> 0x55562b33cab0 len ----> 0x20 nx_mw :DEBUG:Received CRC:0xbbaf Calculated CRC:0xbbaf nx_mw :DEBUG:Retry Counter = 0 nx_mw :DEBUG:phNxpEseProto7816_DecodeFrame I-Frame Received nx_mw :DEBUG:phNxpEseProto7816_DecodeFrame I-Frame lastRcvdIframeInfo.seqNo:0x1 nx_mw :DEBUG:Data[0]=0x2e len=26 Data[25]=0x91 Data[26]=0x0 nx_mw :DEBUG: phNxpEse_Transceive Exit status 0x0 nx_mw :DEBUG:APDU Rx< (Len=26) 2E 7F BE 71 08 3B 2B FF 46 F0 2B E5 66 16 DA 32 F7 34 39 B6 4D EA C7 D7 91 00 nx_mw :DEBUG:FN: nx_DeCrypt nx_mw :DEBUG: Input:rspBuf (Len=26) 2E 7F BE 71 08 3B 2B FF 46 F0 2B E5 66 16 DA 32 F7 34 39 B6 4D EA C7 D7 91 00 nx_mw :DEBUG:Mac verified : (Len=16) 98 F7 45 34 5C 39 81 B6 E5 4D 5F EA 56 C7 C2 D7 nx_mw :DEBUG:Decrypted the response (Len=6) 05 04 08 10 91 00 APDU :DEBUG:ManageCertRepo [CreateCertRepo] APDU :DEBUG: [action] = 0x0 APDU :DEBUG: [repoID] = 0x0 APDU :DEBUG: [cert private keyID] = 0x0 APDU :DEBUG: [repoSize(LSB)] = 0xC00 APDU :DEBUG: [writeAccess] = 0x30 APDU :DEBUG: [readAccess] = 0x30 nx_mw :DEBUG: Input:Native Command code (Len=1) 49 nx_mw :DEBUG: Input:Native Command Header (Len=7) 00 00 00 00 0C 30 30 nx_mw :DEBUG:FN: nx_AES_EV2_MAC_CommandAPDU nx_mw :DEBUG:Command counter = 6 nx_mw :DEBUG:APDU Tx> (Len=21) 90 49 00 00 0F 00 00 00 00 0C 30 30 21 50 44 1A 00 AA 84 A7 00 nx_mw :DEBUG:Enter phNxpEseProto7816_Transceive nx_mw :DEBUG:Transceive data ptr 0x0x7ffff91eaf20 len:21 nx_mw :DEBUG:I-Frame Data Len: 21 Seq. no:0 nx_mw :DEBUG:TransceiveProcess nextTransceiveState 1 nx_mw :DEBUG:phNxpEse_WriteFrame Enter .. nx_mw :DEBUG:TX (axI2CWrite) > (Len=27) 21 00 00 15 90 49 00 00 0F 00 00 00 00 0C 30 30 21 50 44 1A 00 AA 84 A7 00 FA 77 nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RAW Tx> (Len=27) 21 00 00 15 90 49 00 00 0F 00 00 00 00 0C 30 30 21 50 44 1A 00 AA 84 A7 00 FA 77 nx_mw :DEBUG:phNxpEse_read Enter .. nx_mw :DEBUG:phPalEse_i2c_read Read Requested 2 bytes nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RX (axI2CRead): (Len=2) 12 00 nx_mw :DEBUG:phNxpEse_readPacket Read HDR nx_mw :DEBUG:phNxpEse_readPacket SOF FOUND nx_mw :DEBUG:phPalEse_i2c_read Read Requested 2 bytes nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RX (axI2CRead): (Len=2) 00 02 nx_mw :DEBUG:poll_sof_chained_delay value is 0 nx_mw :DEBUG:phPalEse_i2c_read Read Requested 4 bytes nx_mw :DEBUG:Done with rv = 0c nx_mw :DEBUG:RX (axI2CRead): (Len=4) 91 DE 37 A7 nx_mw :DEBUG:RAW Rx< (Len=8) 12 00 00 02 91 DE 37 A7 nx_mw :DEBUG:phNxpEseProto7816_ProcessResponse p_data ----> 0x55562b33cab0 len ----> 0x8 nx_mw :DEBUG:Received CRC:0x37a7 Calculated CRC:0x37a7 nx_mw :DEBUG:Retry Counter = 0 nx_mw :DEBUG:phNxpEseProto7816_DecodeFrame I-Frame Received nx_mw :DEBUG:phNxpEseProto7816_DecodeFrame I-Frame lastRcvdIframeInfo.seqNo:0x0 nx_mw :DEBUG:Data[0]=0x91 len=2 Data[1]=0x91 Data[2]=0xde nx_mw :DEBUG: phNxpEse_Transceive Exit status 0x0 nx_mw :DEBUG:APDU Rx< (Len=2) 91 DE nx_mw :DEBUG:FN: nx_DeCrypt nx_mw :DEBUG: Input:rspBuf (Len=2) 91 DE nx_mw :WARN :nxEnsure:'(ret == SM_OK) || (ret == SM_OK_ALT)' failed. At Line:3713 Function:sss_nx_TXn_AES_EV2 nx_mw :ERROR:nx_ManageCertRepo_CreateCertRepo Failed nx_mw :WARN :nxEnsure:'status == kStatus_SSS_Success' failed. At Line:812 Function:nx_load_se_leaf_keypair_and_cert nx_mw :WARN :nxEnsure:'status == kStatus_SSS_Success' failed. At Line:980 Function:ex_sss_entry nx_mw :ERROR:nx_Personalization Example Failed !!!... nx_mw :INFO :ex_sss Finished nx_mw :ERROR:ex_sss_entry Failed nx_mw :DEBUG:Close i2c device 3. nx_mw :DEBUG:phNxpEse_close - ESE Context deinit completed nx_mw :ERROR:!ERROR! ret != 0. Re: Using correct ENV Variable with nx_personalization demo for A30 Hi @Jansch , Thanks for the clarification! Is it possible to give us a more detailed log by enabling the following cmake option? -DNXMW_Log=Verbose Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------   Re: Using correct ENV Variable with nx_personalization demo for A30 Hi @Kan_Li  Yes, exactly. I can run every other demo and have tried a cuople things that all work, I just struggle to get the SIGMA-I authentication to work. NX_AUTH_CERT_DIR has been changed by me to refer to the folder indicated by section 4.1.1: "Hard coded certificates defined in nx-mw-top/demos/nx/nx_Personalization/nx_Personalization.h" The actual folder for me is found at: ~/a30mw/nxmw_main/demos/nx/nx_Personalization/nx_Personalization.h This is the content of my NX_AUTH_CERT_DIR aswell. Looking into that folder I have various certificates in plaintext, so everything seems to be in order. Greetings Jan Re: Using correct ENV Variable with nx_personalization demo for A30 Hi @Jansch , I understand you are following the steps as listed in section 2.5.3 in nxmw.pdf , but halted in the following step, right? and then you followed the steps in section 4.1.1 to Nx Personalization example with a self defined ENV, right? What is the setting for NX_AUTH_CERT_DIR in this case? Would you please clarify? Please kindly let me know if I made any misunderstanding here. Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: Using correct ENV Variable with nx_personalization demo for A30 Hello @Kan_Li, I'm running this setup on raspbian, therefore I'm unable to run a .bat file. I have followed the nxmw.pdf section 2.5, which refers me to the nx_Personalization example. I had the ENV variable set up wrongly, now I have the correct one. I can read the files, which the output is also indicating but I am still failing at some point: I am opening the session correctly, indicating a correct Symmetric Key being used. Maybe I need to select differen t options on linux when executing the command. I am not sure. nx_mw :INFO :******************************* NOTE ******************************************** nx_mw :INFO :Default top level certificate directory is: /tmp/configuration/a30_hostcert_depth2_x509_rev3_nistp/ nx_mw :INFO :To override this directory path, you need to set env variable as follows: nx_mw :INFO :NX_AUTH_CERT_DIR=..\nx-mw-top\binaries\configuration\cert_depth3_PKCS7_rev1 nx_mw :INFO :********************************************************************************* nx_mw :INFO :Using certificate/key from:'/home/pi/a30mw/nxmw-main/binaries/configuration/cert_depth3_PKCS7_rev1' (ENV=NX_AUTH_CERT_DIR) nx_mw :INFO :Read file from /home/pi/a30mw/nxmw-main/binaries/configuration/cert_depth3_PKCS7_rev1/cert_and_key/nist_p/host_root_certificate.der nx_mw :INFO :Read file from /home/pi/a30mw/nxmw-main/binaries/configuration/cert_depth3_PKCS7_rev1/cert_and_key/nist_p/device_leaf_certificate.der nx_mw :INFO :Read file from /home/pi/a30mw/nxmw-main/binaries/configuration/cert_depth3_PKCS7_rev1/cert_and_key/nist_p/device_leaf_keypair.der nx_mw :WARN :nxEnsure:'(ret == SM_OK) || (ret == SM_OK_ALT)' failed. At Line:3713 Function:sss_nx_TXn_AES_EV2 nx_mw :ERROR:nx_ManageCertRepo_CreateCertRepo Failed nx_mw :WARN :nxEnsure:'status == kStatus_SSS_Success' failed. At Line:812 Function:nx_load_se_leaf_keypair_and_cert nx_mw :WARN :nxEnsure:'status == kStatus_SSS_Success' failed. At Line:980 Function:ex_sss_entry nx_mw :ERROR:nx_Personalization Example Failed !!!... nx_mw :INFO :ex_sss Finished nx_mw :ERROR:ex_sss_entry Failed nx_mw :ERROR:!ERROR! ret != 0. Re: Using correct ENV Variable with nx_personalization demo for A30 Hi @Jansch , Yes, please use the certs and keys in nx-mw-top\binaries\configuration\a30_hostcert_depth2_x509_rev3_nistp to personalize the certificate for A30 . you may simply run the bat file : nxclitool_prov_host_root_cert for that purpose, please kindly refer to NXMW.pdf , section 2.1 set up A30/NTAG_X_DNA sample for more details. Hope that helps, Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------
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s32k1 AIPS-Lite 错误信息位置 Hello 我通过 AIPS-Lite 对某些寄存器的访问进行了限制。我的理解是,如果未经授权访问这些寄存器,系统将进入 HardFault 中断。 现在,我想记录这些未经授权的访问尝试。我该怎么做?我在 S32K-RM.pdf 中没有看到 AIPS-Lite 用于存储此错误信息的相关寄存器。 Re: s32k1 AIPS-Lite error message location 你好,@白川、 正如你所提到的,没有专用的AIPS错误状态寄存器。 发生违规访问时,内核会发出总线故障异常信号。 您可以按照 NXP 文档中的说明读取堆叠的程序计数器 (PC) 值: https://community.nxp.com/t5/S32K-Knowledge-Base/Fault-handling-on-S32K14x/ta-p/1114447 但是,如果异常是不精确的(用 CFSR[IMPRECISERR] 表示),则堆叠的 PC 与导致故障的实际指令不一致。出现这种情况是因为故障是在写缓冲区提交访问后检测到的。 要获得精确的故障信息,需要禁用写缓冲区,但这样做会降低系统性能。 此致, 丹尼尔 Re: s32k1 AIPS-Lite error message location 你好,@白川、 我从一开始就很清楚。 遗憾的是,BusFault 并不精确,这意味着 BFAR 寄存器无效。 如果故障是精确的,BFAR 将包含导致违规访问的外设寄存器地址。 当 BusFault 不精确时,保存在堆栈上的 PC 值也不是触发故障的确切指令。 在这种情况下,唯一的选择是检索堆栈 PC,然后分析前面的指令,找出最近的加载或存储操作,并提取目标地址。 BR,丹尼尔 Re: s32k1 AIPS-Lite error message location 你好@danielmartynek 非常感谢你的耐心解释。也许我没有表达清楚。实际上,我想做的是在 BusFault 处理程序中记录这种未经授权的访问尝试。例如:`pflash:0x00001a74 访问 peripheral[CAN0]:0x40024000` 失败。根据您的描述,PC 指针确实可以提供 pflash 中的地址,但我如何才能检索到它试图访问的目标地址呢?
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UJA1169 をスリープ モードにするにはどうすればよいでしょうか? FNMC、SDMC、SLPC はすべて 0 に設定されています。ただし、スリープ モードに入るコマンドを発行すると、すぐにスタンバイ モードにスイッチします。なぜこのようなことが起こるかご存知ですか? 私は以下の手順に従いました: 1. ウェイクピンの立ち上がりエッジを有効にする 2. CANウェイクアップを無効にする 3. CMCをオフラインに設定する 4. MCをスタンバイに設定する 5. MCをスリープに設定する Re: How can I put the UJA1169 into Sleep mode? スリープ コマンドの後、メイン ステータスをチェックしたところ、0x14 (不正なスリープ モード コマンドを受信した) が見つかりました。 Re: How can I put the UJA1169 into Sleep mode? こんにちは、ブムジンさん UJA1169(A) は、以下の条件がすべて満たされた場合にのみスリープ モードになります。 - スリープ モード コマンドが発行されました (SPI 経由の MC = 0b001)。 - ウェイクアップ イベントは保留中ではありません (すべてのイベント ステータス ビットがクリアされています)。 - 少なくとも 1 つの通常のウェイクアップ ソースが有効になっています (CAN ウェイクアップまたは WAKE ピン)。 - スリープ モードは永続的に無効になっていません (SLPC = 0)。 これらの条件のいずれかが満たされない場合、SBC はスリープ モードになりません。代わりに、リセットモードに移行し、次にスタンバイモードに移行し、リセットソースステータスビット(RSS)を設定して理由を示します(例:0b10100 = 不正なスリープ モード コマンドを受信しました。 したがって、スリープを発行する前にイベント情報レジスタがクリアされていることを確認し、WAKEピンの構成と有効化ビットを再確認してください。 お役に立てれば幸いです。 BRs、トーマス
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S32K144 AUTOSAR RTD CAN Example Build Error – Missing Port_Ci_Port_Ip_Types.h (S32DS 3.6.5) Hello everyone, I am working with S32 Design Studio version 3.6.5 and using the S32K1 AUTOSAR 4.4 – RTD 3.0.0 (QLP02, D2505) package. I tried to create and build the CAN example project provided in the RTD for MCU S32K144, targeting the S32K144EVB board. Environment details: Tool: S32 Design Studio 3.6.5 RTD: S32K1 AUTOSAR 4.4 RTD 3.0.0 (QLP02 D2505) MCU: S32K144 Board: S32K144EVB-Q100 Steps followed: Imported the CAN example using “S32DS Project From Example”. Selected CAN0 related pins (TX/RX) using the configuration tool. Clicked Update Code. Tried to build the project. Issue: During compilation, I consistently get the following error:   ./board/Port_Ci_Port_Ip_Cfg.h:47:10: fatal error: Port_Ci_Port_Ip_Types.h: No such file or directory #include "Port_Ci_Port_Ip_Types.h" compilation terminated. Building file: ../RTD/src/FlexCAN_Ip_Irq.c Invoking: Standard S32DS C Compiler   It looks like the Port IP AUTOSAR generated header file is missing, even after configuring CAN pins and updating the code. I have checked multiple forum posts and tried the suggested steps, but I am still unable to resolve this issue. Questions: Is this CAN example intended to be used directly as an AUTOSAR ECUC-based project in S32DS 3.6.5? Should a separate AUTOSAR RTD project be created first and then the example source files copied? Is there any additional step required to enable the AUTOSAR ECU Configuration editor instead of the SDK Pins/Clocks tool in S32DS 3.6.5? Any guidance on the correct workflow to build this RTD CAN example successfully on S32K144EVB would be greatly appreciated. Thank you. Re: S32K144 AUTOSAR RTD CAN Example Build Error – Missing Port_Ci_Port_Ip_Types.h (S32DS 3.6.5) Hi, RTD CAN demo example shows only internal loopback test, no pins are configured and you need to add it. You can refer to below guide for a reference how the PORT component should be added; https://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/HOWTO-Create-a-Blinking-LED-example-project-using-S32K1xx-RTD/ta-p/1471695 Not sure of other S32K144 CAN demos using MCAL level driver, but you can e.g. refer to S32K3 demos posted on https://community.nxp.com/t5/S32K-Knowledge-Base/RTD600-MCAL-amp-IP-S32K3X4EVB-T172-FlexCAN-Example-Interrupt/ta-p/2142069 . The usage is very similar.   BR, Petr Re: S32K144 AUTOSAR RTD CAN Example Build Error – Missing Port_Ci_Port_Ip_Types.h (S32DS 3.6.5) Hi, refer to modified demo example attached. It sends out 10 messages when tested with S32K144EVB-Q100 with PCAN tool connected Hope it helps. BR, Petr
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S32K144 AUTOSAR RTD CAN 示例版本错误 — 缺少 Port_Ci_Port_Ip_Types.h(S32DS 3.6.5) 大家好 我正在使用 S32 Design Studio 版本 3.6.5 并使用 S32K1 AUTOSAR 4.4 — RTD 3.0.0(QLP02、D2505)软件包。 我尝试创建和构建 MCU S32K144 RTD 中提供的 CAN 示例项目 ,目标是 S32K144EVB 板。 环境详情: 工具S32 Design Studio 3.6.5 rtd: s32k1 autosar 4.4 rtd 3.0.0(QLP02 D2505) MCU: S32K144 板:S32K144EVB-Q100 遵循的步骤 使用"从示例导入S32DS 项目 "导入 CAN 示例。 使用配置工具选择 CAN0 相关引脚(TX/RX)。 点击更新代码。 尝试版本项目。 问题: 在编译过程中,我一直遇到以下错误:   。/board/port_ci_port_port_IP_CFG.H: 47:10:致命错误:port_ci_port_port_IP_TYPES.H:没有 这样的 文件 或 目录 #include"Port_Ci_Port_Ip_Types.h"编译 已终止。构建文件: ./RTD/src/FlexCAN_Ip_Irq.c 调用 标准 S32DS C 编译器   看起来端口 IP AUTOSAR 生成的头文件丢失了,即使在配置 CAN 引脚和更新代码后也是如此。 我查看了论坛上的多个帖子,并尝试了建议的步骤,但仍无法解决这个问题。 问题 该 CAN 示例是否打算直接用作 S32DS 3.6.5 中基于 AUTOSAR ECUC 的项目? 是否应首先创建一个单独的 AUTOSAR RTD 项目,然后再复制示例源文件? 在 S32DS 3.6.5 中启用 AUTOSAR ECU 配置编辑器而不是 SDK 引脚/时钟工具是否需要任何额外步骤? 如果您能就在 S32K144EVB 上成功版本此 RTD CAN 示例的正确工作流程提供任何指导,我们将不胜感激。 谢谢! Re: S32K144 AUTOSAR RTD CAN Example Build Error – Missing Port_Ci_Port_Ip_Types.h (S32DS 3.6.5) 您好, RTD CAN 演示示例只显示了内部环回测试,没有配置引脚,您需要添加引脚。你可以参考下面的指南来参考如何添加 PORT 元器件;https://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/HOWTO-Create-a-Blinking-LED-example-project-using-S32K1xx-RTD/ta-p/1471695 不确定是否有其他 S32K144 CAN 演示使用 MCAL 级驱动程序,但您可以使用其他方法,例如请参阅https://community.nxp.com/t5/S32K-Knowledge-Base/RTD600-MCAL-amp-IP-S32K3X4EVB-T172-FlexCAN-Example-Interrupt/ta-p/2142069上发布的 S32K3 演示。用法非常相似。 BR, Petr Re: S32K144 AUTOSAR RTD CAN Example Build Error – Missing Port_Ci_Port_Ip_Types.h (S32DS 3.6.5) 您好, 请参阅所附的修改后演示示例。 使用连接 PCAN 工具的 S32K144EVB-Q100 进行测试时,它可发送 10 条信息 希望对你有所帮助。 BR, Petr
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S32K148 的 SPI 占空比不是 50% 当我使用 S32K148 的 LSPI0 发送数据时,我发现 SPI 时钟波形的占空比不是 50% 而是 60%。我为 LSPI0 设置的时钟源是 4MHZ,波特率是 2MHZ,寄存器 CCR[SCKDIV] 不是奇数。为什么占空比不能达到 50%?我该如何调整?谢谢! Re: The SPI duty cycle of S32K148 is not 50% 您好, SCK 占空比不可调节,取决于 SCKDIV 和 PRESCALE 设置。如果 SCK 周期为奇数,则 SCK 周期的前半部分将比 SCK 周期的后半部分长一个周期。从寄存器值来看,结果周期为 14 个周期,因此 SCK 占空比应为 50% 。即使不是这样,从从属的角度来看,这也不应该是一个问题,因为 SPI 传输是由 CLK 边沿驱动的。 问题可能是如何使用分频器为 14 的 4MHz SPI 时钟获得 2MHz SCK。 逻辑分析仪也可能带来采样率不正确的问题。尝试提高采样率,或者最好使用示波器测量真实信号。这可能受到引脚驱动设置/能力的影响。 BR, Petr
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MCXN947 ADC FIFO配置咨询 Hi NXP,            我在MCUXpresso IDE里的配置界面,对ADC涉及的FIFO定义有些疑问,请教一下:        1>如下截图,出现FIFO0/FIFO1、Channel A/B FIFO,了解一下,他们之间具体是怎么关联的?          2>在"Conversion triggers configuration"部分,每个trigger都提供Select channel A FIFO和Select channel B FIFO;如果我对2个trigger,都采样如下工具默认配置,是否可行?          3>实际测试:ADC1的分2个独立采样通道,先使能Channel B,并用软件触发采样。                              按照理解,FIFO1是对应Channel B,默认设置为0;在Trigger部分,“Select channel B FIFO”设置为1,代表将使能该FIFO。                              利用轮询方式,调用LPADC_GetConvResult(ADC1_PERIPHERAL, &t_LpadcResultConfigStruct, 1U),并打印结果,发现实际采样的是ADC1_A0通道,不是ADC1_B0通道。                              想确认一下,是哪里出问题了?          谢谢!                            谢谢!   MCXN Re: MCXN947 ADC FIFO配置咨询 你好@jimmyli 以双单端模式运行时,两个通道同时采样和处理。 双单端(CTYPE=11B)的含义是:一次触发会同时启动 A/B 两个 SAR,产生两份独立结果;这两份结果分别由 TCTRLn[FIFO_SEL_A] / TCTRLn[FIFO_SEL_B] 路由到 FIFO0/1(即 A、B 的结果 "独立选择 FIFO")--但只有一个触发事件。你无法让同一条双单端命令里的 A 由定时器触发、B 由软件触发;触发一到,A/B 就一起采了。FIFO_SEL_A / FIFO_SEL_B select FIFO "说的是结果独立、路由可独立,不是触发可独立。   我测试了一下, fifo0和fifo1的数据是不同的。 我认为如果您的真实需求是:A 用定时器周期采样;B 用软件在某些时刻采样(两者各自独立、并不要求严格"同一时刻 "起采),那么正确做法是"两条命令 + 两个触发(单端模式)": CMD_A0 :CTYPE=00b(单端 A),由TRIG_A(硬件)触发; CTYPE=00b(单端 A),由TRIG_A(硬件)触发。触发; CMD_B0 :CTYPE=01b(单端 B),由 TRIG_B(软件) 触发。 在单端模式下,结果写入哪个 FIFO 取决于 TCTRLn[FIFO_SEL_A] 。 BR 哈利 Re: MCXN947 ADC FIFO配置咨询 Hi Harry,        感谢您的回复!        补充一下我这边的实际设计需求:ADC1需要使能2个ADC采样通道同时采样,其中通道A设置为Timer定时触发采样,通道B设置为软件触发采样。         基于上述信息及下述从MCXNx4x Reference Manual文档截图说明,我个人是理解此时ADC1工作为双单通道模式,那么此时可以分别由TCTRLn[FIFO_SEL_A]和TCTRLn[FIFO_SEL_B]指定相应的FIFO[0/1]。         基于上述信息,我才配置为之前截图内容,但实际好像对不上(Pin脚、Clock确认都是OK的)。         另外,我按照您提供的建议,修改并测试,会出现无法正常采样,应该还是哪里有问题。         还要麻烦您帮忙再确认一下。         感谢! Re: MCXN947 ADC FIFO配置咨询 Hi @jimmyli  根据您的描述以及的config tool的截图。 您是需要两个命令 两次触发。 您可以查看MCXNX4X用户手册的描述。 在“单端模式(CTYPE=00b 或 01b)”下,真正决定结果写入哪个 FIFO 的,是 FIFO_SEL_A;FIFO_SEL_B 只有在“双单端(CTYPE=11b)”时才起作用。 这点正是你刚才贴的用户手册截图里写的:FIFO_SEL_A “provides the destination for all single‑ended and differential conversions”;FIFO_SEL_B “only used in dual single‑ended mode (CTYPE=11b)”。因此,单端 B 侧(01b)时也要看 FIFO_SEL_A。 所以我认为您可以 ADC1_B0_trigger 把 A FIFO改为 1。 BR Harry Re: MCXN947 ADC FIFO配置咨询 Hi Harry,       明白了       感谢!
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信息索取 - 基于 i.MX95 的环视监控多摄像头解决方案 亲爱的恩智浦 我们正计划向客户推荐恩智浦的 i.MX95 产品,该产品主要用于环视监控项目。目前,nxp.com 上介绍的解决方案基于 i.MX8Q/6Q 平台。 如果恩智浦正在准备基于 i.MX95 的多摄像头解决方案演示,我们将非常感谢您能分享任何早期信息。这将有助于我们向客户提供最新信息,并鼓励他们在设计时考虑 i.MX95。 感谢您的支持,我们期待您的反馈。 致以最崇高的敬意, JK
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The SPI duty cycle of S32K148 is not 50% When I used the LSPI0 of the S32K148 to send data, I found that the duty cycle of the SPI clock waveform was not 50% but 60%. The clock source I set for LSPI0 is 4MHZ, the baud rate is 2MHZ, and the register CCR[SCKDIV] is not an odd number. Why can't the duty cycle reach 50%? How should I adjust it? Thank you! Re: The SPI duty cycle of S32K148 is not 50% Hi, SCK duty cycle is not adjustable and depends on SCKDIV and PRESCALE setting. If resulted If the SCK period is an odd number of cycles, then the 1st half of the SCK period will be 1 cycle longer than the 2nd half of the SCK period. From register values it seems the resulted period is 14 cycles, so SCK duty should be 50%. Even if not, from the slave point of view, this is should not be an issue since SPI transmission is driven by CLK edges. Question could be how you can get 2MHZ SCK from 4MHz SPI clock with divider by 14. The logic analyzer could also bring an issue with incorrect sampling rate. Try to increase sampling rate or better to use scope to measure real signal. This can be affected by pin driving setting/capability.  BR, Petr
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imx93 mxc-md 42800000.bus:camera: deferring cap_device registration hi linux kernel log: mxc-md 42800000.bus:camera: deferring cap_device registration I don't know why this error occurred, please help me check it together. I am using the 6.6.23 kernel,  Thanks Re: imx93 mxc-md 42800000.bus:camera: deferring cap_device registration imx9_soc_device_register can't finish init process, becase OPTEE not loaded indeed. Need to figure out why firmware didnt started in Uboot Re: imx93 mxc-md 42800000.bus:camera: deferring cap_device registration On my device Optee registered fine: [ 0.000000] OF: reserved mem: 0x0000000096000000..0x0000000097dfffff (30720 KiB) nomap non-reusable optee_core@96000000 [ 0.000000] OF: reserved mem: 0x0000000097e00000..0x0000000097ffffff (2048 KiB) nomap non-reusable optee_shm@97e00000 [ 1.540675] optee: probing for conduit method. [ 1.545155] optee: revision 4.0 (a303fc80) [ 1.545573] optee: dynamic shared memory is enabled [ 1.554907] optee: initialized driver But still efuse failed. 回复: imx93 mxc-md 42800000.bus:camera: deferring cap_device registration I have tested ap1302 camera on IMX93-11x11 evk, the result differs with the kernel versions: 6.1.36: camera works ok, and the sys path /dev/video* exist in system; 6.6.52-lts-next-ge0f9e2afd4cf: camera doesn't work, and no /dev/video* path in sys path. I have found out that the ap1302 node differs in dts, after I change back it to the earlier one 6.1.36, the camera still didn't work. could you pls share your solution of this problem, thanks in advance! Re: imx93 mxc-md 42800000.bus:camera: deferring cap_device registration HI. I've also encountered this problem, can you please tell me how you solved it, I also reported this error Re: imx93 mxc-md 42800000.bus:camera: deferring cap_device registration I may have found the problem. In my initial log.txt, HI [ 1.487391] optee: probe of firmware:optee failed with error -22 [ 1.738045] imx9_init_soc 47510000.efuse:imx93-soc: error -EINVAL: failed to register SoC device I don't know if it's due to the failure of Optee that caused the SOC registration to fail, which in turn affected the driver imx8-isi-core. c+656 line, ret=mxc_isi_stoc_match (mxc_isi, imx8_stoc) failed. I haven't found a solution yet Re: imx93 mxc-md 42800000.bus:camera: deferring cap_device registration do you mind print the sd value in the register_isi_entity of media device driver? refer to your logfile, it seems the  get_subdev_by_node successfully, if sd vaule is 0, you need trace the driver, it seems ISI couldn't be probed Re: imx93 mxc-md 42800000.bus:camera: deferring cap_device registration hi  Unfortunately, the same error still occurs. The attachment is a decompiled dts file from dtb, and it seems that there is no problem. However, imx-isi-capture did not load the driver before fsl,imx93-isi thanks! Re: imx93 mxc-md 42800000.bus:camera: deferring cap_device registration refer to your logfile, it seems that register_isi issue, then I checked your isi in the dts, it seems you didn't set it correctly, try to change this &isi_0 { status = "okay"; }; &cap_device { status = "okay"; }; try to isi node includes the cap_device, like this &isi_0 { status = "okay"; cap_device { status = "okay"; }; }; Re: imx93 mxc-md 42800000.bus:camera: deferring cap_device registration hi I am using my own motherboard, and log.txt is the complete kernel log. I don't know what caused the cap_device to fail registration. I feel that my DTS is correct. Thanks Re: imx93 mxc-md 42800000.bus:camera: deferring cap_device registration pls share more detailed information, how do you get this log? pls share whole logfile with me and tell me how to reproduce this? did you use nxp board or your own board? Re: imx93 mxc-md 42800000.bus:camera: deferring cap_device registration I solved this issue with reflashing boot image: echo 0 > /sys/class/block/mmcblk0boot0/force_ro dd if=imx-boot-ucm-imx93-sd.bin-flash_singleboot of=/dev/mmcblk0boot0
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Why is the MCUXpresso debugger trying to access address 0xdeadbeef? I have some issues with MCUXpresso when using a J-Link probe and when debugging an NXP i.MX RT1020 board. I can upload and run the code. The code executes successfully and I can ping the board's IP address so I know it works. However, some time after I run the code in the debugger, I get the error as shown in the following screenshot. The board still runs, but I am at that point unable to use the debugger. I have no breakpoints set in the debugger. screenshot: https://ibb.co/X8XHfyh Re: Why is the MCUXpresso debugger trying to access address 0xdeadbeef? I see dead bees  Re: Why is the MCUXpresso debugger trying to access address 0xdeadbeef? Hi @surfskidude  Thanks a lot for letting me know and for sharing again the link to download your project, I could download it already. Just give me some more time to check it, and I would appreciate so much your patience, our backlog is higher than usual these days. Please let me know if you have some updates, and also I will keep you informed by our findings as soon as we can test it.  Thanks a lot for your comprehension. Best Regards. Pablo Avalos. Re: Why is the MCUXpresso debugger trying to access address 0xdeadbeef? Hello Pablo, Thank you for the email. I do see my response on the support page (support.nxp.com). I'll just duplicate it here since it is public information and maybe easier for you to find. The complete ready to run project: https://realtimelogic.com/downloads/examples/LspAppMgr-RT1020.zip Project documentation: https://realtimelogic.com/downloads/bas/rt1020/ Re: Why is the MCUXpresso debugger trying to access address 0xdeadbeef? Hi Pablo, did you get a chance to test the download I provided? Now after more testing, I believe there are some issues with the lwIP driver. Re: Why is the MCUXpresso debugger trying to access address 0xdeadbeef? I inherited the project, but I believe all drivers are original and from a recent SDK. The weird thing is that I do not have issues with the built in JTAG. Re: Why is the MCUXpresso debugger trying to access address 0xdeadbeef? Hi @surfskidude  Thanks a lot for reaching our technical support. Regarding your issue, when the MCU is trapped in the 0xdeadbeef address, it is usually due to some incorrect configuration of the peripheral used and actually if you pause the debugger, you might see a HardFault sometimes or simply the debugger is lost due an incorrect flow of the program. So my question is, did you modified something on the SDK example? and also, do you have the Ethernet port connected for that example? Hope we can hit the nail on the head soon, please let me know if you have more questions or comments. Best Regards. Pablo Avalos. Re: Why is the MCUXpresso debugger trying to access address 0xdeadbeef? Additional info: The debugger goes haywire after it executes ENET_SetSMI in fsl_enet.c, after the following line: base->MSCR = mscr; mscr is 304. I get the error as shown above if I try to step after this line. The NXP provided driver is in the SDK at 1020\devices\MIMXRT1021\drivers\fsl_enet.c
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ONNX support I’m planning to use in my product I.MX8MPlus May I kindly ask for clarification. I.MX8MPlus supports using NPU or GPU for ONNX runtime? Thank you in advance. Re: ONNX support Hello @otimofie  I hope you are doing very well. Please take a look to the UG10166 (i.MX Machine Learning User's Guide) Figure 1. NXP eIQ supported compute vs. inference engines: For i.MX8MP, ONNX is supported in CPU, GPU and NPU. Best regards, Salas.
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Potential issue of the writeback check condition in Netc_Eth_Ip_SendFrame. Hello Team, There may be a potential issue with the writeback check condition in Netc_Eth_Ip_SendFrame for both the S32N55 and S32ZE platforms.  Since the writeback bit must be cleared by software, it needs to be reset before transmission. If the buffer descriptor (BD) was part of a chain transmitted previously, the writeback bit will not be set, and consequently, BD->bufConfig will not be updated this time because the condition is not met. Additionally, this condition may cause confusion for customers. Is my understanding correct, or have I missed anything? Thanks! Best regards, Tangsheng. Priority: MEDIUM RTD Source: NXP Internal Re: Potential issue of the writeback check condition in Netc_Eth_Ip_SendFrame. Hi @Tangsheng_Zhou , My understanding is that Tx BD were configured in Eth_Init includes interrupt enable bit and final frame bit enabled. BD exists in 2 formats: normal and writeback. For writeback, this means bit W was set by HW just in case: transmit return errors or extended BD stores timestamp status. Then, in Sendframe function, driver will just handle case writeback, clear this bit and set again bits final, interrupt,... before transmit a new frame. In case, bit W not set, because BD still keep as old, so driver doesn't need to do anything.  So, form my point of view, this is not an issue. Best regards, Nhi Re: Potential issue of the writeback check condition in Netc_Eth_Ip_SendFrame. While customer send a new frame, the buffconfig or extendBuffconfig depends on an old status in the Tx BD memory, instead of the real customer configuration about extend. It's amazing. If it's the 1st time to use the Tx BD, who is charge for setting this W bit, and why? Re: Potential issue of the writeback check condition in Netc_Eth_Ip_SendFrame. Hi @shuangjunzhu , Sorry, I don't understand your opinion. Can you please explain it in detail about what issue made you concern? As I said before, TX BD were initialized first at Eth_Init() in the function Netc_Eth_Ip_InitTxBD(). bit W will be cleared here for first time. Tx BD will be kept until errors were detected, then error flags were raised with bit W raised to indicate status. Or timestamp are in extended BD. For this case, driver will set up again Tx BD in the function SendFrame. If bit W not set, TxBD not change, they were kept as in the first configuration why driver has to configure them in SendFrame? Best regards, Nhi Re: Potential issue of the writeback check condition in Netc_Eth_Ip_SendFrame. 1. Since the Tx BD buffconfig W bit is a response of previous frame from NETC, the device driver should handle this W bit in Netc_Eth_Ip_CheckFrameStatus(), if you would like to keep the Tx BD to default config status likeTX BD were initialized first at Eth_Init(). Is it correct? 2. In Netc_Eth_Ip_SendFrame(), the device driver assume all the Tx BDs will use the default buffConfig and extendBuffConfig in the memory, and assume there is nobody will change the memory. If previous frame has an option like "TimestampRefReq", but current frame has no this option, who will remove it? 3. What's the purpose of this piece of code? for performance to save several cycles? for better read-able? It does not make sense for me. If we want to save cycles, how about this line of code "txBD->RESERVED_0 = (uint32)0U", we might remove it as well. Re: Potential issue of the writeback check condition in Netc_Eth_Ip_SendFrame. Hi  Thanks for your kindly answer. But still have question, actually, the "TimestampRefReq" just an example. Are you sure, for all the management frames, there will be a W bit set by NETC as the response? Or similar, the NETC_ETH_IP_TXSTART option will cause a W bit response as well? Re: Potential issue of the writeback check condition in Netc_Eth_Ip_SendFrame. Hi @shuangjunzhu , From my point of view, all of other options are always request a response, so bit W should be set. We haven't see any problem until now although I think that set up Des2 of BD in sendframe() is ok even bit W not set, as you mentioned that it shouldn't be problem to save performance with this but still need the reason for changing code. So, please let me know if you detect the problem. Best regards, Nhi Re: Potential issue of the writeback check condition in Netc_Eth_Ip_SendFrame. Hi @shuangjunzhu , I understand that TxBD will be configured in the function SendFrame() includes fields as its structure before transmitting a frame. except Des2 that contains bit F, W. Des2 will be in 2 cases: 1 - normal BD that bit W not set. 2 - writeback BD that bit W set.  As RM mentioned that bit W just set in case requested offload or error. So, in case bit W not set, TX BD not change. 1. Set fields of Tx BD were done in the function SendFrame(), so in the function CheckFrameStatus(), driver just returns errors, status, not configure BD . 2. If previous frame has TimestampRefReq = 1, then BD status will returns with bit W set. So, that BD will be configured Des 2(F + W) in the function SendFrame() although current frame without TimestampRefReq . For example: This is TxBD after configured in SendFrame(): After sending frame, BD returns status: 3. I mentioned this above. Best regards, Nhi Re: Potential issue of the writeback check condition in Netc_Eth_Ip_SendFrame. Hi @shuangjunzhu , This is case NETC_ETH_IP_TXSTART, I saw bit W still set. Best regards, Nhi Re: Potential issue of the writeback check condition in Netc_Eth_Ip_SendFrame. Hi Nhi_Nguyen, We did the experiment, if previous frame has the option NETC_ETH_IP_TXSTART. There will be NO W bit response from NETC hardware. The current frame with this Tx BD will has the "dirty" option NETC_ETH_IP_TXSTART from previous transmission action. It does not make sense. Please help to review. Thanks, Re: Potential issue of the writeback check condition in Netc_Eth_Ip_SendFrame. Hi, According to your capture, something wrong with the status 0x60 and W bit is set. So the W bit is for error response, not for NETC_ETH_IP_TXSTART. Thanks, Re: Potential issue of the writeback check condition in Netc_Eth_Ip_SendFrame. Hi @shuangjunzhu , Yes, you're right. Bit W was set because error reported. I tested again and I agree that Des2 in Tx BD should be configured even bit W not set in the function SendFrame(). I created the ticket ARTDCC1-583 for this. Thanks & Best regards, Nhi
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