When I used the LSPI0 of the S32K148 to send data, I found that the duty cycle of the SPI clock waveform was not 50% but 60%. The clock source I set for LSPI0 is 4MHZ, the baud rate is 2MHZ, and the register CCR[SCKDIV] is not an odd number. Why can't the duty cycle reach 50%? How should I adjust it? Thank you!
Hi,
SCK duty cycle is not adjustable and depends on SCKDIV and PRESCALE setting. If resulted If the SCK period is an odd number of cycles, then the 1st half of the SCK period will be 1 cycle longer than the 2nd half of the SCK period. From register values it seems the resulted period is 14 cycles, so SCK duty should be 50%. Even if not, from the slave point of view, this is should not be an issue since SPI transmission is driven by CLK edges.
Question could be how you can get 2MHZ SCK from 4MHz SPI clock with divider by 14.
The logic analyzer could also bring an issue with incorrect sampling rate. Try to increase sampling rate or better to use scope to measure real signal. This can be affected by pin driving setting/capability.
BR, Petr