Unable to access the UART port using A55 core of imx93 board (Digi coreconnect 93) Dear NXP Support Team, I want to attach a sensor in the UART port of the board and access via A55 core. I have tried below things but neither of them worked. Total available port from UART1 to UART8 – 8 Nos The UART4 port as a Xbee interface is available like ttyXBee, so I also attempted to transfer data using c code and directly using command line but none of them where worked. Followed the URAT instruction from this website, and I am getting port ttyLP3, ttyLP5 and ttyLP6 port. The port ttyLP3 and ttyLP5 have no pinout on the board. The ttyLP6 is connected with the console port which is ttyACM0 (UART to USB), so we cannot use it. Tried to configure UART7 (Mikroe interface) but the tty node is not created, maybe it missed configuration from dts side. (I am unsure about it) The UART1 is connected to the Bluetooth chip, so it cannot be accessible. No details found from UART2 and UART8.   Can you guide me how to access the UART port using A55 core of the board and C language programming? Re: Unable to access the UART port using A55 core of imx93 board (Digi coreconnect 93) Hi @rk4! Your UART7 is configured as a rs485 in file ccimx93-dvk.dts &lpuart7 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart7>; linux,rs485-enabled-at-boot-time; digi,rts-gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; /delete-property/dmas; /delete-property/dma-names; status = "okay"; }; only delete the line linux,rs485-enabled-at-boot-time; and the uart7 should be listed in the device folder with the name ttyLP6 Best Regards! Chavira Re: Unable to access the UART port using A55 core of imx93 board (Digi coreconnect 93) Hello @Chavira ,  Please find attached dts file that I am using. Re: Unable to access the UART port using A55 core of imx93 board (Digi coreconnect 93) HI @rk4! Please share your device tree file. Re: Unable to access the UART port using A55 core of imx93 board (Digi coreconnect 93) Dear @Chavira ,  Thanks for prompt response. Could you tell me how to create a ttynode for UART7 (MIKROE interface) in A55 core? OR if its already available in it, can you tell me what is the name of it? Re: Unable to access the UART port using A55 core of imx93 board (Digi coreconnect 93) HI @rk4! Thank you for contacting NXP Support! I don´t have access to the device tree of that board since is not an NXP board. I can help you to analyze the device tree if you can share the device tree with me. Unfortunately we don´t have any guide of how to use UART ports in Linux, but you can check some guides in internet like this guide. For Further support please contact to digi support. Best Regards! Chavira

S32G2 load dtb I got dts both in ATF and in kernal.When the board boots,Which dtb it will actually use?Or it will load both? Thank u. Re: S32G2 load dtb Hi, Both DTB/DTS will be used. When booting, TF-A/uboot will use the TF-A DTS/DTB, when uboot passes the control to the kernel, the kernel will use its own DTB/DTS. There is no conflict between both. Both DTB/DTS should be configured accordingly, if not when uboot passes control to the kernel, devices might not be available to the kernel itself. Please, let us know. Re: S32G2 load dtb Sorry，I can not understand well and could you describe it more detailed.I can find the same device in DTS both in ATF and kernal. Do they conflict with each other? Re: S32G2 load dtb Hi, Both DTB's will be used at the end, but the one that is available under the root partition of the SD card should be the Kernel one. Please, let us know.

iMxRT1040 Boot FlexSPI and DQS Hi, I have a problem with my configuration to fit all the required peripherals. I plan to use external Quad SPI NOR Flash with no Strobe. (as the EVK). I need to use : CCM.CLKO1 [J4] and CCM.CLKO2 [J1]. I need one FlexSPI (for ext Flash) and one uSDHC for SdCard. The 2 clocks outputs prevent me from using uSDHC1. Then, I have to use uSDHC2 for the SdCard that has the CMD signal on [M4]. The [M4] pin is shared with FLEXSPI.A_DQS. What's the best way to use SdCard and boot on FlexSPI ? Can I boot easily on FLEXSPI2.A ? or should I use FlexSPI1.A with internal loopback Strobe ? Thanks in advance, Re: iMxRT1040 Boot FlexSPI and DQS Hi @jfz_arturia , Thank you for your interest in the NXP MIMXRT product, I would  like to provide service for you. Question: Can I boot easily on FLEXSPI2.A ? Answer: No, You can't.  In IMXRT1040RM reference manual, You can see that NOR Flash can only be  boot on FlexSPI1 Question: or should I use FlexSPI1.A with internal loopback Strobe ? Answer:  You can use this mode, but the max Frequency of operation is limited to 60MHz if you use this mode . https://www.nxp.com/webapp/Download?colCode=IMXRT1040RM https://www.nxp.com/docs/en/data-sheet/IMXRT1040CEC.pdf Wish it helps you. If you still have question about it, please kindly let me know. Wish you a nice day! Best Regards MayLiu

I2C MPC5478G Hi, I want to communicate with an amplifier using the MPC5748G. I'm using the i2c_transfer_mpc5748g sample code from the Power Architecture. The amplifier's address is 0x70. What modifications do I need to make to achieve this? also i2c driver sends adress->data  but i want to make it adress of amplifier(adress) ->amplifier register(subadress)-> data. Re: I2C MPC5478G Hi, the Slave device address is set within Component inspector and it is automatically sent as first byte after START is issued. The Slave’s register/memory address, must be stored into first byte(s) of the “txBuffer” depending on address size.   So assuming 16bit address is used and you want to write 8 bytes (1,2,3,..,8) to Slave address 0x000C, then prepare txBuffer as   txBuffer = {0x00, 0x0C, 1, 2, 3, 4, 5, 6, 7, 8};   and use I2C_DRV_MasterSendDataBlocking(instance, txBuffer, 10, true, timeout);   If you want to read 8 bytes from the same memory address then use this   I2C_DRV_MasterSendDataBlocking(instance, txBuffer, 2, false, timeout); // just memory/register address will be sent after Slave address so total 3 bytes, STOP is not generated I2C_DRV_MasterReceiveDataBlocking(instance, rxBuffer, 8, true, timeout); // Repeat Start is issued following Slave address and waiting reading for 8 bytes Hope it helps. BR, Petr

i.mx8MPの最大メモリ密度 こんにちは、NXPチームの皆様、 サポートされているLPDDR4メモリの最大密度 i.MX8MPはどれくらいですか？ ありがとうございます Re: i.mx8MPの最大メモリ密度 ダニエルさん、こんにちは。 この情報はとても役に立ちます。 よろしく、サイモン Re: i.mx8MPの最大メモリ密度 i.MX8MPのメモリ密度はダイあたり32 Gb（ギガビット）で、これはダイあたり4 GB（ギガバイト）に相当します。 答えが分かるといいですね。

If develop something using GoldVIP-1.6.0, cannot use LLCE CAN. I am using GoldVIP-S32G2-v1.6.0 on S32G2 due to some circumstances and I am having a problem. I referred to the User Manual.pdf file of GoldVIP-S32G2 v1.6.0 and proceeded as follows. 1. I installed Goldvip- S32G2 v1.6.0 and EBTresos ACG8.8.7, S32DS 3.4. 2. Follow the steps in Figure 13.4 Building the M7 Application below.   2-1. Generated the default configuration information using EBTresos.   2-2. I built using Util of GoldVIP-S32G2-v1.6.0 and created an Elf file.   2-3. create goldvip-gateway.bin file using objcopy in S32DS Build_tools folder. 3. create an SDcard using fsl-image-goldvip-s32g274ardb2.sdcard and replace only the goldvip-gateway.bin file in the SDcard to write to the board. 4. I checked using Trace32 Debug and found that it booted well and LLCE_CAN0 and LLCE_CAN1 were set to use. 5. The problem was that even though I sent LLCE_CAN0 and LLCE_CAN1 using CANoe, CAN Interrupt did not work, so I could not check the can data coming in. I used GoldVIP-S32G2-v1.0.0 two years ago and experienced that the CanIf_RxIndication function shown in the screen below is called when CANoe successfully sends CAN data in the same way as above. Currently, I confirmed that the CanIf_RxIndication function is not called in the same way, and after debugging, I realized that receiving CAN data does not cause an interrupt. I would be grateful if you could let me know if I missed something and what else I can do and if you need more information to answer. S32G-VNP-RDB2 AUTOSAR GOLDVIP 1.6 Re: If develop something using GoldVIP-1.6.0, cannot use LLCE CAN. Thank you for your continued response. I'm resolved.  When I disable CanMultiplexedTransmission and change both Filter and Mask to 0, I get an interrupt. It looks like filter and mask were preventing the data from coming in. Re: If develop something using GoldVIP-1.6.0, cannot use LLCE CAN. Hi, We might be misunderstanding the overall inquiry. If so we do apologize. For the following comment: "After writing, a CAN data is sent via CANoe, but CANoe shows that the transmission was successful, but no RX interrupt occurs in Trace32." We understand that you are able to receive CAN frames under the S32G2, is this correct? This might seem to be related to Trace32 rather than S32G2 if you are able to receive CAN Frames. Can you replicate the examples available under the BSP User Manual?  Please, let us know. Re: If develop something using GoldVIP-1.6.0, cannot use LLCE CAN. Hello Thank you for the reply. I was refer to GoldVIP-S32G2-1.6.0-User-Manual.pdf. I have attached the file. I didn't use anything related to the Linux BSP.  I used the fsl-image-goldvip-s32g274ardb2.sdcard file provided by NXP to create the SDcard. and then I created the goldvip-gateway.bin file for Firmware and then replaced the goldvip-gateway.bin on the SDcard as described in the question above. After writing, a CAN data is sent via CANoe, but CANoe shows that the transmission was successful, but no RX interrupt occurs in Trace32. For reference, when I installed and developed the RTD and LLCE Driver using S32DesignStudio, I found that CAN Rx interrupts were generated. Re: If develop something using GoldVIP-1.6.0, cannot use LLCE CAN. Hi, We apologize for the delay. Can you help us share the respective logs of your system? Also, were you able to run the available examples for LLCE CAN under the BSP User Manual?  Overall, we have not seen any problems with LLCE CAN not receiving information, for which seems to be a configuration problem.  Please, let us know. Re: If develop something using GoldVIP-1.6.0, cannot use LLCE CAN. There is a typo in the above post. The version of GoldVIP I've been using is v1.1.0, not v1.0.0. I used GoldVIP-S32G2-v1.0.0 two years ago -> I used GoldVIP-S32G2-v1.1.0 two years ago

How to flush the uart FIFO with CTS enabled for S32K146 Hi support team, We're using UART Tx FIFO function with CTS feature enabled. After having checked with the errata file of S32K146, we find that the ERR051629 is related to our case. My understanding of this issue is that if the CTS pin is changed to low during the tx FIFO is flushing with CTS feature enabled, the transmit complete bit will not be set, the workaround is to clear the MODIR[TXCTSE] bit before setting FIFO[TXFLUSH] bit to 1 if the CTS feature is enabled, and then set the MODIR[TXCTSE] bit again, such as the following code changes based on the NXP RTD code: /** * @brief : Flush Tx Buffer * * This function causes all data that is stored in the transmit FIFO/buffer to be flushed. * * * @Param Base LPUART Base pointer */ static inline void Lpuart_Uart_Ip_FlushTxBuffer(LPUART_Type * Base) { Base->MODIR &= 0xFFFFFFFEu; /*Clear (MODIR[TXCTSE]) bit*/ Base->FIFO |= 0x00008000u; /*reset the transmit FIFO (FIFO[TXFLUSH] = 0b1)*/ Base->MODIR |= 0x00000001u; /*Set (MODIR[TXCTSE]) bit*/ } Is my understanding correct? If it's not correct, how should I handle this problem?  Re: How to flush the uart FIFO with CTS enabled for S32K146 HI @snowy, CTS_B is asserted when the input voltage level goes LOW. The CTS_B pin must assert for longer than one bit period to guarantee that a new transmission is started when the transmitter is idle. The transmitter checks the state of the CTS signal each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the TXD signal remains in the mark state and transmission is delayed until CTS is asserted. So, it will not stop transmitting, it will send the data present in the FIFO. Regards, Daniel Re: How to flush the uart FIFO with CTS enabled for S32K146 Hi Daniel, Thank you very much for your reply. Could you please help check the following question? If the CTS pin is changed to low during writing data into tx FIFO, will the data stop transmitting until the CTS pin be changed back to high? Or the tx will be abort directly with data lost? Re: How to flush the uart FIFO with CTS enabled for S32K146 Helle @snowy, Yes, this is correct. If you have any specific question, let me know, BR, Daniel

Availability of board design files for MIMXRT1180-EVK Hello, Would it be possible to share the board design files for the MIMXRT1180-EVK? There is a link in the user manual (UM12021) which unfortunatly does not work (The collateral "MIMXRT1180-EVK-DESIGNFILES" does not exist). Fixing the link would of course also help me. Thank you, Kind regards, Jasper Re: Availability of board design files for MIMXRT1180-EVK Hello, the documentation is not available yet on the page until the launch date will be confirmed. I suggest contact your sales representative. Best regards, Pavel

S32K314 lwip tcp/ip multiple definition issue Hello, I am currently applying the lwIP TCP/IP stack to the S32K314 product and encountered a "multiple definition" error, so I am leaving a question. When I add the TCP/IP stack to the peripherals and build, the following error occurs: However, when I remove the multiple definition issue using linker options, the build succeeds as follows: Using linker options to bypass the multiple definition issue does not seem like a proper solution, so I want to address the root cause of the problem. Thank you. Re: S32K314 lwip tcp/ip multiple definition issue Thank you! Re: S32K314 lwip tcp/ip multiple definition issue Hi @malove  In the actual example, fsdata.c is not included for the compilation. only fs.c included. You can exclude the fsdata.c from build to avoid fsdata.o generation. which will help you to solve the problem without modifying the linker options. Thanks, Sathish. Re: S32K314 lwip tcp/ip multiple definition issue Thank you @PavelL  Re: S32K314 lwip tcp/ip multiple definition issue Hello @malove , I see your point now. Please check this: Re: linker error:multiple definition of `_start' - NXP Community Solved: Multiple definitions of functions 'isprintf' etc - NXP Community   Link Order: Using Multiple Definitions with ARM GNU Linker and Eclipse. Best regards, Pavel Re: S32K314 lwip tcp/ip multiple definition issue Hello @PavelL  What I want to clarify is that I am not trying to have two static IP addresses. Instead, I am trying to resolve the issue where certain elements in the fsdata.c source file are being defined multiple times. However, this file is not something I wrote myself; it is part of the TCP/IP stack that I am using as is. I am not sure how to modify or resolve this issue. Re: S32K314 lwip tcp/ip multiple definition issue Hello @malove , what is your goal? To have two static IP addresses? As far as I know, dual stack IPv4 and IPv6 should work on lwip. However, I did a web search but I didn't find a solution - all questions like this one mapping multiple * IP addresses to one Ethernet interface (LWIP) - NXP Community stayed unanswered or the solution didn't work. So, it looks like not feasible. As David already replied to here S32K3 Lwip iperf test issue - NXP Community, LWIP is an open source and we do not have resources to support. Best regards, Pavel

If its normal behavior 88W8997 2.4G STA bgn mode can only get ~150 Mbps THP in shielding room. platform (Host CPU): i.mx8mm OS: Linux 5.15.71_2.2.1 HW: i.mx8mm customer board + WiFi module: AW-CM276MA-PUR (M.2) BSP version: Linux 5.15.71_2.2.1 Driver version and Wi-Fi and Bluetooth/Bluetooth LE Firmware version: PCIE8997--16.92.21.p55.3-MM5X16366.p5-GPL-(FP92) AP: ASUS and MSI AP Router in Shielding room Customer test 2.4G bgn mode 40MHz THP iperf test. Test 1: Default settings, only can get ~150Mbps Test 2: if set script before iperf test mlanutl mlan0 httxcfg 0x07F mlanutl mlan0 htcapinfo 0x21C20000 THP can reach ~240Mbps -> Customer has questions on Test 1. if its normal behavior? Note: there is no STA bgn mode 40MHz speed result reference data in RN. @Christine_Li  Please help to clarify. Re: If its normal behavior 88W8997 2.4G STA bgn mode can only get ~150 Mbps THP in shielding room. Hi, @yao_feng  Please see your email, I have sent my reply through SFDC's email. Best regards, Christine. Re: If its normal behavior 88W8997 2.4G STA bgn mode can only get ~150 Mbps THP in shielding room. Hi， @yao_feng  I will check it and reply you ASAP. Best regards, Christine.

EmiOSチャネルPWM出力を無効にする方法 こんにちは、EMIOSの特定のチャネルでPWM出力を無効にしたいです。これは関数を通じて実現できますか?その方法を教えてください。 日時:エミオスチャネルのPWM出力を無効にする方法 こんにちは@fengba_360  レジスタに書き込むことでそれを達成することは可能ですか?はい その場合、具体的なプランを教えてください。 主に EMIOS チャネルをディセーブルにするには、チャネルの制御レジスタ 2 とストップ クロックをクリアし、チャネルの制御レジスタをクリアし、An レジスタと Bn レジスタをクリアする必要があります (S32K3xx リファレンス マニュアル、Rev. 8 のセクション 63.8.6 を参照)。追加の手順がある可能性がありますが、一部のチャネル構成で異なります(手順についてはEmios_Pwm_Ip_DeInitChannel()関数で詳しく説明します)。 日時:エミオスチャネルのPWM出力を無効にする方法 レジスタに書き込むことでそれを達成することは可能ですか?その場合、具体的なプランを教えてください。 感謝！

如何禁用 emios 通道 pwm 输出 你好，我想禁用EMIOS特定通道的PWM输出。我可以通过函数实现这个吗？你能告诉我怎么做吗？ 回复：如何禁用 emios 通道 pwm 输出 嗨@fengba_360 是否可以通过写入寄存器来实现？是的 如果有的话，能告诉我具体的计划吗？主要是为了禁用EMIOS通道，您必须清除控制寄存器2并停止通道时钟，清除通道的控制寄存器并清除An和Bn寄存器（参考S32K3xx参考手册第63.8.6节，修订版8）。可能还有其他步骤，但取决于某些通道配置（步骤在 Emios_Pwm_Ip_DeInitChannel() 函数中有详细说明）。 回复：如何禁用 emios 通道 pwm 输出 是否可以通过写入寄存器来实现？如果有的话，能告诉我具体的计划吗？ 谢谢！

S32K344 Lock-step kernel HI, The S32K344 can be used with single-core, multi-core, or Cortex-M7 lock-step cores. I have learned that the highest level of ASIL B/D compliance can be achieved using lock-step nuclei. What do I need to do to be able to use the lockstep core ability Look forward to reply Re: S32K344 Lock-step kernel Hello, I need to verify. What do I need to do I do not understand. What do you need to verify? It is HW feature and once the Lockstep is enabled is in active all the time. If there is and issue in redundancy the FCCU will report fault. There is nothing you can verify. No user access to checker core is possible. there is just no interface. best regards, Peter Re: S32K344 Lock-step kernel HI, Thank you very much for your reply I see that the lock core of the S32K344 is enabled. As far as I know, both cores run the same program to keep them safe after the lockstep core is enabled. I need to verify. What do I need to do Re: S32K344 Lock-step kernel Hello, All information are available in reference manual. There is basically nothing to know as it is HW feature. You can learn more for example from this article: Best regards, Peter Re: S32K344 Lock-step kernel HI， Thank you very much， Can you share more information about S32K344 lockstep? I want to know more about the function of S32K344 lockstep Looking forward to your reply Re: S32K344 Lock-step kernel Hello, An example code using C40 IP driver to write in UTEST memory, please find it in the attachment. It writes 8 bytes with 0xAA in a free location after 0x1B001B00 address. So change the code accordingly to write lockstep_en in UTEST_Misc on first free location in DCF user space. Please be sure MPU is not protecting UTEST memory in your code. Best regards, Peter Re: S32K344 Lock-step kernel Thank you very much for your reply， Forgive me for not understanding your reply Do you have a sample program for my reference？ Re: S32K344 Lock-step kernel Hello, You need to simply switch the device into lock step mode via DCM records. In S32K3xx_DCF_clent excel sheet attached to the reference manual you can see the All you need to do is to program DCF client UTEST_MISC to UTEST memory with bit LOCKSTEP_EN set to 1. For details please refer to reference manual : 21.3 UTest NVM sector You will do the write to DCF user space area of UTEST: Best regards, Peter

MIMXRT1061CVL5B Queries Hello team, We had few queries regarding MIMXRT1061CVL5B: 1. Can we use standard SPI instead of Quad SPI for interfacing NAND Flash? 2. Is there any max capacity limit for external Flash? 3. If we are using same supply for SNVS and main domain, can only main domain be turned off such that we can achieve low sleep/standby current? Or we need to provide separate supplies for both rails? 4. Can the MCU boot from external NAND Flash? Please share details about the booting process. i.MXRT 106x Re: MIMXRT1061CVL5B Queries Hello Omar, Thanks for the feedback. Re: MIMXRT1061CVL5B Queries Any pin capable of interrupt can be used as wake-up source from low power modes different from SNVS mode. Re: MIMXRT1061CVL5B Queries Hello Omar, Thanks for the feedback. I kindly request you to let me know which section of Datasheet or RM has to be referred to know about how many pins are wake-up capable in Suspend Mode. Re: MIMXRT1061CVL5B Queries Hello, I hope you are well. 1. If you plan to use the NAND flash as booting device then it is not possible, for this FlexSPI interface is used. Standard SPI can be used for data but performance will be limited to LPSPI. 2. It is limited to the available addressing space of FlexSPI on the system memory map. 3. If SNVS is also supplied by the main domain then you will be limited when entering on SNVS low power mode only. 4. Yes, it can boot from NAND Flash but it will not support XIP, please refer to chapter 9.6.2 for more details for booting. 5. Yes, that one pin is only limited to wake the device from SNVS mode but other GPIO can be used as wakeup on other power modes.  Best regards, Omar Re: MIMXRT1061CVL5B Queries 5. Can we have more wake-up pins in any other version which has similar features as this, as MIMXRT1061CVL5B has only 1 wake-up capable pin.

Can you provide the FS26 datasheet? Hi, Can you provide the FS26 datasheet?

PDB Interrupt in S32K144 how to enable How to enable the interrupt in PDB module of S32K144 MCU via Autosar RTD of 2108 Re: PDB Interrupt in S32K144 how to enable Hi, Thank you so much for your interest in our products and for using our community. There is no PDB example with autosar mcal, but you could refer to the following community thread: https://community.nxp.com/t5/S32K/ADC-project-using-MCAL/td-p/1616331 Hope it helps you. Have a nice day! Re: PDB Interrupt in S32K144 how to enable Also, in Channel Configuration. I cant select channel Index value of 0 for anothe channel. So how i am supposed multiple channels via PDB for ADC?

NTAG 424 Tamper encryption Hi, need help with NTAG424 TT: enabling tamper function with key 0 (or 1,2,3,4 doesn't care) using SetConfiguration option 07 i get 9100 as response so seems everyting ok. But in the NDEF message the mirroring of TT is always in clear as the key remains at E as the default value. I tried with my Python app and with TagExplore, result is the same. Any hint? Mario Re: NTAG 424 Tamper encryption Im having the same problem! Can you help me? How did you solve it?? Re: NTAG 424 Tamper encryption Thanks Daniel, with several try and fix i managed to have the TTStatus encrypted in NDEF. Mario Re: NTAG 424 Tamper encryption Thanks Daniel, reading better the datasheet, TTStatuskey is not used to encrypt the tamper status in NDEF but as authentication to issue the GetTTStatus command. Unfortunately i dont' find how to encrypt TTStatus in NDEF: i red on AN12196 that is possible using the EncData but don't know how. Moreover fig. 3 and 4 at page 9 show the encryption of TTStatus OR Static data, i'd like to have both if possible Thanks, Mario Re: NTAG 424 Tamper encryption Hi  could you please let me know your detail steps, so I can reproduce your issue on my side with RFIDDiscover? Regards Daniel

Hardware reset related to spi5 Hi community,      Board: S32G399AAAVUC      Software:bsp40      I encountered a strange problem when i use spi5 in Mcore and disabled spi5 node in device tree of Acore . A hardware reset occurred after I used shutdown command and shutdown completed. I deleted spi5 node in device tree of Acore to solve the problem and it didn't happen again. I want to know what could have caused this issue, especially since this node is already disabled. Why do I have to delete it? S32G3  Re: Hardware reset related to spi5 Hello, @yan4  You are welcome Glad to hear that the issue is solved BR Chenyin Re: Hardware reset related to spi5 Hi, @chenyin_h Thanks a lot for your notification, I find a higher level device tree set its status to okay. Sincerely appreciate. BR yan Re: Hardware reset related to spi5 Hi, @yan4  Would you please double confirm that there is not any other &spi5 {} node that existed in other dtsi/dts file from your custom board? which may change the default status that set from s32cc.dtsi? Thanks BR Chenyin Re: Hardware reset related to spi5 Hi, @yan4  Thanks for sharing the findings,  seems other part indeed did not take care of the status node. let me check if it is specific issue that caused by BSP or upstream. BR Chenyin Re: Hardware reset related to spi5 Hi,@chenyin_h     I find out that when device tree node is disabled, spi5 driver is not installed but its interrupt exists in /proc/interrupts. It seems that GIC automatically create the interrupt.     The board im working with is a custom board but it only changes storage medium, so i won't assume that this issue is caused by customization. The device tree is from kernel, arch/arm64/boot/dts/freescale/s32cc.dtsi. Re: Hardware reset related to spi5 Hello, @yan4  Thanks for your post. From my understanding, there would be no differences for the two settings you made, maybe some code do not check whether a node is disabled, which may be the reason for the issues. I assume that you are working with a custom board? the dts you mentioned is from TFA or kernel? BR Chenyin

LPCXpresso860 SPI Hi.I have an SPI issue, may I know how to handle it? The official routine spi_transfer_rma_stlave calls the EXAMPLE_MasterStartDMATransfer() function twice in a row in the main function. The captured SPI waveform shows that the second transfer will raise the CS for each data. We need to send data for the second time, and only raise CS after the data is sent. It's not like raising CS every time we send data LPC800 Re: LPCXpresso860 SPI Hi, If you want to call the function multiple times, you have to poll if the predefined number of data has been transferred, after the DMA transfer completed, then you can call again. int main(void) { /* Initialize the boards */ /* Attach main clock to USART0 (debug console) */ CLOCK_Select(kUART0_Clk_From_MainClk);   BOARD_InitBootPins(); BOARD_BootClockFRO48M(); BOARD_InitDebugConsole();   /* Attach main clock to SPI0. */ CLOCK_Select(kSPI0_Clk_From_MainClk);   PRINTF("This is SPI dma transfer master example!\n\r"); PRINTF("To make sure the transfer work successfully, please start the slave board first!\n\r");   /* Initialize the SPI master with configuration. */ EXAMPLE_SPIMasterInit();   /* Set up DMA configuration. */ EXAMPLE_MasterDMASetup();   /* Start transfer with slave board. */ loop: __asm("nop"); EXAMPLE_MasterStartDMATransfer(); while(masterTxFinished) {} masterTxFinished=false; goto loop; /* Check the received data. */ EXAMPLE_TransferDataCheck();   /* De-initialize the DMA. */ DMA_Deinit(EXAMPLE_SPI_MASTER_DMA_BASEADDR);   /* De-initialize the SPI. */ SPI_Deinit(EXAMPLE_SPI_MASTER);   while (1) { } }   Hope it can help you BR XiangJun Rong Re: LPCXpresso860 SPI yes,demo is called once.  But. I need to modify this demo by calling this function multiple times. How can I avoid a second call where the master sends a data and then raises the CS value? For example. I need to send 8 bytes of data, and I hope to send all 8 bytes of data before raising the CS. The current practice is to go to the initial SPI（EXAMPLE-SPIMasterInit()), before call this function;... It shouldn't be used that way, right? Re: LPCXpresso860 SPI Hi, As the following screenshot, EXAMPLE_MasterStartDMATransfer(); is called only once.   BR XiangJun Rong Re: LPCXpresso860 SPI I don't know why I called this function twice. The first time I called this function to send data, CS was pulled down during the entire data transmission process. The second time I called it, CS was indeed pulled up for each data transmission. Re: LPCXpresso860 SPI Hi, As you know that the SPI is Full Duplex protocol, the transmitter and receiver work synchronously, the spi uses two DMA channels, one is for receiver, another is for transmitter Hope it can help you BR XiangJun Rong Re: LPCXpresso860 SPI Is there any result yet? Re: LPCXpresso860 SPI Hi, Can you send us the project so that we can know the code context? BR Xiangjun Rong

Changes to the p_flash of the S32K312 may cause the program to run erratically. Hi,nxp 1.By modifying the linker_flash_s32k312.ld file, the starting address of p_flash was changed from 0x00400000 to 0x00440200, resulting in the program malfunctioning, as shown in the attached image. The code is included in the attachment. 2.The expected outcome is that the program does not feed the watchdog and should restart from the beginning, rather than malfunctioning. That's all, thank you. Re: Changes to the p_flash of the S32K312 may cause the program to run erratically. Hi, Erase the entire chip and reload the program. Thanks Re: Changes to the p_flash of the S32K312 may cause the program to run erratically. I modified the original project by changing the starting address of int_pflash to 0x00500000 in the linker_flash_s32k312.ld file, but the program still runs incorrectly. Am I misunderstanding something, or is there another area that I haven't changed? 1)linker_flash_s32k312.ld->MEMORY 2)Schematic of program malfunction Re: Changes to the p_flash of the S32K312 may cause the program to run erratically. You can place it at 0x50_0000, which is a valid IVT address and it is in the next block, so it can be programmed by the bootloader in the 0x40_0000 block. Regarding the HSE_FW, please create a new thread. Thank you, BR, Daniel Re: Changes to the p_flash of the S32K312 may cause the program to run erratically. Hi,danielmartnek 1.I understand that this project should be flashed by a bootloader, right? Reply：Yes，There are other matters to pay attention to. 2.But if you flash the project directly (DM181S_S32K312_BOOT.elf), the SBAF then searches for the first valid IVT starting from the lowest address at 0x00400000. Reply：According to your intention, when debugging the app project online without the bootloader, the starting address of int_pflash still needs to be set to 0x00400000. 3.Additionally, if we enable the HSE firmware later on, how should we debug the app project that does not include the bootloader, and how do we allocate memory? Re: Changes to the p_flash of the S32K312 may cause the program to run erratically. Hi @victory, I understand that this project should be flashed by a bootloader, right? But if you flash the project directly (DM181S_S32K312_BOOT.elf), the SBAF then searches for the first valid IVT starting from the lowest address at 0x00400000. Regards, Daniel