Recommended JTAG IMX8MPlus EVK Hello, Just received my iMX8MPlus EVK and I was wondering what is the recommended JTAG proble that allows me low level board bring up.  For example DDR4 setup, and loading U-boot and Fit Image sirectly into DDR. Thank you. Re: Recommended JTAG IMX8MPlus EVK Hello, We suggest Segger JTAG for debug and Download the images to you board. https://www.segger.com/supported-devices/nxp/i-mx-8m-plus regards

How to use GUI Guider to generate bin file fonts? Hello, may I ask if you could help me: In GUI Guider,I found that only fonts can be generated as C files,Can you add an option to generate bin file fonts?  At present, BIN files can be generated on the LVGL official website, but when ported to the project generated by GUI Guider, there may be inconsistent font height display issues,May I ask if there is a solution. I hope to add a tool for generating bin file fonts in the next version! Thanks! Re: How to use GUI Guider to generate bin file fonts? Thanks for your answer. If this feature is implemented in future versions, I will be able to store the fonts binary like images binary in XIP FLASH and not have to update the binary every time when updating software code, which will greatly save program update time. Re: How to use GUI Guider to generate bin file fonts? Hi @White1, This is a great suggestion. I will share this idea internally with the GUI Guider team. In the end, it is up to them to see if this feature is worth implementing on future releases of GUI Guider, but I believe it would be a great addition to the tool! Thanks for your suggestions. BR, Edwin.

S32K312 sleep wakeup Background information I am currently using S32k312 to develop sleep and wake-up functions. I have the following questions. Please ask for advice; 1. I use Normal Wakeup instead of Fast Standby. Can I store the wakeup source in StandbyRam in Normal wakeup mode? I cannot read the valid wakeup source from the WISR register at present. 2. I observed through an oscilloscope that after receiving the wake-up source in the sleep state, K3 first resets and then enters the Icu interrupt. I want to know whether the wake-up is reset first and then enters the Icu interrupt or first enters the Icu interrupt and then reset; 3. I only triggered the level edge interrupt wake-up once after sleep. After waking up, the value in the WISR register shows that all my interrupts configured with the Icu wake-up function were triggered once. Therefore, I doubt whether there are two wake-up sources AB. After waking up the MCU through method A, WISR will record both wake-up events AB at the same time. Please help me solve this problem. Re: S32K312 sleep wakeup Yes, as you said, my program is also designed in this way. For the same wake-up source, for example, I use CAN wake-up. If I only send a wake-up message once, my program will wake up and then go back to sleep. However, when I send two or three wake-up messages, the software can recognize the valid wake-up source and maintain wake-up. Why is this? Thank you. Re: S32K312 sleep wakeup 1. If my software detects a valid wake-up source, it will maintain a wake-up state. In this case, if I only trigger a wake-up event once after the MCU goes to sleep, the MCU will only wake up and then quickly go to sleep again. It is believed that the valid wake-up source is not recognized. If the MCU is triggered two or three times after sleep, it can recognize the valid wake-up source and maintain wake-up. Therefore, I think that on the K3 platform, only triggering a wake-up event once can only wake up and reset the MCU. If there is no second or third wake-up event, the MCU will immediately go to sleep again after resetting. Is my conclusion correct? Thank you

LCD distortion sometimes after reboot on imx6 custom board I have a custom imx6 board and using MI0350B4T_5CL LCD (240*320).  My problem is sometimes after reboot the LCD doesnt work properly. If I store the fb0 as a PNG I can see the picture is true but that picture is not shown correctly on the screen. There is a distortion on the screen, most pixels are white with some black lines. It doesnt work anymore unless I reboot the system again. And it could happen again after reboot. I should say most of the times after reboot it works. This my device tree: mxcfb1: fb@0 { compatible = "fsl,mxc_sdc_fb"; disp_dev = "lcd"; interface_pix_fmt = "RGB24"; mode_str = "ILI9341-1"; default_bpp = <32>; int_clk = <0>; late_init = <0>; status = "okay"; };   lcd@0 { compatible = "fsl,lcd"; ipu_id = <0>; disp_id = <0>; default_ifmt = "RGB24"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ipu1>; status = "okay"; };   pinctrl_ipu1: ipu1grp { fsl,pins = < MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 >; }; Also I added this to `mxc_lcdif.c`: +   /* 240x320 @ 65 Hz, pixel clk @ 6.0MHz */ +   "ILI9341-1", 65, 240, 320, 166667, //167515 +   .left_margin = 20, .right_margin = 10, +   .upper_margin = 2, .lower_margin = 4, +   .hsync_len = 10, .vsync_len = 2, +   .sync = 0, +   .vmode = FB_VMODE_NONINTERLACED, +   .flag = 0,},     Kernel logs: # dmesg | grep mxc [ 0.000000] Kernel command line: noinitrd consoleblank=0 console=ttymxc1,115200 root=/dev/mmcblk3p2 rootwait rw quiet panic=5 [ 0.000020] clocksource: mxc_timer1: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 637086815595 ns [ 0.331436] 2020000.serial: ttymxc0 at MMIO 0x2020000 (irq = 25, base_baud = 5000000) is a IMX [ 0.332127] 21e8000.serial: ttymxc1 at MMIO 0x21e8000 (irq = 66, base_baud = 5000000) is a IMX [ 0.332169] console [ttymxc1] enabled [ 0.332647] 21ec000.serial: ttymxc2 at MMIO 0x21ec000 (irq = 67, base_baud = 5000000) is a IMX [ 0.333227] 21f4000.serial: ttymxc4 at MMIO 0x21f4000 (irq = 68, base_baud = 5000000) is a IMX [ 0.392363] clocksource: Switched to clocksource mxc_timer1 [ 0.421910] mxc_sdc_fb fb@0: registered mxc display driver lcd [ 0.484577] mxc_sdc_fb fb@0: 240x320 h_sync,r,l: 10,38,10 v_sync,l,u: 4,8,4 pixclock=6007000 Hz [ 0.923060] mxc_vdoa 21e4000.vdoa: i.MX Video Data Order Adapter(VDOA) driver probed [ 2.796337] mxc_sdc_fb fb@0: 240x320 h_sync,r,l: 10,38,10 v_sync,l,u: 4,8,4 pixclock=6007000 Hz Any idea? could it be a hardware issue? is there any way to reset LCD by application, driver or ...? Re: LCD distortion sometimes after reboot on imx6 custom board Okay, I updated the lcd initialization in the uboot and its fixed now. Thanks. Re: LCD distortion sometimes after reboot on imx6 custom board Thank you for your quick reply, but sorry I couldn’t understand what your suggestion was. Would you mind please clarify more. Regards Re: LCD distortion sometimes after reboot on imx6 custom board Hello, I think this is a software issue, try to export you current LCD to displa and change the dtb setting regard resolution. regards

Receive DMX512 on LPUART1 S32k146 Hi all, I'm trying to read DMX512 Messages with the LPUART1 (PTC8, PTC9) from the S32k146.  The data is generated by a Slesa-U9 and could be measured and decoded from the oszillator as UART. My problem is, that as GPIO I can receive the data, but as LPUART there is no data in the LPUART1->Data Register. So my question is, if there's any existing project for receiving DMX on a S32k microcontroller.  If not, can you please help me and find my mistake?  Best regards Sandra Re: Receive DMX512 on LPUART1 S32k146 Hi @12914A, Currently there are no DMX512 examples for the S32K1xx's devices. If no data is being received, make sure the LPUART module is being correctly configured for the DMX protocol, as start bits, parity, baud rate, stop bits, etc. You can find inside the AN5413: S32K1xx Series Cookbook an example application for UART over registers. This example performs a simple UART 9600 baud transfer to a COM port on a PC. You could try sending singular bytes to test communication. Best regards, Julián

llce multi-host demo for M7 side based on S32G BSP42 Hi, I noticed that, the llce multi-host feature is supported in SDK BSP42 release, and there needs M7 side demo can_demo_linux.elf support to check this feature, but it seems there is no this can_demo_linux.elf demo in manually built image following the SDK BSP42 release manual. So would you please help to check where I can find the demo and test the feature? Thanks, Zhantao Re: llce multi-host demo for M7 side based on S32G BSP42 Hi @chenyin_h, OK, got it! Thanks, Zhantao Re: llce multi-host demo for M7 side based on S32G BSP42 Hello, @hittzt  Thanks for your interests on this new feature introduced in the BSP42. I feel sorry that this demo is not included in the formal BSP release, as what have been introduced in the BSPUM, it is a sample from LLCE FDK, the LLCE FDK is the premium software released by NXP, it cannot be directly shared through this channel. Sorry for your inconvenience. BR Chenyin

NFC USB Dongle - Displaying data during write Hello team, I'm interested in learning if there's a method to retrieve the data sent to the NFC USB Dongle. Currently, I've successfully executed the 'C' example by enabling the #define CARDEMU_SUPPORT. I can both write to and read from the dongle. However, during the writing process, I'm looking for a way for the application to capture the data record sent by the writer. Any assistance on this matter would be highly appreciated. The specific dongle I'm using can be found here: https://www.mikroe.com/nfc-usb-dongle Re: NFC USB Dongle - Displaying data during write I am using the PN7150 NFC USB Dongle and attempting to communicate with my mobile phone. I ran the NXP-NCI_Windows_example.exe provided in example package SW4335. The application launches successfully, and the command prompt displays: WAITING FOR DEVICE DISCOVERY When I bring my phone close to the dongle, it detects it successfully, and the following messages appear: LISTEN MODE: Activated from remote Reader --- NDEF Record sent Immediately after, the following message is displayed: READER DISCONNECTED I initially suspected this might be a driver issue, but as per your documentation, no drivers are required. I’ve tested this behavior on multiple laptops and phones, but the issue persists. Could you please help me understand why the reader disconnects after the NDEF record is sent? I’ve attached the logs from the command prompt for your reference Re: NFC USB Dongle - Displaying data during write Solved

Can I get ethernet exampel for S32K314? Hello, Does an Ethernet sample project exist for the S32K314 MCU? If so, could you provide a link or file to access it? Thank you. Re: Can I get ethernet exampel for S32K314? thank you! Re: Can I get ethernet exampel for S32K314? Hello @malove , there is lwip example in SW32K3_TCPIP_STACK_2.0.0. Since ethernet belongs to export control, you will need approval. Please follow instruction on the page. Stacks are included in S32k3 Standard and Reference Software, accessible from the S32K3 main page. Best regards, Pavel

Re-generate boot descriptor file from command line Currently using Secure Provision Tool version 8.0 with the iMX RT1176. I am attempting to build images for my own custom bootloader and main applications from the command line. In secure provisioning tools I am able to 'Regenerate all files for this build' using the "Update files" button under the "Build image" tab to update build scripts and configuration files. My issue is the two different images have different start addresses and it appears the imx_application_gen_win.bd is what controls what values are placed into the IVT at the start of the generated .bin file. I don't see a way for me to update this .bd file based on the source executable image from the command line. I could manually create different .bd files for the two images but this seems messy for future updates. I have a batch file similar to the build_image_win.bat to build the applications in MCUXpresso headless mode and attempt to make the applications bootable by using the nxpimage hab export command that SPT seems to use. Re: Re-generate boot descriptor file from command line It appears that section 8 of the MCUXpresso Secure Provisioning Tool User Guide v9 has the documentation need to build the bootable images from the command line properly. Here is what I changed from what I was originally doing in my build process: I generated .s19 srec files from the .axf files using post build scripts to do the following: arm-none-eabi-objcopy -v -O srec "${BuildArtifactFileName}" "${BuildArtifactFileBaseName}.s19" Next in my build script I generate the bootable image using the build command from securep.exe "%SPT%" -w "%SPT_WORKSPACE%" --device MIMXRT1176 build --source-image "%SPT_WORKSPACE%\source_images\boot.s19"   The same thing for the main application. I then am able to find both .bin bootable images in: %UserProfile%\secure_provisioning\bootable_images   Now both images have the correct IVT and boot data structures that previously only had the previous configuration (out of date .bd file) from the last time I opened Secure Provisioning Tools. I hope this helps anyone else trying to automate the build process. Thanks again to @marek-trmac and @liborukropec for pointing me in the right direction.   Best, Brian   Re: Re-generate boot descriptor file from command line Hi Libor, I will upgrade to v9 of the Secure Provisioning Tool. I'm not sure the additional images portion will be as valuable as I will flash the images to varying addresses build-to-build as I create a dynamic file that includes other images for other peripherals that are not fixed in length or position. I'm trying to automate the build process as much as possible and don't want future engineers the need to open up the Secure Provisioning Tool GUI to build each image with the updated IVT and Boot Data Structure. Please see my reply to @marek-trmac for further details. I will explore the hooks in more detail. Thanks, Brian Re: Re-generate boot descriptor file from command line Hi Marek, Thanks for the reply. To further clarify what I am implementing. I have a custom bootloader application that is loaded to QSPI Flash on FlexSPI 2 at 0x6000 0000. My application or bootloader will receive a file containing the bootloader application, arm m7 main application, and additional images for the m4 application and an fpga. My application or bootloader will parse this file and place images in QSPI Flash. When my bootloader reboots and verifies there is a valid arm m7 application it will load it into internal RAM and jump to the application.  Currently, this relies on there being an IVT that is placed in RAM at 0x2000 so my bootloader can read the self address of the IVT and the start absolute address of the image in the boot data structure to be able to jump to the main arm m7 application. #define IVT_ADDRESS 0x2000 static void load_application_image(uint32_t dst, uint32_t offset, uint32_t image_size) {   uint32_t applicationAddress;   uint32_t stackPointer;   uint32_t baseAddress;   baseAddress = NOR_FLEXSPI_AMBA_BASE + offset;   memcpy((void *)dst, (void *)baseAddress, image_size);   uint32_t arm_m7_image_ram = (*(uint32_t *)(IVT_ADDRESS + 20) + *(uint32_t *)(IVT_ADDRESS + 32));   stackPointer = *(uint32_t *)(arm_m7_image_ram); //self + start in ivt   applicationAddress = *(uint32_t *)(arm_m7_image_ram + 4);   jump_to_application(applicationAddress, stackPointer);   }   and    static void jump_to_application(uint32_t applicationAddr, uint32_t stackPointer) {     // Create the function call to the user application.     // Static variables are needed since changed the stack pointer out from under the compiler     // we need to ensure the values we are using are not stored on the previous stack     static uint32_t s_stackPointer = 0;     s_stackPointer = stackPointer;     static void (*s_entry)(void) = 0;     s_entry = (void (*)(void))applicationAddr;     // Turn off interrupts     __disable_irq();     // Set the VTOR to the application vector table address.     SCB->VTOR = (uint32_t)0x2000;     // Memory barriers for good measure.     __ISB();     __DSB();     // Set stack pointers to the application stack pointer.     __set_MSP(s_stackPointer);     __set_PSP(s_stackPointer);     // Jump to the application.     s_entry(); }   This works when I have the IVT and Boot Data Structure at the front of my main arm m7 application hence my reasoning for wanting to append the IVT and Boot Data Structure to the first 0x1000 4KB of my main arm m7 .bin.   I will explore the User Guide and see if I can get the results I want with MCUXpresso Secure Provisioning Tool V9.     Re: Re-generate boot descriptor file from command line Hi Brian, it is not clear why you need to build bootable application if you have bootloader. I suppose the processor starts the bootloader after reset, not the application, so I suppose you do not need bootable application image. There are examples in MCUXpresso SDK how to use "MCUboot" open source bootloader and this use case is supported in MCUXpresso Secure Provisioning tool v9, see User Guide for step-by-step description. Re: Re-generate boot descriptor file from command line Hi Brian, first, could you please upgrade to SEC v9? It brings multiple improvements, including custom hooks which should allow you to be able to add custom scripts without modifying the main build/write scripts created by SEC tool. SEC tool allows "additional" images to be flashed together with the main application, which might be handy for your use case. Using custom "hooks" scripts you can execute your scripts during build & write at different phases of the scripts, without modifying the generated scripts, so special cases not supported by SEC tool can be implemented more easily while still using generated scripts from SEC tool. Could you please describe your use case, what exactly you want to do in SEC tool? Regards, Libor

MCIMX6D6AVT10AD直交インターフェース 直交チャネルは「MCIMX6D6AVT10AD」プロセッサでロータリーエンコーダー信号をデコードするために使用できますか? ボード設計 Re:直交インターフェースMCIMX6D6AVT10AD ご支援いただきありがとうございます

Taplinx iOS 应用程序在标签响应时崩溃 您好，我按照UG10045.pdf 的说明创建了 iOS 应用程序。我创建了 ApduExchangeWithByteArray 方法并实现了其内容。但是，当将标签的响应发送回 Taplinx 库时，应用程序崩溃了，设备日志中显示以下内容： Time Device Name Type PID Tag Message Nov 6 20:44:31 iPhone Notice 5223 MobileFacilityApp Command Set - 1 Nov 6 20:44:31 iPhone Notice 5223 MobileFacilityApp Command Set - Native Nov 6 20:44:31 iPhone Error 0 kernel(Sandbox) Sandbox: MobileFacilityApp(5223) deny(1) sysctl-read kern.bootargs Nov 6 20:44:38 iPhone Notice 5223 MobileFacilityApp(UIKitCore) Received memory warning. Nov 6 20:44:38 iPhone Notice 5223 MobileFacilityApp(UIKitCore) Received memory warning. Nov 6 20:44:40 iPhone Notice 0 kernel EXC_RESOURCE -> MobileFacilityApp[5223] exceeded mem limit: InactiveHard 3072 MB (fatal) Nov 6 20:44:40 iPhone Notice 0 kernel memorystatus: killing process 5223 [MobileFacilityApp] in high band FOREGROUND (100) - memorystatus_available_pages: 44859 当我将空响应发回 taplinx 库（仅 TL_TagAPDUResponse 而未设置 ResponseData）时 - 应用程序不会崩溃，并且我收到有关响应不完整的错误（这是预期的）。我做错了什么？ 回复：Taplinx iOS 应用程序因标签响应而崩溃 后续 - 当我将我的实现更改为使用提供的 TapLinxApduHandler 而不是提供我自己的时 - 那么 apduExchangeWithByteArray 确实符合合同 - (nullable TL_TagAPDUResponse *)apduExchangeWithByteArray:(NSData *_Nonnull)apduData; 回复：Taplinx iOS 应用程序因标签响应而崩溃 @ukcas - taplinx ios 库的哪个版本是“当前”版本？因为我使用的是 2.0.0 版本，当我从 apduExchange 方法返回 TL_TagAPDUResponse 时，它肯定会崩溃，所以它必须是 j2objc 库中的原始 IOSByteArray。我正在使用 taplinx 库的 c# 绑定，但这在这个问题上无关紧要。 回复：Taplinx iOS 应用程序因标签响应而崩溃 你好 崩溃肯定来自 taplinx 库，因为当我更改 - (可空 TL_TagAPDUResponse *)apduExchangeWithByteArray:(NSData *_Nonnull)apduData; 实际上： - （可空的IOSByteArray *）apduExchangeWithByteArray：（IOSByteArray * _Nonnull）apduData； 它开始发挥作用 回复：Taplinx iOS 应用程序因标签响应而崩溃 你好，达米安， 也许错误的原因是由于超出了内存限制而不是 TapLinx 库？ MobileFacilityApp[5223] exceeded mem limit: InactiveHard 3072 MB (fatal) 集成TapLinx库的应用程序可以按如下方式使用（无需在顶层实现ApduExchange） 将委托设置为 APDUHandler let reader = TL_IOSNFCReader(uid: tag.identifier, historicalBytes: tag.historicalBytes ?? Data()) handler = TapLinxApduHandler(reader: reader) handler.delegate = self libraryManager?.setApduHandlerWithApduHandler(handler) 下一步是在应用程序内部实现协议方法 func apduExchange(withByteArray apduData: Data) -> TL_TagAPDUResponse? { var tagAPDUResponse: TL_TagAPDUResponse? if connectedTag != nil { // Send Tag Type Native of ISO and the apdu as NFCISO7816APDU executeAPDUCommandOn7816Tag(tagType: tagtype, apdu: apdu) { data in let appendedData = data tagAPDUResponse = TL_TagAPDUResponse(responseData: appendedData, tag: self.currentTag) semaphore.signal() } let _ = semaphore.wait(timeout: .now() + 3.0) } else if connectedMifareTag != nil { let semaphore = DispatchSemaphore(value: 0) print("MIFARE CAPDU 📱->💳 \(apduData.hex)") executeAPDUCommandOnMIFARETag(apdu: apduData) { data in print("RAPDU 📱<-💳 Data: \(data.hex)") tagAPDUResponse = TL_TagAPDUResponse(responseData: data, tag: self.currentTag) semaphore.signal() } let _ = semaphore.wait(timeout: .now() + 3.0) } print("Tag Response \(String(describing: tagAPDUResponse))") return tagAPDUResponse } 希望这种简化能对您有所帮助。 顺祝商祺！ TapLinx团队 回复：Taplinx iOS 应用程序因标签响应而崩溃 还有一件事 - apduData 实际上也是 IOSByteArray，而不是 NSData 回复：Taplinx iOS 应用程序因标签响应而崩溃 显然 TapLinx-v2.0.0 中包含的标题都是错误的。在TapLinxApduHandler.h中我们看到声明： - (nullable TL_TagAPDUResponse *)apduExchangeWithByteArray:(NSData *_Nonnull)apduData; 但实际上我们应该返回 IOSByteArray*，否则应用程序将崩溃并出现上述症状

PTN3460 Can PTN3460 support converting 640x240 resolution DP signal into 640x240 resolution LVDS signal?

about NFC Antenna Pattern Hello, The back of the NFC antenna pattern in the photo below is designed with a ground pattern. Could you advise on the characteristics this might entail? Thank you. HITAG Reader ICs NFC Controller Solutions NFC Reader Library Re: about NFC Antenna Pattern The chip in the above picture is an NXP chip, but it's not the one we use in our devices. Thank you for your interest. Re: about NFC Antenna Pattern Hello theo-choi,  I know that some customers used similar patterns for better EMI behavior.  BR Tomas  Re: about NFC Antenna Pattern Hello @theo-choi  Could you share the exact type of the IC what you are using? Maybe, some Demo design can be recommended to you for reference. Re: about NFC Antenna Pattern Connecting the center of the antenna pattern to GND improves the characteristics against power noise. from 3ALogistics

MPC5748G EVB 支持多少个 CAN 通道？ 大家好， 我的一个项目中使用了 MPC5748G EVB。我想要连接 2 个 CAN 通道，但我发现 MPC5748G EVB 只有一个 CAN。 您能告诉我 MPC5748G EVB 支持多少个 CAN 通道吗？ 请提供 MPC5748G EVB 的引脚图。 回复：MPC5748G EVB 支持多少个 CAN 通道？ 不，我没有 回复：MPC5748G EVB 支持多少个 CAN 通道？ 请建议如何在 MPC5748G 板上使用 2 个 CAN 通道。如果有其他方法，请告诉我。 回复：MPC5748G EVB 支持多少个 CAN 通道？ 根据参考手册，总共有 8 个 Flexcan 通道可用，我需要在评估板上使用 2 个 CAN 通道，请确认。

FS23: reset time question Hello, I would like to ask a question regarding the system reset time when the watchdog is not refreshed. The configured watchdog is: /* WdWindowReg */ ((uint16)0x0000U) | SBC_FS23_FS_WDW_PERIOD_64MS | SBC_FS23_FS_WDW_RECOVERY_64MS //| SBC_FS23_FS_WDW_EN_MASK | SBC_FS23_FS_WDW_REC_EN_MASK After the system exits the init phase normally, I measured the system restart waveform while not refreshing the watchdog in the task, and the waveform indicates that the reboot time is approximately 340ms. Could you please explain how to calculate the 340ms time in the current configuration? Later, I tried to disable WDW_REC_EN, but I found that the experimental phenomenon remained the same, and the reboot time was still around 340ms. Thanks! Re: FS23: reset time question Hello Gumu, please refer to the sections 19.2.1.2 and 19.2.2 in the full FS23 datasheet. By incorrect or none Watchdog refresh, Watchdog error counter is incremented by 2. By default the Watchdog error counter limit is set to 6. To reach the limit three incorrect or none watchdog refreshes are needed. Please check the WD_ERR_LIMIT[1:0] bits setting. Have you left them in default value 6? The green waveform in your scope is from the RSTB pin, right?  If you have left the WD_ERR_LIMIT[1:0] to 6, then three incorrect or none WD refreshes would be needed (3*64ms=192ms), if to 8 then four (4*64ms=256ms).   Then if the WD recovery is set to 64ms, this would add to the time above. Please check the WDW_REC_EN bit setting. Have you set it to 1? For the MCU fault recovery strategy please refer to the section 19.2.5.  Please check how have you set the FCCUx error impact configuration. Have you left it to default? If yes, please probe the FS0B pin. To compare it with the RSTB pin. When the WD_ERR_LIMIT[1:0] has reached it's maximum value, the FS0B should be pulled low and Error phase should start. Please refer to the Figure 45.  With Best Regards, Jozef

S32G3 M7 boot Hello, After following the S32G-VNP-GLDBOX3 SOFTWARE ENABLEMENT GUIDE, I am not able to get the S32G3 to boot an LED blinking application from QSPI.  The application works properly from SD-Card. I have followed the procedure and successfully boot the LED blink application from SD-Card.  I reconfigured the IVT to boot from QSPI, flash the file using S32 Flash and change the RCON switch to boot QSPI (all switches off), the board seems to go into infinite reset. From the example in the guide, I have not changed anything for the build of the application from the SD Card to the QSPI.  I did, however, change the IVT configuration in the following ways: Changed Interface Selection -> QuadSPI Serial Flash Reclicked "Automatic Alignment" to realign the application bootloader to 0x100 start address Re-exported the blob In S32 Flash Tool: Changed "Algorithm" to MX25UW51245G The download/flash completes properly, and I cycle power to the board.  When the board starts again, D2 Red (reset) LED blinks at about 1 Hz and the LED blinking program does not run.  I feel like there is something I am missing.  I have the S32G-VNP-RDB3 board (it is very new). How do i get an M7 application to boot running from QSPI?  Is this possible?  I have the S32Debugger, how do I debug this situation? Re: S32G3 M7 boot I'm glad to know you were able to solve your issue. Thanks for letting me know and for accepting my reply as a solution! Have a great day, Alejandro Re: S32G3 M7 boot This was absolutely the problem.  Once I re-spun the blob using the QSPI parameters, it worked.  thank you very much. Re: S32G3 M7 boot Hello @adalberto1, From your description it seems that the only issue is that the QSPI parameters are missing, you should be able to find the necessary file in the S32 Design Studio installation directory for example: C:\NXP\S32DS.3.5\eclipse\mcu_data\processors\S32G399A\PlatformSDK_S32XX_4_0_0\quadspi\default_boot_images\mx25_sim133ddr.bin Let me know if this solved your problem. Best regards, Alejandro

IMX VPU Wrapper ドキュメント 私は現在、Yocto Kirkstone 5.10.35 + g5f6f502e525bのvpuラッパーでIMX.8MPを使用しています。usr/lib には libfslvpuwrap.so.3.0.0 共有ライブラリがありますが、usr/include ディレクトリには関連するヘッダー ファイルが表示されません。私はvpu_wrapper githubリポジトリでvpu_wrapper.hを取得しようとしています私のバージョンのヘッダーファイルですが、3.0.0のリリース/タグ付きバージョンが見つかりません。IMX VPUリファレンスマニュアルも使用していますが、使用しているよりも新しいリリースのようです。私のリリースに適したIMX VPUリファレンスマニュアルはどこにありますか? VPUライブラリバージョン:major.minor.rel = 1.1.1 VPU FWバージョン:major.minor.rel_rcode=1.1.1_r0 VPUラッパーバージョン:major.minor.rel = 3.0.0 i.MX 8ファミリ | i.MX 8QuadMax (8QM) | 8QuadPlus

DDR can't work when I disable DDRC data_init at BL2 stage I'm optimizing BL2 boot time based on lx2160 yocto kirkstone version, get a issue when disable ddr data init. I check the spec of LX2160ARM.pdf and see D_INIT register function: DRAM data initialization. This bit is set by software, and it is cleared by hardware. If software sets this bit before the memory controller is enabled, the controller will automatically initialize DRAM after it is enabled. This bit will be automatically cleared by hardware once the initialization is completed. This data initialization bit should only be set when the controller is idle. 0b - There is not data initialization in progress, and no data initialization is scheduled 1b - The memory controller will initialize memory once it is enabled. This bit will remain asserted until the initialization is complete. The value in DDR_DATA_INIT register will be used to initializememory. I thinks if we set this bit, only one function is write 0xdeadbeef to dram, so I disable this bit before ddr enable. want to save bootup time about 1440ms by skip this waiting. /*      * total memory / bus width = transactions needed      * transactions needed / data rate = seconds      * to add plenty of buffer, double the time      * For example, 2GB on 666MT/s 64-bit bus takes about 402ms      * Let's wait for 800ms      */ bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) >> SDRAM_CFG_DBW_SHIFT); timeout = ((total_mem_per_ctrl_adj << (6 - bus_width)) * 100 /            (clk >> 20)) << 2; total_mem_per_ctrl_adj >>= 4;   /* shift down to gb size */ if ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) != 0) { debug("total size %d GB\n", total_mem_per_ctrl_adj); debug("Need to wait up to %d ms\n", timeout * 10); do { mdelay(10);         } while (timeout-- > 0 &&              ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)) != 0); if (timeout <= 0) { if (ddr_in32(&ddr->debug[1]) & 0x3d00) { ERROR("Found training error(s): 0x%x\n", ddr_in32(&ddr->debug[1]));             } ERROR("Error: Waiting for D_INIT timeout.\n"); return -EIO;         }    }   but when load bl31 image to dram, it failed, console output stuck when read from sdcard.   NOTICE: 16 GB DDR4, 64-bit, CL=22, ECC on, 256B NOTICE: Time used by DDR driver 3381 ms INFO: DDR Controller 1. INFO: Configuring TrustZone Controller INFO: Configuring TrustZone Controller INFO: DDR Controller 2. INFO: Configuring TrustZone Controller INFO: Configuring TrustZone Controller INFO: BL2: Doing platform setup INFO: BL2: Loading image id 3 INFO: sd-mmc read done. INFO: sd-mmc read done. INFO: sd-mmc read done. INFO: Loading image id=3 at address 0xfbe00000 INFO: sd-mmc read done.   anyone can help me for this issue? thanks!   Re: DDR can't work when I disable DDRC data_init at BL2 stage Please use non zero value. This configuration is optional and, if not used, memory will be initialized to all-zeros—the register’s default value. Re: DDR can't work when I disable DDRC data_init at BL2 stage thanks for replay, I change init value from 0xDEADBEEF to 0, system will crash too. does the init value must be 0xDEADBEEF or some special pattern? Re: DDR can't work when I disable DDRC data_init at BL2 stage Controller will write 32 bytes beginning with the address at DDR_INIT_ADDR register during the initialization sequence. But with ECC enabled, the content of DRAM must be initialized also so the the ECC captured values are correct. In other words, with ECC on if you read a memory location that does not have correct ECC capture value you will get a false ECC error.

NXP RTOS OS_MKOBJID Error I have encountered error when I include OS into the project.     Line 11304: make[3]: *** [BoseCore/coreServices/BIPC/src/subdir.mk:43: BoseCore/coreServices/BIPC/src/asd_mcapi_idt_datalink_mcu_spi.o] Error 1 Line 12188:   737 |       A2B_APP_INFO_LOG("Error while sending discovery message."); Line 13363: C:/subversions/branches/branch1/ZEUS-1579_RTD_5_0_0/control/Mcal/DP1/Integrate/include/Os_cfg.h:137:41: error: expected ')' before 'OS_MKOBJID' Line 13377: C:/subversions/branches/branch1/ZEUS-1579_RTD_5_0_0/control/Mcal/DP1/Integrate/include/Os_cfg.h:138:43: error: expected ')' before 'OS_MKOBJID' Line 13395: C:/subversions/branches/branch1/ZEUS-1579_RTD_5_0_0/control/Mcal/DP1/Integrate/include/Os_cfg.h:137:41: error: expected ')' before 'OS_MKOBJID' Line 13401: C:/subversions/branches/branch1/ZEUS-1579_RTD_5_0_0/control/Mcal/DP1/Integrate/include/Os_cfg.h:135:29: error: expected ')' before 'OS_MKOBJID' Line 13415: C:/subversions/branches/branch1/ZEUS-1579_RTD_5_0_0/control/Mcal/DP1/Integrate/include/Os_cfg.h:138:43: error: expected ')' before 'OS_MKOBJID' Line 13421: C:/subversions/branches/branch1/ZEUS-1579_RTD_5_0_0/control/Mcal/DP1/Integrate/include/Os_cfg.h:134:34: error: expected ')' before 'OS_MKOBJID' Line 13438: C:/subversions/branches/branch1/ZEUS-1579_RTD_5_0_0/control/Mcal/DP1/Integrate/include/Os_cfg.h:135:29: error: expected ')' before 'OS_MKOBJID' Line 13444: C:/subversions/branches/branch1/ZEUS-1579_RTD_5_0_0/control/Mcal/DP1/Integrate/include/Os_cfg.h:131:50: error: expected ')' before 'OS_MKOBJID' Line 13457: C:/subversions/branches/branch1/ZEUS-1579_RTD_5_0_0/control/Mcal/DP1/Integrate/include/Os_cfg.h:134:34: error: expected ')' before 'OS_MKOBJID' Line 13463: C:/subversions/branches/branch1/ZEUS-1579_RTD_5_0_0/control/Mcal/DP1/Integrate/include/Os_cfg.h:132:50: error: expected ')' before 'OS_MKOBJID' Line 13496: C:/subversions/branches/branch1/ZEUS-1579_RTD_5_0_0/control/Mcal/DP1/Integrate/include/Os_cfg.h:131:50: error: expected ')' before 'OS_MKOBJID' Line 13509: C:/subversions/branches/branch1/ZEUS-1579_RTD_5_0_0/control/Mcal/DP1/Integrate/include/Os_cfg.h:132:50: error: expected ')' before 'OS_MKOBJID' Line 13561: C:/subversions/branches/branch1/ZEUS-1579_RTD_5_0_0/control/Mcal/DP1/Integrate/include/Os_cfg.h:134:34: error: expected ')' before 'OS_MKOBJID' Line 1362   Here is the Os_cfg.h    /****************************************************************************** * *       NXP(TM) and the NXP logo are trademarks of NXP. *       All other product or service names are the property of their respective owners. *       (C) Freescale Semiconductor, Inc. 2013-2016 *       Copyright 2024 NXP * *       THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT *       BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF NXP. * *       Description: Configuration Header file * *       Note: The implementation that was used is: AUTOSAR_S32K3xx *       System Generator for AUTOSAR OS/S32K3xx - Version: 4.7 Build 4.7.152 * ********************************************************************************/ #ifndef OSCFG_H #define OSCFG_H /* Applications */ #define OsApplication0 ((ApplicationType)OS_MKOBJID(OBJECT_APPLICATION, 0U)) /* Application ID */ /* Spinlock */ /* Application modes */ #define OsAppMode0 ((AppModeType)0U)       /* AppMode ID */ /* Common stack */ #define OSTask10msSTKSIZE 1032U            /* stack size of Task10ms */ #define OSTask10msSTKBOS OSRUNNABLESTKBEG  /* Task10ms bos */ #define OSTask10msSTKTOS ((OSTask10msSTKBOS) + (OSTask10msSTKSIZE/4U)) /* Task10ms tos */ #define OSTask1sSTKSIZE 1032U              /* stack size of Task1s */ #define OSTask1sSTKBOS OSTask10msSTKTOS    /* Task1s bos */ #define OSTask1sSTKTOS ((OSTask1sSTKBOS) + (OSTask1sSTKSIZE/4U)) /* Task1s tos */ #define OSDSP2_SPI_TaskSTKSIZE 1032U       /* stack size of DSP2_SPI_Task */ #define OSDSP2_SPI_TaskSTKBOS OSTask1sSTKTOS /* DSP2_SPI_Task bos */ #define OSDSP2_SPI_TaskSTKTOS ((OSDSP2_SPI_TaskSTKBOS) + (OSDSP2_SPI_TaskSTKSIZE/4U)) /* DSP2_SPI_Task tos */ #define OSDSP1_SPI_TaskSTKSIZE 1032U       /* stack size of DSP1_SPI_Task */ #define OSDSP1_SPI_TaskSTKBOS OSDSP2_SPI_TaskSTKTOS /* DSP1_SPI_Task bos */ #define OSDSP1_SPI_TaskSTKTOS ((OSDSP1_SPI_TaskSTKBOS) + (OSDSP1_SPI_TaskSTKSIZE/4U)) /* DSP1_SPI_Task tos */ #define OSBIPC_NonBlk_Sync_TaskSTKSIZE 1032U /* stack size of BIPC_NonBlk_Sync_Task */ #define OSBIPC_NonBlk_Sync_TaskSTKBOS OSDSP1_SPI_TaskSTKTOS /* BIPC_NonBlk_Sync_Task bos */ #define OSBIPC_NonBlk_Sync_TaskSTKTOS ((OSBIPC_NonBlk_Sync_TaskSTKBOS) + (OSBIPC_NonBlk_Sync_TaskSTKSIZE/4U)) /* BIPC_NonBlk_Sync_Task tos */ #define OSDspPlatCom_ResponseTaskSTKSIZE 1032U /* stack size of DspPlatCom_ResponseTask */ #define OSDspPlatCom_ResponseTaskSTKBOS OSBIPC_NonBlk_Sync_TaskSTKTOS /* DspPlatCom_ResponseTask bos */ #define OSDspPlatCom_ResponseTaskSTKTOS ((OSDspPlatCom_ResponseTaskSTKBOS) + (OSDspPlatCom_ResponseTaskSTKSIZE/4U)) /* DspPlatCom_ResponseTask tos */ #define OSTalariaResponse_TaskSTKSIZE 1032U /* stack size of TalariaResponse_Task */ #define OSTalariaResponse_TaskSTKBOS OSDspPlatCom_ResponseTaskSTKTOS /* TalariaResponse_Task bos */ #define OSTalariaResponse_TaskSTKTOS ((OSTalariaResponse_TaskSTKBOS) + (OSTalariaResponse_TaskSTKSIZE/4U)) /* TalariaResponse_Task tos */ #define OSRMDLControl_TaskSTKSIZE 1032U    /* stack size of RMDLControl_Task */ #define OSRMDLControl_TaskSTKBOS OSTalariaResponse_TaskSTKTOS /* RMDLControl_Task bos */ #define OSRMDLControl_TaskSTKTOS ((OSRMDLControl_TaskSTKBOS) + (OSRMDLControl_TaskSTKSIZE/4U)) /* RMDLControl_Task tos */ #define OSNVRAM_TaskSTKSIZE 1032U          /* stack size of NVRAM_Task */ #define OSNVRAM_TaskSTKBOS OSRMDLControl_TaskSTKTOS /* NVRAM_Task bos */ #define OSNVRAM_TaskSTKTOS ((OSNVRAM_TaskSTKBOS) + (OSNVRAM_TaskSTKSIZE/4U)) /* NVRAM_Task tos */ /* Task definitions */ #define Task1ms ((TaskType)OS_MKOBJID(OBJECT_TASK, 0U)) /* Task ID */ extern void FuncTask1ms(void); /* Task entry point */ #define Task10ms ((TaskType)OS_MKOBJID(OBJECT_TASK, 1U)) /* Task ID */ extern void FuncTask10ms(void); /* Task entry point */ #define Task100ms ((TaskType)OS_MKOBJID(OBJECT_TASK, 2U)) /* Task ID */ extern void FuncTask100ms(void); /* Task entry point */ #define Task1s ((TaskType)OS_MKOBJID(OBJECT_TASK, 3U)) /* Task ID */ extern void FuncTask1s(void); /* Task entry point */ #define DSP2_SPI_Task ((TaskType)OS_MKOBJID(OBJECT_TASK, 4U)) /* Task ID */ extern void FuncDSP2_SPI_Task(void); /* Task entry point */ #define DSP1_SPI_Task ((TaskType)OS_MKOBJID(OBJECT_TASK, 5U)) /* Task ID */ extern void FuncDSP1_SPI_Task(void); /* Task entry point */ #define BIPC_NonBlk_Sync_Task ((TaskType)OS_MKOBJID(OBJECT_TASK, 6U)) /* Task ID */ extern void FuncBIPC_NonBlk_Sync_Task(void); /* Task entry point */ #define DspPlatCom_ResponseTask ((TaskType)OS_MKOBJID(OBJECT_TASK, 7U)) /* Task ID */ extern void FuncDspPlatCom_ResponseTask(void); /* Task entry point */ #define TalariaResponse_Task ((TaskType)OS_MKOBJID(OBJECT_TASK, 8U)) /* Task ID */ extern void FuncTalariaResponse_Task(void); /* Task entry point */ #define RMDLControl_Task ((TaskType)OS_MKOBJID(OBJECT_TASK, 9U)) /* Task ID */ extern void FuncRMDLControl_Task(void); /* Task entry point */ #define NVRAM_Task ((TaskType)OS_MKOBJID(OBJECT_TASK, 10U)) /* Task ID */ extern void FuncNVRAM_Task(void); /* Task entry point */ #define InitTask ((TaskType)OS_MKOBJID(OBJECT_TASK, 11U)) /* Task ID */ extern void FuncInitTask(void); /* Task entry point */ /* ISR functions */ #define OS_isr_SIUL2_EXT_IRQ_0_7_ISR SIUL2_EXT_IRQ_0_7_ISR /* ISRs definition */ #define OSISREMIOS1_4_IRQ() OSISR2DISP(EMIOS1_4_IRQ) /* IrqChannel is EXTERNAL */ extern void OS_isr_EMIOS1_4_IRQ(void); /* irq: EMIOS1_4_IRQ; channel: EXTERNAL; category: 2 */ #define EMIOS1_4_IRQLEVEL 4U               /* interrupt level of EMIOS1_4_IRQ */ #define EMIOS1_4_IRQPRIORITY 4U            /* priority of EMIOS1_4_IRQ */ #define OSISRLPI2C0_Master_Slave_IRQHandler() OSISR2DISP(LPI2C0_Master_Slave_IRQHandler) /* IrqChannel is EXTERNAL */ extern void OS_isr_LPI2C0_Master_Slave_IRQHandler(void); /* irq: LPI2C0_Master_Slave_IRQHandler; channel: EXTERNAL; category: 2 */ #define LPI2C0_Master_Slave_IRQHandlerLEVEL 5U /* interrupt level of LPI2C0_Master_Slave_IRQHandler */ #define LPI2C0_Master_Slave_IRQHandlerPRIORITY 5U /* priority of LPI2C0_Master_Slave_IRQHandler */ #define OSISRLPI2C1_Master_Slave_IRQHandler() OSISR2DISP(LPI2C1_Master_Slave_IRQHandler) /* IrqChannel is EXTERNAL */ extern void OS_isr_LPI2C1_Master_Slave_IRQHandler(void); /* irq: LPI2C1_Master_Slave_IRQHandler; channel: EXTERNAL; category: 2 */ #define LPI2C1_Master_Slave_IRQHandlerLEVEL 5U /* interrupt level of LPI2C1_Master_Slave_IRQHandler */ #define LPI2C1_Master_Slave_IRQHandlerPRIORITY 5U /* priority of LPI2C1_Master_Slave_IRQHandler */ #define OSISRLpspi_Ip_LPSPI_5_IRQHandler() OSISR2DISP(Lpspi_Ip_LPSPI_5_IRQHandler) /* IrqChannel is EXTERNAL */ extern void OS_isr_Lpspi_Ip_LPSPI_5_IRQHandler(void); /* irq: Lpspi_Ip_LPSPI_5_IRQHandler; channel: EXTERNAL; category: 2 */ #define Lpspi_Ip_LPSPI_5_IRQHandlerLEVEL 5U /* interrupt level of Lpspi_Ip_LPSPI_5_IRQHandler */ #define Lpspi_Ip_LPSPI_5_IRQHandlerPRIORITY 5U /* priority of Lpspi_Ip_LPSPI_5_IRQHandler */ #define OSISRMCL_FLEXIO_ISR() OSISR2DISP(MCL_FLEXIO_ISR) /* IrqChannel is EXTERNAL */ extern void OS_isr_MCL_FLEXIO_ISR(void); /* irq: MCL_FLEXIO_ISR; channel: EXTERNAL; category: 2 */ #define MCL_FLEXIO_ISRLEVEL 5U             /* interrupt level of MCL_FLEXIO_ISR */ #define MCL_FLEXIO_ISRPRIORITY 5U          /* priority of MCL_FLEXIO_ISR */ #define OSISRPIT_0_ISR() OSISR2DISP(PIT_0_ISR) /* IrqChannel is EXTERNAL */ extern void OS_isr_PIT_0_ISR(void); /* irq: PIT_0_ISR; channel: EXTERNAL; category: 2 */ #define PIT_0_ISRLEVEL 2U                  /* interrupt level of PIT_0_ISR */ #define PIT_0_ISRPRIORITY 2U               /* priority of PIT_0_ISR */ #define OSISRPIT_1_ISR() OSISR2DISP(PIT_1_ISR) /* IrqChannel is EXTERNAL */ extern void OS_isr_PIT_1_ISR(void); /* irq: PIT_1_ISR; channel: EXTERNAL; category: 2 */ #define PIT_1_ISRLEVEL 3U                  /* interrupt level of PIT_1_ISR */ #define PIT_1_ISRPRIORITY 3U               /* priority of PIT_1_ISR */ #define OSISRSIUL2_EXT_IRQ_0_7_ISR() OSISR2DISP(SIUL2_EXT_IRQ_0_7_ISR) /* IrqChannel is EXTERNAL */ extern void OS_isr_SIUL2_EXT_IRQ_0_7_ISR(void); /* irq: SIUL2_EXT_IRQ_0_7_ISR; channel: EXTERNAL; category: 2 */ #define SIUL2_EXT_IRQ_0_7_ISRLEVEL 5U      /* interrupt level of SIUL2_EXT_IRQ_0_7_ISR */ #define SIUL2_EXT_IRQ_0_7_ISRPRIORITY 5U   /* priority of SIUL2_EXT_IRQ_0_7_ISR */ #define OSISRSIUL2_EXT_IRQ_16_23_ISR() OSISR2DISP(SIUL2_EXT_IRQ_16_23_ISR) /* IrqChannel is EXTERNAL */ extern void OS_isr_SIUL2_EXT_IRQ_16_23_ISR(void); /* irq: SIUL2_EXT_IRQ_16_23_ISR; channel: EXTERNAL; category: 2 */ #define SIUL2_EXT_IRQ_16_23_ISRLEVEL 5U    /* interrupt level of SIUL2_EXT_IRQ_16_23_ISR */ #define SIUL2_EXT_IRQ_16_23_ISRPRIORITY 5U /* priority of SIUL2_EXT_IRQ_16_23_ISR */ #define OSISRSTM_0_ISR() OSISR2DISP(STM_0_ISR) /* IrqChannel is EXTERNAL */ extern void OS_isr_STM_0_ISR(void); /* irq: STM_0_ISR; channel: EXTERNAL; category: 2 */ #define STM_0_ISRLEVEL 1U                  /* interrupt level of STM_0_ISR */ #define STM_0_ISRPRIORITY 1U               /* priority of STM_0_ISR */ #define EMIOS1_4_IRQ ((ISRType)OS_MKOBJID(OBJECT_ISR, 0U)) /* ISR ID */ #define LPI2C0_Master_Slave_IRQHandler ((ISRType)OS_MKOBJID(OBJECT_ISR, 1U)) /* ISR ID */ #define LPI2C1_Master_Slave_IRQHandler ((ISRType)OS_MKOBJID(OBJECT_ISR, 2U)) /* ISR ID */ #define Lpspi_Ip_LPSPI_5_IRQHandler ((ISRType)OS_MKOBJID(OBJECT_ISR, 3U)) /* ISR ID */ #define MCL_FLEXIO_ISR ((ISRType)OS_MKOBJID(OBJECT_ISR, 4U)) /* ISR ID */ #define PIT_0_ISR ((ISRType)OS_MKOBJID(OBJECT_ISR, 5U)) /* ISR ID */ #define PIT_1_ISR ((ISRType)OS_MKOBJID(OBJECT_ISR, 6U)) /* ISR ID */ #define SIUL2_EXT_IRQ_0_7_ISR ((ISRType)OS_MKOBJID(OBJECT_ISR, 7U)) /* ISR ID */ #define SIUL2_EXT_IRQ_16_23_ISR ((ISRType)OS_MKOBJID(OBJECT_ISR, 8U)) /* ISR ID */ #define STM_0_ISR ((ISRType)OS_MKOBJID(OBJECT_ISR, 9U)) /* ISR ID */ /* ISR1 id */ /* Resources definitions */ #define A2B_I2C_RESOURCE ((ResourceType)OS_MKOBJID(OBJECT_RESOURCE, 0U)) /* Resource ID */ #define BIPC_Alarm_Resource ((ResourceType)OS_MKOBJID(OBJECT_RESOURCE, 1U)) /* Resource ID */ #define BIPC_Non_Blk_Mutex ((ResourceType)OS_MKOBJID(OBJECT_RESOURCE, 2U)) /* Resource ID */ #define MCAPI_Event_Handler ((ResourceType)OS_MKOBJID(OBJECT_RESOURCE, 3U)) /* Resource ID */ #define NVRAM_RequestList ((ResourceType)OS_MKOBJID(OBJECT_RESOURCE, 4U)) /* Resource ID */ #define NVRAM_RequestQueue ((ResourceType)OS_MKOBJID(OBJECT_RESOURCE, 5U)) /* Resource ID */ #define OsResource_FG1 ((ResourceType)OS_MKOBJID(OBJECT_RESOURCE, 6U)) /* Resource ID */ #define RES_SCHEDULER ((ResourceType)OS_MKOBJID(OBJECT_RESOURCE, 7U)) /* Resource ID */ /* Events definition */ #define DSP_SPI_Rx_Ready ((EventMaskType)4U) /* Event mask */ #define DSP_SPI_Tx_Ready ((EventMaskType)2U) /* Event mask */ #define DSP_SPI_Wait_Complete ((EventMaskType)64U) /* Event mask */ #define MCAPI_NONBLK_EVENT ((EventMaskType)256U) /* Event mask */ #define MCAPI_TIMEOUT_EVENT ((EventMaskType)512U) /* Event mask */ #define MCAPI_Timeout_Task_Event ((EventMaskType)65536U) /* Event mask */ #define MCAPI_WAKEUP_EVENT ((EventMaskType)8U) /* Event mask */ #define NVRAM_Event ((EventMaskType)32U)   /* Event mask */ #define NVRAM_Queue_Event ((EventMaskType)131072U) /* Event mask */ #define RMDLControl_Event ((EventMaskType)2048U) /* Event mask */ /* Alarms identification */ #define DSP1_SPI_Wait_Alarm ((AlarmType)OS_MKOBJID(OBJECT_ALARM, 0U)) /* Alarm ID */ #define MCAPI_NonBlk_Sync_Alarm ((AlarmType)OS_MKOBJID(OBJECT_ALARM, 1U)) /* Alarm ID */ #define NVRAM_TimeoutAlarm ((AlarmType)OS_MKOBJID(OBJECT_ALARM, 2U)) /* Alarm ID */ #define NVRAM_TimeoutQueueAlarm ((AlarmType)OS_MKOBJID(OBJECT_ALARM, 3U)) /* Alarm ID */ #define OsAlarm_1ms ((AlarmType)OS_MKOBJID(OBJECT_ALARM, 4U)) /* Alarm ID */ #define OsAlarm_ASW_100ms ((AlarmType)OS_MKOBJID(OBJECT_ALARM, 5U)) /* Alarm ID */ #define OsAlarm_ASW_10ms ((AlarmType)OS_MKOBJID(OBJECT_ALARM, 6U)) /* Alarm ID */ #define OsAlarm_BSW_100ms ((AlarmType)OS_MKOBJID(OBJECT_ALARM, 7U)) /* Alarm ID */ #define OsAlarm_BSW_10ms ((AlarmType)OS_MKOBJID(OBJECT_ALARM, 8U)) /* Alarm ID */ /* Counters identification */ #define OsCounter_0 ((CounterType)OS_MKOBJID(OBJECT_COUNTER, 0U)) /* Counter ID */ #define OSMINCYCLE_OsCounter_0 ((TickType)0x1U) /* OsCounter_0 */ #define OSMAXALLOWEDVALUE_OsCounter_0 ((TickType)0xffffffffU) /* OsCounter_0 */ #define OSTICKSPERBASE_OsCounter_0 1UL     /* OsCounter_0 */ #define OS_TICKS2NS_OsCounter_0(ticks) (PhysicalTimeType)((ticks)*10000U) /*  */ #define OS_TICKS2US_OsCounter_0(ticks) (PhysicalTimeType)(((OSQWORD)(ticks))*10000ULL/1000UL) /*  */ #define OS_TICKS2MS_OsCounter_0(ticks) (PhysicalTimeType)(((OSQWORD)(ticks))*10000ULL/1000000UL) /*  */ #define OS_TICKS2SEC_OsCounter_0(ticks) (PhysicalTimeType)(((OSQWORD)(ticks))*10000ULL/1000000000UL) /*  */ #define OSMINCYCLE ((TickType)0x1U)        /* SysTimer */ #define OSMAXALLOWEDVALUE ((TickType)0xffffffffU) /* SysTimer */ #define OSTICKSPERBASE 1UL                 /* SysTimer */ #define OSTICKDURATION 10000UL             /* SysTimer */ /* Messages identification */ /* Flags identification */ /* Message callback prototypes */ /* scheduletable */ #define APP_STOP_SEC_CODE #include    "Os_memmap.h" #define OS_START_SEC_CONST_UNSPECIFIED #define OS_STOP_SEC_CONST_UNSPECIFIED #endif /* OSCFG_H */ Re: NXP RTOS OS_MKOBJID Error Description Resource Path Location Type expected ')' before 'OS_MKOBJID' chc_app line 131, external location: C:\subversions\branches\branch2\Proj1579_RTD_5_0_0\control\Mcal\DP1\Integrate\include\Os_cfg.h C/C++ Problem Unfortunately, the errors are still there. We are using following OS and RTD 5.0.0 versions: S32K3xx_NXP_RTOS_4_7_152_CODEDROP_0_4_1_D2312 SW32K3_S32M27x_RTD_R21-11_5.0.0 Re: NXP RTOS OS_MKOBJID Error The issue was resolved. I was actually replacing freertos and there were conflicts which eventually generated errors.  Re: NXP RTOS OS_MKOBJID Error Hello, Hmm, you included OS in RTD 5.0.0 project. Which version and which OS do you used? Are you sure it is compatible with RTD 5.0.0.? Have you check the release notes and compatibility? Best regards, Peter

Where can I download attached demo for AN14178(MCXNx4x Flash Command Example)? Hi NXP: I am currently trying to access the internal flash by MCXN FMU, and your documentation AN14178 has been very helpful. However, I am unable to find the download link for the demo project, could you please help confirm its location? Thank you! https://docs.nxp.com/bundle/AN14178/page/topics/introduction.html   Boot ROM|Booting | Flash MCXN Re: Where can I download attached demo for AN14178(MCXNx4x Flash Command Example)? No problem, thank you for your hard work! Re: Where can I download attached demo for AN14178(MCXNx4x Flash Command Example)? Hi @onejoeluo, We are still working on some final details to get the software package uploaded to the nxp.com website. It should be publicly available soon. Thank you for your patience and I apologize for the delay on this package. BR, Edwin. Re: Where can I download attached demo for AN14178(MCXNx4x Flash Command Example)? Hi Edwin, Any updates regarding the software package (flash_command_example.zip)? Re: Where can I download attached demo for AN14178(MCXNx4x Flash Command Example)? Hi @alanlow, You can find the AN14178SW package on the following link: https://www.nxp.com/docs/en/application-note-software/AN14178SW.zip