Type Fixup overflow in adc_int, to ix.2 type 1, at offset 0x10B C/C++ Problem Hi, I am porting old code from the Cosmic compiler for MC9S08DZ60ACLH to Code Warrior 11.1, which is the last version that supports this processor. I am getting a bunch of errors that I don't understand: Fixup overflow in adc_int, to ix.2 type 1, at offset 0x1D (filename)C/C++ Problem Can anyone tell me what this means? I'll post a screenshot of the whole list of errors. Lloyd Re: Type Fixup overflow in adc_int, to ix.2 type 1, at offset 0x10B C/C++ Problem Hi @lslonim, I'm glad to hear that you managed to replicate the outcome on your side. Thank you for bringing this to our attention, I will notify the internal team about this matter. Best Regards, Pablo Re: Type Fixup overflow in adc_int, to ix.2 type 1, at offset 0x10B C/C++ Problem Yes @Pablo_Ramos it worked and I very much appreciate you finding this out. But there never was a warning message from the compiler that @tiny was not supported. So I have wasted about 6 weeks because the compiler doesn't flag an error for this declaration. How can I report this so it will be fixed for the next person who has to port Cosmic code to NXP? Thanks, Lloyd Re: Type Fixup overflow in adc_int, to ix.2 type 1, at offset 0x10B C/C++ Problem Hi @lslonim, I noticed that some variables still use the @tiny keyword, which is not supported in CodeWarrior. After removing the @tiny keyword, I was able to successfully compile the project. Could you please help verify if you can replicate this behavior by removing the @tiny keyword on your end? Best regards, Pablo Re: Type Fixup overflow in adc_int, to ix.2 type 1, at offset 0x10B C/C++ Problem Thanks @Pablo_Ramos , can't wait to put this error behind me so I can start working on the operation of the product. Lloyd Re: Type Fixup overflow in adc_int, to ix.2 type 1, at offset 0x10B C/C++ Problem Hi, Thanks, I have received your private message with the files. I'm running some tests and will let you know of any progress. Best Regards, Pablo Re: Type Fixup overflow in adc_int, to ix.2 type 1, at offset 0x10B C/C++ Problem Hi @Pablo_Ramos , I sent you a private message with the projects attached. Thanks, Lloyd Re: Type Fixup overflow in adc_int, to ix.2 type 1, at offset 0x10B C/C++ Problem Yes @Pablo_Ramos I can send you the whole project. Can you tell me how to send it directly to you without posting it in public?  Thanks, Lloyd Re: Type Fixup overflow in adc_int, to ix.2 type 1, at offset 0x10B C/C++ Problem Hi @lslonim., Apologies for the delay in getting back to you. I’ve tried to replicate the issue on my end but haven’t been able to reproduce it. If you could share the project with me, that would be very helpful in identifying the problem more accurately. Looking forward to your response. Best regards, Pablo Re: Type Fixup overflow in adc_int, to ix.2 type 1, at offset 0x10B C/C++ Problem Hi @ZhangJennie , You were able to help me with another problem, can you take a look at this one? The error messages are a complete mystery to me. Thanks, Lloyd Slonim Re: Type Fixup overflow in adc_int, to ix.2 type 1, at offset 0x10B C/C++ Problem Hi @Pablo_Ramos I'm back on this project after time away. I still can't figure out anything that is causing these 14 errors. Can I send you the whole project zipped up for you to look at? This is a totally normal C function with no modifiers and no special linker commands. This is preventing me from doing any work on the project. Thanks, Lloyd Re: Type Fixup overflow in adc_int, to ix.2 type 1, at offset 0x10B C/C++ Problem The function is very simple. There are no special linker commands, and no special memory directives, it's just the default that the IDE uses. Can you tell me exactly what the error message means? void adc_init(void) /* init adc */ { ADCCFG = ADCCFG_VAL; APCTL1 = 0x08; APCTL2 = 0x00; APCTL3 = 0xE0; // analog input conversion sequence initiated by 1ms timer interrupt } Re: Type Fixup overflow in adc_int, to ix.2 type 1, at offset 0x10B C/C++ Problem Hi @lslonim, Could you help me with further explanation on your settings? Are you using noncontiguous memory areas? How are you declaring adc_init function? Could you share with me the section of code where the error is happening?

Cannot connect P&E MultiLink to MIMXRT1064: "Warning: Unable to go to background. Core is running" We are unable to connect from a MultiLink to the SWD interface of an i.MX RT1064 on a custom board design. The board is new and nothing has been loaded into the RT1064. Both blue and yellow LEDs on the MultiLink are on when plugged into the RT1064's SWD port and there is clock and data traffic on the SWD pins when trying to connect. We have also probed the RT1064 and verified that there is correct voltage on power rails and that its 24 MHz oscillator is running. We get the following warning repeated several times in P&E PROGACMP before it fails. We also cannot connect using MCUXpresso. "Warning: Unable to go to background. Core is running" We are pretty sure this is a hardware issue specific to this custom design. We have other custom RT1064 board designs that we can connect to using the same MultiLink unit. However, we are having trouble finding the cause of this. Any ideas on what else we can check? Re: Cannot connect P&E MultiLink to MIMXRT1064: "Warning: Unable to go to background. Core Hi @mayliu1  Problem solved. The hardware issue was resolved by using a different debugger tool. Marking this as resolved. Thank you for your assistance. Regards, Jason Re: Cannot connect P&E MultiLink to MIMXRT1064: "Warning: Unable to go to background. Core Hi @jlzm , Thanks for your updated information. The current status cannot determine whether the chip is operating normally or if there is a hardware design issue related to the SWD circuit. So I suggest you can use SEC Tool to boot the RT1064. If the RT1064 board can connect with PC by LPUART1 or USB1, it means the RT1064 chip work well, then we can continue find root cause. https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-secure-provisioning-tool:MCUXPRESSO-SECURE-PROVISIONING 1: set RT1064 board as serial downloader mode. 2:open SEC Tool, create a new workspace about RT1064 3: connect by LPUART1 or USB(depend on your bard design) Please try it. Best Regards MayLiu Re: Cannot connect P&E MultiLink to MIMXRT1064: "Warning: Unable to go to background. Core Hi @mayliu1 , We have checked the power-on sequence and verified it meets the requirement defined in the RT1064 datasheet. In our design, VDD_SNVS_IN, VDD_HIGH_IN, and DCDC_IN are shorted together. DCDC_PSWITCH is delayed to >1 ms after DCDC_IN is stable. The POR_B is held low during the power-up sequence. Afterwards, we can see that DCDC_LP is outputting about +1.15V. The 24 MHz oscillator circuit is also running. We have tried changing BOOT_MODE to boot into Serial Downloader mode. We get the same result where the debugger is unable to put the RT1064 into debug mode. We do not have J-Link debuggers available at the moment. However, it should be noted that this P&E MultiLink unit works fine on our other custom boards that also use RT1064 microcontroller. We have also done a thorough review of the design schematic to make sure that there are no other power supply rails driving any of the microcontroller pins prior to its being powered-on. Any other possible things that could cause the microcontroller to do this? Regards, Jason Re: Cannot connect P&E MultiLink to MIMXRT1064: "Warning: Unable to go to background. Core Hi @jlzm , Thanks for your updated information. First, I suggest you check whether your board power on is success. Please check the power on sequence is correct as the following Fig show. https://www.nxp.com/webapp/Download?colCode=MIMXRT105060HDUG Please note that DCDC_PSWITCH need be delayed more than 1 ms to switch on the internal DCDC. Second,  did you try to set your board in serial downloader mode, and use LPUART1 or USB to connect your PC and board by using SEC Tool. https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-secure-provisioning-tool:MCUXPRESSO-SECURE-PROVISIONING If you can connect your bard by UART1 or USB, it means your board power on is success. Third, did you try to use J-link device to debug by use SWD(default SWD) Wish it helps you. If you still have question about it, please kindly let me know. Wish you a nice day! Best Regards MayLiu Re: Cannot connect P&E MultiLink to MIMXRT1064: "Warning: Unable to go to background. Core Hi @mayliu1, Thank you for the reply.  Using oscilloscope, we have verified that the reset pin (POR_B) is pulled low immediately on power-up. It remains low until after VDD_SNVS_IN, DCDC_IN, and DCDC_PSWITCH finish ramping up to 3.3 V. This seems normal as we are using the internal DC-DC. SWD signals are stable with clean transitions between high and low logic levels. I am not certain if the data being transmitted is correct or not. We have tried all SWD debug speed options that are available in the P&E tool. The results are the same. We have checked that BOOT_MODE logic levels are correct. We tried both, BOOT_MODE=01 and BOOT_MODE=10 (serial downloader and internal flash boot), but results are the same. All BOOT_CFG pins are pulled down. Do you have any other ideas as to what else should be checked? Regards, Jason Re: Cannot connect P&E MultiLink to MIMXRT1064: "Warning: Unable to go to background. Core Hi @jlzm , Thank you so much for your interest in our products and for using our community. I suggest you check the following points: 1：Please check if the Reset pin is properly pulled low to reset the RT1064 chip, Use an       oscilloscope to confirm the reset pulse duration and stability.     Please  use an oscilloscope to check whether the SWD signals are stable and normal. 2:   Please try to lower the speed of SWD clock speed? (RT1064 default debug is SWD) 3:   Did you check your BOOT MODE[1:0] pins and BOOT CFG pins setting correctly?         Best Regards MayLiu

S32G3 Bootloader launch core0 and Core1 hi NXP erperts I am currently debugging a bootloader to bring up core0 and core1. The core0 can be released from reset and can be lanutched, but core1 fail to start running. Using the UDE debug tool, core1 can be successfully brought up. In my bootloader EB Configuration, I have already configured the reset handler address and load address for both core0 and core1. How should I proceed with further debugging? how can i debug the bootloader? i am also test the IPCF_Example_multi_instance_S32G399A project, but this project the core0 and core1 both failed. thanks. Re: S32G3 Bootloader launch core0 and Core1 Hello, @xlfd_1981  I feel sorry for your inconvenience. Commonly, in this community board, we support the basic usage of all software packages, hardware specifications provisioned by NXP, also, we support issues directly found in using demo/sample code within  the software packages, etc. For specific or customization requirement, we usually suggest raising support ticket via the support.nxp.com, since it is private channel, and is more convenient for sharing the code/project. Currently, there are not such kind of demo which could directly support your requirement, only the code in AN1350 is a little similar but it also involved A53 cores, it may be possible to disable the A53 part to simulate your requests, not sure if you have referenced it. For your status, in order for help you directly for debugging your issues, I suggest directly raising a private ticket via support.nxp.com, then sharing your bootloader and applications(M7_0 and M7_1), we could help to check it. BR Chenyin Re: S32G3 Bootloader launch core0 and Core1 NXP experts It's been many days and I still haven't received a response to my question. Let's keep it simple now: please provide a demo program that can start both core0 and core1 using the bootloader. I need both the bootloader project and the application project. Also, please let me know if there are any special requirements for generating the blob file. I will use your demo to verify whether core0 and core1 can be started properly. The issue I'm facing now is that the image for core1 can be loaded, but core1 just won't start. I don't know whether the problem is with the startup code or if core1 simply isn't being triggered at all. There are also no registers available to check if it started. Please help me by providing a demo and suggestions. This is quite urgent. Thank you very much. Re: S32G3 Bootloader launch core0 and Core1 Hello, @xlfd_1981  Thanks for your reply. May I know how you creating the IVT, have you included DCD while trying booting from the QSPI? I am not very sure of your design, you are using the bootloader(M7_0) to load core0.bin and core1.bin(IPCF instances) to the corresponding core, or other kind of implementation? BR Chenyin Re: S32G3 Bootloader launch core0 and Core1 chengyin i update my debugging results below, It might be related to the bootloader. When debugging with UDE, the ELF file is downloaded into memory and we can see that the Core1 region has valid data. However, after a power cycle — where the system boots from Flash running the bootloader code — and using UDE to observe the Core1 memory area, we find that the data has been cleared to zero. Could this be caused by the bootloader? Regards Re: S32G3 Bootloader launch core0 and Core1 chengyin In addition, my IPCF codes, please check, it will be compiled to core0.bin and core1.bin  Re: S32G3 Bootloader launch core0 and Core1 Chenyin We are currently working on the RDB3 platform, developing a bootloader based on your IPCF Multi-Core Demo (v4.10.0). We're encountering an issue during the boot process of Core1 and would appreciate your assistance. Current Setup: Our bootloader is developed based on your demo project(UM_BOOTLOADER_Rev_2023.02) and configured via EB. When debugging with UDE: Data exists in both Core0 and Core1 memory regions  Code successfully jumps to Core0's Reset_Handler  However, we noticed that: The SRAM area used by Core1 (e.g., 0x34680000) gets cleared to zero  As a result, Core1 fails to start  Questions: Who triggers this SRAM clearing? Is it caused by UDE? Or is it part of the reset behavior? Could it be due to some initialization code in the bootloader? In addition, in the function Sys_StartSecondaryCores(), we set: IP_MC_ME->PRTN0_CORE1_ADDR = 0x34780000; Could you please confirm what this address should point to: Should it be the load address of the Core1 image in SRAM (i.e., the location of .intc_vector)? Or should it be the vector table offset (VTOR)? Our linker script shows that .intc_vector is located at 0x34780400, while the image starts at 0x34680000. Thank you very much for your support! If needed, I can provide .map files, .ld scripts, or screenshots for further analysis. Best regards, Re: S32G3 Bootloader launch core0 and Core1 Hello, @xlfd_1981  Thanks for your post. Would you mind providing more information about your test? 1. It is done on a S32G3 custom board or RDB3/EVB3 from NXP? 2. Where is the bootloader from? it is a custom one or from NXP, if from NXP, which version? 3. It is mentioned that core0&1 are used, may I know if they are M7_0 and M7_1 or other combination? Commonly, the bootloader is running on the M7_0, it could be debugged directly with your debugger, not different from other M7 applications. BR Chenyin

I have a S32K344 with a S32KX4EVB-T172 I have followed all instructions from Getting Started with the S32K3X4EVB-T172 Evaluation Board for Automotive General Purpose | NXP Semiconductors  and I am now in the Build, Run phase. Compilation of the code with the Port Example for S32K344 was successful but for some reason, when going into debug, I am facing these errors: UsageFault: A coprocessor access error has occurred. The coprocessor is disabled or not present. UsageFault: An instruction executed with an invalid EPSR.T or EPSR.IT field. BusFault: A bus fault has occurred during lazy floating-point state preservation. Possible BusFault location: 0xF87AF003. BusFault: A bus fault has occurred on exception entry. MemManage: The processor attempted a load or store at a location that does not permit the operation. MemManage: The processor attempted an instruction fetch from a location that does not permit execution. HardFault: A fault has been escalated to a hard fault. HardFault: A BusFault has occurred on a vector table read during exception processing. Note: I have the FreeMaster Serial Communication Driver installed. The debugger initially would show: However, upon clicking either Resume/ Step Over, these errors would then occur. Any advice will be very much appreciated.  

IMX8DXL flashing issue Hello NXP team, Our custom board using the i.MX8DXL processor, one of our customers reported a flashing issue when flashing the device using a Windows system. The error appears to be USB-related; however, we have been unable to reproduce the issue on our end. Do you have any suggestions or potential causes that could be related to the customer's laptop? Below is the logs UUU Tool\iW-PRGOT-R3.0-REL1.0-TelematicsGateway_Linux6.1.22_UUU> .\uuu.exe .\iW-PRGOT-R3.0-REL1.0-B0-iMX8DXL_Linux_6.1.22_UUU.uuu uuu (Universal Update Utility) for nxp imx chips -- libuuu_1.4.243-0-ged48c51 Success 0 Failure 1 2:7 1/ 0 [Failure open usb device ] U-Boot 2023.04-iwg27_6.1.22_2.0.0_1.1+gb6bf789da2 (Mar 20 2024 - 05:40:28 +0000) CPU: NXP i.MX8DXL RevB A35 at 1200 MHz at 34C Model: iW-RainboW-G46M-i.MX8DXL-OSM Board: iWave iMX8DXL IWG46M OSM Boot: USB DRAM: 2 GiB Core: 169 devices, 25 uclasses, devicetree: separate MMC: FSL_SDHC: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Board Info: BSP Version : iW-PRGOT-SC-R3.0-REL1.0-Linux6.1.22 SOM Version : iW-PRGWZ-AP-01-R3.80000000 CPU Unique ID : 0x301E880E8293EE1C Carrier Board Version : iW-PRGJJ-AP-01-RX.X(Custom) BuildInfo: - SCFW 6638c032, SECO-FW 80649c52, IMX-MKIMAGE 5cfd2180, ATF 8103e82 - U-Boot 2023.04-iwg27_6.1.22_2.0.0_1.1+gb6bf789da2 - V2X-FW 75e63de2 version 1.2.1 switch to partitions #0, OK mmc0(part 0) is current device Detect USB boot. Will enter fastboot mode! Net: Could not get PHY for FEC0: addr 4 Could not get PHY for FEC0: addr 4 Get shared mii bus on ethernet@5b050000 eth1: ethernet@5b050000 Fastboot: Normal Setting bus to 3 Valid chip addresses: 17 51 6A 6B 74 77 Boot from USB for mfgtools *** Warning - Use default environment for mfgtool s , using default environment Run bootcmd_mfg: run mfgtool_args;if iminfo ${initrd_addr}; then if test ${tee} = yes; then bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; else booti ${loadaddr} ${initrd_addr} ${fdt_addr}; fi; else echo "Run fastboot ..."; fastboot auto; fi ; Hit any key to stop autoboot: 0 ## Checking Image at 83100000 ... Unknown image format! Run fastboot ... auto usb 1 Re: IMX8DXL flashing issue Hi @Tanushree  Sorry, I talked with our internal team, For now,  there is no solution about uuu can not work on win10 but can work fine on win11 and Ubuntu OS. The best way is using Ubuntu or Win11 OS run the uuu tool. B.R Re: IMX8DXL flashing issue Hi @pengyong_zhang  Is it possible to flash one i.MX8DXL device using another i.MX8DXL device? Has anyone tried this approach before? We would appreciate any suggestions or guidance you may have.  The observations with UUU are the same as what you shared in the last reply. Re: IMX8DXL flashing issue Hi @Tanushree  Please try use below uuu version try the test on windows10 OS: https://github.com/nxp-imx/mfgtools/releases/download/uuu_1.5.201/uuu.exe B.R Re: IMX8DXL flashing issue Hello @pengyong_zhang  In Device Manager, the device is listed under "Other devices" as "USB Download Gadget." Please let us know the specific driver that needs to be installed so we can proceed with testing. Re: IMX8DXL flashing issue Please try uninstall the USB driver and re install it. It is very strange, i have never meet this problem before. Re: IMX8DXL flashing issue Yes, we tried that as well, but it still fails with the error: 'Failed to open USB device'. Re: IMX8DXL flashing issue please try use the uuu -b command flash the image to your board. Re: IMX8DXL flashing issue Hello, Please see below — it has detected Connected Known USB Devices         Path     Chip    Pro     Vid     Pid     BcdVersion         ==================================================         1:1      MX8DXL  SDPS:   0x1FC9 0x0147   0x0003 Re: IMX8DXL flashing issue Hi @Tanushree  Can you find your board device when you type thre uuu -lsusb command? B.R Re: IMX8DXL flashing issue Hello @pengyong_zhang  Please find the attached failed log of windows 10. Re: IMX8DXL flashing issue hi @Tanushree  the windows 10 should not the root cause, please share the fail log on your windows10 OS. B.R Re: IMX8DXL flashing issue I reviewed the release notes for the Linux 6.1.22 kernel version and noticed that it recommends using UUU version 1.5.21. Currently, I am using the following specific UUU version as shown below:  While flashing works correctly on Windows 11 and Ubuntu 20.04 or later, it fails on Windows 10. However, I did not find any mention of supported or unsupported Windows versions in the release notes—only Ubuntu 20.04 is mentioned. Re: IMX8DXL flashing issue hi @Tanushree  Please share your UUU fail log on Windows10 OS. And what is your uuu version? please use the latest uuu version. B.R Re: IMX8DXL flashing issue We are encountering an issue where Kernel 6.1.22 is not flashing on Windows 10, whereas it flashes successfully on Windows 11. Could this be due to a lack of support for Windows 10? Additionally, we recently migrated from Kernel version 5.15.52 to 6.1.22. The UUU tool was functioning correctly with version 5.15.52 on Windows 10. Re: IMX8DXL flashing issue Hi @Tanushree  There is no specially about Windows setting of UUU. B.R Re: IMX8DXL flashing issue Hello @pengyong_zhang  Thank you for the reply. There doesn't appear to be any issue with the UUU script, as the same procedure works on some laptops. We're using our own custom build. Are there any specific Windows settings that could affect UUU tool flashing or UMS detection? Regards, Tanushree Re: IMX8DXL flashing issue Hi @Tanushree  What is your result if you run the uuu -b emmc_all <.wic>  command？ Do not choose the uuu script file flash. B.R

56F8300 编程软件 你好，需要读出 56F8323 的固件。 我能否使用《56800E 闪存编程器用户指南》？   Re: 56F8300 programming software 我添加了一些克隆 MCU 的信息。你只需要读出 568323 中的 2 个文件： 1) flash 568323_flash.cfg 程序 Flash.s-rp0x 00000:0 x03fff-p0x378 2) flash 568323_flash.cfg 启动 flash.s-rp0x 20000:0 x20fff-p0x378 据我所知，数据闪存区域 (0x01000 0x01FFF) 不是那么需要它 Re: 56F8300 programming software 你好@Fduch，我很高兴听到这个消息。 如有任何新问题，欢迎创建新帖。 Re: 56F8300 programming software 终于解决了！需要安装 CodeWarrior for 56800E 数字信号控制器 v8.3.exe+ FLSHPROGRAMMER_V1.2_WIN32.exe，并移动到如下目录： C:\Program Files\ Freescale\ FlashProgrammer v1.2\ bin > fflash 568323_flash.cfg 1623 0_p.s-rp0x 0:0 xfff-s-p0x378 56800E Flash 程序员 v1.1 程序 运行 时间：2025 年 7 月 21 日星期一 14:45:06 连接到本地 CCS 服务器配置为在 LP T1 端口使用并行命令转换器使用配置文件：568323_flash.cfg 配置文件中定义的 3 个闪存单元。 芯片 ID：0x01f4001d 核心 ID：0x02211004, 1 - 普通模式 将设备置于调试模式，请稍候... 读取内存：****************，完成 将设备重置为用户模式... 初始化：2907 毫秒，读取内存：3297 毫秒，退出调试：921 毫秒，总计：7125 毫秒 Re: 56F8300 programming software 操作系统是 Win XP。我也没有在上面安装 CodeWarrior。只需在 56800E Flash Programmer.exe& FFLASH.exe 档案中下载 56800E Flash Programmer 用户指南。是否需要安装 CodeWarrior？ Re: 56F8300 programming software 您的 56F8300 编程软件是什么版本，它是哪个版本的 CodeWarrior 插件？此外，您的 Windows 操作系统是什么？ 我注意到日志中有" CCCSClient::Open：Connection refused" 。 可能与中央案例研究有关，请参考。 Windows 7/10：在适用于 DSC 的 CodeWarrior 上使用 USB TAP-恩智浦社区 Re: 56F8300 programming software 下面是正确的 CMD 和我与你的 *cfg： C:\JtagV2>fflash 568323_flash.cfg 16230_x.S -rx0x0:0xfff -p0x378 56800E 闪存编程器 v1.0 程序运行于Mon Jul 21 13:48:18 2025 CCCSClient::Open：拒绝连接 C:\JtagV2> Re: 56F8300 programming software 您好，我在 Codewarrior v8.3 中找到了另一个 56F8323 配置文件，能否请您再试一次？ Re: 56F8300 programming software 嗯，有些行动： C:\JtagV2>flashJtagLoader 568323_flash.cfg 16230_x.S -rX0x0:0xfff -p0x378 DSP56F801x 闪存加载器。编译于 2006 年 11 月 3 日 18:00:59。 版本 Alpha 2.0 (c) Freescale, TIC, 2006 by William Jiang 部分版权 2000-2002，Zloba Alexander I/O 端口驱动程序启动 使用地址为 0x378 的打印机端口。 芯片 ID：0x01f4001d 在编程中重置部件后，JTAG 路径现在如下所示： JTAG IR 路径长度：8 JTAG DR 路径长度：1 (BYPASS) 核心 ID：0x02211004 核心状态：0x0d - 调试 在编程中选择该部件的核心 TAP 后，JTAG 路径现在更改了！！！ JTAG IR 路径长度：4 JTAG DR 路径长度：1 (BYPASS) 调试请求状态：0xd - 调试 启用 OnCE 状态：0xd - 调试 启用 OnCE 成功，目标芯片进入调试模式 修剪松弛振荡器成功！，调整值 =0x026c 芯片不安全 闪存配置文件命令被忽略：target_code_sets_hfmclkd 1 闪存配置文件命令被忽略：set_hfm_config_base 0x003FF7 闪存配置文件命令被忽略：set_hfm_programmer_base 0x2F800 闪存配置文件命令被忽略：set_hfm_prog_buffer_base 0 闪存配置文件命令被忽略：set_hfm_prog_buffer_size 512 配置文件中定义的 3 个闪存单元。 下载代码失败，验证 PRAM 基地址 C:\JtagV2> 怎么了？ Re: 56F8300 programming software 又见面了我又回来了......我看到我需要 flash.cfg 文件来进行操作。但 56800E Flash Programmer.exe 中没有任何 *cfg 文件，在哪里可以找到？如果要更精确一些 - flash8323.cfg Re: 56F8300 programming software 你好@Fduch、 由于这是一个 LPC 频道，如有任何其他与 DSC 相关的问题，请帮助在数字信号控制器 - 恩智浦社区上创建一个新帖子。 预先感谢您的理解。 BRs， 西莱斯特 Re: 56F8300 programming software 以后肯定会有问题。为此需要进行一些调查 Re: 56F8300 programming software 你好@Fduch、 感谢您的支持。 是的，您可以使用《56800E 闪存编程器用户指南》从 56F8323 读取存储器。 请下载 56F8XXXFP 软件： 适用于 mc56f832x 和 mc56f812x DSC 的 EVK | 恩智浦半导体 然后打开文件 56800EFPUG，并按照 "2.2.3 查看内存 "部分的步骤操作： 打开文件 56800EFPUG，并按照 "2.2.3 查看内存 "部分的步骤操作。 希望能帮到你。 BRs， 西莱斯特 ------------------------------------------------------------------------------------------------------------------- 注：如果本帖回答了您的问题，请点击"ACCEPT AS SOLUTION" 按钮。Thank you! -------------------------------------------------------------------------------------------------------------------

PN7642 OM27642EVK SDK Keil uVision I'm looking for SW to build SDK for PN7642 ARM Cortex M-33 core. I have OM27642EVK development kit and would like to connect in with Keil uVision. Debugger: ULink Pro Re: PN7642 OM27642EVK SDK Keil uVision Hallo Daniel,   thank you for the link. I was able to build the SDK and download it, also the stand-alone examples. What is now missing is the Software Pack for PN7642     I tried to download and install it but I cannot reach the site: 403 Forbidden https://mcuxpresso.nxp.com/cmsis_pack/repo/   Can you please provide the Pack/give me rights to download it?   Thank you for your support, Radoslaw Re: PN7642 OM27642EVK SDK Keil uVision Hello @RadoslawTomasik, Good Day! Thank you for your interest in our products. We do have a PN7642 SDK for Keil available for download at SDK Builder | MCUXpresso SDK Builder (select "Keil MDK" in the "Toolchain/IDE" field), however, please consider that as this is quite old, the recommended alternative is to develop using the SDK v02.15.003 for the MCUXpresso IDE. My best regards, Daniel

When I create a Device Tree, I get "Missing #address-cels" in the imx7s.dtsi file Hello. The imx7s.dtsi file is included to create the Device Tree. A warning message appears saying "imx7s.dtsi: Missing #address-cels in interrupt provider". imx7d.dtsi gives the warning "usbphynop2: missing or empty reg/range property".   usbphynop2: usbphynop2 {       compatible = "usb-nop-xceiv";       clocks = <&clks IMX7D_USB_PHY2_CLK>;       clock-names = "main_clk";   }; Why are these warnings appearing if this was made for the SABRE board? Thank you. Re: When I create a Device Tree, I get "Missing #address-cels" in the imx7s.dtsi file You are welcome, any question contact us freely. Wish you have a nice day Re: When I create a Device Tree, I get "Missing #address-cels" in the imx7s.dtsi file Thank you. I understand that the warning can be ignored. I'm still debugging, so I haven't checked the warning part yet. Anything without warnings is working fine. If I have any problems debugging the warning part, I'll ask again. Best regards. Re: When I create a Device Tree, I get "Missing #address-cels" in the imx7s.dtsi file For the warnings you can ignore it, are you met the error in your side?

IPパワーダウン例外制御レジスタ2、3、4、6の説明 次の SOC リファレンス マニュアルでは、IPPDEXPCR0、IPPDEXPCR1、および IPPDEXPCR5 の説明のみが提供されているようですが、DTS では 7 つのレジスタがリストされています。これらのレジスタの説明はどこにありますか? https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi rcpm: ウェイクアップコントローラ@1e34040 { 互換性 = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+"; レジスタ = <0x0 0x1e34040 0x0 0x1c>; #fsl、rcpm-wakeup-cells = <7>; リトルエンディアン; }; ftm_alarm0: rtc@2800000 { 互換性 = "fsl,lx2160a-ftm-alarm"; レジスタ = <0x0 0x2800000 0x0 0x10000>; fsl、rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 割り込み = ; }; QorIQ LX2160A リファレンスマニュアル LX2120AおよびLX2080Aをサポート（Rev. 1、2021年10月） Re: description of IP powerdown exception control register 2, 3, 4, 6 こんにちは、 fsl-lx2160a.dtsi に記載されているように、レジスタ IPPDEXPCR4 (0x1e34050) に 0x4000 を書き込むと、スリープ中にフレックス タイマーの電源が切れるのを防ぐことができることを確認しました。残念ながら、NXP は隠しレジスタに関する文書を共有できません。ただし、この機能は LSDKUG に文書化されています。関連する章を添付しましたので、お役に立てれば幸いです。 よろしくお願いします。 Re: description of IP powerdown exception control register 2, 3, 4, 6 問題は、ls2060ARDB の場合、サスペンド状態 (suspend-to-ram 機能) 中に FTM モジュールの電源を維持するように PMU を構成する必要があることです。設定によると、これはIPPDEXPCR4（以下の設定をご確認ください）レジスタでのみ実行可能なため、IPPDEXPCR4は内部テスト用ではないと思われます。少なくとも、これはsuspend-to-ram機能の依存関係です。別のサポート担当者は、LS2160A RDBでsuspend-to-ramが動作することを確認済みだと主張しています。これらのレジスタの説明を明確にして、ご提供ください。 fsl、rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; Re: description of IP powerdown exception control register 2, 3, 4, 6 こんにちは、 正解です。RM (リファレンス マニュアル) には、レジスタ IPPDEXPCR0、IPPDEXPCR1、および IPPDEXPCR5 のみが記載されています。これは、LX2160A に適用可能なレジスタはこれらだけだからです。残りのレジスタは内部テスト目的のみを目的としており、お客様が使用できるように文書化されていません。これらは DTSI ファイルに含まれていますが、内部参照専用です。 Re: description of IP powerdown exception control register 2, 3, 4, 6 こんにちは、 現在これに取り組んでいますので、更新があればお知らせします。 よろしくお願いします。

S32K344 eMIOS ICU信号測定デューティサイクル100% こんにちは、 eMIOS ICU ドライバを使用して、入力 PWM 信号のデューティ サイクルを測定しようとしています。 私はRTD600、S32DS 3.6.2を使用しています。S32K3X4EVB-T172-RevB 評価キットを使用します。 私の立ち上げの目的のため、出力ピンを 50% のデューティ サイクルで PWM 信号として切り替えるだけの PIT を使用しています。オシロスコープを使用して出力動作が意図したとおりであることを確認しました。 プロジェクトをデバッグ モードで実行すると、検出されたデューティ サイクルは 100%、アクティブ時間と周期時間は 65536 のみが表示されます。その他の値はありません。 参考までに、設定のスクリーンショット、コードのスニペット、プロジェクト自体を添付します。 私は、 https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-eMIOS-DS3-5-RTD500/ta-p/1992245?profile.language=en 同じように。 SAIC モードと IPWM モードを試しましたが、どちらも効果がありませんでした。(提供されている例からプロジェクトを実行してみましたが、ICUピンからPWM信号を切断しても、読み取り値はすべて100%のデューティサイクルでした) 誰かが私を助けてくれて、私が何を間違っているのか教えてくれるとありがたいです。 Re: S32K344 eMIOS ICU signal measurement duty cycle at 100% こんにちは@PetrS 、 ご返信ありがとうございます！ あなたのアドバイスに従って、MCL で共通 eMIOS バスを構成しましたが、SAIC モードでは適切な読み取り値が得られましたが、IPWM モードでは得られませんでした。 たとえば、IPWM モードで 100 回の読み取りを行った場合、最初の 73 回程度の読み取りは 100% のデューティ サイクル、74 番目の読み取りは 340%、残りは 24% になりますが、これはやや不明瞭な値であり、意味を理解できません。説明のために、IPWM モードでは、毎回 Emios_Icu_Ip_GetDutyCycleValues を呼び出す前に Emios_Icu_Ip_GetPulseWidth を呼び出しており、ICU 構成で IcuSignalMeasureWithoutInterrupt が有効になっています。 SAICモード（IcuSignalMeasureWithoutInterruptが無効で、Emios_Icu_Ip_GetPulseWidthを呼び出さない）では、49～50%前後で推移する適切な値が得られます。 どちらの場合も、返された periodTime が 0 の場合、Emios_Icu_Ip_GetDutyCycleValues の結果を無視します。 IPWMモードに関して何か間違っているのでしょうか？eMIOS ICUとして設定した特定のチャネルに何か制限があるのでしょうか？ これまでのサポートに大変感謝しています。少なくとも SAIC モードが動作しているようで嬉しいです! Re: S32K344 eMIOS ICU signal measurement duty cycle at 100% こんにちは、 チャネルの内部カウンターが開始されていません。これは、モジュールの GBTE ビットが設定されておらず、チャネルがプリスケール クロックを使用しているために発生します。したがって、グローバル プリスケーラも有効にする必要があります。 理想的には、MCL設定でeMIOS共通サポートを有効にします。 コード内で Emios_Mcl_Ip_Init(INST_EMIOS_0, &Emios_Mcl_Ip_Sa_0_Config) を呼び出します。 BR、ペトル Re: S32K344 eMIOS ICU signal measurement duty cycle at 100% NXP またはコミュニティの誰かがこの件で私を助けてくれることを願っています。残念ながらまだここに留まっている

SPD and DMA modules are used at the same time, a hardfault will occur Hi team, I encountered some problems when testing SPD. As long as I use DMA and SPD modules at the same time, the program will enter hardfault. The strange thing is that I didn't even include these drivers, but I still encountered such errors. Attached is the test project, which is actually the routine in S32 DS （S32 DS V3.5 + RTD 5.0.0+SPD 1.0.5）, adding SPD components and DMA. thanks for you help always. BR,jim. RTD S32_CONFIG_TOOL S32DS Safety_SW Re: SPD and DMA modules are used at the same time, a hardfault will occur Hi @cuongnguyenphu  one more finding: RTD Port example enables MPU in the startup, when you disable MPU, the bus fault is not happening. This is instruction causing the issue: as you can see it resides in MPU Region 6 where I don't see any issue with that. If I do write into the address 0x2040938 via Lauterbach it's not a problem. Anyway disabling MPU helped, so not sure what's going on now. I'm leaving for vacation today so I can't support until 1st August. Kind Regards, Radoslav Re: SPD and DMA modules are used at the same time, a hardfault will occur Hi@ @cuongnguyenphu  Thanks for your help, is there any way we can avoid this problem or how to explain it to customers? Or is this a bug? Re: SPD and DMA modules are used at the same time, a hardfault will occur Hi @cuongnguyenphu , when adding the SAF drivers, I'd add correctly SAF mem sections into linker file (not relying on default placement) and maybe examine size of regions if there is enough reserve. I can now confirm just the fact that original SIUL2 example + SAF does work, but + DMA doesn't. Kind Regards, Radoslav Re: SPD and DMA modules are used at the same time, a hardfault will occur Hi @RadoslavB , I see the hardfault happend when I add eMCEM and SafetyBase to our working project, even we doesn't call any APIs from it SPD APIs. When deeper investigate, I see it raised a Bus fault error when trying to access 0x20430938. I'm wonder did I missed any steps when include eMCEM and SafetyBase module? Below is my debugging screenshot and .map file 1. Add eMCeM and SafetyBase: 2. SBC->BFAR: 3. Program counter when Hardfault: 4. Map file: Re: SPD and DMA modules are used at the same time, a hardfault will occur Hi @Senlent  Yes I can reporduce the issue at my side. it jumped to hardfault when trying to access exclusive area. It seems that when adding SPD/DMA, there're memory protection of the address exclusive area Re: SPD and DMA modules are used at the same time, a hardfault will occur Hi@ cuongnguyenphu Thank you very much for your help, could you please let me know if you can reproduce the problem? Re: SPD and DMA modules are used at the same time, a hardfault will occur Hi @Senlent  Let me check this issue and feedback to you soon

i.MX RT1060 の Zephyr で MCUboot RAM ロードを使用する 現在、i.MX RT1060 用の Zephyr で MCUboot を使用して RAM の読み込みを動作させようとしていますが、ブートローダーでイメージを起動できません。これまでに行った手順は次のとおりです。 「samples/sysbuild/with_mcuboot/sysbuild.conf」に、SB_CONFIG_MCUBOOT_MODE_RAM_LOAD=y を追加しました。 samples/sysbuild/with_mcuboot-sysbuild/mcuboot.conf で CONFIG_SRAM_SIZE=128 を設定します。 生成された.configファイルを見ると、CONFIG_SRAM_BASE_ADDRESS=0x80000000 となっており、正しいようです。しかし、MCUboot はアプリケーションを起動する代わりに、「起動可能なイメージが見つかりません」というエラー メッセージを報告します。 私は Zephyr リリース 4.1.0 を使用しています。 他に何か変更する必要はありますか? ありがとうございます。 イルディコ Re: Using MCUboot RAM loading with Zephyr for i.MX RT1060 参考までに@ildiko_pocsaiと@Omar_Anguiano 、 この記事には、RT1060 EVK で RAM ロードを有効にするための手順と Git パッチが記載されています。https ://community.nxp.com/t5/Zephyr-Project-Knowledge-Base/MCUboot-RAM-Loading-with-Zephyr/ta-p/2139539を参照してください。 よろしくお願いいたします。 Re: Using MCUboot RAM loading with Zephyr for i.MX RT1060 Secure Provisioning Tool や MCUBootUtility などのツールを使用してイメージに DCD を追加し、生成されたバイナリから DCD を追加できます。まだ dcd がない場合は、ConfigTools で生成できます。 よろしくお願いします、 オマール Re: Using MCUboot RAM loading with Zephyr for i.MX RT1060 こんにちは、オマールさん。 ご返信ありがとうございます。はい、外部 SDRAM を使用したいと思います。Zephyr でイメージに DCD を追加する方法を教えてください。私は、MCUboot と、MCUboot imgtool を使用してイメージに署名するアプリケーションをビルドするために、Zephyr の sysbuild ビルド システムを使用しています。しかし、DCD を追加するための imgtool のオプションが見つかりません。 ありがとうございます。 イルディコ Re: Using MCUboot RAM loading with Zephyr for i.MX RT1060 こんにちは。お元気でお過ごしでしょうか。 アドレス0x80000000 は外部 SDRAM 用です。この SDRAM にイメージをロードしますか? そのCASEは、イメージに DCD を追加して、ブート時に SDRAM が初期化されるようにする必要があります。SOすれば、コードが SDRAM に移動されたときに実行できるようになります。 よろしくお願いします、 オマール

[enersys][Nextracker]Regarding the AES key provisioned via EL2Go Hello Experts, There are some follow ups from Enersys and Nextracker, Please kindly refer to the following for details. Enersys: Well, that’s good news that this is a bug that can be fixed. However… it may be too late for us to use this key, as we already have devices provisioned and out in the field. Is there any way to apply this read policy after the fact? I did see some policy-related commands in the ssscli documentation, but I’m not sure how to use them. Nextracker:  Reading the response, I am a bit confused on current status – We already flashed close to 1000 elements, are these recoverable? Or do we need to scrap them all? Also, am I understanding correctly that there is nothing we can do on our side to fix this (i.e. we are blocked until El2go it fixed by NXP)? Last but not least, this response worries me of El2g0 maturity – using AES and secure provisioning seems to me  pretty basic SE functionality, if I understand correctly the response, it seems this was never used by any customer?? As I would expect this bug to arise for anyone trying to use it. I have told them the policy can not be updated unless they delete the AES key and re-provision them manually or via EL2Go, but wondering if there is any better solution for this case, would you please advise?  Best Regards, Kan Re: [enersys][Nextracker]Regarding the AES key provisioned via EL2Go Hi Kan,  like discussed earlier one option is provisioning new aes key with correct policies to new object id. For other option(more details), where, if we want to use already provisioned aes key (which cannot be read), this example code can be used.  Please find below two files: one is AES_key_without_read.cpp (changed to .c format as .cpp is not allowed to upload here) and other is aes_key_without_readtype_logs.txt.   If you use the code as mentioned in AES_key_without_read.cpp, it will just use checkobjectexist APDU and cipheroneshot apdu and will not use the readtype apdu as shown in aes_key_without_readtype_logs.txt.   So, using this you can use the already provisioned key without reading it.   One of the two options can be used. Kind regards, Parth Re: [enersys][Nextracker]Regarding the AES key provisioned via EL2Go Hi @nxg11900 , Thanks for the info! I will share with the customer.  Best Regards, Kan Re: [enersys][Nextracker]Regarding the AES key provisioned via EL2Go Hello Kan, At Elgo portal now Read policy can be selected, this issue is fixed. It was small error, where for this one particular product type(se050) and for this one particular secure object, read policy was not not selectable and which is fixed now.  It is not possible to change policy of secure object once it's already created in El2go or provisioned in device, with certain policies. And this ssscli policy related commands (for Enersys) are to create policy file which can be used/assigned  to an object when we create an object or display policy(referred by dump in MW doc: AN13030).  These two options can be suggested for now, for the devices which are already in field: 1. Creating new AES key with right policies and provisioning it to a different object id. 2. for the already provisioned key instead of using "sss api" use "se05x api"( which is one layer below sss) and not read the AES secure object. Kan, i will also see if we can work with sss api also for the already provisioned AES key. Kind regards, Parth

imxrt1061 Hard fault points to clock API call Good day I use imxrt1061 running ThreadX RTOS in my project. During the stability runs we occasionally can catch hard fault. It is hard to reproduce it and it occurs under unknown circumstances. It may occur approximately one time per 5000 test runs. Usually it happens after controlled reboot - all activities are done, reboot initiated, main application (init thread) starts and during init thread execution it may fail Here is a listing part (all functions inside CLOCK_SetLowSpeed call are located in I-TCM RAM) 601020d0 : 601020d0: b580 push {r7, lr} 601020d2: af00 add r7, sp, #0 601020d4: f14c fd80 bl 6024ebd8 <__CLOCK_SystemCoreClockSwitchLowPower_veneer> 601020d8: f14c fd82 bl 6024ebe0 <__CLOCK_DeinitArmPll_veneer> 601020dc: f7ff ff8a bl 60101ff4 601020e0: 2000 movs r0, #0 601020e2: f14c fd3d bl 6024eb60 <__CLOCK_DeinitSysPfd_veneer> 601020e6: 2001 movs r0, #1 601020e8: f14c fd3a bl 6024eb60 <__CLOCK_DeinitSysPfd_veneer> 601020ec: 2118 movs r1, #24 601020ee: 2002 movs r0, #2 601020f0: f14c fd56 bl 6024eba0 <__CLOCK_InitSysPfd_veneer> 601020f4: 2003 movs r0, #3 601020f6: f14c fd33 bl 6024eb60 <__CLOCK_DeinitSysPfd_veneer> 601020fa: f14c fd55 bl 6024eba8 <__CLOCK_DeinitUsb2Pll_veneer> 601020fe: f14c fd1b bl 6024eb38 <__CLOCK_DeinitAudioPll_veneer> 60102102: f14c fd11 bl 6024eb28 <__CLOCK_DeinitVideoPll_veneer> 60102106: f14c fce3 bl 6024ead0 <__CLOCK_DeinitEnetPll_veneer> 6010210a: f14c fd5d bl 6024ebc8 <__CLOCK_SystemCoreClockSwitchLowSpeed_veneer> 6010210e: 46bd mov sp, r7 60102110: e8bd 4080 ldmia.w sp!, {r7, lr} 60102114: f05f be04 b.w 60161d20 and a stack printout REBOOT OCCURED\n", TYPE: HARD FAULT\n", --- Stack frame -------------------------------------------------------\n", IPSR= 0x00000003 >>>>> HardFault <<<<\n", R0 = 0x00000008\n", R1 = 0x5018505B\n", R2 = 0x400D8000\n", R3 = 0x00000080\n", R12 = 0x00000280\n", LR = 0x601020E7\n", PC = 0x60102100\n", PSR = 0x0100000E\n", SP (when faulted) = 0x20077F08\n", --- System Control Block (SCB) ----------------------------------------\n", 0x00080000 - CFSR - Configurable Fault Status Register\n", > The processor has attempted to access a coprocessor\n", 0x40000000 - HFSR - HardFault Status Register\n", > Forced HardFault\n", 0x411FC271 - CPUID - CPUID Base Register\n", 0x00481003 - ICSR - Interrupt Control and State Register\n", 0x60100400 - VTOR - Vector Table Offset Register\n", 0xFA050000 - AIRCR - Application Interrupt and Reset Control Register\n", 0x00000000 - SCR - System Control Register\n", 0x00070200 - CCR - Configuration Control Register\n", 0x00F00000 - CPACR - Coprocessor Access Control Register\n", Please advise how this issue can be localized. Any suggestions are appreciated. Thank you Re: imxrt1061 Hard fault points to clock API call @EdwinHz The question is actually not about ThreadX but more about xip approach and its limitations so due to we use xip approach in our project are there any document which describes memory access limitations when using xip and external QSPI flash ? Re: imxrt1061 Hard fault points to clock API call Hi @swisst, Unfortunately, ThreadX is no longer supported by us. I highly recommend you look for support of this OS on the ThreadX services and support website: Eclipse ThreadX Services and Support | The Eclipse Foundation I apologize for the inconvenience this may cause. BR, Edwin. Re: imxrt1061 Hard fault points to clock API call Hi @EdwinHz  I do understand that the amount of information provided in the ticket is very limited but anyway that's all I have. So the issue is still here unfortunately We got another hard fault during runtime with backtrace that points to memcpy function implemented in fsl_memcpy.S. So I checked several times that over code is linked exactly with fsl_memcpy implementation and not using library implementation. 00002e48 : 2e48: b5f1 push {r0, r4, r5, r6, r7, lr} 2e4a: 2a00 cmp r2, #0 2e4c: d04b beq.n 2ee6 00002e4e : 2e4e: f011 0303 ands.w r3, r1, #3 2e52: d006 beq.n 2e62 2e54: f811 4b01 ldrb.w r4, [r1], #1 2e58: 3a01 subs r2, #1 2e5a: f800 4b01 strb.w r4, [r0], #1 2e5e: d042 beq.n 2ee6 2e60: e7f5 b.n 2e4e memcpy is placed in ITCM memory and PC held 0x00002E54 value when hard fault occurred. I reviewed implementation of this function and see no differences with latest SDK. I accidentally noticed that ticket so question arise and I could not find the answer -so due to we use xip approach in our project are there any document which describes memory access limitations when using xip and external QSPI flash ? Thank you Re: imxrt1061 Hard fault points to clock API call @EdwinHz  Sorry for a late reply I would say only our specific application because we already went too far from examples. As you can see the main problem is unstable reproduce of the issue. We use NXP USB middleware (CDC class device) so we have our logger and shell input/output over USB. My first assumption was that clock peripheral section was not de-initialized correctly before reboot. Reboot is controlled so some actions are performed in software (stop services, close connections) and NVIC reset request at the end. But from other side all peripherals should reset to default values on reset. Re: imxrt1061 Hard fault points to clock API call Hi @swisst, Do you also see this happening with example codes we provide for ThreadX on your board? Or only with that specific application you are running?

Bluetooth Configuration (bt_vendor.conf) for the libbt in Android 11 Hi, Currently I'm working on imx8mp with android 11. We have our bluetooth module rtl8822bu ,which  we have connected it to the imx8mp based evk through the mini PCIe port which is internally connected to the USB. We are trying to bring up the bluetooth module and could see the bt_vendor.conf file under the directory path android_build/hardware/nxp/libbt/conf/nxp/evk_8mp, that is related to UART. bt_vendor.conf: mchar_port = /dev/ttymxc0 pFileName_helper = /vendor/firmware/mrvl/helper_uart_3000000.bin pFileName_image = /vendor/firmware/mrvl/uart8997_bt_v4.bin baudrate_dl_helper = 115200 baudrate_dl_image = 3000000 iSecondBaudrate = 0 baudrate_fw_init = 115200 baudrate_bt = 3000000 enable_download_fw=0 here we could see the configuration are related to the UART but not to the USB. What are the changes that has to be done in this bt_vendor.conf file, to bring-up  the bluetooth module? Please provide your inputs. Thanks. Android i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: Bluetooth Configuration (bt_vendor.conf) for the libbt in Android 11 Hi @ducho7783  @Dhruvit  We're encountering the same issue with the QCA9377 WiFi/BT USB module. It works successfully on kernel version 5.4.70, but we're facing problems when using it with Android 11. Could you please share how you resolved this issue? Thanks and regards, Deepak Kumar Beniya Re: Bluetooth Configuration (bt_vendor.conf) for the libbt in Android 11 Hi @ducho7783, I hope you are doing well. Thanks for the clarification. But still, there is Vendor HAL integration is required in Android to make your chipset work. ->Please make sure to add the HAL libraries at the below-given location. ->Edit mek_8q.mk located at “ /device/fsl/ imx8q/mek_8q/”, and add the product package. ->I have shared the example based on the NXP reference, please select realtek HAL libraries and the package that is provided. For example purpose:- # WiFi NXP HAL libraries PRODUCT_PACKAGES += \  libbt-vendor \  lib_driver_cmd_nxp # Bluetooth HAL PRODUCT_PACKAGES += \  android.hardware.bluetooth@1. 0-impl \  wifilogd \  wificond Thanks & Regards, Dhruvit Vasavada Re: Bluetooth Configuration (bt_vendor.conf) for the libbt in Android 11 Hi @Dhruvit , Thanks for your response, So as I'm seeing this issue is occurred in android but same thing I did in Linux platform and It is working fine, I loaded same driver and same firmware, even I checked Bluetooth logs from Dmesg that is also same. See here (both android and linux logs), ///////////////////////////////////////Android logs /////////////////////////////////////////////////////////////////////////////// phyboard_pollux:/ # dmesg |grep Bluetooth [ 0.145549] Bluetooth: Core ver 2.22 [ 0.145576] Bluetooth: HCI device and connection manager initialized [ 0.145585] Bluetooth: HCI socket layer initialized [ 0.145592] Bluetooth: L2CAP socket layer initialized [ 0.145599] Bluetooth: SCO socket layer initialized [ 2.078613] Bluetooth: HCI UART driver ver 2.3 [ 2.083076] Bluetooth: HCI UART protocol H4 registered [ 2.088223] Bluetooth: HCI UART protocol BCSP registered [ 2.093577] Bluetooth: HCI UART protocol LL registered [ 2.098724] Bluetooth: HCI UART protocol ATH3K registered [ 2.104156] Bluetooth: HCI UART protocol Three-wire (H5) registered [ 2.110670] Bluetooth: HCI UART protocol Broadcom registered [ 2.116360] Bluetooth: HCI UART protocol QCA registered [ 2.543073] Bluetooth: RFCOMM TTY layer initialized [ 2.547968] Bluetooth: RFCOMM socket layer initialized [ 2.553113] Bluetooth: RFCOMM ver 1.11 [ 2.556871] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 [ 2.562189] Bluetooth: BNEP filters: protocol multicast [ 2.567441] Bluetooth: BNEP socket layer initialized [ 2.572420] Bluetooth: HIDP (Human Interface Emulation) ver 1.2 [ 2.578352] Bluetooth: HIDP socket layer initialized [ 5.287075] Bluetooth: hci0: command 0xfc18 tx timeout [ 7.582211] Bluetooth: hci1: RTL: examining hci_ver=07 hci_rev=000b lmp_ver=07 lmp_subver=8822 [ 7.596121] Bluetooth: hci1: RTL: rom_version status=0 version=2 [ 7.602203] Bluetooth: hci1: RTL: loading rtl_bt/rtl8822b_fw.bin [ 7.616147] Bluetooth: hci1: RTL: loading rtl_bt/rtl8822b_config.bin [ 7.626129] Bluetooth: hci1: RTL: cfg_sz 14, total sz 20270 [ 8.383877] Bluetooth: hci1: RTL: fw version 0xab6b705c [ 13.283103] Bluetooth: hci0: BCM: failed to write update baudrate (-110) [ 13.289865] Bluetooth: hci0: Failed to set baudrate [ 15.299101] Bluetooth: hci0: command 0x0c03 tx timeout [ 23.523087] Bluetooth: hci0: BCM: Reset failed (-110) //////////////////////////////////////////////////Linux logs /////////////////////////////////////////////////////////////////////////// root@phyboard-pollux-imx8mp-2:~# root@phyboard-pollux-imx8mp-2:~# root@phyboard-pollux-imx8mp-2:~# dmesg | grep Bluetooth [ 0.085671] Bluetooth: Core ver 2.22 [ 0.085701] Bluetooth: HCI device and connection manager initialized [ 0.085709] Bluetooth: HCI socket layer initialized [ 0.085718] Bluetooth: L2CAP socket layer initialized [ 0.085731] Bluetooth: SCO socket layer initialized [ 1.660212] Bluetooth: HCI UART driver ver 2.3 [ 1.664671] Bluetooth: HCI UART protocol H4 registered [ 1.669816] Bluetooth: HCI UART protocol BCSP registered [ 1.675165] Bluetooth: HCI UART protocol LL registered [ 1.680308] Bluetooth: HCI UART protocol ATH3K registered [ 1.685733] Bluetooth: HCI UART protocol Three-wire (H5) registered [ 1.692124] Bluetooth: HCI UART protocol Broadcom registered [ 1.697814] Bluetooth: HCI UART protocol QCA registered [ 1.703047] Bluetooth: HCI UART protocol AG6XX registered [ 2.187207] Bluetooth: RFCOMM TTY layer initialized [ 2.192100] Bluetooth: RFCOMM socket layer initialized [ 2.197263] Bluetooth: RFCOMM ver 1.11 [ 2.201039] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 [ 2.206356] Bluetooth: BNEP filters: protocol multicast [ 2.211590] Bluetooth: BNEP socket layer initialized [ 2.216561] Bluetooth: HIDP (Human Interface Emulation) ver 1.2 [ 2.222489] Bluetooth: HIDP socket layer initialized [ 4.393652] Bluetooth: hci1: RTL: examining hci_ver=07 hci_rev=000b lmp_ver=07 lmp_subver=8822 [ 4.403608] Bluetooth: hci1: RTL: rom_version status=0 version=2 [ 4.409633] Bluetooth: hci1: RTL: loading rtl_bt/rtl8822b_fw.bin [ 4.420974] Bluetooth: hci1: RTL: loading rtl_bt/rtl8822b_config.bin [ 4.428100] Bluetooth: hci1: RTL: cfg_sz 14, total sz 20270 [ 5.178236] Bluetooth: hci1: RTL: fw version 0xab6b705c [ 5.374577] Bluetooth: hci0: command 0xfc18 tx timeout [ 13.534838] Bluetooth: hci0: BCM: failed to write update baudrate (-110) [ 13.541560] Bluetooth: hci0: Failed to set baudrate [ 15.550852] Bluetooth: hci0: command 0x0c03 tx timeout [ 23.774857] Bluetooth: hci0: BCM: Reset failed (-110) Can you give some input here basis on this. Thanks . Re: Bluetooth Configuration (bt_vendor.conf) for the libbt in Android 11 Hi @ducho7783, I hope you are doing well. If one is not using NXP Wifi/Bt chipset for the same then one has to integrate that chip with the custom board and for that purpose Please Contact Realtek vendor. Because It is seen from the logs that the chipset is not getting bonded and that is the reason for its service getting shut down every time. Please contact the chipset vendor for the same. Thanks & Regards. Dhruvit Vasavada Re: Bluetooth Configuration (bt_vendor.conf) for the libbt in Android 11 Hi @Dhruvit , Thanks for your support. The board that we are using is phycore i.mx 8M plus and we don't have any wifi/bt modules integrated in that. We are using the separate BT/Wifi module(rtl8822bu) which from the vendor Realtek. And we tried the way that you have mentioned i.e. setenforce permissive for giving the permission. Still we stuck with the same issue. Please help in resolving the issue. Thanks. Re: Bluetooth Configuration (bt_vendor.conf) for the libbt in Android 11 Hi @ducho7783, I hope you are doing well. And we are using USB so why add hci_uart.ko? ->It is because the nxp chipset provides wifi and bt support, where wifi is accessible via sdio, PCIe & bt is accessible via uart and that is recommended & for that I recommended. From the logs, it is seen that the bt service tried to start but it received signal 6 and got dead. It may be an issue of permission. Please check with the below command to give all permission to let the service start and nothing can restrict them. setenforce permissive Then also check the permission status by giving the below command. getenforce Thanks & Regards. Dhruvit Vasavada Re: Bluetooth Configuration (bt_vendor.conf) for the libbt in Android 11 Hi @Dhruvit, Thanks for your response. Here we are working with btusb driver so we added btintel.ko and btusb.ko in Boardconfig.mk file BOARD_VENDOR_KERNEL_MODULES += \ $(KERNEL_OUT)/drivers/net/wireless/broadcom/brcm80211/brcmfmac/brcmfmac.ko \ $(KERNEL_OUT)/drivers/net/wireless/broadcom/brcm80211/brcmutil/brcmutil.ko \ $(KERNEL_OUT)/drivers/bluetooth/btintel.ko\ $(KERNEL_OUT)/drivers/bluetooth/btusb.ko. And we are using USB so why to add hci_uart.ko ? we have also configured bt_vendor.conf file as below, which is in the path hardware/nxp/libbt/conf/nxp/evk_8mp/bt_vendor.conf. mchar_port = /dev/ttyUSB0 is_uart_port = 1 baudrate_bt = 115200 baudrate_fw_init = 3000000 bd_address = 00:0E:8E:BA:9C:C3  and we tried service call bluetooth_manager 6  but still we are getting the same issue, phyboard_pollux:/ # [ 130.613196] binder: release 381:381 transaction 102338 in, still active [ 130.618284] init: Untracked pid 2068 exited with status 0 [ 130.624843] binder: send failed reply for transaction 102338 to 2019:2063 [ 130.625756] init: Service 'vendor.bluetooth-1-0' (pid 381) received signal 6 [ 130.639905] init: Sending signal 9 to service 'vendor.bluetooth-1-0' (pid 381) process group... [ 130.649573] libprocessgroup: Successfully killed process cgroup uid 1002 pid 381 in 0ms [ 130.663488] init: Untracked pid 2070 exited with status 0 [ 130.671540] init: starting service 'vendor.bluetooth-1-0'... [ 132.170331] init: Untracked pid 2077 exited with status 0 [ 132.183551] init: Untracked pid 2080 exited with status 0 [ 132.189615] binder: undelivered death notification, b400fbe68b305430 [ 132.975210] init: Untracked pid 2138 exited with status 0 [ 132.982704] binder: release 2078:2082 transaction 117792 in, still active [ 132.989946] init: Service 'vendor.bluetooth-1-0' (pid 2078) received signal 6 [ 132.997356] binder: send failed reply for transaction 117792 to 2090:2133 [ 133.803851] binder: undelivered death notification, b400fbe68b304b40 [ 135.033733] binder: release 2203:2204 transaction 134781 in, still active [ 135.040654] binder: send failed reply for transaction 134781 to 2157:2199 [ 135.817674] init: Untracked pid 2218 exited with status 0 [ 135.829812] init: Untracked pid 2220 exited with status 0 [ 135.852323] binder: undelivered death notification, b400fbe68b305590 [ 137.110735] init: starting service 'vendor.bluetooth-1-0'... [ 137.119695] init: Control message: Processed ctl.interface_start for '[email protected]::IBluetoothHci/default' from pid: 242 (/system/bin/hwservicemanager) [ 137.135703] init: Control message: Processed ctl.interface_start for '[email protected]::IBluetoothHci/default' from pid: 242 (/system/bin/hwservicemanager) [ 137.229808] init: Untracked pid 2281 exited with status 0 [ 137.233920] binder: release 2275:2275 transaction 150957 in, still active [ 137.235522] init: Service 'vendor.bluetooth-1-0' (pid 2275) received signal 6 [ 137.249332] init: Sending signal 9 to service 'vendor.bluetooth-1-0' (pid 2275) process group... [ 137.250210] binder: send failed reply for transaction 150957 to 2229:2271 [ 137.258604] libprocessgroup: Successfully killed process cgroup uid 1002 pid 2275 in 0ms [ 137.276012] init: Untracked pid 2283 exited with status 0 [ 138.018302] binder: undelivered death notification, b400fbe68b30cff0 [ 139.744951] AidlLazyServiceRegistrar: Trying to shut down the service. No clients in use for any service in process. [ 139.756441] AidlLazyServiceRegistrar: Unregistered all clients and exiting [ 139.766204] printk: Binder:310_3: 221 output lines suppressed due to ratelimiting [ 140.235868] binder: release 2346:2348 transaction 151341 in, still active [ 140.242779] binder: send failed reply for transaction 151341 to 2300:2342 [ 140.982090] init: Untracked pid 2362 exited with status 0 [ 140.993324] init: Untracked pid 2364 exited with status 0 [ 141.006019] binder: undelivered death notification, b400fbe68b306560 [ 142.256253] init: starting service 'vendor.bluetooth-1-0'... [ 142.264741] init: Control message: Processed ctl.interface_start for '[email protected]::IBluetoothHci/default' from pid: 242 (/system/bin/hwservicemanager) [ 142.280467] init: Control message: Processed ctl.interface_start for '[email protected]::IBluetoothHci/default' from pid: 242 (/system/bin/hwservicemanager) [ 142.373321] init: Untracked pid 2424 exited with status 0 [ 142.380679] binder: release 2418:2418 transaction 151673 in, still active [ 142.380978] init: Service 'vendor.bluetooth-1-0' (pid 2418) received signal 6 [ 142.387502] binder: send failed reply for transaction 151673 to 2372:2414 [ 142.401996] init: Sending signal 9 to service 'vendor.bluetooth-1-0' (pid 2418) process group... [ 142.411619] libprocessgroup: Successfully killed process cgroup uid 1002 pid 2418 in 0ms [ 142.420565] init: updatable process 'vendor.bluetooth-1-0' exited 4 times in 4 minutes [ 143.146742] binder: undelivered death notification, b400fbe68b30a080 [ 147.267761] init: starting service 'vendor.bluetooth-1-0'... Please help us in resolving the issue. Thanks. Re: Bluetooth Configuration (bt_vendor.conf) for the libbt in Android 11 Hi @ducho7783, I hope you are doing well. ->Please check File: android_build/device/fsl/ imx8m/evk_8mq/BoardConfig.mk has below settings made. BOARD_VENDOR_KERNEL_MODULES += $(KERNEL_OUT)/drivers/net/ wireless/marvell/mrvl8887/ muart_src/hci_uart.ko BOARD_HAVE_BLUETOOTH := true ->One can set an early init config file to load the Bluetooth driver on early boot insmod vendor/lib/modules/hci_uart.ko ->Please make sure the bt_vendor.conf file has a configuration like the below example. mchar_port = /dev/ttyUSB0 is_uart_port = 1 baudrate_bt = 115200 baudrate_fw_init = 3000000 bd_address = 12:34:56:78:9a:bc ->One can use the below command to enable Bluetooth adb shell service call bluetooth_manager 6 Thanks & Regards, Dhruvit Vasavada Re: Bluetooth Configuration (bt_vendor.conf) for the libbt in Android 11 Hi @Dhruvit, Thanks for your support. We tried configuration changes whatever you provided, but still we are not able to enable bluetooth. Is there any other way  that we can fix this issue,so please provide us. Thanks, Re: Bluetooth Configuration (bt_vendor.conf) for the libbt in Android 11 Hi @ducho7783, I hope you are doing well. AOSP includes the HCI UART as an embedded driver in the kernel. NXP provides a modified version of this code. To enable HCI UART driver one needs to include some changes in the code parameters. These parameters can include different compile options, like m or y, and need to be set as shown in the snippet below.    Note that the configuration parameter option CONFIG_USB_SERIAL_FTDI_SIO is only necessary if you are accessing the UART interface over FTDI.   File: android_build/vendor/nxp- opensource/kernel_imx/arch/ arm/configs/imx_v7_android_ defconfig CONFIG_BT_HCIUART=m CONFIG_USB_SERIAL=y CONFIG_USB_SERIAL_FTDI_SIO=y Please make sure to do these needful changes. Thanks & Regards. Dhruvit Vasavada

Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi All,      I am trying to import a "lpcxpresso54s018_hello_world_qspi_xip" to my custom board. But I got an error message "File 'lpcxpresso54s018_hello_world_qspi_xip_HelloWorldSPIFI004.bin' load failure: Ef(11). No flash configured at the specified address." . The goal is to upload an image to the EXT SPI FLASH and the MCU will boot from the EXT SPI FLASH.      Can anyone please give an advice on how to fix the issue?   Error Message: Executing flash operation 'Program' (Program file into flash: lpcxpresso54s018_hello_world_qspi_xip_HelloWorldSPIFI004.bin) - Mon Jun 16 10:48:33 PDT 2025 Checking MCU info... Scanning for targets... Executing flash action... LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink.exe build 869) ( 0) Reading remote configuration Wc(03). No cache support. Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpcxpresso54s018_hello_world_qspi_xip_HelloWorldSPIFI004/Debug\LPC54S018.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors) Serial Number: F4ON0DG121ZHK VID:PID: 1FC9:0143 USB Path: 0001:000f:00 Using memory from core 0 after searching for a good core On debug connection - use system reset, stalling when 0x40000040 is accessed Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall Boot ROM stalled - at read watch #1 address 0x40000040 ( 30) Emulator Connected ( 40) Debug Halt ( 50) CPU ID debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0 processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0 number of h/w breakpoints = 6 number of flash patches = 2 number of h/w watchpoints = 4 Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info: Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled. Content of CoreSight Debug ROM(s): RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1) ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0) ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0) ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0) ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0) ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core NXP: LPC54S018 DAP stride is 4096 bytes (1024 words) ( 65) Chip Setup Complete Connected: was_reset=false. was_stopped=true ( 70) License Check Complete File 'lpcxpresso54s018_hello_world_qspi_xip_HelloWorldSPIFI004.bin' load failure: Ef(11). No flash configured at the specified address. (100) Target Operation Failed Unable to perform operation! Command failed with exit code 1 Thanks, 6/16/2025 LPC54xxx Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry,      Thanks for your advice on the PIO0_4,5,6!      Although I am unable to see the "hello world" message in the "lpc54018iotmodule_led_blinky_Custom Board 000", I followed your instruction on PIO0_4,5,6, and I am able to run the "lpcxpresso54s018_led_blinky_lpc_blinky_Custom Board 000". I also disconnect the SWD and power on the custom board and the blink still on going, this should be enough to proof the SPI BOOT is working right?        How do I view the "Hello World" message for the "lpc54018iotmodule_led_blinky_Custom Board 000" project?         For the PIO0_4,5,6, if I set it to all high so it should be in auto-boot mode, I wonder why it will prevent from uploading .bin file to the SPI NOR FLASH?        Also, can I use the MCU-LINK PRO and the MCUExpresso IDE for production programming?   Thanks, 7/25/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi @mtsang  I got some new idea from our internal team. You can check the ISP pins, to ensure that the chip boot type is SPIFI flash boot. And they suggest to refer to the AN12122 . You can use lpcxpresso54s018_hello_world_qspi_xip this demo. BR Harry Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry,      Thank you so much for your help and please give me an update if you got a result from the internal team. How soon will I hear back from you or the internal team?      Can you think of any other part of the schematics/code that will cause the board to be able to upload/erase code to the SPI NOR Flash but not able to boot and debug? I will double check base on your suggestion.      Currently I am using "lpc54018iotmodule_hello_world" example. Thanks, 7/15/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi @mtsang  I think this may be due to an incorrect SPI Descriptor, but unfortunately, I don't have a flash chip(IS25LP128F-JBLA3) on hand, so i can not test it, i will seek help from internal team.  I will inform you as soon as there is a result. Thanks for  your understanding. BR Harry Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry,      I can't debug the unit. It has below error output. LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink build 869) Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpc54018iotmodule_hello_world_lpc54018iotmodule/Debug\LPC54018.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors) Serial Number: F4ON0DG121ZHK VID:PID: 1FC9:0143 USB Path: 0001:0009:00 Using memory from core 0 after searching for a good core On debug connection - use system reset, stalling when 0x40000040 is accessed Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall Waiting for target to stop... Warning - processor did not halt - gave up waiting debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0 processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0 number of h/w breakpoints = 6 number of flash patches = 2 number of h/w watchpoints = 4 Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info: Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled. Content of CoreSight Debug ROM(s): RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1) ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0) ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0) ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0) ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0) ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core NXP: LPC54018 DAP stride is 4096 bytes (1024 words) Inspected v.2 External Flash Device on SPI LPC540xx_SPIFI_SFDP.cfx Image 'LPC540xx_JEDEC_SFDP Dec 18 2024 17:26:01' Opening flash driver LPC540xx_SPIFI_SFDP.cfx Sending SYSRESETREQ to run flash driver rst - Boot ROM stall address was not accessed (but we entered debug on VectorCatch anyway) There was a problem after we succesfully downloaded flash driver code to the target, so we are going to compare the flash driver code with the memory where it was loaded. Note that, after driver initialization, some difference is normal in 'generic' drivers. Driver from AXF file: //------------------ //Flash Data //------------------ AFTER driver startup timeout (302 5ms retries) Driver Addresses Start: 00000000 Entry: 0000009D End: 0000128C Stack: 00002290 Mailbox:0000A290 Driver Register State R0: 00000000 R1: 200273F8 R2: 0300AF21 R3: 00000000 R4: 40000000 R5: 00000000 R6: 00000000 R7: 00000000 R8: 00000000 R9: 00000000 R10: 00000000 R11: 00000000 R12: 00000000 SP: 00002288 LR: 0300BBA5 PC: 0300BDF2 xPSR: 21000000 MSP: 00002288 PSP: 00002290 CFBP: 00000001 (CONTROL=0x0, FAULTMASK=0x0, BASEPRI=0x0, PRIMASK=0x1) Flash Driver V.2 startup failed - rc Ef(34): Timed-out initializing flash. chip initialization failed - Ef(34): Timed-out initializing flash. failed to initialize flash driver LPC540xx_SPIFI_SFDP.cfx I click on "Attach to running target using Link server", and there what I got: I clicked on the "Verify Only" in the GUI Flash Tool and it seems to be able to download the .bin file to the SPI NOR Flash Executing flash operation 'Program' (Program file into flash: lpc54018iotmodule_hello_world_lpc54018iotmodule.bin) - Mon Jul 14 15:05:56 PDT 2025 Checking MCU info... Scanning for targets... Executing flash action... LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink.exe build 869) ( 0) Reading remote configuration Wc(03). No cache support. Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpc54018iotmodule_hello_world_lpc54018iotmodule/Debug\LPC54018.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors) Serial Number: F4ON0DG121ZHK VID:PID: 1FC9:0143 USB Path: 0001:0009:00 Using memory from core 0 after searching for a good core On debug connection - use system reset, stalling when 0x40000040 is accessed Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall Waiting for target to stop... Warning - processor did not halt - gave up waiting ( 30) Emulator Connected ( 40) Debug Halt ( 50) CPU ID debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0 processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0 number of h/w breakpoints = 6 number of flash patches = 2 number of h/w watchpoints = 4 Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info: Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled. Content of CoreSight Debug ROM(s): RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1) ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0) ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0) ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0) ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0) ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core NXP: LPC54018 DAP stride is 4096 bytes (1024 words) Inspected v.2 External Flash Device on SPI LPC540xx_SPIFI_SFDP.cfx Image 'LPC540xx_JEDEC_SFDP Dec 18 2024 17:26:01' Opening flash driver LPC540xx_SPIFI_SFDP.cfx Using SOFT reset to run the flash driver rst - Boot ROM stall address was not accessed (but we entered debug on Halt anyway) Flash variant 'JEDEC_SFDP_9D6018' detected (16MB = 256*64K at 0x10000000) Closing flash driver LPC540xx_SPIFI_SFDP.cfx ( 65) Chip Setup Complete Connected: was_reset=false. was_stopped=false ( 70) License Check Complete Verifying 'lpc54018iotmodule_hello_world_lpc54018iotmodule.bin' Binary section 0 at 0x10000000 len 0x3BA4 Opening flash driver LPC540xx_SPIFI_SFDP.cfx (already resident) Using SOFT reset to run the flash driver Flash variant 'JEDEC_SFDP_9D6018' detected (16MB = 256*64K at 0x10000000) ( 0) Comparing Flash against file at 0x10000000 Closing flash driver LPC540xx_SPIFI_SFDP.cfx (100) File matches flash. Read 0x3BA4 bytes in 43ms (about 355kB/s) - verify succeeded Thanks, 7/14/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi @mtsang  Can you debug successfully? BR Harry Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry,      I used the SPIFI descriptor you posted, but still it has the same problem. I got the following error message after I clicked on "Debug with Linkserver Probes" LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink build 869) Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpc54018iotmodule_hello_world_lpc54018iotmodule/Debug\LPC54018.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors) Serial Number: F4ON0DG121ZHK VID:PID: 1FC9:0143 USB Path: 0001:0014:00 Using memory from core 0 after searching for a good core On debug connection - use system reset, stalling when 0x40000040 is accessed Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall Boot ROM stalled - at read watch #1 address 0x40000040 debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0 processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0 number of h/w breakpoints = 6 number of flash patches = 2 number of h/w watchpoints = 4 Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info: Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled. Content of CoreSight Debug ROM(s): RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1) ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0) ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0) ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0) ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0) ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core NXP: LPC54018 DAP stride is 4096 bytes (1024 words) Inspected v.2 External Flash Device on SPI LPC540xx_SPIFI_SFDP.cfx Image 'LPC540xx_JEDEC_SFDP Dec 18 2024 17:26:01' Opening flash driver LPC540xx_SPIFI_SFDP.cfx SYSRESETREQ reset omitted - already reset Flash variant 'JEDEC_SFDP_9D6018' detected (16MB = 256*64K at 0x10000000) Closing flash driver LPC540xx_SPIFI_SFDP.cfx Connected: was_reset=false. was_stopped=true Awaiting telnet connection to port 3330 ... GDB nonstop mode enabled Opening flash driver LPC540xx_SPIFI_SFDP.cfx (already resident) Retask watch 0 address 0x0 (unused) for boot rom stall Sending SYSRESETREQ to run flash driver Boot ROM stalled accessing address 0x40000040 (restoring watchpoint 1) AFTER driver startup timeout (302 5ms retries) Driver Addresses Start: 00000000 Entry: 0000009D End: 0000128C Stack: 00002290 Mailbox:0000A290 Driver Register State R0: 0000A290 R1: 00000000 R2: 00000000 R3: 00000000 R4: 00000000 R5: 00000000 R6: 00000000 R7: 00000000 R8: 00000000 R9: 00000000 R10: 00000000 R11: 00000000 R12: 00000000 SP: 00002290 LR: 0000009D PC: 000000A0 xPSR: 61000000 MSP: 00002290 PSP: 00002290 CFBP: 00010001 (CONTROL=0x0, FAULTMASK=0x1, BASEPRI=0x0, PRIMASK=0x1) Flash Driver V.2 startup failed - rc Ef(34): Timed-out initializing flash. (100) Writing Flash ended with an error. Target error from Commit Flash write: Ef(34): Timed-out initializing flash. GDB stub (C:\nxp\LinkServer_24.12.21\binaries\crt_emu_cm_redlink) terminating - GDB protocol problem: Pipe has been closed by GDB. Thanks, 7/10/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi @mtsang  If you want to XIP. Did you try to change to it in startup_lpc54s018.c? #ifdef IS25LP128F-JBLA3 /* SPI Descriptor - IS25LP128F-JBLA3 */ (void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ;DevStrAdr (void (*)(void))0x0018609D, // mfgId + extCount (void (*)(void))0x00000000, // extid 0-3 (void (*)(void))0x00000000, // reserved (void (*)(void))0x1301001D, // caps (void (*)(void))0x00000100, // Blks + RESV1 (void (*)(void))0x00010000, // blkSize (void (*)(void))0x00000000, // reserved (void (*)(void))0x00000100, // pageSize + RESV2 (void (*)(void))0x00003F00, // maxReadSize (void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate (void (*)(void))0x06020050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId (void (*)(void))0x14110F0B, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId #endif BR Harry Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry,      Thanks for the schematics correction! However it seems like I am able to flash the .bin file to the SPI NOR Flash, but the MCU is not able to boot from the SPI NOR Flash. I installed and removed PIO0_6 pull-up resistor but it didnt help. Flash the SPI NOR FLASH Executing flash operation 'Program' (Program file into flash: Debug\lpc54018iotmodule_hello_world_lpc54018iotmodule.axf) - Wed Jul 09 16:39:19 PDT 2025 Checking MCU info... Scanning for targets... Executing flash action... LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink.exe build 869) ( 0) Reading remote configuration Wc(03). No cache support. Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpc54018iotmodule_hello_world_lpc54018iotmodule/Debug\LPC54018.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors) Serial Number: F4ON0DG121ZHK VID:PID: 1FC9:0143 USB Path: 0001:000b:00 Using memory from core 0 after searching for a good core On debug connection - use system reset, stalling when 0x40000040 is accessed Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall Waiting for target to stop... Warning - processor did not halt - gave up waiting ( 30) Emulator Connected ( 40) Debug Halt ( 50) CPU ID debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0 processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0 number of h/w breakpoints = 6 number of flash patches = 2 number of h/w watchpoints = 4 Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info: Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled. Content of CoreSight Debug ROM(s): RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1) ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0) ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0) ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0) ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0) ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core NXP: LPC54018 DAP stride is 4096 bytes (1024 words) Inspected v.2 External Flash Device on SPI LPC540xx_SPIFI_SFDP.cfx Image 'LPC540xx_JEDEC_SFDP Dec 18 2024 17:26:01' Opening flash driver LPC540xx_SPIFI_SFDP.cfx Using SOFT reset to run the flash driver rst - Boot ROM stall address was not accessed (but we entered debug on Halt anyway) Flash variant 'JEDEC_SFDP_9D6018' detected (16MB = 256*64K at 0x10000000) Closing flash driver LPC540xx_SPIFI_SFDP.cfx ( 65) Chip Setup Complete Connected: was_reset=false. was_stopped=false ( 70) License Check Complete Loading 'lpc54018iotmodule_hello_world_lpc54018iotmodule.axf' ELF 0x10000000 len 0x3BA4 Opening flash driver LPC540xx_SPIFI_SFDP.cfx (already resident) Using SOFT reset to run the flash driver Flash variant 'JEDEC_SFDP_9D6018' detected (16MB = 256*64K at 0x10000000) Writing 15268 bytes to address 0x10000000 in Flash 1 of 1 ( 0) Writing sectors 0-0 at 0x10000000 with 15268 bytes ( 0) at 10000000: 0 bytes - 0/15268 (100) at 10000000: 65536 bytes - 65536/15268 Sectors written: 0, unchanged: 1, total: 1 Erased/Wrote sector 0-0 with 15268 bytes in 30msec Closing flash driver LPC540xx_SPIFI_SFDP.cfx (100) Finished writing Flash successfully. Flash Write Done Loaded 0x3BA4 bytes in 89ms (about 171kB/s) Reset target (romstall) Starting execution using system reset with a stall address Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall Boot ROM stalled accessing address 0x40000040 (restoring watchpoint 1) Stopped (Was Reset) [Reset from Unknown]: Watchpoint (Temp) #1 - read watchpoint at 0x40000040 Data watch for bootloader stall restart on reset Verify the SPI NOR FLASH's content Executing flash operation 'Program' (Program file into flash: lpc54018iotmodule_hello_world_lpc54018iotmodule.bin) - Wed Jul 09 16:43:17 PDT 2025 Checking MCU info... Scanning for targets... Executing flash action... LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink.exe build 869) ( 0) Reading remote configuration Wc(03). No cache support. Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpc54018iotmodule_hello_world_lpc54018iotmodule/Debug\LPC54018.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors) Serial Number: F4ON0DG121ZHK VID:PID: 1FC9:0143 USB Path: 0001:000b:00 Using memory from core 0 after searching for a good core On debug connection - use system reset, stalling when 0x40000040 is accessed Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall Boot ROM stalled - at read watch #1 address 0x40000040 ( 30) Emulator Connected ( 40) Debug Halt ( 50) CPU ID debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0 processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0 number of h/w breakpoints = 6 number of flash patches = 2 number of h/w watchpoints = 4 Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info: Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled. Content of CoreSight Debug ROM(s): RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1) ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0) ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0) ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0) ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0) ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core NXP: LPC54018 DAP stride is 4096 bytes (1024 words) Inspected v.2 External Flash Device on SPI LPC540xx_SPIFI_SFDP.cfx Image 'LPC540xx_JEDEC_SFDP Dec 18 2024 17:26:01' Opening flash driver LPC540xx_SPIFI_SFDP.cfx Using SOFT reset to run the flash driver Flash variant 'JEDEC_SFDP_9D6018' detected (16MB = 256*64K at 0x10000000) Closing flash driver LPC540xx_SPIFI_SFDP.cfx ( 65) Chip Setup Complete Connected: was_reset=false. was_stopped=true ( 70) License Check Complete Verifying 'lpc54018iotmodule_hello_world_lpc54018iotmodule.bin' Binary section 0 at 0x10000000 len 0x3BA4 Opening flash driver LPC540xx_SPIFI_SFDP.cfx (already resident) Using SOFT reset to run the flash driver Flash variant 'JEDEC_SFDP_9D6018' detected (16MB = 256*64K at 0x10000000) ( 0) Comparing Flash against file at 0x10000000 Closing flash driver LPC540xx_SPIFI_SFDP.cfx (100) File matches flash. Read 0x3BA4 bytes in 41ms (about 372kB/s) - verify succeeded Thanks, 7/9/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry,      I am terribly sorry I didn't check the SPI NOR Flash pin out. Thanks for your catch!!! I used jumper cable to fix the problem for now.      Seems like I am able to program and mass erase the custom board right now. At least it didnt show any error message.      I am using "lpc54018iotmodule_hello_world_virtual_com_xip" as an example. Is there anything I can do to verify the SPI boot function? Also where the "HELLO WORLD" message will shows up? Thanks a lot! 7/8/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi @mtsang  I think your schematics of the SPI NOR FLASH is wrong. In the NOR FLASH Data sheet. PIN 5 SI should be connected IO0. PIN 2 SO should be connected IO1. But in your schematic. PIN 5 SI is connected IO1. BR Harry Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry,      Sure! Attached is the schematics of the SPI NOR FLASH. SPIFI_CSN -> LPC54S018JET180E_N7 SPIFI_IO0 -> LPC54S018JET180E_M7 SPIFI_IO1 -> LPC54S018JET180E_K8 SPIFI_IO2 -> LPC54S018JET180E_M9 SPIFI_IO3 -> LPC54S018JET180E_L9 SPIFI_SCK -> LPC54S018JET180E_M13 Thanks, 7/7/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi @mtsang  Can you share your schematic about the flash? BR Harry Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry, Thanks for your detailed response, but I am still getting the same error. Executing flash operation 'Program' (Program file into flash: Debug\lpc54018iotmodule_hello_world_lpc54018iotmodule.axf) - Thu Jul 03 14:29:23 PDT 2025 Checking MCU info... Scanning for targets... Executing flash action... LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink.exe build 869) ( 0) Reading remote configuration Wc(03). No cache support. Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpc54018iotmodule_hello_world_lpc54018iotmodule/Debug\LPC54018.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors) Serial Number: F4ON0DG121ZHK VID:PID: 1FC9:0143 USB Path: 0001:001a:00 Using memory from core 0 after searching for a good core On debug connection - use system reset, stalling when 0x40000040 is accessed Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall Waiting for target to stop... Warning - processor did not halt - gave up waiting ( 30) Emulator Connected ( 40) Debug Halt ( 50) CPU ID debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0 processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0 number of h/w breakpoints = 6 number of flash patches = 2 number of h/w watchpoints = 4 Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info: Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled. Content of CoreSight Debug ROM(s): RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1) ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0) ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0) ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0) ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0) ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core NXP: LPC54018 DAP stride is 4096 bytes (1024 words) Inspected v.2 External Flash Device on SPI LPC540xx_SPIFI_SFDP.cfx Image 'LPC540xx_JEDEC_SFDP Dec 18 2024 17:26:01' Opening flash driver LPC540xx_SPIFI_SFDP.cfx Using SOFT reset to run the flash driver rst - Boot ROM stall address was not accessed (but we entered debug on Halt anyway) Driver V.2 dynamic startup failed - driver Init provided no flash parameters Flash Driver V.2 startup failed - rc Ef(55): Dynamic flash driver startup failed to provide flash parameters. Terminate (0x0, 0x0, 0x0) status 0x40 - driver reports init failure - EXTSPI driver rc 15 (0xF) chip initialization failed - Ef(55): Dynamic flash driver startup failed to provide flash parameters. failed to initialize flash driver LPC540xx_SPIFI_SFDP.cfx ( 65) Chip Setup Complete (100) Target Operation Failed Unable to perform operation! Command failed with exit code 1 Thanks, 7/3/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi @mtsang  About the different register define. I think you can refer to the UM11060 Table 12. Image header for the LPC540xx devices. I checked the IS25LP128F-JBLA3 DATA SHEET. Regarding how to configure relevant parameters, let me give an example to illustrate. 1. So setStatusFxId is 0B. 2. So setOptionsFxId is 0F 3. So the getReadCmdFxId is 0x11. 4. So getStatusFxId is 06. And so on. And i write one based on the  IS25LP128F-JBLA3 data sheet and the  SDK startup_lpc54s018.c #ifdef IS25LP128F-JBLA3 /* SPI Descriptor - IS25LP128F-JBLA3 */ (void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ;DevStrAdr (void (*)(void))0x0018609D, // mfgId + extCount (void (*)(void))0x00000000, // extid 0-3 (void (*)(void))0x00000000, // reserved (void (*)(void))0x1301001D, // caps (void (*)(void))0x00000100, // Blks + RESV1 (void (*)(void))0x00010000, // blkSize (void (*)(void))0x00000000, // reserved (void (*)(void))0x00000100, // pageSize + RESV2 (void (*)(void))0x00003F00, // maxReadSize (void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate (void (*)(void))0x06020050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId (void (*)(void))0x14110F0B, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId #endif You can double check. And then  You can replace it with IS25LP128F-JBLA3. BR Harry Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry,      Sorry for the late reply and thanks for the infos.      I am still confused about how to find the info marked with BOLD Text. Can you please provide advice on how to find those infos in the IS25LP128F datasheet.      Also for the macro marked with BOLD text. Once I changed the macro, is there anything I need to change to the entire project setup like (Project Setting, 'startup_lpc54018.c', etc) What I found so far, please double check if I am correct //maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate Clock Frequency except for fast read: 166Mhz (A3h) Clock Frequency for read (03h): 80Mhz (50h) #ifdef IS25LP128F-JBLA3 /* SPIFI Descriptor - IS25LP128F-JBLA3 */ (void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ；DevStrAdr (void (*)(void))0x0018609D, // mfgId + extCount (void (*)(void))0x00000000, // extid 0-3 (void (*)(void))0x00000000, // extid 4-7 (void (*)(void))0x0001001D, // caps (void (*)(void))0x00000100, // Blks + RESV1 (void (*)(void))0x00010000, // blkSize (void (*)(void))0x00000000, // subBlks + subBlkSize (void (*)(void))0x00000100, // pageSize + RESV2 (void (*)(void))0x00003F00, // maxReadSize (void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate (void (*)(void))0x04030050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId, (void (*)(void))0x14110D09, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId #endif Thanks, 6/30/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry,      Sorry for the late reply and thanks for the info.      However I am still confused about how to find the info marked with Red Text. Can you please provide advice on how to find those infos in the IS25LP128F datasheet.      Also for the macro marked with blue text. Once I changed the macro, is there anything I need to change to the entire project setup like (Project Setting, 'startup_lpc54018.c', etc) Here's what I found, please double check if they are correct: //maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate Clock Frequency except for fast read: 166Mhz (A3h) Clock Frequency for read (03h): 80Mhz (50h) #ifdef IS25LP128F-JBLA3 /* SPIFI Descriptor - IS25LP128F-JBLA3 */ (void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ；DevStrAdr (void (*)(void))0x0018609D, // mfgId + extCount (void (*)(void))0x00000000, // extid 0-3 (void (*)(void))0x00000000, // extid 4-7 (void (*)(void))0x0001001D, // caps (void (*)(void))0x00000100, // Blks + RESV1 (void (*)(void))0x00010000, // blkSize (void (*)(void))0x00000000, // subBlks + subBlkSize (void (*)(void))0x00000100, // pageSize + RESV2 (void (*)(void))0x00003F00, // maxReadSize (void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate (void (*)(void))0x04030050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId, (void (*)(void))0x14110D09, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId #endif Thanks, 6/30/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi @mtsang  You are right. You need to modify the SPIFI Descriptor. You currently have: (void (*)(void))0x001870EF, // mfgId + extCount This corresponds to: mfgId = 0xEF (Winbond, not correct for IS25LP128F) device ID = 0x70 (part of JEDEC ID for W25Q128) But for IS25LP128F, the JEDEC ID is:   Manufacturer ID = 0x9D (ISSI) Memory type = 0x60 Capacity = 0x18   So you should change:   (void (*)(void))0x0018609D, // mfgId + extCount (extCount = 1, mfgId = 0x9D, memType = 0x60, capacity = 0x18)   And you should also verify (void (*)(void))0x04030050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId, (void (*)(void))0x14110D09, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId BR Harry Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry,      Thank you so much for the reply!      I am using "IS25LP128F-JBLA3" for the custom board. According to the datasheet(please see attached IS25LP128F-JBLA3 datasheet), it seems to support SFDP. I am switching back to "LPC540xx_SPIFI_SFDP.cfx" for memory config.    I checked the "SPIFI Descriptor"  in the "LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip" startup_lpc54018.c I saw the SPIFI Descriptor : #ifdef W25Q128JVFM /* SPIFI Descriptor - W25Q128JVFM */ (void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ；DevStrAdr (void (*)(void))0x001870EF, // mfgId + extCount (void (*)(void))0x00000000, // extid 0-3 (void (*)(void))0x00000000, // extid 4-7 (void (*)(void))0x0001001D, // caps (void (*)(void))0x00000100, // Blks + RESV1 (void (*)(void))0x00010000, // blkSize (void (*)(void))0x00000000, // subBlks + subBlkSize (void (*)(void))0x00000100, // pageSize + RESV2 (void (*)(void))0x00003F00, // maxReadSize (void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate (void (*)(void))0x04030050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId, (void (*)(void))0x14110D09, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId #endif      Should I change the SPIFI Descriptor(I modified the Bold Text)? Also I am unsure what to change for the under-line section. What else I need to change in order to make the example project works on my custom board: #ifdef IS25LP128F-JBLA3 /* SPIFI Descriptor - IS25LP128F-JBLA3 */ (void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ；DevStrAdr (void (*)(void))0x001870EF, // mfgId + extCount (void (*)(void))0x00000000, // extid 0-3 (void (*)(void))0x00000000, // extid 4-7 (void (*)(void))0x0001001D, // caps (void (*)(void))0x00000100, // Blks + RESV1 (void (*)(void))0x00010000, // blkSize (void (*)(void))0x00000000, // subBlks + subBlkSize (void (*)(void))0x00000100, // pageSize + RESV2 (void (*)(void))0x00003F00, // maxReadSize (void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate (void (*)(void))0x04030050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId, (void (*)(void))0x14110D09, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId #endif Thanks, 6/23/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi @mtsang  From your log: Flash Driver V.2 startup failed - rc Ef(55): Dynamic flash driver startup failed to provide flash parameters. The SPIFI  flash driver attempted to probe your external flash device via SFDP, but failed to identify valid parameters for your flash. What is the exact part number of the flash IC on your custom board? Check its datasheet for SFDP support — not all parts provide SFDP data. BR Harry Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry,      I deselect the "Link Application to RAM" and I got the below error message: Executing flash operation 'Program' (Program file into flash: Debug\lpcxpresso54s018_hello_world_qspi_xip_HelloWorldSPIFI003.axf) - Tue Jun 17 12:17:21 PDT 2025 Checking MCU info... Scanning for targets... Executing flash action... LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink.exe build 869) ( 0) Reading remote configuration Wc(03). No cache support. Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpcxpresso54s018_hello_world_qspi_xip_HelloWorldSPIFI003/Debug\LPC54S018.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors) Serial Number: F4ON0DG121ZHK VID:PID: 1FC9:0143 USB Path: 0001:0018:00 Using memory from core 0 after searching for a good core On debug connection - use system reset, stalling when 0x40000040 is accessed Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall Waiting for target to stop... Warning - processor did not halt - gave up waiting ( 30) Emulator Connected ( 40) Debug Halt ( 50) CPU ID debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0 processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0 number of h/w breakpoints = 6 number of flash patches = 2 number of h/w watchpoints = 4 Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info: Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled. Content of CoreSight Debug ROM(s): RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1) ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0) ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0) ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0) ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0) ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core NXP: LPC54S018 DAP stride is 4096 bytes (1024 words) Inspected v.2 External Flash Device on SPI LPC540xx_SPIFI_SFDP.cfx Image 'LPC540xx_JEDEC_SFDP Dec 18 2024 17:26:01' Opening flash driver LPC540xx_SPIFI_SFDP.cfx Using SOFT reset to run the flash driver rst - Boot ROM stall address was not accessed (but we entered debug on Halt anyway) Driver V.2 dynamic startup failed - driver Init provided no flash parameters Flash Driver V.2 startup failed - rc Ef(55): Dynamic flash driver startup failed to provide flash parameters. Terminate (0x0, 0x0, 0x0) status 0x40 - driver reports init failure - EXTSPI driver rc 15 (0xF) chip initialization failed - Ef(55): Dynamic flash driver startup failed to provide flash parameters. failed to initialize flash driver LPC540xx_SPIFI_SFDP.cfx ( 65) Chip Setup Complete (100) Target Operation Failed Unable to perform operation! Command failed with exit code 1 Thanks, 6/17/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi @mtsang  I have a question. According to your need. Why you select the "link application to ram" You can deselect this, and try again. BR Harry

Import of Simulink created Project to S32DS Currently working with the S32K144 EVB and utilizing MATLAB Model-Based Design (MBD) for code generation, issues are being encountered while trying to import the generated project into S32 Design Studio. Despite following all instructions and references from NXP community forums and official documentation, the project fails to import into the development environment. Other manually created projects can be successfully built, imported, and deployed without any issues, but Simulink-generated projects consistently encounter this problem. Details regarding the issue: MATLAB/Simulink Version: MATLAB 2024a MBD Toolbox Version: v4.2.0 S32 Design Studio Version: S32DS v3.5 Steps taken: Guidelines from community resources have been followed.    The generated ProjectInfo.xml file has been verified. Compatibility between the MBD Toolbox and S32 Design Studio has been checked. How to export Generated Code to S32 Design Studio IDE (applicable for MBDT for MPC5744P v2.0) - NXP Community Re: How to export S32K144 MBDT Generated Code to S32 Design Studio - NXP Community A snapshot highlighting the specific point of the issue is attached for reference. Re: Import of Simulink created Project to S32DS I'm also facing same issue while importing xml file to s32ds. I'm using S32DS version 3.5 and MATLAB R2021b. Someone please help me with this

LPC55S36 I3C Slave Speed Limitation Two LPC55S36 boards were connected for I3C communication, with one configured as the I3C Master and the other as the I3C Slave. When the Master’s push-pull baud rate is set to 1.25 Mbps, communication proceeds without issues. However, increasing the baud rate to 2.0 Mbps causes the Slave to fail in receiving data properly, resulting in a NACK response. The question is whether there are any configuration parameters or tuning methods available that would allow the I3C Slave to reliably handle higher baud rates. Note: The sample code being used employs the function I3C_BusMasterDoTransferToI3CDev, which is defined in the fsl_component_i3c_adapter.h header. This function performs a write to the device address followed by a read, even during read operations. In contrast, the SDK example lpcxpresso55s36_i3c_polling_b2b_transfer_master uses the function I3C_MasterTransferBlocking, which performs a pure read operation during reads. Due to this behavioral difference, the latter example (I3C_MasterTransferBlocking) is able to operate correctly at 2.0 Mbps, whereas the former (I3C_BusMasterDoTransferToI3CDev) leads to reception failures at the same baud rate. At even higher baud rates, both approaches result in failed receptions on the Slave side. Re: LPC55S36 I3C Slave Speed Limitation Thank you for the explanation. As you noted, when the speed is too high, the Slave does not have sufficient time to fill the TX FIFO, so it responds with a NACK. Re: LPC55S36 I3C Slave Speed Limitation Hi @bell_huang  I have debugged the slave code. I add one toggle signal. The start address header uses open-drain baudrate (typically less than 2MHz), allowing the target more time to fill the TX FIFO and thereby achieve ACK. However, the repeated start address header uses push-pull baudrate, and if set above 4MHz, the target doesn't have sufficient time to fill the TX FIFO, resulting in NACK. Based on current MCU performance, if we want to achieve higher rates, we need to optimize the target code to accelerate its response speed. BR Harry Re: LPC55S36 I3C Slave Speed Limitation Hi @Harry_Zhang , Thank you for the information about setting the optimization level to O3. After adjusting the Slave configuration, the Master now appears to reach 4 Mbps. (I’m not sure why, but after a Slave reset the Master’s first Read fails, while subsequent Reads succeed.) Could you confirm whether 4 Mbps is indeed the limit on the Slave side? As mentioned earlier, the I3C specification allows up to 12.5 Mbps; even the Building an I3C Sensor Network Using LPC553x/LPC55S3x example operates at 10 Mbps. Re: LPC55S36 I3C Slave Speed Limitation Hi @bell_huang  I have tested it. When the PP Baud is setted to 2M. baudrate_config.i3cPushPullBaud = 2000000; baudrate_config.i3cOpenDrainBaud = 625000; You can try to improve the optimization level of the code. It can work. BR Harry Re: LPC55S36 I3C Slave Speed Limitation As mentioned in the note of my first post: The simple examples in the SDK (such as lpcxpresso55s36_i3c_polling_b2b_transfer_master) use a Single message format, which means: Write: Slave Address (RnW = 0) → Data Read: Slave Address (RnW = 1) → Data However, almost all sensors in the industry (for example, lpcxpresso55s36_i3c_master_read_sensor_icm42688p) use a Combined format, which means: Write: Slave Address (RnW = 0) → Register Address → Data Read: Slave Address (RnW = 0) → Register Address → repeated START → Slave Address (RnW = 1) → Data This explains why your Single message example can reach up to 2.0 Mbps, while my Combined format example can only achieve a maximum of 1.25 Mbps. In lpcxpresso55s36_i3c_polling_b2b_transfer_master, if you modify masterXfer to use the Combined format by adding the following code, it will switch to the Combined format. Then you will observe that the maximum achievable speed drops to 1.25 Mbps. Please refer to the attachment in this reply. masterXfer.subaddress = 0x34; masterXfer.subaddressSize = 1; Additionally, the most important point is that the I3C specification defines the baud rate to support up to 12.5 Mbps. Both Single message (Max = 2.0 Mbps) and Combined format (Max = 1.25 Mbps) are far below this limit. This is why I would like to know if there is any way to improve the Slave’s capability to accept higher baud rates. Re: LPC55S36 I3C Slave Speed Limitation Hi @bell_huang  I tested the lpc5536 SDK i3c example. I changed the EXAMPLE_I3C_PP_BAUDRATE #define EXAMPLE_I3C_PP_BAUDRATE 2000000 It can work. So it  proves that it can work at this speed. BR Harry Re: LPC55S36 I3C Slave Speed Limitation Hi @Harry_Zhang , Test steps: (1) Reset slave board (2) Reset master board Also check out the speed configuration in master code: baudrate_config.i3cPushPullBaud = 1250000; baudrate_config.i3cOpenDrainBaud = 625000; If we modify i3cPushPullBaud to 2000000, then the master cannot read correct data. Re: LPC55S36 I3C Slave Speed Limitation Hi @bell_huang  Can you share your project? So I can reproduce this issue. BR Harry

Inquiry on Cryptographic Features of LX2160A RDB I hope this message finds you well. I am evaluating the LX2160A Reference Design Board (RDB) for a secure networking application and would appreciate clarification on some aspects related to its cryptographic capabilities. Specifically, I would like to know: Cryptographic Boundary: Does the cryptographic engine within the LX2160A SoC have a defined cryptographic boundary in line with security certification frameworks (e.g., FIPS 140-2)? Code and Memory Isolation: Is the cryptographic code logically isolated from other software components? Is there any form of physical separation between the crypto code and the rest of the system? Does the SoC reserve dedicated memory for cryptographic operations? Sandbagging Support: Does the platform support any kind of sandbagging—i.e., deliberate buffering, obfuscation, or timing equalization to mitigate side-channel attacks? FIPS 140-2 Level 3: Is it possible to achieve FIPS 140-2 Level 3 compliance using the LX2160A platform, either directly or through integration with external secure elements? Documentation: Are there any white papers, application notes, or security architecture documents available that detail the cryptographic and isolation mechanisms implemented in the LX2160A or the RDB? Re: Inquiry on Cryptographic Features of LX2160A RDB Hey. While the answer satisfied my query, i need a clarification. Are the cryptographic algorithms implemented within the chip or is it just a blank accelerator where i have to implement the algorithms myself by writing a crypto code. I'll clarify by mentioning that i wish to implement DES, 3DES, AES-128, AES-256, RSA(748, 1024, 2048 bit), ECDSA (256/384 bit). MD5, SHA, SHA-256, SHA-384, SHA-512. Are these already available in the chip or a code has to be written for its implementation in software? Re: Inquiry on Cryptographic Features of LX2160A RDB We have FSLNISTCAVP.pdf, but as far as I know, we don't have an update. FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP® Cryptographic Accelerators - White Paper   We have been telling customers to check the individual crypto suites that they need.  Because the LX2160 uses the same engine as the LS processors. If you have a particular algorithm that you are interested in, I can check with our internal team about it. But as this is related to the SEC, please create a case https://support.nxp.com/s/?language=en_US And confirm you have a NDA in place. Thanks

LX2160A RDBの暗号化機能に関するお問い合わせ このメッセージがあなたに届いて、お元気でいらっしゃることを願っております。私は、安全なネットワーク アプリケーション用にLX2160A リファレンス デザイン ボード (RDB)を評価しており、その暗号化機能に関連するいくつかの側面について明確に説明していただければ幸いです。 具体的には、次の点を知りたいです。 暗号化境界: LX2160A SoC 内の暗号化エンジンには、セキュリティ認証フレームワーク (FIPS 140-2 など) に準拠した暗号化境界が定義されていますか? コードとメモリのアイソレータ: 暗号化コードは他のソフトウェア コンポーネントから論理的に分離されていますか? 暗号コードとシステムの残りの部分の間には、何らかの物理的な分離がありますか? SoC は暗号化操作用に専用のメモリを予約していますか? サンドバッギングのサポート: プラットフォームは、サイドチャネル攻撃を軽減するための意図的なバッファリング、難読化、タイミング均等化など、あらゆる種類のサンドバッギングをサポートしていますか? FIPS 140-2 レベル 3 : LX2160A プラットフォームを直接使用して、または外部のセキュア エレメントと統合して、 FIPS 140-2 レベル 3 準拠を達成することは可能ですか? ドキュメント: LX2160A または RDB に実装されている暗号化およびアイソレータメカニズムの詳細を説明したホワイト ペーパー、アプリケーションノート、またはセキュリティ アーキテクチャ ドキュメントはありますか? Re: Inquiry on Cryptographic Features of LX2160A RDB おい。回答は私の質問に満足しましたが、説明が必要です。暗号アルゴリズムはチップ内に実装されていますか、それとも暗号コードを記述して自分でアルゴリズムを実装する必要がある単なる空のアクセラレータですか。DES、3DES、AES-128、AES-256、RSA (748、1024、2048 ビット)、ECDSA (256/384 ビット) を実装したいということを明記しておきます。MD5、SHA、SHA-256、SHA-384、SHA-512。これらはすでにチップ内で利用可能でしょうか、それともソフトウェアで実装するためにコードを書く必要がありますか? Re: Inquiry on Cryptographic Features of LX2160A RDB FSLNISTCAVP.pdfがあります。しかし、私の知る限り、更新情報はありません。 FSLNISTCAVP、NXP ®暗号アクセラレータ向け NIST 暗号アルゴリズム検証プログラム認証 - ホワイトペーパー お客様には、必要な個別の暗号スイートを確認するようご案内しています。LX2160 は LS プロセッサと同じエンジンを使用しているためです。 特定のアルゴリズムにご興味がある場合は、弊社の社内チームに CAN 確認させていただきます。 しかし、これはSECに関係しているので、CASEを作成してください https://support.nxp.com/s/?language=en_US また、NDA が締結されていることを確認してください。 よろしくお願いします。