Bluetooth Configuration (bt_vendor.conf) for the libbt in Android 11 Hi, Currently I'm working on imx8mp with android 11. We have our bluetooth module rtl8822bu ,which  we have connected it to the imx8mp based evk through the mini PCIe port which is internally connected to the USB. We are trying to bring up the bluetooth module and could see the bt_vendor.conf file under the directory path android_build/hardware/nxp/libbt/conf/nxp/evk_8mp, that is related to UART. bt_vendor.conf: mchar_port = /dev/ttymxc0 pFileName_helper = /vendor/firmware/mrvl/helper_uart_3000000.bin pFileName_image = /vendor/firmware/mrvl/uart8997_bt_v4.bin baudrate_dl_helper = 115200 baudrate_dl_image = 3000000 iSecondBaudrate = 0 baudrate_fw_init = 115200 baudrate_bt = 3000000 enable_download_fw=0 here we could see the configuration are related to the UART but not to the USB. What are the changes that has to be done in this bt_vendor.conf file, to bring-up  the bluetooth module? Please provide your inputs. Thanks. Android i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: Bluetooth Configuration (bt_vendor.conf) for the libbt in Android 11 Hi @ducho7783  @Dhruvit  We're encountering the same issue with the QCA9377 WiFi/BT USB module. It works successfully on kernel version 5.4.70, but we're facing problems when using it with Android 11. Could you please share how you resolved this issue? Thanks and regards, Deepak Kumar Beniya Re: Bluetooth Configuration (bt_vendor.conf) for the libbt in Android 11 Hi @ducho7783, I hope you are doing well. Thanks for the clarification. But still, there is Vendor HAL integration is required in Android to make your chipset work. ->Please make sure to add the HAL libraries at the below-given location. ->Edit mek_8q.mk located at “ /device/fsl/ imx8q/mek_8q/”, and add the product package. ->I have shared the example based on the NXP reference, please select realtek HAL libraries and the package that is provided. For example purpose:- # WiFi NXP HAL libraries PRODUCT_PACKAGES += \  libbt-vendor \  lib_driver_cmd_nxp # Bluetooth HAL PRODUCT_PACKAGES += \  android.hardware.bluetooth@1. 0-impl \  wifilogd \  wificond Thanks & Regards, Dhruvit Vasavada Re: Bluetooth Configuration (bt_vendor.conf) for the libbt in Android 11 Hi @Dhruvit , Thanks for your response, So as I'm seeing this issue is occurred in android but same thing I did in Linux platform and It is working fine, I loaded same driver and same firmware, even I checked Bluetooth logs from Dmesg that is also same. See here (both android and linux logs), ///////////////////////////////////////Android logs /////////////////////////////////////////////////////////////////////////////// phyboard_pollux:/ # dmesg |grep Bluetooth [ 0.145549] Bluetooth: Core ver 2.22 [ 0.145576] Bluetooth: HCI device and connection manager initialized [ 0.145585] Bluetooth: HCI socket layer initialized [ 0.145592] Bluetooth: L2CAP socket layer initialized [ 0.145599] Bluetooth: SCO socket layer initialized [ 2.078613] Bluetooth: HCI UART driver ver 2.3 [ 2.083076] Bluetooth: HCI UART protocol H4 registered [ 2.088223] Bluetooth: HCI UART protocol BCSP registered [ 2.093577] Bluetooth: HCI UART protocol LL registered [ 2.098724] Bluetooth: HCI UART protocol ATH3K registered [ 2.104156] Bluetooth: HCI UART protocol Three-wire (H5) registered [ 2.110670] Bluetooth: HCI UART protocol Broadcom registered [ 2.116360] Bluetooth: HCI UART protocol QCA registered [ 2.543073] Bluetooth: RFCOMM TTY layer initialized [ 2.547968] Bluetooth: RFCOMM socket layer initialized [ 2.553113] Bluetooth: RFCOMM ver 1.11 [ 2.556871] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 [ 2.562189] Bluetooth: BNEP filters: protocol multicast [ 2.567441] Bluetooth: BNEP socket layer initialized [ 2.572420] Bluetooth: HIDP (Human Interface Emulation) ver 1.2 [ 2.578352] Bluetooth: HIDP socket layer initialized [ 5.287075] Bluetooth: hci0: command 0xfc18 tx timeout [ 7.582211] Bluetooth: hci1: RTL: examining hci_ver=07 hci_rev=000b lmp_ver=07 lmp_subver=8822 [ 7.596121] Bluetooth: hci1: RTL: rom_version status=0 version=2 [ 7.602203] Bluetooth: hci1: RTL: loading rtl_bt/rtl8822b_fw.bin [ 7.616147] Bluetooth: hci1: RTL: loading rtl_bt/rtl8822b_config.bin [ 7.626129] Bluetooth: hci1: RTL: cfg_sz 14, total sz 20270 [ 8.383877] Bluetooth: hci1: RTL: fw version 0xab6b705c [ 13.283103] Bluetooth: hci0: BCM: failed to write update baudrate (-110) [ 13.289865] Bluetooth: hci0: Failed to set baudrate [ 15.299101] Bluetooth: hci0: command 0x0c03 tx timeout [ 23.523087] Bluetooth: hci0: BCM: Reset failed (-110) //////////////////////////////////////////////////Linux logs /////////////////////////////////////////////////////////////////////////// root@phyboard-pollux-imx8mp-2:~# root@phyboard-pollux-imx8mp-2:~# root@phyboard-pollux-imx8mp-2:~# dmesg | grep Bluetooth [ 0.085671] Bluetooth: Core ver 2.22 [ 0.085701] Bluetooth: HCI device and connection manager initialized [ 0.085709] Bluetooth: HCI socket layer initialized [ 0.085718] Bluetooth: L2CAP socket layer initialized [ 0.085731] Bluetooth: SCO socket layer initialized [ 1.660212] Bluetooth: HCI UART driver ver 2.3 [ 1.664671] Bluetooth: HCI UART protocol H4 registered [ 1.669816] Bluetooth: HCI UART protocol BCSP registered [ 1.675165] Bluetooth: HCI UART protocol LL registered [ 1.680308] Bluetooth: HCI UART protocol ATH3K registered [ 1.685733] Bluetooth: HCI UART protocol Three-wire (H5) registered [ 1.692124] Bluetooth: HCI UART protocol Broadcom registered [ 1.697814] Bluetooth: HCI UART protocol QCA registered [ 1.703047] Bluetooth: HCI UART protocol AG6XX registered [ 2.187207] Bluetooth: RFCOMM TTY layer initialized [ 2.192100] Bluetooth: RFCOMM socket layer initialized [ 2.197263] Bluetooth: RFCOMM ver 1.11 [ 2.201039] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 [ 2.206356] Bluetooth: BNEP filters: protocol multicast [ 2.211590] Bluetooth: BNEP socket layer initialized [ 2.216561] Bluetooth: HIDP (Human Interface Emulation) ver 1.2 [ 2.222489] Bluetooth: HIDP socket layer initialized [ 4.393652] Bluetooth: hci1: RTL: examining hci_ver=07 hci_rev=000b lmp_ver=07 lmp_subver=8822 [ 4.403608] Bluetooth: hci1: RTL: rom_version status=0 version=2 [ 4.409633] Bluetooth: hci1: RTL: loading rtl_bt/rtl8822b_fw.bin [ 4.420974] Bluetooth: hci1: RTL: loading rtl_bt/rtl8822b_config.bin [ 4.428100] Bluetooth: hci1: RTL: cfg_sz 14, total sz 20270 [ 5.178236] Bluetooth: hci1: RTL: fw version 0xab6b705c [ 5.374577] Bluetooth: hci0: command 0xfc18 tx timeout [ 13.534838] Bluetooth: hci0: BCM: failed to write update baudrate (-110) [ 13.541560] Bluetooth: hci0: Failed to set baudrate [ 15.550852] Bluetooth: hci0: command 0x0c03 tx timeout [ 23.774857] Bluetooth: hci0: BCM: Reset failed (-110) Can you give some input here basis on this. Thanks . Re: Bluetooth Configuration (bt_vendor.conf) for the libbt in Android 11 Hi @ducho7783, I hope you are doing well. If one is not using NXP Wifi/Bt chipset for the same then one has to integrate that chip with the custom board and for that purpose Please Contact Realtek vendor. Because It is seen from the logs that the chipset is not getting bonded and that is the reason for its service getting shut down every time. Please contact the chipset vendor for the same. Thanks & Regards. Dhruvit Vasavada Re: Bluetooth Configuration (bt_vendor.conf) for the libbt in Android 11 Hi @Dhruvit , Thanks for your support. The board that we are using is phycore i.mx 8M plus and we don't have any wifi/bt modules integrated in that. We are using the separate BT/Wifi module(rtl8822bu) which from the vendor Realtek. And we tried the way that you have mentioned i.e. setenforce permissive for giving the permission. Still we stuck with the same issue. Please help in resolving the issue. Thanks. Re: Bluetooth Configuration (bt_vendor.conf) for the libbt in Android 11 Hi @ducho7783, I hope you are doing well. And we are using USB so why add hci_uart.ko? ->It is because the nxp chipset provides wifi and bt support, where wifi is accessible via sdio, PCIe & bt is accessible via uart and that is recommended & for that I recommended. From the logs, it is seen that the bt service tried to start but it received signal 6 and got dead. It may be an issue of permission. Please check with the below command to give all permission to let the service start and nothing can restrict them. setenforce permissive Then also check the permission status by giving the below command. getenforce Thanks & Regards. Dhruvit Vasavada Re: Bluetooth Configuration (bt_vendor.conf) for the libbt in Android 11 Hi @Dhruvit, Thanks for your response. Here we are working with btusb driver so we added btintel.ko and btusb.ko in Boardconfig.mk file BOARD_VENDOR_KERNEL_MODULES += \ $(KERNEL_OUT)/drivers/net/wireless/broadcom/brcm80211/brcmfmac/brcmfmac.ko \ $(KERNEL_OUT)/drivers/net/wireless/broadcom/brcm80211/brcmutil/brcmutil.ko \ $(KERNEL_OUT)/drivers/bluetooth/btintel.ko\ $(KERNEL_OUT)/drivers/bluetooth/btusb.ko. And we are using USB so why to add hci_uart.ko ? we have also configured bt_vendor.conf file as below, which is in the path hardware/nxp/libbt/conf/nxp/evk_8mp/bt_vendor.conf. mchar_port = /dev/ttyUSB0 is_uart_port = 1 baudrate_bt = 115200 baudrate_fw_init = 3000000 bd_address = 00:0E:8E:BA:9C:C3  and we tried service call bluetooth_manager 6  but still we are getting the same issue, phyboard_pollux:/ # [ 130.613196] binder: release 381:381 transaction 102338 in, still active [ 130.618284] init: Untracked pid 2068 exited with status 0 [ 130.624843] binder: send failed reply for transaction 102338 to 2019:2063 [ 130.625756] init: Service 'vendor.bluetooth-1-0' (pid 381) received signal 6 [ 130.639905] init: Sending signal 9 to service 'vendor.bluetooth-1-0' (pid 381) process group... [ 130.649573] libprocessgroup: Successfully killed process cgroup uid 1002 pid 381 in 0ms [ 130.663488] init: Untracked pid 2070 exited with status 0 [ 130.671540] init: starting service 'vendor.bluetooth-1-0'... [ 132.170331] init: Untracked pid 2077 exited with status 0 [ 132.183551] init: Untracked pid 2080 exited with status 0 [ 132.189615] binder: undelivered death notification, b400fbe68b305430 [ 132.975210] init: Untracked pid 2138 exited with status 0 [ 132.982704] binder: release 2078:2082 transaction 117792 in, still active [ 132.989946] init: Service 'vendor.bluetooth-1-0' (pid 2078) received signal 6 [ 132.997356] binder: send failed reply for transaction 117792 to 2090:2133 [ 133.803851] binder: undelivered death notification, b400fbe68b304b40 [ 135.033733] binder: release 2203:2204 transaction 134781 in, still active [ 135.040654] binder: send failed reply for transaction 134781 to 2157:2199 [ 135.817674] init: Untracked pid 2218 exited with status 0 [ 135.829812] init: Untracked pid 2220 exited with status 0 [ 135.852323] binder: undelivered death notification, b400fbe68b305590 [ 137.110735] init: starting service 'vendor.bluetooth-1-0'... [ 137.119695] init: Control message: Processed ctl.interface_start for '[email protected]::IBluetoothHci/default' from pid: 242 (/system/bin/hwservicemanager) [ 137.135703] init: Control message: Processed ctl.interface_start for '[email protected]::IBluetoothHci/default' from pid: 242 (/system/bin/hwservicemanager) [ 137.229808] init: Untracked pid 2281 exited with status 0 [ 137.233920] binder: release 2275:2275 transaction 150957 in, still active [ 137.235522] init: Service 'vendor.bluetooth-1-0' (pid 2275) received signal 6 [ 137.249332] init: Sending signal 9 to service 'vendor.bluetooth-1-0' (pid 2275) process group... [ 137.250210] binder: send failed reply for transaction 150957 to 2229:2271 [ 137.258604] libprocessgroup: Successfully killed process cgroup uid 1002 pid 2275 in 0ms [ 137.276012] init: Untracked pid 2283 exited with status 0 [ 138.018302] binder: undelivered death notification, b400fbe68b30cff0 [ 139.744951] AidlLazyServiceRegistrar: Trying to shut down the service. No clients in use for any service in process. [ 139.756441] AidlLazyServiceRegistrar: Unregistered all clients and exiting [ 139.766204] printk: Binder:310_3: 221 output lines suppressed due to ratelimiting [ 140.235868] binder: release 2346:2348 transaction 151341 in, still active [ 140.242779] binder: send failed reply for transaction 151341 to 2300:2342 [ 140.982090] init: Untracked pid 2362 exited with status 0 [ 140.993324] init: Untracked pid 2364 exited with status 0 [ 141.006019] binder: undelivered death notification, b400fbe68b306560 [ 142.256253] init: starting service 'vendor.bluetooth-1-0'... [ 142.264741] init: Control message: Processed ctl.interface_start for '[email protected]::IBluetoothHci/default' from pid: 242 (/system/bin/hwservicemanager) [ 142.280467] init: Control message: Processed ctl.interface_start for '[email protected]::IBluetoothHci/default' from pid: 242 (/system/bin/hwservicemanager) [ 142.373321] init: Untracked pid 2424 exited with status 0 [ 142.380679] binder: release 2418:2418 transaction 151673 in, still active [ 142.380978] init: Service 'vendor.bluetooth-1-0' (pid 2418) received signal 6 [ 142.387502] binder: send failed reply for transaction 151673 to 2372:2414 [ 142.401996] init: Sending signal 9 to service 'vendor.bluetooth-1-0' (pid 2418) process group... [ 142.411619] libprocessgroup: Successfully killed process cgroup uid 1002 pid 2418 in 0ms [ 142.420565] init: updatable process 'vendor.bluetooth-1-0' exited 4 times in 4 minutes [ 143.146742] binder: undelivered death notification, b400fbe68b30a080 [ 147.267761] init: starting service 'vendor.bluetooth-1-0'... Please help us in resolving the issue. Thanks. Re: Bluetooth Configuration (bt_vendor.conf) for the libbt in Android 11 Hi @ducho7783, I hope you are doing well. ->Please check File: android_build/device/fsl/ imx8m/evk_8mq/BoardConfig.mk has below settings made. BOARD_VENDOR_KERNEL_MODULES += $(KERNEL_OUT)/drivers/net/ wireless/marvell/mrvl8887/ muart_src/hci_uart.ko BOARD_HAVE_BLUETOOTH := true ->One can set an early init config file to load the Bluetooth driver on early boot insmod vendor/lib/modules/hci_uart.ko ->Please make sure the bt_vendor.conf file has a configuration like the below example. mchar_port = /dev/ttyUSB0 is_uart_port = 1 baudrate_bt = 115200 baudrate_fw_init = 3000000 bd_address = 12:34:56:78:9a:bc ->One can use the below command to enable Bluetooth adb shell service call bluetooth_manager 6 Thanks & Regards, Dhruvit Vasavada Re: Bluetooth Configuration (bt_vendor.conf) for the libbt in Android 11 Hi @Dhruvit, Thanks for your support. We tried configuration changes whatever you provided, but still we are not able to enable bluetooth. Is there any other way  that we can fix this issue,so please provide us. Thanks, Re: Bluetooth Configuration (bt_vendor.conf) for the libbt in Android 11 Hi @ducho7783, I hope you are doing well. AOSP includes the HCI UART as an embedded driver in the kernel. NXP provides a modified version of this code. To enable HCI UART driver one needs to include some changes in the code parameters. These parameters can include different compile options, like m or y, and need to be set as shown in the snippet below.    Note that the configuration parameter option CONFIG_USB_SERIAL_FTDI_SIO is only necessary if you are accessing the UART interface over FTDI.   File: android_build/vendor/nxp- opensource/kernel_imx/arch/ arm/configs/imx_v7_android_ defconfig CONFIG_BT_HCIUART=m CONFIG_USB_SERIAL=y CONFIG_USB_SERIAL_FTDI_SIO=y Please make sure to do these needful changes. Thanks & Regards. Dhruvit Vasavada

Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi All,      I am trying to import a "lpcxpresso54s018_hello_world_qspi_xip" to my custom board. But I got an error message "File 'lpcxpresso54s018_hello_world_qspi_xip_HelloWorldSPIFI004.bin' load failure: Ef(11). No flash configured at the specified address." . The goal is to upload an image to the EXT SPI FLASH and the MCU will boot from the EXT SPI FLASH.      Can anyone please give an advice on how to fix the issue?   Error Message: Executing flash operation 'Program' (Program file into flash: lpcxpresso54s018_hello_world_qspi_xip_HelloWorldSPIFI004.bin) - Mon Jun 16 10:48:33 PDT 2025 Checking MCU info... Scanning for targets... Executing flash action... LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink.exe build 869) ( 0) Reading remote configuration Wc(03). No cache support. Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpcxpresso54s018_hello_world_qspi_xip_HelloWorldSPIFI004/Debug\LPC54S018.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors) Serial Number: F4ON0DG121ZHK VID:PID: 1FC9:0143 USB Path: 0001:000f:00 Using memory from core 0 after searching for a good core On debug connection - use system reset, stalling when 0x40000040 is accessed Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall Boot ROM stalled - at read watch #1 address 0x40000040 ( 30) Emulator Connected ( 40) Debug Halt ( 50) CPU ID debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0 processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0 number of h/w breakpoints = 6 number of flash patches = 2 number of h/w watchpoints = 4 Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info: Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled. Content of CoreSight Debug ROM(s): RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1) ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0) ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0) ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0) ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0) ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core NXP: LPC54S018 DAP stride is 4096 bytes (1024 words) ( 65) Chip Setup Complete Connected: was_reset=false. was_stopped=true ( 70) License Check Complete File 'lpcxpresso54s018_hello_world_qspi_xip_HelloWorldSPIFI004.bin' load failure: Ef(11). No flash configured at the specified address. (100) Target Operation Failed Unable to perform operation! Command failed with exit code 1 Thanks, 6/16/2025 LPC54xxx Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry,      Thanks for your advice on the PIO0_4,5,6!      Although I am unable to see the "hello world" message in the "lpc54018iotmodule_led_blinky_Custom Board 000", I followed your instruction on PIO0_4,5,6, and I am able to run the "lpcxpresso54s018_led_blinky_lpc_blinky_Custom Board 000". I also disconnect the SWD and power on the custom board and the blink still on going, this should be enough to proof the SPI BOOT is working right?        How do I view the "Hello World" message for the "lpc54018iotmodule_led_blinky_Custom Board 000" project?         For the PIO0_4,5,6, if I set it to all high so it should be in auto-boot mode, I wonder why it will prevent from uploading .bin file to the SPI NOR FLASH?        Also, can I use the MCU-LINK PRO and the MCUExpresso IDE for production programming?   Thanks, 7/25/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi @mtsang  I got some new idea from our internal team. You can check the ISP pins, to ensure that the chip boot type is SPIFI flash boot. And they suggest to refer to the AN12122 . You can use lpcxpresso54s018_hello_world_qspi_xip this demo. BR Harry Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry,      Thank you so much for your help and please give me an update if you got a result from the internal team. How soon will I hear back from you or the internal team?      Can you think of any other part of the schematics/code that will cause the board to be able to upload/erase code to the SPI NOR Flash but not able to boot and debug? I will double check base on your suggestion.      Currently I am using "lpc54018iotmodule_hello_world" example. Thanks, 7/15/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi @mtsang  I think this may be due to an incorrect SPI Descriptor, but unfortunately, I don't have a flash chip(IS25LP128F-JBLA3) on hand, so i can not test it, i will seek help from internal team.  I will inform you as soon as there is a result. Thanks for  your understanding. BR Harry Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry,      I can't debug the unit. It has below error output. LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink build 869) Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpc54018iotmodule_hello_world_lpc54018iotmodule/Debug\LPC54018.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors) Serial Number: F4ON0DG121ZHK VID:PID: 1FC9:0143 USB Path: 0001:0009:00 Using memory from core 0 after searching for a good core On debug connection - use system reset, stalling when 0x40000040 is accessed Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall Waiting for target to stop... Warning - processor did not halt - gave up waiting debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0 processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0 number of h/w breakpoints = 6 number of flash patches = 2 number of h/w watchpoints = 4 Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info: Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled. Content of CoreSight Debug ROM(s): RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1) ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0) ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0) ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0) ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0) ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core NXP: LPC54018 DAP stride is 4096 bytes (1024 words) Inspected v.2 External Flash Device on SPI LPC540xx_SPIFI_SFDP.cfx Image 'LPC540xx_JEDEC_SFDP Dec 18 2024 17:26:01' Opening flash driver LPC540xx_SPIFI_SFDP.cfx Sending SYSRESETREQ to run flash driver rst - Boot ROM stall address was not accessed (but we entered debug on VectorCatch anyway) There was a problem after we succesfully downloaded flash driver code to the target, so we are going to compare the flash driver code with the memory where it was loaded. Note that, after driver initialization, some difference is normal in 'generic' drivers. Driver from AXF file: //------------------ //Flash Data //------------------ AFTER driver startup timeout (302 5ms retries) Driver Addresses Start: 00000000 Entry: 0000009D End: 0000128C Stack: 00002290 Mailbox:0000A290 Driver Register State R0: 00000000 R1: 200273F8 R2: 0300AF21 R3: 00000000 R4: 40000000 R5: 00000000 R6: 00000000 R7: 00000000 R8: 00000000 R9: 00000000 R10: 00000000 R11: 00000000 R12: 00000000 SP: 00002288 LR: 0300BBA5 PC: 0300BDF2 xPSR: 21000000 MSP: 00002288 PSP: 00002290 CFBP: 00000001 (CONTROL=0x0, FAULTMASK=0x0, BASEPRI=0x0, PRIMASK=0x1) Flash Driver V.2 startup failed - rc Ef(34): Timed-out initializing flash. chip initialization failed - Ef(34): Timed-out initializing flash. failed to initialize flash driver LPC540xx_SPIFI_SFDP.cfx I click on "Attach to running target using Link server", and there what I got: I clicked on the "Verify Only" in the GUI Flash Tool and it seems to be able to download the .bin file to the SPI NOR Flash Executing flash operation 'Program' (Program file into flash: lpc54018iotmodule_hello_world_lpc54018iotmodule.bin) - Mon Jul 14 15:05:56 PDT 2025 Checking MCU info... Scanning for targets... Executing flash action... LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink.exe build 869) ( 0) Reading remote configuration Wc(03). No cache support. Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpc54018iotmodule_hello_world_lpc54018iotmodule/Debug\LPC54018.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors) Serial Number: F4ON0DG121ZHK VID:PID: 1FC9:0143 USB Path: 0001:0009:00 Using memory from core 0 after searching for a good core On debug connection - use system reset, stalling when 0x40000040 is accessed Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall Waiting for target to stop... Warning - processor did not halt - gave up waiting ( 30) Emulator Connected ( 40) Debug Halt ( 50) CPU ID debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0 processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0 number of h/w breakpoints = 6 number of flash patches = 2 number of h/w watchpoints = 4 Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info: Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled. Content of CoreSight Debug ROM(s): RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1) ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0) ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0) ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0) ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0) ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core NXP: LPC54018 DAP stride is 4096 bytes (1024 words) Inspected v.2 External Flash Device on SPI LPC540xx_SPIFI_SFDP.cfx Image 'LPC540xx_JEDEC_SFDP Dec 18 2024 17:26:01' Opening flash driver LPC540xx_SPIFI_SFDP.cfx Using SOFT reset to run the flash driver rst - Boot ROM stall address was not accessed (but we entered debug on Halt anyway) Flash variant 'JEDEC_SFDP_9D6018' detected (16MB = 256*64K at 0x10000000) Closing flash driver LPC540xx_SPIFI_SFDP.cfx ( 65) Chip Setup Complete Connected: was_reset=false. was_stopped=false ( 70) License Check Complete Verifying 'lpc54018iotmodule_hello_world_lpc54018iotmodule.bin' Binary section 0 at 0x10000000 len 0x3BA4 Opening flash driver LPC540xx_SPIFI_SFDP.cfx (already resident) Using SOFT reset to run the flash driver Flash variant 'JEDEC_SFDP_9D6018' detected (16MB = 256*64K at 0x10000000) ( 0) Comparing Flash against file at 0x10000000 Closing flash driver LPC540xx_SPIFI_SFDP.cfx (100) File matches flash. Read 0x3BA4 bytes in 43ms (about 355kB/s) - verify succeeded Thanks, 7/14/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi @mtsang  Can you debug successfully? BR Harry Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry,      I used the SPIFI descriptor you posted, but still it has the same problem. I got the following error message after I clicked on "Debug with Linkserver Probes" LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink build 869) Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpc54018iotmodule_hello_world_lpc54018iotmodule/Debug\LPC54018.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors) Serial Number: F4ON0DG121ZHK VID:PID: 1FC9:0143 USB Path: 0001:0014:00 Using memory from core 0 after searching for a good core On debug connection - use system reset, stalling when 0x40000040 is accessed Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall Boot ROM stalled - at read watch #1 address 0x40000040 debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0 processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0 number of h/w breakpoints = 6 number of flash patches = 2 number of h/w watchpoints = 4 Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info: Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled. Content of CoreSight Debug ROM(s): RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1) ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0) ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0) ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0) ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0) ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core NXP: LPC54018 DAP stride is 4096 bytes (1024 words) Inspected v.2 External Flash Device on SPI LPC540xx_SPIFI_SFDP.cfx Image 'LPC540xx_JEDEC_SFDP Dec 18 2024 17:26:01' Opening flash driver LPC540xx_SPIFI_SFDP.cfx SYSRESETREQ reset omitted - already reset Flash variant 'JEDEC_SFDP_9D6018' detected (16MB = 256*64K at 0x10000000) Closing flash driver LPC540xx_SPIFI_SFDP.cfx Connected: was_reset=false. was_stopped=true Awaiting telnet connection to port 3330 ... GDB nonstop mode enabled Opening flash driver LPC540xx_SPIFI_SFDP.cfx (already resident) Retask watch 0 address 0x0 (unused) for boot rom stall Sending SYSRESETREQ to run flash driver Boot ROM stalled accessing address 0x40000040 (restoring watchpoint 1) AFTER driver startup timeout (302 5ms retries) Driver Addresses Start: 00000000 Entry: 0000009D End: 0000128C Stack: 00002290 Mailbox:0000A290 Driver Register State R0: 0000A290 R1: 00000000 R2: 00000000 R3: 00000000 R4: 00000000 R5: 00000000 R6: 00000000 R7: 00000000 R8: 00000000 R9: 00000000 R10: 00000000 R11: 00000000 R12: 00000000 SP: 00002290 LR: 0000009D PC: 000000A0 xPSR: 61000000 MSP: 00002290 PSP: 00002290 CFBP: 00010001 (CONTROL=0x0, FAULTMASK=0x1, BASEPRI=0x0, PRIMASK=0x1) Flash Driver V.2 startup failed - rc Ef(34): Timed-out initializing flash. (100) Writing Flash ended with an error. Target error from Commit Flash write: Ef(34): Timed-out initializing flash. GDB stub (C:\nxp\LinkServer_24.12.21\binaries\crt_emu_cm_redlink) terminating - GDB protocol problem: Pipe has been closed by GDB. Thanks, 7/10/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi @mtsang  If you want to XIP. Did you try to change to it in startup_lpc54s018.c? #ifdef IS25LP128F-JBLA3 /* SPI Descriptor - IS25LP128F-JBLA3 */ (void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ;DevStrAdr (void (*)(void))0x0018609D, // mfgId + extCount (void (*)(void))0x00000000, // extid 0-3 (void (*)(void))0x00000000, // reserved (void (*)(void))0x1301001D, // caps (void (*)(void))0x00000100, // Blks + RESV1 (void (*)(void))0x00010000, // blkSize (void (*)(void))0x00000000, // reserved (void (*)(void))0x00000100, // pageSize + RESV2 (void (*)(void))0x00003F00, // maxReadSize (void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate (void (*)(void))0x06020050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId (void (*)(void))0x14110F0B, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId #endif BR Harry Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry,      Thanks for the schematics correction! However it seems like I am able to flash the .bin file to the SPI NOR Flash, but the MCU is not able to boot from the SPI NOR Flash. I installed and removed PIO0_6 pull-up resistor but it didnt help. Flash the SPI NOR FLASH Executing flash operation 'Program' (Program file into flash: Debug\lpc54018iotmodule_hello_world_lpc54018iotmodule.axf) - Wed Jul 09 16:39:19 PDT 2025 Checking MCU info... Scanning for targets... Executing flash action... LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink.exe build 869) ( 0) Reading remote configuration Wc(03). No cache support. Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpc54018iotmodule_hello_world_lpc54018iotmodule/Debug\LPC54018.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors) Serial Number: F4ON0DG121ZHK VID:PID: 1FC9:0143 USB Path: 0001:000b:00 Using memory from core 0 after searching for a good core On debug connection - use system reset, stalling when 0x40000040 is accessed Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall Waiting for target to stop... Warning - processor did not halt - gave up waiting ( 30) Emulator Connected ( 40) Debug Halt ( 50) CPU ID debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0 processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0 number of h/w breakpoints = 6 number of flash patches = 2 number of h/w watchpoints = 4 Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info: Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled. Content of CoreSight Debug ROM(s): RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1) ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0) ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0) ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0) ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0) ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core NXP: LPC54018 DAP stride is 4096 bytes (1024 words) Inspected v.2 External Flash Device on SPI LPC540xx_SPIFI_SFDP.cfx Image 'LPC540xx_JEDEC_SFDP Dec 18 2024 17:26:01' Opening flash driver LPC540xx_SPIFI_SFDP.cfx Using SOFT reset to run the flash driver rst - Boot ROM stall address was not accessed (but we entered debug on Halt anyway) Flash variant 'JEDEC_SFDP_9D6018' detected (16MB = 256*64K at 0x10000000) Closing flash driver LPC540xx_SPIFI_SFDP.cfx ( 65) Chip Setup Complete Connected: was_reset=false. was_stopped=false ( 70) License Check Complete Loading 'lpc54018iotmodule_hello_world_lpc54018iotmodule.axf' ELF 0x10000000 len 0x3BA4 Opening flash driver LPC540xx_SPIFI_SFDP.cfx (already resident) Using SOFT reset to run the flash driver Flash variant 'JEDEC_SFDP_9D6018' detected (16MB = 256*64K at 0x10000000) Writing 15268 bytes to address 0x10000000 in Flash 1 of 1 ( 0) Writing sectors 0-0 at 0x10000000 with 15268 bytes ( 0) at 10000000: 0 bytes - 0/15268 (100) at 10000000: 65536 bytes - 65536/15268 Sectors written: 0, unchanged: 1, total: 1 Erased/Wrote sector 0-0 with 15268 bytes in 30msec Closing flash driver LPC540xx_SPIFI_SFDP.cfx (100) Finished writing Flash successfully. Flash Write Done Loaded 0x3BA4 bytes in 89ms (about 171kB/s) Reset target (romstall) Starting execution using system reset with a stall address Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall Boot ROM stalled accessing address 0x40000040 (restoring watchpoint 1) Stopped (Was Reset) [Reset from Unknown]: Watchpoint (Temp) #1 - read watchpoint at 0x40000040 Data watch for bootloader stall restart on reset Verify the SPI NOR FLASH's content Executing flash operation 'Program' (Program file into flash: lpc54018iotmodule_hello_world_lpc54018iotmodule.bin) - Wed Jul 09 16:43:17 PDT 2025 Checking MCU info... Scanning for targets... Executing flash action... LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink.exe build 869) ( 0) Reading remote configuration Wc(03). No cache support. Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpc54018iotmodule_hello_world_lpc54018iotmodule/Debug\LPC54018.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors) Serial Number: F4ON0DG121ZHK VID:PID: 1FC9:0143 USB Path: 0001:000b:00 Using memory from core 0 after searching for a good core On debug connection - use system reset, stalling when 0x40000040 is accessed Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall Boot ROM stalled - at read watch #1 address 0x40000040 ( 30) Emulator Connected ( 40) Debug Halt ( 50) CPU ID debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0 processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0 number of h/w breakpoints = 6 number of flash patches = 2 number of h/w watchpoints = 4 Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info: Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled. Content of CoreSight Debug ROM(s): RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1) ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0) ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0) ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0) ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0) ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core NXP: LPC54018 DAP stride is 4096 bytes (1024 words) Inspected v.2 External Flash Device on SPI LPC540xx_SPIFI_SFDP.cfx Image 'LPC540xx_JEDEC_SFDP Dec 18 2024 17:26:01' Opening flash driver LPC540xx_SPIFI_SFDP.cfx Using SOFT reset to run the flash driver Flash variant 'JEDEC_SFDP_9D6018' detected (16MB = 256*64K at 0x10000000) Closing flash driver LPC540xx_SPIFI_SFDP.cfx ( 65) Chip Setup Complete Connected: was_reset=false. was_stopped=true ( 70) License Check Complete Verifying 'lpc54018iotmodule_hello_world_lpc54018iotmodule.bin' Binary section 0 at 0x10000000 len 0x3BA4 Opening flash driver LPC540xx_SPIFI_SFDP.cfx (already resident) Using SOFT reset to run the flash driver Flash variant 'JEDEC_SFDP_9D6018' detected (16MB = 256*64K at 0x10000000) ( 0) Comparing Flash against file at 0x10000000 Closing flash driver LPC540xx_SPIFI_SFDP.cfx (100) File matches flash. Read 0x3BA4 bytes in 41ms (about 372kB/s) - verify succeeded Thanks, 7/9/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry,      I am terribly sorry I didn't check the SPI NOR Flash pin out. Thanks for your catch!!! I used jumper cable to fix the problem for now.      Seems like I am able to program and mass erase the custom board right now. At least it didnt show any error message.      I am using "lpc54018iotmodule_hello_world_virtual_com_xip" as an example. Is there anything I can do to verify the SPI boot function? Also where the "HELLO WORLD" message will shows up? Thanks a lot! 7/8/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi @mtsang  I think your schematics of the SPI NOR FLASH is wrong. In the NOR FLASH Data sheet. PIN 5 SI should be connected IO0. PIN 2 SO should be connected IO1. But in your schematic. PIN 5 SI is connected IO1. BR Harry Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry,      Sure! Attached is the schematics of the SPI NOR FLASH. SPIFI_CSN -> LPC54S018JET180E_N7 SPIFI_IO0 -> LPC54S018JET180E_M7 SPIFI_IO1 -> LPC54S018JET180E_K8 SPIFI_IO2 -> LPC54S018JET180E_M9 SPIFI_IO3 -> LPC54S018JET180E_L9 SPIFI_SCK -> LPC54S018JET180E_M13 Thanks, 7/7/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi @mtsang  Can you share your schematic about the flash? BR Harry Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry, Thanks for your detailed response, but I am still getting the same error. Executing flash operation 'Program' (Program file into flash: Debug\lpc54018iotmodule_hello_world_lpc54018iotmodule.axf) - Thu Jul 03 14:29:23 PDT 2025 Checking MCU info... Scanning for targets... Executing flash action... LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink.exe build 869) ( 0) Reading remote configuration Wc(03). No cache support. Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpc54018iotmodule_hello_world_lpc54018iotmodule/Debug\LPC54018.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors) Serial Number: F4ON0DG121ZHK VID:PID: 1FC9:0143 USB Path: 0001:001a:00 Using memory from core 0 after searching for a good core On debug connection - use system reset, stalling when 0x40000040 is accessed Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall Waiting for target to stop... Warning - processor did not halt - gave up waiting ( 30) Emulator Connected ( 40) Debug Halt ( 50) CPU ID debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0 processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0 number of h/w breakpoints = 6 number of flash patches = 2 number of h/w watchpoints = 4 Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info: Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled. Content of CoreSight Debug ROM(s): RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1) ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0) ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0) ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0) ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0) ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core NXP: LPC54018 DAP stride is 4096 bytes (1024 words) Inspected v.2 External Flash Device on SPI LPC540xx_SPIFI_SFDP.cfx Image 'LPC540xx_JEDEC_SFDP Dec 18 2024 17:26:01' Opening flash driver LPC540xx_SPIFI_SFDP.cfx Using SOFT reset to run the flash driver rst - Boot ROM stall address was not accessed (but we entered debug on Halt anyway) Driver V.2 dynamic startup failed - driver Init provided no flash parameters Flash Driver V.2 startup failed - rc Ef(55): Dynamic flash driver startup failed to provide flash parameters. Terminate (0x0, 0x0, 0x0) status 0x40 - driver reports init failure - EXTSPI driver rc 15 (0xF) chip initialization failed - Ef(55): Dynamic flash driver startup failed to provide flash parameters. failed to initialize flash driver LPC540xx_SPIFI_SFDP.cfx ( 65) Chip Setup Complete (100) Target Operation Failed Unable to perform operation! Command failed with exit code 1 Thanks, 7/3/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi @mtsang  About the different register define. I think you can refer to the UM11060 Table 12. Image header for the LPC540xx devices. I checked the IS25LP128F-JBLA3 DATA SHEET. Regarding how to configure relevant parameters, let me give an example to illustrate. 1. So setStatusFxId is 0B. 2. So setOptionsFxId is 0F 3. So the getReadCmdFxId is 0x11. 4. So getStatusFxId is 06. And so on. And i write one based on the  IS25LP128F-JBLA3 data sheet and the  SDK startup_lpc54s018.c #ifdef IS25LP128F-JBLA3 /* SPI Descriptor - IS25LP128F-JBLA3 */ (void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ;DevStrAdr (void (*)(void))0x0018609D, // mfgId + extCount (void (*)(void))0x00000000, // extid 0-3 (void (*)(void))0x00000000, // reserved (void (*)(void))0x1301001D, // caps (void (*)(void))0x00000100, // Blks + RESV1 (void (*)(void))0x00010000, // blkSize (void (*)(void))0x00000000, // reserved (void (*)(void))0x00000100, // pageSize + RESV2 (void (*)(void))0x00003F00, // maxReadSize (void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate (void (*)(void))0x06020050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId (void (*)(void))0x14110F0B, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId #endif You can double check. And then  You can replace it with IS25LP128F-JBLA3. BR Harry Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry,      Sorry for the late reply and thanks for the infos.      I am still confused about how to find the info marked with BOLD Text. Can you please provide advice on how to find those infos in the IS25LP128F datasheet.      Also for the macro marked with BOLD text. Once I changed the macro, is there anything I need to change to the entire project setup like (Project Setting, 'startup_lpc54018.c', etc) What I found so far, please double check if I am correct //maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate Clock Frequency except for fast read: 166Mhz (A3h) Clock Frequency for read (03h): 80Mhz (50h) #ifdef IS25LP128F-JBLA3 /* SPIFI Descriptor - IS25LP128F-JBLA3 */ (void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ；DevStrAdr (void (*)(void))0x0018609D, // mfgId + extCount (void (*)(void))0x00000000, // extid 0-3 (void (*)(void))0x00000000, // extid 4-7 (void (*)(void))0x0001001D, // caps (void (*)(void))0x00000100, // Blks + RESV1 (void (*)(void))0x00010000, // blkSize (void (*)(void))0x00000000, // subBlks + subBlkSize (void (*)(void))0x00000100, // pageSize + RESV2 (void (*)(void))0x00003F00, // maxReadSize (void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate (void (*)(void))0x04030050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId, (void (*)(void))0x14110D09, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId #endif Thanks, 6/30/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry,      Sorry for the late reply and thanks for the info.      However I am still confused about how to find the info marked with Red Text. Can you please provide advice on how to find those infos in the IS25LP128F datasheet.      Also for the macro marked with blue text. Once I changed the macro, is there anything I need to change to the entire project setup like (Project Setting, 'startup_lpc54018.c', etc) Here's what I found, please double check if they are correct: //maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate Clock Frequency except for fast read: 166Mhz (A3h) Clock Frequency for read (03h): 80Mhz (50h) #ifdef IS25LP128F-JBLA3 /* SPIFI Descriptor - IS25LP128F-JBLA3 */ (void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ；DevStrAdr (void (*)(void))0x0018609D, // mfgId + extCount (void (*)(void))0x00000000, // extid 0-3 (void (*)(void))0x00000000, // extid 4-7 (void (*)(void))0x0001001D, // caps (void (*)(void))0x00000100, // Blks + RESV1 (void (*)(void))0x00010000, // blkSize (void (*)(void))0x00000000, // subBlks + subBlkSize (void (*)(void))0x00000100, // pageSize + RESV2 (void (*)(void))0x00003F00, // maxReadSize (void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate (void (*)(void))0x04030050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId, (void (*)(void))0x14110D09, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId #endif Thanks, 6/30/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi @mtsang  You are right. You need to modify the SPIFI Descriptor. You currently have: (void (*)(void))0x001870EF, // mfgId + extCount This corresponds to: mfgId = 0xEF (Winbond, not correct for IS25LP128F) device ID = 0x70 (part of JEDEC ID for W25Q128) But for IS25LP128F, the JEDEC ID is:   Manufacturer ID = 0x9D (ISSI) Memory type = 0x60 Capacity = 0x18   So you should change:   (void (*)(void))0x0018609D, // mfgId + extCount (extCount = 1, mfgId = 0x9D, memType = 0x60, capacity = 0x18)   And you should also verify (void (*)(void))0x04030050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId, (void (*)(void))0x14110D09, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId BR Harry Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry,      Thank you so much for the reply!      I am using "IS25LP128F-JBLA3" for the custom board. According to the datasheet(please see attached IS25LP128F-JBLA3 datasheet), it seems to support SFDP. I am switching back to "LPC540xx_SPIFI_SFDP.cfx" for memory config.    I checked the "SPIFI Descriptor"  in the "LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip" startup_lpc54018.c I saw the SPIFI Descriptor : #ifdef W25Q128JVFM /* SPIFI Descriptor - W25Q128JVFM */ (void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ；DevStrAdr (void (*)(void))0x001870EF, // mfgId + extCount (void (*)(void))0x00000000, // extid 0-3 (void (*)(void))0x00000000, // extid 4-7 (void (*)(void))0x0001001D, // caps (void (*)(void))0x00000100, // Blks + RESV1 (void (*)(void))0x00010000, // blkSize (void (*)(void))0x00000000, // subBlks + subBlkSize (void (*)(void))0x00000100, // pageSize + RESV2 (void (*)(void))0x00003F00, // maxReadSize (void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate (void (*)(void))0x04030050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId, (void (*)(void))0x14110D09, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId #endif      Should I change the SPIFI Descriptor(I modified the Bold Text)? Also I am unsure what to change for the under-line section. What else I need to change in order to make the example project works on my custom board: #ifdef IS25LP128F-JBLA3 /* SPIFI Descriptor - IS25LP128F-JBLA3 */ (void (*)(void))0x00000000, // 0xFFFFFFFF to default 1-bit SPI mode ；DevStrAdr (void (*)(void))0x001870EF, // mfgId + extCount (void (*)(void))0x00000000, // extid 0-3 (void (*)(void))0x00000000, // extid 4-7 (void (*)(void))0x0001001D, // caps (void (*)(void))0x00000100, // Blks + RESV1 (void (*)(void))0x00010000, // blkSize (void (*)(void))0x00000000, // subBlks + subBlkSize (void (*)(void))0x00000100, // pageSize + RESV2 (void (*)(void))0x00003F00, // maxReadSize (void (*)(void))0x68506850, // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate (void (*)(void))0x04030050, // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId, (void (*)(void))0x14110D09, // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId #endif Thanks, 6/23/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi @mtsang  From your log: Flash Driver V.2 startup failed - rc Ef(55): Dynamic flash driver startup failed to provide flash parameters. The SPIFI  flash driver attempted to probe your external flash device via SFDP, but failed to identify valid parameters for your flash. What is the exact part number of the flash IC on your custom board? Check its datasheet for SFDP support — not all parts provide SFDP data. BR Harry Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi Harry,      I deselect the "Link Application to RAM" and I got the below error message: Executing flash operation 'Program' (Program file into flash: Debug\lpcxpresso54s018_hello_world_qspi_xip_HelloWorldSPIFI003.axf) - Tue Jun 17 12:17:21 PDT 2025 Checking MCU info... Scanning for targets... Executing flash action... LinkServer RedlinkMulti Driver v24.12 (Dec 18 2024 18:34:07 - crt_emu_cm_redlink.exe build 869) ( 0) Reading remote configuration Wc(03). No cache support. Found chip XML file in C:/Users/tsangm/Documents/MCUXpressoIDE_24.12.148/workspace/lpcxpresso54s018_hello_world_qspi_xip_HelloWorldSPIFI003/Debug\LPC54S018.xml ( 5) Remote configuration complete Reconnected to existing LinkServer process. Probe Firmware: MCU-LINK Pro (r0CF) CMSIS-DAP V3.153 (NXP Semiconductors) Serial Number: F4ON0DG121ZHK VID:PID: 1FC9:0143 USB Path: 0001:0018:00 Using memory from core 0 after searching for a good core On debug connection - use system reset, stalling when 0x40000040 is accessed Retask read watchpoint 1 at 0x40000040 to use for boot ROM stall Waiting for target to stop... Warning - processor did not halt - gave up waiting ( 30) Emulator Connected ( 40) Debug Halt ( 50) CPU ID debug interface type = CoreSight DP (DAP DP ID 2BA01477) over SWD TAP 0 processor type = Cortex-M4 (CPU ID 00000C24) on DAP AP 0 number of h/w breakpoints = 6 number of flash patches = 2 number of h/w watchpoints = 4 Probe(0): Connected&Reset. DpID: 2BA01477. CpuID: 00000C24. Info: Debug protocol: SWD. RTCK: Disabled. Vector catch: Enabled. Content of CoreSight Debug ROM(s): RBASE E00FF000: CID B105100D PID 04000BB4C4 ROM (type 0x1) ROM 1 E000E000: CID B105E00D PID 04000BB00C Gen SCS (type 0x0) ROM 1 E0001000: CID B105E00D PID 04003BB002 Gen DWT (type 0x0) ROM 1 E0002000: CID B105E00D PID 04002BB003 Gen FPB (type 0x0) ROM 1 E0000000: CID B105E00D PID 04003BB001 Gen ITM (type 0x0) ROM 1 E0040000: CID B105900D PID 04000BB9A1 CSt TPIU type 0x11 Trace Sink - TPIU ROM 1 E0041000: CID B105900D PID 04000BB925 CSt ETM type 0x13 Trace Source - Core NXP: LPC54S018 DAP stride is 4096 bytes (1024 words) Inspected v.2 External Flash Device on SPI LPC540xx_SPIFI_SFDP.cfx Image 'LPC540xx_JEDEC_SFDP Dec 18 2024 17:26:01' Opening flash driver LPC540xx_SPIFI_SFDP.cfx Using SOFT reset to run the flash driver rst - Boot ROM stall address was not accessed (but we entered debug on Halt anyway) Driver V.2 dynamic startup failed - driver Init provided no flash parameters Flash Driver V.2 startup failed - rc Ef(55): Dynamic flash driver startup failed to provide flash parameters. Terminate (0x0, 0x0, 0x0) status 0x40 - driver reports init failure - EXTSPI driver rc 15 (0xF) chip initialization failed - Ef(55): Dynamic flash driver startup failed to provide flash parameters. failed to initialize flash driver LPC540xx_SPIFI_SFDP.cfx ( 65) Chip Setup Complete (100) Target Operation Failed Unable to perform operation! Command failed with exit code 1 Thanks, 6/17/2025 Re: Custom Board LPC54S018JET180E lpcxpresso54s018_hello_world_qspi_xip Question Hi @mtsang  I have a question. According to your need. Why you select the "link application to ram" You can deselect this, and try again. BR Harry

Import of Simulink created Project to S32DS Currently working with the S32K144 EVB and utilizing MATLAB Model-Based Design (MBD) for code generation, issues are being encountered while trying to import the generated project into S32 Design Studio. Despite following all instructions and references from NXP community forums and official documentation, the project fails to import into the development environment. Other manually created projects can be successfully built, imported, and deployed without any issues, but Simulink-generated projects consistently encounter this problem. Details regarding the issue: MATLAB/Simulink Version: MATLAB 2024a MBD Toolbox Version: v4.2.0 S32 Design Studio Version: S32DS v3.5 Steps taken: Guidelines from community resources have been followed.    The generated ProjectInfo.xml file has been verified. Compatibility between the MBD Toolbox and S32 Design Studio has been checked. How to export Generated Code to S32 Design Studio IDE (applicable for MBDT for MPC5744P v2.0) - NXP Community Re: How to export S32K144 MBDT Generated Code to S32 Design Studio - NXP Community A snapshot highlighting the specific point of the issue is attached for reference. Re: Import of Simulink created Project to S32DS I'm also facing same issue while importing xml file to s32ds. I'm using S32DS version 3.5 and MATLAB R2021b. Someone please help me with this

LPC55S36 I3C Slave Speed Limitation Two LPC55S36 boards were connected for I3C communication, with one configured as the I3C Master and the other as the I3C Slave. When the Master’s push-pull baud rate is set to 1.25 Mbps, communication proceeds without issues. However, increasing the baud rate to 2.0 Mbps causes the Slave to fail in receiving data properly, resulting in a NACK response. The question is whether there are any configuration parameters or tuning methods available that would allow the I3C Slave to reliably handle higher baud rates. Note: The sample code being used employs the function I3C_BusMasterDoTransferToI3CDev, which is defined in the fsl_component_i3c_adapter.h header. This function performs a write to the device address followed by a read, even during read operations. In contrast, the SDK example lpcxpresso55s36_i3c_polling_b2b_transfer_master uses the function I3C_MasterTransferBlocking, which performs a pure read operation during reads. Due to this behavioral difference, the latter example (I3C_MasterTransferBlocking) is able to operate correctly at 2.0 Mbps, whereas the former (I3C_BusMasterDoTransferToI3CDev) leads to reception failures at the same baud rate. At even higher baud rates, both approaches result in failed receptions on the Slave side. Re: LPC55S36 I3C Slave Speed Limitation Thank you for the explanation. As you noted, when the speed is too high, the Slave does not have sufficient time to fill the TX FIFO, so it responds with a NACK. Re: LPC55S36 I3C Slave Speed Limitation Hi @bell_huang  I have debugged the slave code. I add one toggle signal. The start address header uses open-drain baudrate (typically less than 2MHz), allowing the target more time to fill the TX FIFO and thereby achieve ACK. However, the repeated start address header uses push-pull baudrate, and if set above 4MHz, the target doesn't have sufficient time to fill the TX FIFO, resulting in NACK. Based on current MCU performance, if we want to achieve higher rates, we need to optimize the target code to accelerate its response speed. BR Harry Re: LPC55S36 I3C Slave Speed Limitation Hi @Harry_Zhang , Thank you for the information about setting the optimization level to O3. After adjusting the Slave configuration, the Master now appears to reach 4 Mbps. (I’m not sure why, but after a Slave reset the Master’s first Read fails, while subsequent Reads succeed.) Could you confirm whether 4 Mbps is indeed the limit on the Slave side? As mentioned earlier, the I3C specification allows up to 12.5 Mbps; even the Building an I3C Sensor Network Using LPC553x/LPC55S3x example operates at 10 Mbps. Re: LPC55S36 I3C Slave Speed Limitation Hi @bell_huang  I have tested it. When the PP Baud is setted to 2M. baudrate_config.i3cPushPullBaud = 2000000; baudrate_config.i3cOpenDrainBaud = 625000; You can try to improve the optimization level of the code. It can work. BR Harry Re: LPC55S36 I3C Slave Speed Limitation As mentioned in the note of my first post: The simple examples in the SDK (such as lpcxpresso55s36_i3c_polling_b2b_transfer_master) use a Single message format, which means: Write: Slave Address (RnW = 0) → Data Read: Slave Address (RnW = 1) → Data However, almost all sensors in the industry (for example, lpcxpresso55s36_i3c_master_read_sensor_icm42688p) use a Combined format, which means: Write: Slave Address (RnW = 0) → Register Address → Data Read: Slave Address (RnW = 0) → Register Address → repeated START → Slave Address (RnW = 1) → Data This explains why your Single message example can reach up to 2.0 Mbps, while my Combined format example can only achieve a maximum of 1.25 Mbps. In lpcxpresso55s36_i3c_polling_b2b_transfer_master, if you modify masterXfer to use the Combined format by adding the following code, it will switch to the Combined format. Then you will observe that the maximum achievable speed drops to 1.25 Mbps. Please refer to the attachment in this reply. masterXfer.subaddress = 0x34; masterXfer.subaddressSize = 1; Additionally, the most important point is that the I3C specification defines the baud rate to support up to 12.5 Mbps. Both Single message (Max = 2.0 Mbps) and Combined format (Max = 1.25 Mbps) are far below this limit. This is why I would like to know if there is any way to improve the Slave’s capability to accept higher baud rates. Re: LPC55S36 I3C Slave Speed Limitation Hi @bell_huang  I tested the lpc5536 SDK i3c example. I changed the EXAMPLE_I3C_PP_BAUDRATE #define EXAMPLE_I3C_PP_BAUDRATE 2000000 It can work. So it  proves that it can work at this speed. BR Harry Re: LPC55S36 I3C Slave Speed Limitation Hi @Harry_Zhang , Test steps: (1) Reset slave board (2) Reset master board Also check out the speed configuration in master code: baudrate_config.i3cPushPullBaud = 1250000; baudrate_config.i3cOpenDrainBaud = 625000; If we modify i3cPushPullBaud to 2000000, then the master cannot read correct data. Re: LPC55S36 I3C Slave Speed Limitation Hi @bell_huang  Can you share your project? So I can reproduce this issue. BR Harry

Inquiry on Cryptographic Features of LX2160A RDB I hope this message finds you well. I am evaluating the LX2160A Reference Design Board (RDB) for a secure networking application and would appreciate clarification on some aspects related to its cryptographic capabilities. Specifically, I would like to know: Cryptographic Boundary: Does the cryptographic engine within the LX2160A SoC have a defined cryptographic boundary in line with security certification frameworks (e.g., FIPS 140-2)? Code and Memory Isolation: Is the cryptographic code logically isolated from other software components? Is there any form of physical separation between the crypto code and the rest of the system? Does the SoC reserve dedicated memory for cryptographic operations? Sandbagging Support: Does the platform support any kind of sandbagging—i.e., deliberate buffering, obfuscation, or timing equalization to mitigate side-channel attacks? FIPS 140-2 Level 3: Is it possible to achieve FIPS 140-2 Level 3 compliance using the LX2160A platform, either directly or through integration with external secure elements? Documentation: Are there any white papers, application notes, or security architecture documents available that detail the cryptographic and isolation mechanisms implemented in the LX2160A or the RDB? Re: Inquiry on Cryptographic Features of LX2160A RDB Hey. While the answer satisfied my query, i need a clarification. Are the cryptographic algorithms implemented within the chip or is it just a blank accelerator where i have to implement the algorithms myself by writing a crypto code. I'll clarify by mentioning that i wish to implement DES, 3DES, AES-128, AES-256, RSA(748, 1024, 2048 bit), ECDSA (256/384 bit). MD5, SHA, SHA-256, SHA-384, SHA-512. Are these already available in the chip or a code has to be written for its implementation in software? Re: Inquiry on Cryptographic Features of LX2160A RDB We have FSLNISTCAVP.pdf, but as far as I know, we don't have an update. FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP® Cryptographic Accelerators - White Paper   We have been telling customers to check the individual crypto suites that they need.  Because the LX2160 uses the same engine as the LS processors. If you have a particular algorithm that you are interested in, I can check with our internal team about it. But as this is related to the SEC, please create a case https://support.nxp.com/s/?language=en_US And confirm you have a NDA in place. Thanks

LX2160A RDBの暗号化機能に関するお問い合わせ このメッセージがあなたに届いて、お元気でいらっしゃることを願っております。私は、安全なネットワーク アプリケーション用にLX2160A リファレンス デザイン ボード (RDB)を評価しており、その暗号化機能に関連するいくつかの側面について明確に説明していただければ幸いです。 具体的には、次の点を知りたいです。 暗号化境界: LX2160A SoC 内の暗号化エンジンには、セキュリティ認証フレームワーク (FIPS 140-2 など) に準拠した暗号化境界が定義されていますか? コードとメモリのアイソレータ: 暗号化コードは他のソフトウェア コンポーネントから論理的に分離されていますか? 暗号コードとシステムの残りの部分の間には、何らかの物理的な分離がありますか? SoC は暗号化操作用に専用のメモリを予約していますか? サンドバッギングのサポート: プラットフォームは、サイドチャネル攻撃を軽減するための意図的なバッファリング、難読化、タイミング均等化など、あらゆる種類のサンドバッギングをサポートしていますか? FIPS 140-2 レベル 3 : LX2160A プラットフォームを直接使用して、または外部のセキュア エレメントと統合して、 FIPS 140-2 レベル 3 準拠を達成することは可能ですか? ドキュメント: LX2160A または RDB に実装されている暗号化およびアイソレータメカニズムの詳細を説明したホワイト ペーパー、アプリケーションノート、またはセキュリティ アーキテクチャ ドキュメントはありますか? Re: Inquiry on Cryptographic Features of LX2160A RDB おい。回答は私の質問に満足しましたが、説明が必要です。暗号アルゴリズムはチップ内に実装されていますか、それとも暗号コードを記述して自分でアルゴリズムを実装する必要がある単なる空のアクセラレータですか。DES、3DES、AES-128、AES-256、RSA (748、1024、2048 ビット)、ECDSA (256/384 ビット) を実装したいということを明記しておきます。MD5、SHA、SHA-256、SHA-384、SHA-512。これらはすでにチップ内で利用可能でしょうか、それともソフトウェアで実装するためにコードを書く必要がありますか? Re: Inquiry on Cryptographic Features of LX2160A RDB FSLNISTCAVP.pdfがあります。しかし、私の知る限り、更新情報はありません。 FSLNISTCAVP、NXP ®暗号アクセラレータ向け NIST 暗号アルゴリズム検証プログラム認証 - ホワイトペーパー お客様には、必要な個別の暗号スイートを確認するようご案内しています。LX2160 は LS プロセッサと同じエンジンを使用しているためです。 特定のアルゴリズムにご興味がある場合は、弊社の社内チームに CAN 確認させていただきます。 しかし、これはSECに関係しているので、CASEを作成してください https://support.nxp.com/s/?language=en_US また、NDA が締結されていることを確認してください。 よろしくお願いします。

Crypto_43_HSE 错误的配置导出 你好 我使用的是 Crypto_43_HSE RTD 驱动程序 v5.0.0。 我在 EB Tresos 中配置了驱动程序，然后执行输出程序生成 .arxml文件，以便将其导入外部工具（达芬奇配置器） 不过，生成器创建导出文件的方式似乎有些问题。更具体地说，在导出的 ARXML 中，参数 HseKeyCatalogGroupRef 被定义为 upper multiplicity = lower multiplicity = 1，因此这意味着必须始终填写该参数。 但在有些情况下，这种情况是不可能发生的。 例如，当我定义 KeyElementId=2 和 6 的 KeyElements SHE Mac Proof 和 SHE Cipher Proof 时，我没有选择 "Use Hse Key"（使用 HSE 密钥）选项，因为这些密钥不能链接到 HSE 密钥槽，因此 HseKeyCatalogGroupRef 仍然为空（并发出警告） 所以、既然存在 HseKeyCatalogGroupRef 可能为空的情况，我认为导出程序以多重性 = (1,1) 的方式生成参数是错误的，因为这意味着必须始终定义该参数。 事实上，当我通过 .arxml文件时，该工具会抱怨 HseKeyCatalogGroupRef 参数为空，原因如上所述。 此致敬礼， Re: Crypto_43_HSE wrong configuration export 你好 看得出来，问题似乎还没有解决。 例如，分析与最新 Crypto_43_HSE 模块捆绑在一起的 Crypto_43_HSE_s32k312_hdqfp100.epd 文件，可以看到该参数的上多重性 = 下多重性 = 1： DaVinci 配置器从该文件中提取定义信息，正如我所说，我不得不对其进行配置。 Re: Crypto_43_HSE wrong configuration export 你好@strofald 很抱歉延迟回复。我刚刚收到以下反馈： " 开发团队已经确认，在最新的代码库中，hsekeyCatalogGroupref 的多重性配置正确，使其成为可选的。这意味着多重性有效，并且允许在不适用时将该字段留空。" "在密码配置中，HseKeyCatalogGroupRef 没有添加多重性，而工具本身默认将下多重性和上多重性添加为 1。" 此致， Lukas Re: Crypto_43_HSE wrong configuration export 你好@strofald 很抱歉延迟回复。 我已经向 SW 团队询问了这个问题，稍后会让你们知道他们的反馈。感谢您的耐心等待。 此致， Lukas

RT1170: Using MIPI-CSI with grayscale or raw image sensors Dear all, according to another topic here on the forum the MIPI-CSI2 peripheral on the RT1170 does not support grayscale and RAW image sensors due to a silicon bug. Since this is a major issue for anyone using the MCU for e.g. computer vision applications it would be great to discuss possible work-arounds or solutions in this topic. More specifically, could someone from NXP please comment on the following questions: Are there any work-arounds/hacks to make a grayscale/RAW8 sensor work with the RT1170? Maybe even by using additional hardware, or tricks in software? Will this bug be fixed in a future revision of the silicon, and if yes, is there a rough timeline on when an updated RT1170 MCU will be available? Again, I'd like to emphasize how bad this issue is. This is not just an "inconvenience" but instead will prevent the MCU from being used for many applications in computer vision, where it would otherwise be a perfect fit! Please, NXP, treat this issue with the importance it deserves! If anyone else has any tipps or suggestions I'd be happy to hear them! Unless I find a fix for this issue, this will kill the product I am working on. Best, Michael Re: RT1170: Using MIPI-CSI with grayscale or raw image sensors   Hi Michael-parthei, Did you get this "lying" trick working? Re: RT1170: Using MIPI-CSI with grayscale or raw image sensors Is RGB mode working ? Re: RT1170: Using MIPI-CSI with grayscale or raw image sensors Hi @michael_parthei Did you manage to capture RAW8 data using MIPI CSI-2? If not did you find a workaround? Best regards Re: RT1170: Using MIPI-CSI with grayscale or raw image sensors Dear @kerryzhou, Can you please advise if our iMXRT1170 has fixed the video mux bug, that prevented the MIPI-CSI2 from supporting the 14-bit raw data? Waiting for your kind feedback, many thanks. Regards, Shai Re: RT1170: Using MIPI-CSI with grayscale or raw image sensors hi nxp ! any update regarding the problem we use rt1176 and we need 14bit raw data support!!!!!! the camera support only raw format   workaround ? new silicon rev fixes it? Re: RT1170: Using MIPI-CSI with grayscale or raw image sensors Hi michael_parthei，   You are welcome. 1. About your idea, I think you can use it, you can use the RGB mode to receive your raw data, then try to display it, whether the result is Ok or not, you can test it at first, just to confirm the thought. 2. About 8bit-grayscale/RAW image sensors, sorry, I didn't use that type of convert sensor in the previous time. RT1170 already has the CSI interface, that is the parallel interface, which is not the MIPI_CSI2. Wish it helps you! Best Regards, Kerry Re: RT1170: Using MIPI-CSI with grayscale or raw image sensors Thanks Kerry for your help! It would be great to get your input on the following possible solutions: Would it work to use the MIPI CSI peripheral in RGB mode with a 8-bit RAW camera sensor by "lying" about the resolution? For instance: let's say the camera sensor is 640x480 with 8-bit grayscale values. Could one configure the MIPI CSI peripheral on the MCU to use RGB565 (that is, two bytes per pixel) with 320x480 resolution? In the end, this would result in the same about of data send per frame (actually, even same amount for each image row), and I'd say the MIPI CSI peripheral shouldn't really care about the interpretation of that data. Would this approach work, or am I missing something? The camera parallel interface of the RT1170 supports 8bit-grayscale/RAW image sensors, correct?  Do you have any experience with using a dedicated MIPI CSI-to-parallel converter IC like the STMIPID02? Can you recommend any other chips that act as such a bridge, and are confirmed to work with the RT1170? Best, Michael Re: RT1170: Using MIPI-CSI with grayscale or raw image sensors Hello michael_parthei,    Thanks for your new question post.    Today, I help you to confirm it internally again.   RT1170 due to the video mux bug, the MIPI-CSI2 can't support the raw data, and no workaround now.   If customer want to use the raw data method, they can use the parallel CSI interface instead of the mipi-csi.   Until now, RT1170 still doesn't have the fixed plan for it, maybe in the next RT version, it will be fixed.   BTW, do you meet these issues when you design your company's product?   If yes, I suggest you use your company and product information to create the account and create a nxp internal case, then I will help you to report it internally, now, in this post, you just use the 3rd part email. Case create process: 1. Open below SUPPORT site, click blue "Go to Tickets" in the middle. http://www.nxp.com/support/support:SUPPORTHOME 2.Then you will be requested to Login, if you have no an account, please first Register with your business email. 3.After login, please "Create New Cases" button in the middle, then you can submit your question. Please note, use the company email! Best Regards, Kerry Re: RT1170: Using MIPI-CSI with grayscale or raw image sensors Michael, I am also interested in this NXP MCU RT1170, and I hope there will a solution so I can use AR1335 with it. Any hope guys?

Software reset error when adapting TJA1120 driver to linux 5.15, error code -110 I'm having problems with software reset when adapting TJA1120 driver (from Linux 6.6) to Linux 5.15 with error code -110, I'm not sure about the cause as well as I don't know how to fix this problem. I refer to this post NXP_C45_TJA11XX Driver Soft Reset Issue, made changes to nxp_c45_soft_reset, but it has no effect, the code is as follows. static int nxp_c45_soft_reset(struct phy_device *phydev) { int ret; ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, DEVICE_CONTROL_RESET); if (ret) return ret; usleep_range(2000, 2050); return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, ret, !(ret & DEVICE_CONTROL_RESET), 20000, 240000, true); }: Error. [ 6.188117] sunxi-mdio 4500048.mdio0. sunxi_mdio_probe() BEGIN [ 6.265731] sunxi-mdio 4500048.mdio0. phy id: 0x001bb031, adr: 0x1b, device: 4500048.mdio0-mii:1b, DRIVER: NXP C45 TJA1120 [ 6.278218] sunxi-mdio 4500048.mdio0. sunxi_mdio_probe() SUCCESS [ 47.166283] NXP C45 TJA1120 4500048.mdio0-mii:1b:. nxp_c45_soft_reset failed: -110 Re: TJA1120驱动适配linux5.15时出现软件复位错误，错误码-110 Hello, As far as I know, tja1120 is not supported on 5.15. So did you backport the driver from the latest bsp? Is it working? Thanks! Best Regards. Re: TJA1120驱动适配linux5.15时出现软件复位错误，错误码-110 Hello @miipo , I can help only from device point of view. Can you distinguish if the error code has been generated by phy_write_mmd or by phy_read_mmd_poll_timeout ? Have you tried to increase time in usleep_range ? Best regards, Pavel

SPD eMcem Init I am using S32K344 to run SPD demo V1.0.4. I found that the first calling eMcem_Init fuction always fail, what's the problem? It seems that Could not acquire exclusiveaccess to FCCU. Re: SPD eMcem Init I'm using lauterbach and I'm also having the problem with how to modify the T32 script @RadoslavB  Re: SPD eMcem Init This RCCU error is most likely caused by the debugger. AFAIK the debugger disables the RCCU functionality after attaching to the core, causing those FCCU errors. For Lauterbach I have tested working workaround to force functional reset and then attach to the core using Trace32 commands. For PE Micro I can't test, but here is advice I have received: Customer need to download firmware first. Then press reset button.  Then reconnect PE debugger with attach option: uncheck "Load Executable", and check "Attach to Running Target" in the debug configuration "Startup" tab. Please let me know if that solution works for you. Kind Regards, Radoslav Re: SPD eMcem Init OK, so it's Lockstep error, for specific root cause please share also DCMROD3, DCMROD4 and DCMROD8 register values. Are you using Lauterbach or another debugger? Is it happening only after POR or external reset or even after SW functional reset? Kind Regards, Radoslav Re: SPD eMcem Init before and after: Re: SPD eMcem Init Hello @WeiC, the diagnostic info implies that there is some FCCU fault pending before eMcem init and it's not possible to clear the fault. Therefore, it's some permanent fault where we need to find the root cause (might be wrong HW setup, lockstep error etc.). Please could you share screenshot with FCCU status registers - NCF_S[]. Also please try to investigate when the fault occurred, if it's right in the beginning of startup after reset, or after some memory init in the startup, after some RTD init function etc. Kind Regards, Radoslav

是 S32K3 TCPIP RTM 1.0.1HF1基于 S32K3 RTD RTM2.0.0 或基于 S32K3 RTD RTM2.0.1 我使用 S32K3_T_BOX_LWIP_for_S32K3.zip 测试了 S32K3-T-BOX。我安装了 S32K3 RTD RTM2.0.0 和 FreeRTOS2.0.0，但无法安装 TCPIP RTM 1.0.1HF1（它无法安装 TCPIP RTM 1.0.1HF1）。提示我安装 S32K3 RTD RTM2.0.1）。 不过，恩智浦 WEB 支持的代码依赖于 S32K3 RTD RTM2.0.0。 我在 nxp 网站上找不到不带 HF1 的 TCPIP RTM 1.0.1，只有 TCPIP RTM 1.0.1HF1。 能否提供基于 S32K3 RTD RTM2.0.1 或不带 HF1 的 TCPIP RTM 1.0.1 的代码？ Re: Is S32K3 TCPIP RTM 1.0.1HF1 based on S32K3 RTD RTM2.0.0 or based on S32K3 RTD RTM2.0.1 你好，@xMaryAES、 请通过 支持票单 输入 支持 案例。 Re: Is S32K3 TCPIP RTM 1.0.1HF1 based on S32K3 RTD RTM2.0.0 or based on S32K3 RTD RTM2.0.1 你好@Julián_AragónM、 能否与我分享不含 HF1 的 TCP/IP RTM 1.0.1 版，或告诉我在哪里可以找到？ S32K3-T-BOX 谢谢！此致问候 Re: Is S32K3 TCPIP RTM 1.0.1HF1 based on S32K3 RTD RTM2.0.0 or based on S32K3 RTD RTM2.0.1 你好@Julián_AragónM、 能否与我分享与 S32K3 RTD RTM2.0.0 兼容的不含 HF1 的 TCP/IP RTM 1.0.1？ 此致， T1AES Re: Is S32K3 TCPIP RTM 1.0.1HF1 based on S32K3 RTD RTM2.0.0 or based on S32K3 RTD RTM2.0.1 能否将不含 hf1 的 S32K3 TCPIP RTM 1.0.1 发送给我？谢谢。 Re: Is S32K3 TCPIP RTM 1.0.1HF1 based on S32K3 RTD RTM2.0.0 or based on S32K3 RTD RTM2.0.1 嗨，@SCoder41、 我不确定 Flexera 中的可见性，但我已向您发送了一条私人信息，其中包含 TCP/IP RTM 1.0.1（不含 HF1）的 UpdateSite。 致以最诚挚的问候， Julián

一个 arduino 中的 2 个 mpr121 传感器 -> 串行通信 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 我正在尝试连接 2 个（0x5A、0x5B）地址。 在代码和数据表中，只需将 addr 引脚连接到（默认为 3.3v）就可以进行通信。 Arduino 可以识别其他传感器，但无法同时读取两个触摸传感器。只是告诉我 i=0 ~ 11 如何让 i=12~23 运行？ 如何在代码中区分两个传感器？ mpr121 传感器与 mpr121 传感器之间可以通信吗？ 我非常想知道如何在一个 arduino 中连接两个传感器。 我还尝试用 i2c 扫描仪检查线路 奇怪的是，串行监测只告诉我一个传感器。 这是我的代码 我是否应该在第一处添加一些定义以示区别？ 或 转换环 为{ } 请尽快告诉我 X( ------------------------------------------------------------------------------------------------------------------------------------ #include"SoftwareSerial.h" //#define defaultPatch 15 //악기 초기화 버튼 설정 악기호 SoftwareSerial mySerial(2, 3); //SW시리얼핀 정의 D3이 MIDI신호 전송용, D2는 미사용 字节音符 = 0; //MIDI 音符 () 字节 resetMIDI = 4;//VS1053 重置字节 LED 引脚 = 13; //MIDI 音符 LED LED LED #include #include"Adafruit_MPR121.h" #ifndef _BV #define _BV(bit) (1<< (bit)) #endif Adafruit_MPR121 cap = Adafruit_MPR121(); #define MPR121addr 0x5A #define MPR121addr 0x5B uint16_t lasttouched = 0; uint16_t currtouched = 0； #include int btn[]={60, 62, 64, 65, 67,69, 71, 72, 74, 76, 77, 79, 81, 83, 84, 86, 88, 89, 91, 93, 95, 96, 98, 100}； 字节字节数据； void setup() { Serial.begin(9600)； mySerial.begin(9600)； /* while (!Serial) { // 需要防止 leonardo/micro 启动过快！ delay(10); } */ Serial.println("Adafruit MPR121 电容式触摸传感器测试"); // 默认地址为 0x5A，如果绑在 3.3V 上，则为 0x5B // 如果绑在 SDA 上，则为 0x5C，如果绑在 SCL 上，则为 0x5D if (!cap.begin(0x5A)) { Serial.println("MPR121-A未找到，请检查接线？"); while (1); } Serial.println("MPR121-Afound!"); // if (!cap.begin(0x5B)){ Serial.println("MPR121-B未找到，请检查接线？"); while (1); } Serial.println("MPR121-B")； //重置 VS1053 pinMode（重置 MIDI，输出）； digitalWrite（重置 MIDI，LOW）； 延迟（100）；dig italWrite（重置 MIDI，HIGH）；延 迟（100）； } void loop () {currtouched = cap.touched ()； for (uint8_t i=0; i<12; i++) { // it if *is* touched and *wasnt* touched before, alert! if ((currtouched& _BV(i))&& !(lasttouched& _BV(i)) ){ Serial.print(i)；Serial.println("touched"); // tone(0, btn[i],100); noteOn(0, btn[i],100); //tone(buzzerPin, frequency[i], 330); } } for (uint8_t i=12; i<24; i++) { // 如果*被*触及且*之前未*触及，则发出警报！ if ((currtouched& _BV(i))&& !(lasttouched& _BV(i)) ){ Serial.print(i); Serial.println(" touched")； // tone(0, btn[i],100)； noteOn(0, btn[i],100)； //tone(buzzerPin, frequency[i], 330)； } } //*************** MIDI LOOPBACK ******************// if(Serial.available()> 0) { byteData = Serial.read()； mySerial.write(byteData); } lasttouched = currtouched； 返回； } //发送 MIDI 音符开启信息。就像按下钢琴键一样 //通道范围从 0-15 void noteOn（字节通道、字节音符、字节攻击力度）{t alkMIDI ((0x90 | 通道)、音符、attack_velocity);} //发送 MIDI 音符关闭信息。比如释放钢琴键 void noteOff（字节通道、字节音符、字节释放_速度）{t alkMIDI ((0x80 | 通道)、音符、release_velocity);} //播放一个 MIDI 音符。不检查 cmd 是否大于 127，或者数据值是否小于 127 void talkMIDI（字节 cmd，字节数据 1，字节数据 2）{d igitalWrite（ledPin，HIGH）；mySerial.Write (cmd) ); mySerial.write(data1); //有些命令只有一个数据字节。所有小于 0xBN 的命令都有 2 个数据字节 //（有点像：http://253.ccarh.org/handout/midiprotocol/） if( (cmd& 0xF0)<= 0xB0) mySerial.write(data2)); digitalWrite(ledPin, LOW); } 触摸传感器 Re: 2 mpr121 sensors in one arduino -> serial communication 我只有一个 MPR121，所以无法尝试代码，但我认为应该像下面这样更改： for (uint8_t i=0; i<12; i++) { // it if *is* touched and *wasnt* touched before, alert! if ((currtouched& _BV(i))&& !(lasttouched& _BV(i)) ){ Serial.print(i)；Serial.println("touched"); // tone(0, btn[i],100); noteOn(0, btn[i],100); //tone(buzzerPin, frequency[i], 330); } } for (uint8_t i=0; i<12; i++) { // it if *is* touched and *wasnt* touched before, alert! if ((currtouched2 & _BV(i))&& !(lasttouched2& _BV(i)) ){ //when sensor is touched do something Serial.print(i+12)；Serial.println("touched"); noteOn(0, btn[i],100); } } MPR121 有 12 个输入端，"_BV(bit) "位参数应始终介于 0-12 之间，然后使用currtouched2选择不同的 ADDR。 Lib's line-230:https://github.com/adafruit/Adafruit_MPR121/blob/master/Adafruit_MPR121.cpp Re: 2 mpr121 sensors in one arduino -> serial communication 我已经将两个 MPR121 板连接到我的 Arduino Uno，地址为 0x5C 和 0x5A。板可以正确识别。但是，我想了解如何将两块板设置为自动配置模式，以及如何调整两块板上每个传感器的触摸和版本阈值。目前我使用.CPP 文件进行这些设置，但它似乎只能在 0x5a 地址板上使用。谢谢！ Re: 2 mpr121 sensors in one arduino -> serial communication <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 嗨，金、 很高兴听到你设法将所有四个 MPR121 传感器连接在同一 I2C 总线上。 我不太清楚您当前的问题，但我想您可以根据当前与之通信的传感器地址，在 sw 中轻松完成。 顺祝商祺！ 托马斯 Re: 2 mpr121 sensors in one arduino -> serial communication <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 瓦切尔卡先生 非常感谢 联系的可能性让我松了一口气。 感谢您的热情回复，我成功连接了所有 4 个 mpr121 传感器！.....！ 我面临的最后一个问题是，"将触摸按钮的数量扩展到 24 个。" 每个触摸传感器都会给出 0 到 11 的数值。 我怎样才能做到 0-11、12-23、24-35、36-47？ ----------------------------------------------------------------------------------------------------------------------------------------------------- #include"SoftwareSerial.h" //#define defaultPatch 15 //악기 초기화 버튼 설 정 악기호 SoftwareSerial mySerial(2, 3); //SW시리얼핀 정의 D3이 MIDI신호 전송용, D2는 미사용 字节音符 = 0; //MIDI 音符 () 字节 resetMIDI = 4;//VS1053 重置字节 LED 引脚 = 13; //MIDI 音符 LED LED LED #include #include"Adafruit_MPR121.h" #ifndef _BV #define _BV(bit) (1<< (bit)) #endif //一条 i2c 总线上最多可以有 4 个，但一根足够测试！ adafruit_mpr121 上限 = adafruit_mpr121 ()；adafruit_mpr121 cap2 = adafruit_mpr121 ()；adafruit_mpr121 cap3 = adafruit_mpr121 ()； adafruit_mpr121 cap4 = Adafruit_mpr121 ()； //记录上次触摸的引脚/ /这样我们就知道按钮何时 “版本” uint16_t lasttouched = 0; uint16_t currtouched = 0; uint16_t currtouched = 0; uint16_t lasttouched2 = 0; uint16_t currtouched2 = 0； uint16_t lasttouched3 = 0; uint16_t currtouched3 = 0； uint16_t lasttouched4 = 0; uint16_t currtouched4 = 0； int btn[]={21, 23, 24, 26, 28, 29, 31, 33, 35, 36, 38, 40, 41, 43, 45, 47, 48, 50, 52, 53, 55, 57, 59, 60, 62, 64, 65, 67,69, 71, 72, 74, 76, 77, 79, 81, 83, 84, 86, 88, 89, 91, 93, 95, 96, 98, 100, 101}； 字节字节数据； void setup() { Serial.begin(9600)； mySerial.begin(9600)； while (!Serial) { // 需要防止 leonardo/micro 启动过快！ delay(10); } Serial.println("Adafruit MPR121 电容式触摸传感器测试"); // 默认地址为 0x5A，如果绑在 3.3V 上，则为 0x5B // 如果绑在 SDA 上，则为 0x5C，如果绑在 SCL 上，则为 0x5D if (!cap.begin(0x5A)) { Serial.println("MPR121-A未找到，请检查接线？"); while (1); } Serial.println("MPR121-Afound!"); // 如果 (!cap2.begin(0x5B)){ Serial.println("MPR121-B未找到，请检查接线？"); while (1); } Serial.println("MPR121-Bfound!"); // 如果 (!cap3.begin(0x5C)){ Serial.println("MPR121-C未找到，请检查接线？"); while (1); } Serial.println("MPR121-Cfound!"); // 如果 (!cap4.begin(0x5D)){ Serial.println("MPR121-D未找到，请检查接线？"); while (1); } Serial.println("MPR121-D找到了！"); //RESET VS1053 pinMode（RESET MIDI，输出）； digitalWrite（resetMIDI，LOW）； 延迟（100）； digitalWrite（resetMIDI，HIGH）； 延迟（100）； //这是循环内部所以你可以热插板 //如果你不需要热插件你可以把它放到设置中 () cap.begin (0x5A)；cap2.begin (0x5B) ； cap3.begin（0x5C）； cap4.begin（0x5D）； } void loop() { // 获取当前触摸的焊盘 currtouched = cap.touched()； currtouched2 = cap2.touched()； currtouched3 = cap3.touched()； currtouched4 = cap4.touched()； f@@ or (uint8_t i=0; i < 48; i++) { //如果 *被*触摸过而且 *以前没有*触摸过，警报！ i f ((currtouched & _BV (i)) & &!(las t touched & _BV (i))) {Serial.Print (i)；Serial.println (" touched "); //音调 (0，btn [i] ,100)；/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////i f ((currtouched2 & _BV (i)) & &!(lasttouched2 & _BV (i))) {//当触摸传感器时做点什么 Serial.print (i)；Serial.println (" touched ")；n oteOn (0，btn [i] ,100)；}/////////////////////////////////////////////////////////////////////////////////////////////////////////////V (i)) && &!（lasttouched3 & _BV (i))) {//当触摸传感器时做点什么 Serial.print (i)；Serial.println (" touched ")；n oteOn (0，btn [i] ,100);}//////////////////////////////////////////////////////////////////////////////////////////////////////////////(i)) && &!(lasttouched4 & _BV (i))) { //当触摸传感器时做点什么 Serial.print (i); Serial.println (" 触摸 "); n oteOn (0, btn [i] ,100); } } //RESET我们上次触摸的状态 = currtouched2; lasttouched3 = currtouched3; lasttouched4 = currtouched4; retur n; //***************** MIDI LOOPBACK ********************/// if (Serial.Available > 0) { byteData = Serial.read()； mySerial.write(byteData); } } //发送 MIDI 音符开启信息。就像按下钢琴键一样 //通道范围从 0-15 void noteOn（字节通道、字节音符、字节攻击力度）{t alkMIDI ((0x90 | 通道)、音符、attack_velocity);} //发送 MIDI 音符关闭信息。比如释放钢琴键 void noteOff（字节通道、字节音符、字节释放_速度）{t alkMIDI ((0x80 | 通道)、音符、release_velocity);} //播放一个 MIDI 音符。不检查 cmd 是否大于 127，或者数据值是否小于 127 void talkMIDI（字节 cmd，字节数据 1，字节数据 2）{d igitalWrite（ledPin，HIGH）；mySerial.Write (cmd) ); mySerial.write(data1); //有些命令只有一个数据字节。所有小于 0xBN 的命令都有 2 个数据字节 //（有点像：http://253.ccarh.org/handout/midiprotocol/） if( (cmd& 0xF0)<= 0xB0) mySerial.write(data2)); digitalWrite(ledPin, LOW); }   Re: 2 mpr121 sensors in one arduino -> serial communication <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 嗨，金、 是的，可以与同一 I2C 总线上的两个 MPR121 传感器通信，以便将触摸按钮的数量扩展到 24 个。 实际上，根据 ADDR 引脚的连接情况，您可以为 MPR121 分配四个 I2C 地址：   例如，当 ADDR=VDD（写入时转换为 0xB4，读取时转换为 0xB5）时，一个 MPR121 从属服务器的 7 位 I2C 地址为 0x5A，当一个 ADDR=GND 时，另一个从 I2C 地址为 0x5B（写入转换为 0xB6，读取时转换为 0xB7）。 希望对你有所帮助！ 顺祝商祺！ 托马斯

NTAG424 DNA で CMAC、UID、COUNTER、RAND を有効にするにはどうすればいいですか? 最新の Android SDKs ライブラリを使用して、AES キーに基づいて動的 URL を設定しようとしていますが、できません。 nxpnfcandroidlib-release-protected.aar これは私のコードです override fun onNewIntent(intent: Intent) { Log.i("NFC", "Intent action: ${intent.action}") super.onNewIntent(intent) Log.i("MainActivity", "NFC tag discovered") val cardType = libInstance.getCardType(intent) Log.i("MainActivity", "Detected card type: $cardType") if (cardType == CardType.NTAG424DNA) { val ntag424DNA: INTAG424DNA = DESFireFactory.getInstance().getNTAG424DNA(libInstance.customModules) val reader: IReader = ntag424DNA.reader try { if (!reader.isConnected) { reader.connect() } ntag424DNA.isoSelectApplicationByDFName(NTAG424DNA_APP_NAME) Log.i("NFC", "ISO selected app by DF Name ✅") authenticateTag(ntag424DNA, KEY_AES128_DEFAULT) creatingNDEFmessage(ntag424DNA) authenticateTag(ntag424DNA, KEY_AES128_DEFAULT) changeFileSettings(ntag424DNA, 0x01) authenticateTag(ntag424DNA, KEY_AES128_DEFAULT) ntag424DNA.setPICCConfiguration(true) Log.i("MainActivity", "✅ PICC Configuration updated to enable SDM globally.") authenticateTag(ntag424DNA, KEY_AES128_DEFAULT) changeSDMFileSettings(ntag424DNA, 0x01) if (reader.isConnected) { reader.close() } } catch (e: Exception) { e.printStackTrace() } } } private fun creatingNDEFmessage(ntag424DNA: INTAG424DNA) { // 1. Creating URI NDEF message val msg = NdefMessageWrapper( NdefRecordWrapper( NdefRecordWrapper.TNF_ABSOLUTE_URI, "https://domain.com?uid=04BB38D2AA1191&ctr=0001&cmac=3ab665b76b795cb9bf76a17956cc9fb3&rand=422def08-8a1c-49c9-9138-434cde858faa".toByteArray( Charset.forName("US-ASCII") ), ByteArray(0), ByteArray(0) ) ) ntag424DNA.writeNDEF(msg); Log.i("MainActivity", "URI NDEF message written successful ✅") val ndefRead = ntag424DNA.readNDEF() Log.i("MainActivity", "Read URI NDEF message ${CustomModules.getUtility().dumpBytes(ndefRead.toByteArray())}") } private fun changeFileSettings(ntag424DNA: INTAG424DNA, fileNumber: Int) { // 3. Create NTAG 424 DNA file settings for E104 val fileSettings = NTAG424DNAFileSettings( MFPCard.CommunicationMode.Encrypted, // = 0x03 = Full ENC + CMAC (SUN) 0x0E.toByte(), // Read access = key slot 0x00 maybe 0x01 0x0E.toByte(), // Write access = always 0x0E.toByte(), // RW access = always 0x0E.toByte() // Change access = always ) Log.i("MainActivity", "Prepare for saving changes in file $fileNumber") ntag424DNA.changeFileSettings(fileNumber, fileSettings) Log.i("NFC", "🔐 File settings updated $fileNumber") } private fun changeSDMFileSettings(ntag424DNA: INTAG424DNA, fileNumber: Int) { val fileSettings = ntag424DNA.getFileSettings(fileNumber); fileSettings.isSDMEnabled = true; fileSettings.isUIDMirroringEnabled = true; fileSettings.piccDataOffset = intTo2ByteArray(51) fileSettings.sdmMacOffset = intTo2ByteArray(51) fileSettings.sdmMacInputOffset = intTo2ByteArray(51) fileSettings.sdmReadCounterOffset = intTo2ByteArray(51) fileSettings.uidOffset = intTo2ByteArray(51) fileSettings.sdmAccessRights = byteArrayOf(0x00, 0x00) Log.i("MainActivity", "Prepare for saving SDM changes in file $fileNumber") ntag424DNA.changeFileSettings(fileNumber, fileSettings) Log.i("NFC", "🔐 File settings updated: SUN CMAC enabled on $fileNumber") } private fun intTo2ByteArray(value: Int): ByteArray { return byteArrayOf( ((value shr 😎 and 0xFF).toByte(), (value and 0xFF).toByte() ) } オフセット番号が URL 内のポジショニングと一致しないことはわかっていますが、何を変更してもこのエラーが発生します。何らかの理由で、この方法ではこれらの設定を保存できないようです。 ntag424DNA.changeFileSettings(fileNumber, fileSettings) これはエラーメッセージです com.nxp.nfclib.exceptions.UsageException: Invalid Parameters! {Invalid Value for PICC Offset} コード・サンプル Re: How can i enable CMAC, UID, COUNTER and RAND in NTAG424 DNA? この問題はオフセット値が間違っているために発生しました。ntag は 21 のデフォルト インデックスを予約しているようです。今、ファクトリー128 AESキーを変更しようとしていますが、changekey()関数は機能しませんでした。 @ukcas Re: How can i enable CMAC, UID, COUNTER and RAND in NTAG424 DNA? ちょっと、そこ、 このThreadに従って JSON データを設定していますが、うまくいきません。ハードウェアを扱うのは初めてなので、非常に困難になっています。私は、NXP Android ライブラリと、ここからのサンプル Android アプリケーションを使用しています: https://www.nxp.com/design/design-center/software/rfid-developer-resources/taplinx-software-development-kit-sdk:TAPLINX 以下はSample_Application_Android/src/main/java/com/nxp/sampletaplinx/WriteActivity.java内のコードです。 public static byte[] intTo2ByteArray(int value) { return new byte[] { (byte) (value & 0xFF), // LSB (byte) ((value >> 8) & 0xFF), // middle byte (byte) ((value >> 16) & 0xFF) // MSB }; } private void tag424DNACardLogic(INTAG424DNA ntag424DNA) { byte[] KEY_AES128_DEFAULT = new byte[] { (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, }; byte[] NTAG424DNA_APP_NAME = {(byte) 0xD2, (byte) 0x76, 0x00, 0x00, (byte) 0x85, 0x01, 0x01}; byte[] data ={ 0x73, 0x75, 0x73, 0x68, 0x69, 0x6C }; mStringBuilder.append("\n\n"); int timeOut = 2000; try { ntag424DNA.isoSelectApplicationByDFName(NTAG424DNA_APP_NAME); KeyData aesKeyData = new KeyData(); Key keyDefault = new SecretKeySpec(KEY_AES128_DEFAULT, "AES"); aesKeyData.setKey(keyDefault); ntag424DNA.authenticateEV2First(0, aesKeyData, null); mStringBuilder.append(getString(R.string.Authentication_status_true)); mStringBuilder.append("\n\n"); ntag424DNA.setPICCConfiguration(true); String jsonTemplate = "{\"uuid\":\"00000000000000\",\"counter\":\"000000\",\"cmac\":\"0000000000000000\",\"domain1\":" + 1 + ",\"domain2\":" + 1 + "}"; byte[] jsonBytes = jsonTemplate.getBytes("UTF-8"); NTAG424DNAFileSettings fs = new NTAG424DNAFileSettings( CommunicationMode.Plain, // or MAC/ENC depending on your security (byte) 0x0E, // Read access: Key 0 (byte) 0x0E, // Write access: Key 0 (byte) 0x0E, // Read/Write: Key 0 (byte) 0x00 // Change access: Free ); byte[] type = "U".getBytes("US-ASCII"); fs.setSDMEnabled(true); fs.setUIDMirroringEnabled(true); fs.setSDMReadCounterEnabled(true); byte[] bytes = new byte[] { (byte)0xE0, (byte)0x00, (byte)0x00 }; fs.setSdmAccessRights(bytes); byte[] uuidOffset = intTo2ByteArray(8); fs.setUidOffset(uuidOffset); byte[] readCounterOffset = intTo2ByteArray(35); fs.setSdmReadCounterOffset(readCounterOffset); byte[] macOffset = intTo2ByteArray(51); fs.setSdmMacInputOffset(uuidOffset); fs.setSdmMacOffset(macOffset); ntag424DNA.changeFileSettings(FILE_NUMBER, fs); // Create NDEF record NdefRecordWrapper record = new NdefRecordWrapper( NdefRecordWrapper.TNF_WELL_KNOWN, type, new byte[0], // empty ID jsonBytes // payload (your JSON) ); // Wrap record into NDEF message NdefMessageWrapper msg = new NdefMessageWrapper(record); ntag424DNA.writeNDEF(msg); NxpLogUtils.save(); } catch (Exception e) { writeFailedMessage(); mStringBuilder.append(e.getMessage()); Log.i("MainActivity", "URI NDEF message written successful $msg " + e.getMessage() ); showMessage(mStringBuilder.toString(), PRINT); NxpLogUtils.save(); } } 誰かがこれを手伝ってCANととても助かります Re: How can i enable CMAC, UID, COUNTER and RAND in NTAG424 DNA? 助けてくれてありがとう！私のオフセットの値が間違っているというのはその通りです。変更した内容はこれで、設定を保存CANようになりました。 override fun onNewIntent(intent: Intent) { Log.i("NFC", "Intent action: ${intent.action}") super.onNewIntent(intent) Log.i("MainActivity", "NFC tag discovered") val cardType = libInstance.getCardType(intent) Log.i("MainActivity", "Detected card type: $cardType") if (cardType == CardType.NTAG424DNA) { val ntag424DNA: INTAG424DNA = DESFireFactory.getInstance().getNTAG424DNA(libInstance.customModules) val reader: IReader = ntag424DNA.reader try { if (!reader.isConnected) { reader.connect() } ntag424DNA.isoSelectApplicationByDFName(NTAG424DNA_APP_NAME) Log.i("NFC", "ISO selected app by DF Name ✅") authenticateTag(0x00, ntag424DNA, KEY_AES128_DEFAULT) creatingNDEFmessage(ntag424DNA) authenticateTag(0x00, ntag424DNA, KEY_AES128_DEFAULT) changeFileSettings(ntag424DNA, 0x02) if (reader.isConnected) { reader.close() } } catch (e: Exception) { Log.e("MainActivity", e.localizedMessage ?: "No Error Message"); e.printStackTrace() } } } private fun changeFileSettings(ntag424DNA: INTAG424DNA, fileNumber: Int) { // 3. Create NTAG 424 DNA file settings for E104 val fileSettings = NTAG424DNAFileSettings( MFPCard.CommunicationMode.Plain, // = 0x03 = Full ENC + CMAC (SUN) 0x0E.toByte(), // Read access = key slot 0x00 maybe 0x01 0x0E.toByte(), // Write access = always 0x0E.toByte(), // RW access = always 0x00.toByte() // Change access = always ) fileSettings.isSDMEnabled = true fileSettings.isUIDMirroringEnabled = true fileSettings.isSDMReadCounterEnabled = true fileSettings.sdmAccessRights = byteArrayOf(0xfe.toByte(), 0xe1.toByte()) fileSettings.uidOffset = byteArrayOf(0x1A, 0x00, 0x00) fileSettings.sdmReadCounterOffset = byteArrayOf(0x2d, 0x00, 0x00) fileSettings.sdmMacOffset = byteArrayOf(0x39, 0x00, 0x00) fileSettings.sdmMacInputOffset = byteArrayOf(0x39, 0x00, 0x00) Log.i("MainActivity", "Prepare for saving changes in file $fileNumber") ntag424DNA.changeFileSettings(fileNumber, fileSettings) Log.i("MainActivity", "🔐 File settings updated $fileNumber") } private fun creatingNDEFmessage(ntag424DNA: INTAG424DNA) { // 1. Creating URI NDEF message val payload = byteArrayOf(0x04) + "noexample.xxxx?uid=00000000000000&ctr=000000&cmac=0000000000000000".toByteArray() val msg = NdefMessageWrapper( NdefRecordWrapper( NdefRecordWrapper.TNF_WELL_KNOWN, "U".toByteArray(StandardCharsets.US_ASCII), ByteArray(0), payload ) ) ntag424DNA.writeNDEF(msg); Log.i("MainActivity", "URI NDEF message written successful ✅") val ndefRead = ntag424DNA.readNDEF() Log.i("MainActivity", "Read URI NDEF message ${CustomModules.getUtility().dumpBytes(ndefRead.toByteArray())}") } Re: How can i enable CMAC, UID, COUNTER and RAND in NTAG424 DNA? 親愛なるロッキー2様 jimmyvhan が参照しているドキュメントとデータシートを確認してください。 オフセットが重複していますが、これはデータシートでは許可されていません。 ご希望のURLを検討中です。NFCCounter のスペースが 3 バイトと少なすぎます。SO、以下の設定は修正された URL に適しています。 https://domain.com?uid=04BB38D2AA1191&ctr=000001&cmac=3ab665b76b795cb9bf76a17956cc9fb3&rand=422def08-8a1c-49c9-9138-434cde858faa SDM 構成にはこれらのパラメータを使用する必要があります。CMAC 計算のための入力データも決定します。この例では、UIDOffset を出発点として使用しました。 fileSettings.sdmMacOffset = intTo2ByteArray(53) fileSettings.sdmMacInputOffset = intTo2ByteArray(22) fileSettings.sdmReadCounterOffset = intTo2ByteArray(41) fileSettings.uidOffset = intTo2ByteArray(22) よろしくお願いします、 TapLinxチーム Re: How can i enable CMAC, UID, COUNTER and RAND in NTAG424 DNA? この文書はあなたにとって役に立つかもしれません。 NTAG 424 DNAとNTAG 424 DNA TagTamperの機能とヒント

PFE on S32G A53 QNX ERROR     Hi,NXP experts We have a custom board that we want to run QNX and PFE drivers on. But we have encountered the following problem and would like to ask PFE experts to help analyze it.     software information: PFE QNX driver version: 1.8.0 PFE FW version: 1.11.0 QNX SDP version: 7.1.0 BSP version of QNX S32G399A: BSP_nxp-s32g-rdb3_br-710_be-710_SVN996606_JBN10   hardware information: The difference in hardware between us and the NXP S32G399ARDB3 EVN board is that DDR has been changed to 2GB, and we have already adapted it in Linux, and the pfe Ethernet driver is normal. The changes are as follows:           1. Changes in images/s32g399a-rdb.build file，   2. Changes in src\hardware\startup\boards\s32g\s32g399a-rdb\s32g_init_raminfo.c file：     3. Other insignificant changes, unrelated to the PFE driver.       My test commands are： # slog2info -c   # slog2info -w & # io-pkt-v6-hc -p tcpip pkt_typed_mem=pfe_ddr -d /proc/boot/devnp-pfe-2.so class_fw=/proc/boot/s32g_pfe_class.fw,util_fw=/proc/boot/s32g_pfe_util.fw   However, after running, the error message appears.Log is here. -------------------Appendix------------------     NOTICE:  The list of clocks found enabled during the SCMI agent reset command: NOTICE:         linflex_lin NOTICE:         usdhc_core board_smp_num_cpu: 8 cores MMU: 16-bit ASID 40-bit PA TCR_EL1=b5183519 ARM GIC-500 r1p1, arch v3.0 detected board_smp_num_cpu: 8 cores board_smp_num_cpu: 8 cores No SPI intrinfo. Add default entry for 32 -> 575 vectors, Ok cpu0: MPIDR=80000000 cpu0: MIDR=410fd034 Cortex-A53 r0p4 cpu0: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu0: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu0: L1 Icache 32K linesz=64 set/way=256/2 cpu0: L1 Dcache 32K linesz=64 set/way=128/4 cpu0: L2 Unified 1024K linesz=64 set/way=1024/16 board_smp_num_cpu: 8 cores   A53 CORE CLOCK : 1000MHz DDR CLOCK      : 800MHz SERDES CLOCK   : 2000MHz LINFLEXD CLOCK : 125MHz GMAC TS CLOCK  : 48MHz SPI CLOCK      : 48MHz QSPI CLOCK     : 800MHz SDHC CLOCK     : 800MHz   Loading IFS...decompressing...done board_smp_start: cpu_cluster_id: 0, cpu_id: 1 NOTICE:  S32 TF-A: s32_pwr_domain_on: booting up core 1 (0)  running cpu1: MPIDR=80000001 cpu1: MIDR=410fd034 Cortex-A53 r0p4 cpu1: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu1: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu1: L1 Icache 32K linesz=64 set/way=256/2 cpu1: L1 Dcache 32K linesz=64 set/way=128/4 cpu1: L2 Unified 1024K linesz=64 set/way=1024/16 board_smp_start: cpu_cluster_id: 0, cpu_id: 2 NOTTCE:  S32 T TA: s323pw_pdomrin_on: bootingnup cor  2u 0) nning cpu2: MPIDR=80000002 cpu2: MIDR=410fd034 Cortex-A53 r0p4 cpu2: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu2: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu2: L1 Icache 32K linesz=64 set/way=256/2 cpu2: L1 Dcache 32K linesz=64 set/way=128/4 cpu2: L2 Unified 1024K linesz=64 set/way=1024/16 board_smp_start: cpu_cluster_id: 0, cpu_id: 3 ngTICE:  SS32TT-A:: 32_pwr_rodain_on: booting up cpre 3 (0n cpu3: MPIDR=80000003 cpu3: MIDR=410fd034 Cortex-A53 r0p4 cpu3: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu3: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu3: L1 Icache 32K linesz=64 set/way=256/2 cpu3: L1 Dcache 32K linesz=64 set/way=128/4 cpu3: L2 Unified 1024K linesz=64 set/way=1024/16 board_smp_start: cpu_cluster_id: 1, cpu_id: 0 NOTICE:  S32 TF-A: s32_pwr_domain_on: booting up core 4 (0) NOTICE:  S32 TF-A: s32_pwr_domain_on_finish: cpu 4 running cpu4: MPIDR=80000100 cpu4: MIDR=410fd034 Cortex-A53 r0p4 cpu4: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu4: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu4: L1 Icache 32K linesz=64 set/way=256/2 cpu4: L1 Dcache 32K linesz=64 set/way=128/4 cpu4: L2 Unified 1024K linesz=64 set/way=1024/16 board_smp_start: cpu_cluster_id: 1, cpu_id: 1 NOTICE:  S32 TF-A: s32_pwr_domain_on: booting up core 5 (0) cpu 5 running cpu5: MPIDR=80000101 cpu5: MIDR=410fd034 Cortex-A53 r0p4 cpu5: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu5: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu5: L1 Icache 32K linesz=64 set/way=256/2 cpu5: L1 Dcache 32K linesz=64 set/way=128/4 cpu5: L2 Unified 1024K linesz=64 set/way=1024/16 board_smp_start: cpu_cluster_id: 1, cpu_id: 2 NOTICE:  S32 TF-A: s32_pwr_domain_on: booting up core 6 (0) nning cpu6: MPIDR=80000102 cpu6: MIDR=410fd034 Cortex-A53 r0p4 cpu6: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu6: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu6: L1 Icache 32K linesz=64 set/way=256/2 cpu6: L1 Dcache 32K linesz=64 set/way=128/4 cpu6: L2 Unified 1024K linesz=64 set/way=1024/16 board_smp_start: cpu_cluster_id: 1, cpu_id: 3 NOTICE:  S32 TF-A: s32_pwr_domain_on: booting up core 7 (0) 7 running cpu7: MPIDR=80000103 cpu7: MIDR=410fd034 Cortex-A53 r0p4 cpu7: CWG=4 ERG=4 Dminline=4 Iminline=4 VIPT cpu7: CLIDR=a200023 LoUU=1 LoC=2 LoUIS=1 cpu7: L1 Icache 32K linesz=64 set/way=256/2 cpu7: L1 Dcache 32K linesz=64 set/way=128/4 cpu7: L2 Unified 1024K linesz=64 set/way=1024/16   System page at phys:00000000a0010000 user:ffffff8040315000 kern:ffffff8040311000 Starting next program at vffffff8060097300 ClockCycles samples:  0 62957977  1 62957977  2 62957978  3 62957977  4 62957977  5 62957977  6 62957977  7 62957977 All ClockCycles offsets within tolerance Welcome to QNX Neutrino 7.1.0 on the NXP S32G399A RDB Board!! Starting watchdog... Starting serial driver ... Starting Networking driver (/dev/socket)... Starting SPI driver (/dev/spi0,1,2,3,4,5)... Starting I2C 0/1/2/3/4 driver (/dev/i2c0,1,2,3,4)... Starting USDHC0 memory card driver... Path=Starting CAN driver... 0 - imx  target=0 lun=0     Direct-Access(0) - SDMMC: AAM20E Rev: 1.0 # # # # slog2info -c   Process 4117 (slog2info) exited status=0. ghccu# slog2info -w & [1] 12309                                           random.4                  low     0  -----UNSYNC-----                                           random.4                 high     0  -----UNSYNC----- Jan 01 00:00:00.022                      console.3                           0  -----ONLINE-----                                          console.3                  out     0  -----UNSYNC----- Jan 01 00:00:00.027                       random.4                           0  -----ONLINE-----                                           random.4              default     0  -----UNSYNC----- Jan 01 00:00:00.028                    random.4..0                           0  -----ONLINE-----                                        random.4..0                 slog     0  -----UNSYNC----- Jan 01 00:00:00.050             devc_serlinflexd.7                           0  -----ONLINE-----                                 devc_serlinflexd.7                 slog     0  -----UNSYNC----- Jan 01 00:00:00.055                   spi_master.8                           0  -----ONLINE-----                                       spi_master.8               normal     0  -----UNSYNC----- Jan 01 00:00:00.059                   spi_master.9                           0  -----ONLINE-----                                       spi_master.9               normal     0  -----UNSYNC----- Jan 01 00:00:00.063                  spi_master.10                           0  -----ONLINE-----                                      spi_master.10               normal     0  -----UNSYNC----- Jan 01 00:00:00.067                  spi_master.11                           0  -----ONLINE-----                                      spi_master.11               normal     0  -----UNSYNC----- Jan 01 00:00:00.088             devb_sdmmc_mx8x.17                           0  -----ONLINE-----                                 devb_sdmmc_mx8x.17                 slog     0  -----UNSYNC----- Jan 01 00:00:04.268                       qconn.20                           0  -----ONLINE-----                                           qconn.20                 slog     0  -----UNSYNC----- # # # # io-pkt-v6-hc -p tcpip pkt_typed_mem=pfe_ddr -d /proc/boot/devnp-pfe-2.so class_fw=/proc/boot/s32g_pfe_class.fw,util_fw=/proc/boot/s32g_pfe_util.fw # Jan 01 00:00:14.060                    iopkt.16408                           0  -----ONLINE----- Jan 01 00:00:14.060                    iopkt.16408          main_buffer*     0  detect_armv8ce_hw: armv8ce is supported! Jan 01 00:00:14.061                    iopkt.16408          main_buffer      0  tcpip starting Jan 01 00:00:14.062                    iopkt.16408          main_buffer      0  smmu support is disabled Jan 01 00:00:14.063                    iopkt.16408          main_buffer      0  initializing IPsec... Jan 01 00:00:14.063                    iopkt.16408          main_buffer      0   done   Jan 01 00:00:14.064                    iopkt.16408          main_buffer      0  IPsec: Initialized Security Association Processing.   Jan 01 00:00:14.067                    iopkt.16408          main_buffer      0  /proc/boot/devnp-pfe-2.so class_fw=/proc/boot/s32g_pfe_class.fw,util_fw=/proc/boot/s32g_pfe_util.fw Jan 01 00:00:14.068             io_pkt_v6_hc.16408                           0  -----ONLINE----- Jan 01 00:00:14.068             io_pkt_v6_hc.16408                 slog*     0  INF[src/pfe_drv.c:1346]: VERSION INFO         Driver version: 1.8.0         Driver commit hash: 57b6eefdb35cbff7a43ecfbdca3334760b1d0553         PFE_CFG_MULTI_INSTANCE_SUPPORT: 0         PFE_CFG_LOCAL_IF: 6         PFE_CFG_MASTER_IF: 6         PFE_CFG_SC_HIF: 1         PFE_CFG_HIF_RING_LENGTH: 256         PFE_CFG_PFE0_PROMISC: 1         PFE_CFG_PFE1_PROMISC: 1         PFE_CFG_PFE2_PROMISC: 1     Jan 01 00:00:14.068             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_drv.c:1353]: --- Safe IRQ enabled. No InterrupAttach() or InterruptAttach_r() allowed.   Jan 01 00:00:14.068             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_fw.c:94]: 45724 bytes read   Jan 01 00:00:14.068             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_fw.c:100]: Loaded firmware file: /proc/boot/s32g_pfe_class.fw   Jan 01 00:00:14.068             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_fw.c:94]: 23352 bytes read   Jan 01 00:00:14.069             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_fw.c:100]: Loaded firmware file: /proc/boot/s32g_pfe_util.fw   Jan 01 00:00:14.069             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_drv.c:1449]: MII mode configuration for pfe0/EMAC0 not found. Using SGMII.   Jan 01 00:00:14.069             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_drv.c:1449]: MII mode configuration for pfe1/EMAC1 not found. Using SGMII.   Jan 01 00:00:14.069             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_drv.c:1449]: MII mode configuration for pfe2/EMAC2 not found. Using SGMII.   Jan 01 00:00:14.069             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_drv.c:1467]: Issuing PFE peripheral reset...   Jan 01 00:00:14.179             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_drv.c:1468]: PFE reset OK.   Jan 01 00:00:14.179             io_pkt_v6_hc.16408                 slog      0  INF[hw/s32g/pfe_platform_master.c:2826]: PFE CBUS p0x46000000 mapped @ v0x1e2a574000 (0x1000000 bytes)   Jan 01 00:00:14.179             io_pkt_v6_hc.16408                 slog      0  INF[hw/s32g/pfe_platform_master.c:2831]: HW version 0x101   Jan 01 00:00:14.179             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_hw_feature.c:95]: Silicon S32G3   Jan 01 00:00:14.179             io_pkt_v6_hc.16408                 slog      0  WRN[hw/s32g/pfe_platform_master.c:2843]: Fail-Stop mode disabled   Jan 01 00:00:14.254             io_pkt_v6_hc.16408                 slog      0  INF[hw/s32g/pfe_platform_master.c:2093]: PFE_ERRORS:Parity instance created   Jan 01 00:00:14.254             io_pkt_v6_hc.16408                 slog      0  INF[hw/s32g/pfe_platform_master.c:2108]: PFE_ERRORS:Watchdog instance created   Jan 01 00:00:14.254             io_pkt_v6_hc.16408                 slog      0  INF[hw/s32g/pfe_platform_master.c:2124]: PFE_ERRORS:Bus Error instance created   Jan 01 00:00:14.254             io_pkt_v6_hc.16408                 slog      0  INF[hw/s32g/pfe_platform_master.c:2137]: PFE_ERRORS:FW Fail Stop instance created   Jan 01 00:00:14.254             io_pkt_v6_hc.16408                 slog      0  INF[hw/s32g/pfe_platform_master.c:2150]: PFE_ERRORS:Host Fail Stop instance created   Jan 01 00:00:14.254             io_pkt_v6_hc.16408                 slog      0  INF[hw/s32g/pfe_platform_master.c:2163]: PFE_ERRORS:Fail Stop instance created   Jan 01 00:00:14.254             io_pkt_v6_hc.16408                 slog      0  INF[hw/s32g/pfe_platform_master.c:2176]: PFE_ERRORS:ECC Err instance created   Jan 01 00:00:14.254             io_pkt_v6_hc.16408                 slog      0  INF[hw/s32g/pfe_platform_master.c:1097]: BMU1 buffer base: p0xc0000000   Jan 01 00:00:14.255             io_pkt_v6_hc.16408                 slog      0  ERR[src/oal_mm_qnx.c:98]: (DRIVER) event 1 - Driver runtime error: mmap64() failed: 1   Jan 01 00:00:14.255             io_pkt_v6_hc.16408                 slog      0  ERR[src/oal_mm_qnx.c:171]: (DRIVER) event 1 - Driver runtime error: Can't get memory block   Jan 01 00:00:14.255             io_pkt_v6_hc.16408                 slog      0  ERR[hw/s32g/pfe_platform_master.c:1125]: (DRIVER) event 1 - Driver runtime error: Unable to get BMU2 pool memory   Jan 01 00:00:14.256             io_pkt_v6_hc.16408                 slog      0  ERR[src/pfe_drv.c:1529]: (DRIVER) event 1 - Driver runtime error: Unable to initialize the platform   Jan 01 00:00:14.257                    iopkt.16408          main_buffer      0  Unable to init /proc/boot/devnp-pfe-2.so: No such device   Jan 01 00:00:14.257             io_pkt_v6_hc.16408                 slog      0  INF[src/pfe_drv.c:1302]: PFE entry failed, PFE driver terminated     # # # # # #     Re: PFE on S32G A53 QNX ERROR Hello, @SandalWood  I feel very sorry for late response. Not sure if the issue has been resolved? May I know if there was a environment variable skip_scmi_reset_agent set in your uboot? If not, try setting the following: "setenv skip_scmi_reset_agent '1'" BR Chenyin   Re: PFE on S32G A53 QNX ERROR Hello, @SandalWood  Thanks for the reply. 1. I suggest reviewing the "PFE_QNX_DRV_IntegrationManual.pdf", which is included in PFE driver release package and assure that each step(Building, Running driver) is correct. 2. If the DTB file worked well in Linux, then the original one in QNX should be replaced with it. Would you mind trying it again and let me know the test result. BR Chenyin Re: PFE on S32G A53 QNX ERROR Hello, @SandalWood  Thanks for you reply. Yes, I understand the situation now. Will investigate it and reply you later when there are any findings. BR Chenyin Re: PFE on S32G A53 QNX ERROR 1.The location of the pfe DDR cannot use the example provided in the NXP manual and must be changed to an idle location to prevent overlap with the reserved memory. 2.I haven't made any dynamic changes.My run cmd is:io-pkt-v6-hc -p tcpip pkt_typed_mem=pfe_ddr -d /proc/boot/devnp-pfe-2.so pfe0_link=1000-1-3,pfe0_mac=025556000050,class_fw=/proc/boot/s32g_pfe_class.fw,util_fw=/proc/boot/s32g_pfe_util.fw And I did not make any dynamic changes, I did not modify the environment variables of uboot. Linux and QNX use the same uboot image. So, I understand that the configuration of Serdes on QNX should be the same as Linux, right?  Re: PFE on S32G A53 QNX ERROR Hello, @SandalWood  Glad that the ddr issue resolved, would you mind sharing the reasons? For the ping issue mentioned, have you mentioned the driver limitation below: BR Chenyin Re: PFE on S32G A53 QNX ERROR Hi, We have resolved the ddr error, but there may be an new issue during ping. The pfe0 in our board is directly connected to the external swtich through MAC-TO-MAC(SGMII MODE). In a Linux environment, this link is normal and can communicate with the external environment normally, such as ping being OK. But after replacing Linux with the current QNX, the ping problem will occur. In Linux, we changed the device tree and configured pfe0 to fix sgmii mode. I suspect it's related to this, but I don't know how to configure it in QNX。 The log please see the attach. Re: PFE on S32G A53 QNX ERROR 160 is hex 0xa0,it seems that pfe_ddr is ok # pidin sys=asinfo Header size=0x00000108, Total Size=0x00001050, #Cpu=8, Type=257 Section:asinfo offset:0x00000b90 size:0x00000200 elsize:0x00000020 0000) 0000000000000000-0000ffffffffffff o:ffff a:0010 p:100 c:0 n:/memory 0020) 0000000000000000-00000000ffffffff o:0000 a:0010 p:100 c:0 n:/memory/below4G 0040) 0000000080000000-00000000ffffffff o:0020 a:0017 p:100 c:0 n:/memory/below4G/ram 0060) 0000000880000000-00000008dfffffff o:0000 a:0017 p:100 c:0 n:/memory/ram 0080) 00000000ff800000-00000000ff83afff o:0040 a:0005 p:100 c:0 n:/memory/below4G/ram/atf 00a0) 0000000080000000-0000000083ffffff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/pfe_ddr 00c0) 0000000050800000-000000005080ffff o:0000 a:0003 p:100 c:0 n:/memory/gicd 00e0) 0000000050900000-00000000509fffff o:0000 a:0003 p:100 c:0 n:/memory/gicr 0100) 0000000088000080-0000000088007fff o:0040 a:0005 p:100 c:0 n:/memory/below4G/ram/fdt 0120) 00000000800d10a8-00000000815fa8b3 o:0000 a:0005 p:100 c:0 n:/memory/imagefs 0140) 0000000080080fa0-00000000800d10a7 o:0000 a:0007 p:100 c:0 n:/memory/startup 0160) 00000000800d10a8-00000000815fa8b3 o:0000 a:0007 p:100 c:0 n:/memory/bootram 0180) 00000000a0000000-00000000a0007fff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram 01a0) 00000000a0014000-00000000ff7fffff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram 01c0) 00000000ff83b000-00000000ffffffff o:0040 a:0007 p:100 c:0 n:/memory/below4G/ram/sysram 01e0) 0000000880000000-00000008dd5e2fff o:0060 a:0007 p:100 c:0 n:/memory/ram/sysram Re: PFE on S32G A53 QNX ERROR Hello, @Chen  Thanks for reply.The return code see the log. BR SandalWood  Re: PFE on S32G A53 QNX ERROR Hello, @SandalWood  Thanks for the post. Seems the memory is not correctly mapped, may I know if there is a log indicating that as_add_containing() was successful called? BR Chenyin

使用 UUU 闪存 i.MX8MM SD 卡的问题 我一直在尝试在 i.MX8MM 上闪存 SD 卡，但遇到了一些问题。我查看了文档，但并没有完全解开我的困惑。 关于 UUU，我已经下载了最新的 1.4.127 版：https://github.com/NXPmicro/mfgtools/releases/tag/uuu_1.4.127 而且我还下载了最新的预构建的 Linux 二进制文件 L5.10.9_1.0.0_MX8MM：https://www.nxp.com/webapp/Download?colCode=L5.10.9_1.0.0_MX8MM& apptype=License 我使用 UUU 通过以下方式将这个 5.10 Linux 版本闪存到我的 eMMC 中： uuu.exe uuu.auto 闪烁和启动都很正常。然后，我尝试通过更新 uuu.auto 文件将其闪存到 SD 卡，具体方法如下： # SD Programming: FB: ucmd setenv fastboot_dev mmc FB: ucmd setenv mmcdev ${sd_dev} FB: ucmd mmc dev ${sd_dev} FB: flash -raw2sparse all imx-image-multimedia-imx8mmevk.wic FB: flash bootloader imx-boot-imx8mmevk-sd.bin-flash_evk FB: ucmd if env exists sd_ack; then ; else setenv sd_ack 0; fi; FB: ucmd mmc partconf ${sd_dev} ${sd_ack} 1 0 FB: done # Emmc programming: #FB: ucmd setenv fastboot_dev mmc #FB: ucmd setenv mmcdev ${emmc_dev} #FB: ucmd mmc dev ${emmc_dev} #FB: flash -raw2sparse all imx-image-multimedia-imx8mmevk.wic #FB: flash bootloader imx-boot-imx8mmevk-sd.bin-flash_evk #FB: ucmd if env exists emmc_ack; then ; else setenv emmc_ack 0; fi; #FB: ucmd mmc partconf ${emmc_dev} ${emmc_ack} 1 0 #FB: done 在以下步骤中失败了： uuu.exe uuu.auto uuu (Universal Update Utility) for nxp imx chips -- libuuu_1.4.127-0-g08c58c9 Success 0 Failure 1 2:2 7/ 8 [ ] FB: ucmd mmc partconf ${sd_dev} ${sd_ack} 1 0 这让我觉得我不能简单地把一个换成另一个。所以我的问题是，如何使用 uuu 将 v5.10 预发布的 Linux 二进制文件闪存到 i.mx8mm EVK 上的 SD 卡中？ i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: Issue flashing i.MX8MM SD card with UUU 我同意，UUU 的文档非常少，如果不反复试验，很难使用。 如果恩智浦能派一名以英语为母语的应用工程师对其进行彻底更新，提供适当的使用案例，并采用标准的 Linux 风格命令行帮助语法，用户将受益匪浅。 我可以帮忙，但自己没有足够的业余时间...... Re: Issue flashing i.MX8MM SD card with UUU 使用脚本没有问题。 你需要的是常见的基本知识。 因为从"FB: ucmd mmc partconf${sd_dev} ${sd_ack} 1 0", 可以了解到你对 emmc 和 SD 卡一无所知，因为你不知道 WIC。 下面是闪存 SD 卡的脚本。uuuuuu.sd.auto，即可使用。 uuu.sd.auto uuu_version 1.2.39 # 此命令将在 i.mx6/7 i.mx8MM、i.mx8MQ SDP: 启动 -f imx-boot-imx-boot-imx8mmevk-sd.bin-flash_evk 时 # 这个命令将在 ROM 支持直播模式时运行 # i.mx8QXP，i.mx8QM SDPS：启动 -f imx- 启动-imx-启动-imx8mmevk-sd.bin-flash_ev k # 使用 SPL 时将运行这些命令，如果没有 spl # SDPU 将被弃用，则跳过这些命令。请使用 SDPV 代替 SDPU # { SDPU：延迟 1000 SDPU：write -f imx-boot-imx8mmevk-sd.bin-flash_evk-offset 0x57c00 SDPU: jump # } # 这些命令将在使用 SPL 时运行，如果没有 spl 则会跳过 # if（SPL 支持 SDPV） # {SDPV：延迟 1000 SDP V：write-f imx-boot-imx8mmevk-sd.bin-flash_evk -skipspl SDPV: jump # } FB: ucmd setenv fastboot_dev mmc FB: ucmd setenv mmcdev${emmc_sd} FB: ucmd mmc dev${emmc_sd} FB: flash -raw2sparse all imx-image-multimedia-imx8mmevk.wic FB: 已完成 Re: Issue flashing i.MX8MM SD card with UUU 要想知道什么是 wic，你就应该掌握 yocto 知识。 而 wic 与 .sdcard 相同。 Re: Issue flashing i.MX8MM SD card with UUU 谢谢您的建议。如果通过 `.sdcard` 文件闪存，文档和 `uuu` 输出都会提到 sdcard： sd_all burn whole image to sd card arg0: _flash.bin arg1: _rootfs.sdcard 显然，在这种情况下，它是一个 `.wic` 文件。是否有地方提到过，而我却忽略了？ 第二个问题：在内置命令起作用的同时，uuu.auto 文件也可以用于 SD 卡刷机吗？ Re: Issue flashing i.MX8MM SD card with UUU 使用 uuu 版本命令只需要一个命令行 uuu -b sd_all imx-启动-imx8mmevk-sd.bin-flash_evkimx-image-multimedia-imx8mmevk.wic 建议阅读 uuu 手册或键入 uuu（不带参数）以显示帮助

RSA usage examples I'm working on a s32k344 board and I'm trying to develop a digital signature verification routine that uses RSA. The aim is to import the RSA public key from outside and use it to verify the signature over a file loaded in flash. Is there any example code that shows how to import RSA key and perform  RSA crypto operations? Thanks Re: RSA usage examples Good morning, I have a similar problem with K32L2B31VLH0A. I would like to validate a signature with 2048-byte RSA or with ECDS, which should require fewer resources for the same result. My problem is insufficient RAM, or at least that's what the NXP mbed TLS library returns. Are there any working examples on this microcontroller, or is 32 KB of RAM not enough? I have four products with this microcontroller and I need to understand if I need to replace the microcontroller or if there are possible solutions. What I need is to be able to validate a signed firmware upgrade. Re: RSA usage examples Hi @niccolentini  See please attached example.  Environment: S32K344 with HSE FW 0_2_40_0 S32DS 3.5 RTD 4.0.0 HF01 EB 29.0 Regards, Lukas

SysTickタイマーの実行速度が速すぎます <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> MK64FN1M0VLQ12 を使用したデザインがあります。ボードの 1 つが異常な動作をしていますが、他のボードは正常です。 症状としては、SysTick タイマーが明らかに 25 倍速くカウントしているようです。オシロスコープを使用してすべてのクロックを測定したところ（ピン PTA6 に接続）、すべて正しい周波数でした。カウントが速すぎることの証拠は、OSA_TimeDelay() 呼び出しで指定した時間の 1/25 が返されることです。 クロックの構成: EXTAL および XTAL 上の 6.49 MHz 水晶。 PLL は 118.98333 MHz の MCGOUTCLK を生成します。 コアクロック分周比は 1 です。 バスクロック分周比は 2 です。 FlexBus クロック分周器は 4 です。 フラッシュクロック分周比は 8 です。 OSCERCLK (6.49MHz の信号が 2 つの ADC に送られます。 デバッガー (IAR EWARM) を使用して、正常なボードと不良なボードの両方で SysTick 制御およびリロード レジスタを調べました。良いボードと悪いボードの両方で同じ値が表示されます。不良ボード上のすべては正常に動作していますが、MQX 時間遅延がすべて 25 倍短すぎます。 この「不良」ボードは、MCU が交換され、ジャンパー ワイヤがスーパー グルーを使用してボードに接着されるなど、数回にわたって修理されています。このスーパーグルーは JTAG コネクタの下とピンの周囲に塗布されました。MCU が電源投入時にこれらのピンをサンプリングし、インピーダンスがいくらか低いために MCU が文書化されていない動作モードに切り替わる可能性はありますか?リファレンスマニュアルでブートストラップピンに関する記述を検索しましたが、何も見つかりませんでした。 MCU を交換しても問題は解決しませんでした。適切な溶剤でスーパーグルーをすべて除去しても問題は解決しませんでした。 あらゆるご指摘をいただければ幸いです。 Kinetis KシリーズMCU Re: SysTick timer is running too fast なぜこのようなことが起こったのか説明はありますか?現在、S32K344 で MCUBoot を実行しているときに、このクロック速度の問題 (25 倍速すぎる) が発生しています。 Re: SysTick timer is running too fast <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> こんにちは、 これまでこの問題に遭遇したことはありません。 OSA_TimeDelay() 関数で設定した値はどうでしょうか? そして、どうすれば予想通りより速く時間遅延を測定できるのか興味があります。 可能であれば、より詳細な情報を提供してもらえますか?ありがとう。 すてきな一日を、 馬慧 ----------------------------------------------------------------------------------------------------------------------- 注: この投稿で質問が解決した場合は、「正解」ボタンをクリックしてください。ありがとう！ -----------------------------------------------------------------------------------------------------------------------

OP-TEEキー こんにちは、 iMX8M miniにYocto BSPを使用しています。ここがこの質問をするのに適切な場所かどうかわかりません。そうでないCASEはお知らせください。 https://source.codeaurora.org/external/imx/imx-optee-os/tree/documentation/porting_guidelines.md?h=imx_4.19.35_1.1.0をご覧ください 私はそれを読むことができます ## 9. Trusted Application private/public keypair By default all Trusted Applications (TA's) are signed with the pre-generated 2048-bit RSA development key (private key). This key is located in the `keys` folder (in the root of optee_os.git) and is named `default_ta.pem`. This key **must** be replaced with your own key and you should **never ever** check-in this private key in the source code tree when in use in a real product.   また、次の場所でもご覧いただけます: https://optee.readthedocs.io/en/latest/building/trusted_applications.html#tas の署名 警告 「optee_os には、開発、テスト、デバッグ、QA を容易にするために、ソースにデフォルトの秘密キーが付属しています。このキーを使用してoptee_osバイナリを本番環境にデプロイしないでください。代わりに、このキーをできるだけ早く公開キーに置き換え、キーの秘密部分をオフラインで、できれば HSM 上に保管してください。」   はい、その後、新しいキーペアを生成し、公開キーを抽出しました。 次に、抽出した公開キーをキー フォルダーに配置し、名前を default_ta.pem に変更して、元の default_ta.pem を上書きします。 つまり、default_ta.pem には現在公開鍵のみが存在することになります。 現在、 optee-os-imx は正しくビルドされますが、 optee-test-imx はエラーを発生させます。これは、信頼できるアプリであり、署名に秘密キーが必要であるため、理解できます。 SO、私の質問は、default_ta.pemを別のKEYPAIR.pemに置き換えたらどうなるでしょうか？私が生成したファイルは安全ですか?optee-os-imx と optee-test-imx は正しくビルドされますが、キーペアの秘密キー部分は optee-os バイナリ ファイルから削除されますか?または、default_ta.pem キーペアはイメージに完全に埋め込まれますか? この最後のCASEでは、ビルド中のソースに秘密鍵を入れないようにという指示と少し衝突することになります。 この部分を処理するスクリプトをCAN教えていただけますか? ご協力の程、よろしくお願い申し上げます。 Re: OP-TEE key Yocto ビルドで HSM を使用して署名するために何を変更する必要があるかわかっている人はいますか? Re: OP-TEE key 私は、Yocto を使用して imx93 にセキュア ストレージを実装する予定です。この投稿に従い、実装方法は明確ですが、次の 2 つの点が明確ではありません。 -ハードウェアユニークキー（HUK）はTEEに既に存在しますか？SO、何もする必要はありません。 - TA を追加する必要がない場合でも、default_ta.pem を変更する必要がありますか?これに関するガイドはありますか？（キー生成 + Yocto での置換） HUK を抽出する方法はないと思うので、デバッグ目的であっても、別のハードウェア (組み込みまたはノートPC) でデータを解読することはできないと思いますが、本当でしょうか? Re: OP-TEE key はい、その通りです@IvanRuiz 。 唯一の問題は、imx-optee-test レシピもビルドし、これには optee-os が必要であり、optee-os ビルド フォルダーから秘密キーを取得しようとすることです。 とにかく、Tee イメージに埋め込む前に、秘密鍵がキーペアから取り除かれることがわかりました。これは次のスクリプトによって実行されます。 pem_to_pub_c.py キーペアから抽出された公開キーの情報のみを含む ac ファイルを生成します。 それが tee.bin ファイルに追加されます。 あなたのドキュメントに従って、私たちは秘密鍵をソースとともにリポジトリにコミットするつもりはありません。 Re: OP-TEE key こんにちは、 セキュリティ上の理由から、 keys/default_ta.pemに秘密鍵を保存することは推奨されません。ドキュメントによると、生成された公開鍵のみを使用することが推奨されています。これは、公開鍵は暗号化にのみ使用され、秘密鍵はできれば HSM に保存されるためです。TA は、ドキュメントに記載されているように、OP-TEE のsign_encrypt.pyを使用して署名されます。 お役に立てれば幸いです！ BR、 イワン。

Reg: Need the Ubuntu OS 22.04 LTS support chipset Dear Team, we got the new opportunity to work in the Robotics based application project where we need the processor which can support Ubuntu OS with 22.04 LTS version with ROS support also. so kindly pls suggest which chipset we can go with.

S32K3 セーフティ分析レポート こんにちは、NXP S32K3の機能安全について勉強しています。マニュアルによると、セーフティ分析レポートではFMEDA、DFA、FTAを組み合わせることができるとのことです。参考例はどこで入手できますか？ よろしくお願いします、 シアンロン Re: S32K3 Safety Analysis Report こんにちは、 実際の FMEDA/DFA/FTA テンプレートまたは例を探している場合は、通常、以下が提供されています。 NDA（秘密保持契約）に基づき NXPサポートまたはお近くのFAE（フィールドアプリケーションエンジニア）を通じて すべてのセーフティ関連文書は、NXP の S32K3 ウェブページの安全なファイルの下にあります。 https://www.nxp.com/products/S32K3?ticket=ST-2386-bOAWTUGgQ9aB9hAx3KqTeCycCAc-nxp#myDocument NXP FAE が直接対応しているので、例については直接問い合わせることをお勧めします。 よろしくお願いいたします。 ピーター