NCJ29D6 Problems after upgrading to new Firmware Hello, After upgrading the board to a new firmware and adapting the application (APP_INFO, new SDK/API), the device remains in HostIF BKP (0x401504 bkpt 0xFF). Flashing the application was initially possible. Debugging (SWD) works, but I get an exception when I try to call NDP functions (debugger only shows ?? for this memory). Re-flashing with Lauterbach script is now also not possible (the memory for the flash driver also shows ??). But I can still attach and debug the currently flashed application. My guess is that the new application cannot be found and the device has now activated SWUP? I'm not quite sure why flashing the new application didn't work and how I should proceed from here? Best regards, Stefan Re: NCJ29D6 Problems after upgrading to new Firmware Hello, Hope you are doing well. Sorry for the inconvenience this might cause you but as the information of this product it's under NDA (Non-Disclosure Agreement) the information it's not public. For more information about the chip could you please contact one of our distributors available in the Distributor Network|NXP? Or if you have any direct contact, please contact them. Regards, Ricardo

S32G3 BSP41 PFE2 RGMII to RGMII without PHY on the customized board Hi, Our hardware design connects PFE2 RGMII directly to the switch RGMII without a PHY. The PFE2 is configured with rgmii-id, and we have verified the 125MHz TX clock output. I have come across discussions suggesting the use of a common external clock for both sides. Is clock drifting the only concern in this setup? If so, is it possible to configure PFE2 as a clock slave and use the clock output from the switch to synchronize TX and RX? Thanks, XD Re: S32G3 BSP41 PFE2 RGMII to RGMII without PHY on the customized board Hello @XD, I am glad you found the information helpful. Thanks for accepting my answer as a solution. Best regards, Alejandro  Re: S32G3 BSP41 PFE2 RGMII to RGMII without PHY on the customized board Hi @alejandro_e , Thank you again for your help. This information is very helpful. Thanks, XD Re: S32G3 BSP41 PFE2 RGMII to RGMII without PHY on the customized board Hello @XD, I can not access the technical information for the Marvell Switch, however, I see it is relatively similar to the SJA1110, for which you can check the following document: AN13335.pdf, in particular please check section 2.2 RGMII interface in page 8:     Let me know if this information solved your problem.   Re: S32G3 BSP41 PFE2 RGMII to RGMII without PHY on the customized board Hi @alejandro_e , We have a Marvell switch port running in RGMII mode, connected to PFE2 on our hardware. Thanks, XD Re: S32G3 BSP41 PFE2 RGMII to RGMII without PHY on the customized board Hello @XD, To the best of my knowledge the same guidelines should apply to any device connected using RGMII, either a PHY or a switch.  with that said, can you share the RGMII device you are connecting the S32G3 to? So I can check if there could be special considerations. Thanks in advance. Re: S32G3 BSP41 PFE2 RGMII to RGMII without PHY on the customized board Hi @alejandro_e , It's great that you're helping me again—I really appreciate it. The guideline you provided is for an RGMII-to-PHY scenario. Do you have any guidelines for a direct RGMII-to-RGMII connection without a PHY? Thanks, XD Re: S32G3 BSP41 PFE2 RGMII to RGMII without PHY on the customized board Hello @XD, It is good to support you again. About your question, please refer the the S32G3 - Hardware Design Guidelines, in particular please check sections: 10 Communication Peripherals, 10.1.1 RGMII signal routing requirements and 13.3 High-speed routing recommendations. There you should be able to find all the relevant information about RGMII on a HW level. Let me know if you have more questions about this topic.    

S23K312EVB MCUに存在するADCに接続するジャンパーピンを特定するのを手伝ってくれる人はいますか 日時:S23K312EVB どうもありがとうございます！

How to obtain the commutation timing sequence table? Hello all:     I am testing the BLDC using the MCSPTE1 AK144 kit.      When I was reading the AN12435.pdf, I saw the Figure 4 "Six-step switching sequence" of page 5, and please refer to the attached sequence.png file.     I want to know how this switching sequence is obtained? What method can be used to obtain the sequence?     Thanks! Best regards, Fedora Re: How to obtain the commutation timing sequence table? Hello Leo:    Ok, I understand now. I will continue my research. Thanks for your help. Best regards, Fedora Re: How to obtain the commutation timing sequence table? Hi, Thank you so much for your interest in our products and for using our community. You could refer to Figure 2. 3-phase BEMF voltages and phase currents of a BLDC motor from the same app note. On the other hand, Six-step commutation is a very common method for driving a 3-phase star-connected BLDC motor, maybe there are more detailed documentation about this on the web. We usually just describe the basics to implement motor control with our MCUs. Hope it helps you. Have a nice day!

How do RFLevel values change the sensitivity of the RF Level Detector on the PN512? Increasing the RFLevel increases the V~Rx [Vpp] based on the table 155 in the pn512 datasheet. What does that mean in terms of sensitivity for the RF Level Detector? Does raising the V~Rx[Vpp] mean I am increasing sensitivity?  Does increasing RFLevel increase the gain for some kind of amplifier thereby increasing the sensitivity or is it raising some type of threshold thereby decreasing the sensitivity?  Thank you NFC Frontend Solutions Re: How do RFLevel values change the sensitivity of the RF Level Detector on the PN512? Hi, Sensitivity should increase as RF level value goes from 0xF to 0x0. Regards, Eduardo. Re: How do RFLevel values change the sensitivity of the RF Level Detector on the PN512? Thank you for your reply. So as RFLevel increases from 0x00 to 0x0F I am increasing the sensitivity of the RFLevel Detector? Or is it the other way around where the sensitivity of the RFLevel Detector is increasing as RFLevel goes from 0x0F to 0x00. Thank you Re: How do RFLevel values change the sensitivity of the RF Level Detector on the PN512? Hello @user_leo Hope you are doing well. The RF level detector detects the presence of an external RF-field delivered by the antenna to the RX pin. The values listed in Table 155 should correspond to a typical voltage that would be seen at the RX pin. However, the sensitivity itself depends on the antenna configuration and tuning. Lower sensitivities are prone to intrinsic noise in the environment, causing misleading results. To increase the sensitivity of the RF level detector an amplifier can be activated by setting the bit RFLevelAmp, but it would be recommended to use it with upper values. Regards, Eduardo.

S32K312ピンマップまたはピン配置図 コミュニティの皆さん、こんにちは。 s32k312EVB-Q172ボードのピンマップまたはピン配置図はどこにありますか? よろしく Re:S32K312ピンマップまたはピン配置図 また、s32k312EVB-Q172 ボードのピン配置も探しています。リファレンスマニュアルをダウンロードしましたが、S32K312_IOMUX.xlsxファイルがありません。PDFにどのように添付されますか?別のダウンロードURLへのリンクはありますか?

freeRTOS for s32k3 2.0.3 ( s32ds v3.4 ) not install During the time of installation i got error which can not be solve using any way that i tried ,    Re: freeRTOS for s32k3 2.0.3 ( s32ds v3.4 ) not install I got my  files through change into location path .  Re: freeRTOS for s32k3 2.0.3 ( s32ds v3.4 ) not install Hi, Thank you so much for your interest in our products and for using our community. For S32K3 FreeRTOS version 2.0.3 you also need S32 Design Studio IDE v3.4 Update 3. This update include the item you need. You can found it in S32K3 page -> Design Resources -> Software -> S32K3 Standard Software -> Automotive SW - S32K3 - S32 Design Studio -> Previous: Then install it in S32DS -> Help -> Install New Software Hope it helps you. Have a nice day!

IMX8QM DP++ (DisplayPort Dual-Mode) Hi, We've a custom (imx8qm) board with an mDP (mini DisplayPort) connector, and I'd like to connect an external HDMI screen using a passive mDP-HDMI adapter. My understanding is that this should be possible if DP++ (DisplayPort Dual-Mode) is supported. I have a few questions regarding DP++ support on the i.MX8QM: i.MX8QM DP++ Support: Does the i.MX8QM processor itself support DP++? Cadence Firmware DP++ Support: Does the Cadence firmware for the i.MX8QM's DisplayPort controller support DP++? Device Tree Configuration: Are there any necessary device tree (dtb) configurations required to enable and utilize DP++ functionality? If so, could you please provide details on the specific settings? Thank you for your assistance. Re: IMX8QM DP++ (DisplayPort Dual-Mode) Hello, Unfortunately DisplayPort Dual-Mode is not supported in i.MX8QM, you need to look into another adapter. I apologize the inconvenience that this may affect your design. Best regards.

What does it mean HSE_SWT_RST on S32K311!!! Hello all. Where can I found information about HSE_SWT_RST reset? With the following clock configuration: PLL_PHI0_CLK=120MHz CORE_CLK=PLL_PHI0_CLK/1=120MHz AIPS_PLAT_CLK=PLL_PHI0_CLK/2=60MHz AIPS_SLOW_CLK=PLL_PHI0_CLK/4=30MHz HSE_CLK=PLL_PHI0_CLK/1=120MHz DCM_CLK=PLL_PHI0_CLK/4=30MHz at power on I occasionally get the reset HSE_SWT_RST. What is the cause? I probably need to reduce the HSE clock to 60 MHz or change the value of HSE_CLK_MODE_AND_GSKT_CTRL to 10 of the dcf_client_utest_misc client. Where can I find documentation that explains this? Best regards E. Re: What does it mean HSE_SWT_RST on S32K311!!! Hi @enricoantonioli  The HSE_SWT_RST is usually caused by wrong clock configuration. It was found out that it is possible to configure 120MHz HSE_CLK only during reset by DCF record. It cannot be done later by software for some reasons. That means it is necessary to set PLL_ENABLE in BCW (Boot Configuration Word) in IVT, it is necessary to program crystal oscillator configuration flag in UTEST at 0x1B000050 (see section 32.4.3.2 Crystal oscillator configuration flag in the S32K3 RM), it is necessary to program the dcf_client_utest_misc - HSE_CLK_MODE_AND_GSKT_CTRL equal to 10 or 11. Re: What does it mean HSE_SWT_RST on S32K311!!! Hi, Thanks for the precious information, but I still don't understand why in my situation there is a HSE_SWT_RST reset. What is the cause? What's wrong with the HSE? Best regards E. Re: What does it mean HSE_SWT_RST on S32K311!!! Hi @enricoantonioli  What does HSE_SWT_RST mean? It stands for HSE Software Watchdog Timer Reset. Is it a reset due to an internal HSE watchdog or what? The HSE CPU is mainly composed of Arm Cortex-M0+, which one of its essential peripherals is the watchdog.  So yes, it is trigger by HSE SWT as the name implies. Why this reset occurs if no firmware is programmed into the HSE memory? The HSE CPU, even if the HSE firmware is not loaded, is active because it contains the SBAF code. Re: What does it mean HSE_SWT_RST on S32K311!!! HI Vane, first of all, thank you very much for your quick reply. At the moment I have reduced the HSE_CLOCK to 60 MHz because in the HSE there isn't programmed a firmware. I will activate HSE soon. What does HSE_SWT_RST mean? Is it a reset due to an internal HSE watchdog or what? What I don't understand is why this reset occurs if no firmware is programmed into the HSE memory? If I understand correctly, at power on the HSE processor executes the SBAF code and then stops in a WFI. So who triggers the HSE_SWT_RST reset? Best regards E. Re: What does it mean HSE_SWT_RST on S32K311!!! Hi @enricoantonioli  According to the information, it seems that the problem is due to incorrect clock configuration. The HSE_CLK_MODE_AND_GSKT_CTRL (bit 30-29) must be set to 1x if you want to use HSE_CLK equal to 120 MHZ. On the other hand, if HSE_CLK_MODE_AND_GSKT_CTRL was set to 00, it is necessary to change HSE_CLK to 60 MHZ. Refer to S32K3xx_DCF_clients file attached to the S32K3xx Reference Manual.  This must be done by writing to dcf in UTEST memory using Flash controller. You can check the following article, it might be a good reference.  [S32K3] Restrict the debug access with a password when HSE is not used BR,VaneB

3V coin cell backup for imx93 Hello everyone, I would like to know if there is any way to use a 3V Coin Cell battery backup for the NVCC_BBSM_1P8 power rail of the imx93 with the PCA9451A PMIC. As I must keep the RTC and Tampers working once the main supply has been shutted down, a Coin Cell backup is needed. In the "4.1.3 Power architecture" section of the imx93 datasheet there is an image which shows the basic diagram for a backup battery. I wonder if there is a way to connect the 3V CC to the PMIC. In order to achive an uninterrumpted NVCC_BBSM_1P8 (provided by LDO1), I must keep INL1 and VSYS above 2.7V  due to the UVLO feature of the PMIC (which is impossible with a 3V CC). Anyway, a LDO with a CC would be pretty bad in terms of efficiency. Is there any way to use a 3V CC backup alongside the PCA9451A to keep NVCC_BBSM_1P8 power rail on? If no, is a power mux with ideal diodes needed to do a custom switchover between the PMIC's LDO output and a regulated (with a buck converter) 3V coin cell to manage this issue? Best regards, Gorka. Re: 3V coin cell backup for imx93 Hello, As is mentioned in PMIC's datasheet, the suggested option is connect a battery and a regulator in NVCC_BBSM_1P8 power rail to keep this power domain on and switch between the PMIC's LDO and regulated output from coin cell. Best regards.

ISO-26262 ASIL-C compliant PIL testing with S32G-VNP-GLDBOX Hi, it there some ISO 26262 certification of S32G-VNP-GLDBOX used together with Matlab Simulink plugin for PIL testing, and some guidelines to prove the toolchain can be considered as qualified? I mean something like MathWorks have their ICE Certification kit?  Simulink plugin: Model-Based Design Toolbox | NXP Semiconductors Re: ISO-26262 ASIL-C compliant PIL testing with S32G-VNP-GLDBOX Hi @Jan_S,  Thanks for the questions. Unfortunately, we do not have the expertise with the MBDT software to give a support with that you can ask at: Model-Based Design Toolbox (MBDT) community, the Goldbox there is known as HCP.  Regarding to the ISO 26262 you can find the following on the S32G3 Reference Manual:   [Page 3660, S32G3 Reference Manual, Rev. 4, 02/2024] Also, at the Product details of the GoldBox 3 Vehicle Networking Development Platform site you could find the next:

FS26 OTP Configuration Report for MFS2633AMDAJAD Hi, I'm currently involved in the design of a product with the S32K358 and we intend to use the FS26 as the SBC for the system. Where can I get OTP configuration data for oderable parts as shown in Table 2 of FS26 Product Data Sheet rev 4.1. Table 260 of the same document only covers a small subset of parts. I am particularly interested in FS2633AMDAJAD as we have samples of that but would also like OTP configuration data for all the oderable FS2633 line to see if one of the oderable parts is suitable for our application. https://www.nxp.com/part/MFS2633AMDAJAD Thanks, Jon Re: FS26 OTP Configuration Report for MFS2633AMDAJAD Many thanks Tomas. I think I scrolled all the way to the parametric table and missed the comparison table, thanks for pointing it out. Re: FS26 OTP Configuration Report for MFS2633AMDAJAD Hello Jon, Please find attached the required OTP configuration report for the MFS2633AMDAJAD. The OTP files and reports are available in the Comparison Table of the FS26 website. BRs, Tomas

DAC 和 ADC 位于同一 SAI 上 你好， 我正在尝试设置一个设备树，以便我们可以使用相同的 SAI（SAI1）来使用 AK4458 DAC 和 AK5558 ADC。我已经成功为 AK4458 设置了一个简单的音频卡设备树节点，但现在我正尝试集成 AK5558。我只是想知道这是否可以通过简单的音频卡实现。请注意，它们应该使用相同的格式。它们都使用 TDM256、32 位、MSB。这是我当前测试设备树的摘录。在当前配置下，在相应卡上开始录制时似乎没有任何 RX 帧同步。 / { custom-audio-card { compatible = "simple-audio-card"; #address-cells = <1>; #size-cells = <0>; simple-audio-card,name = "Custom Audio"; system-clock-fixed; system-clock-direction-out; simple-audio-card,dai-link@0 { format = "left_j"; bitclock-master = <&sai1cpu0_master>; frame-master = <&sai1cpu0_master>; sai1cpu0_master: cpu { sound-dai = <&sai1>; dai-tdm-slot-num = <8>; dai-tdm-slot-width = <32>; dai-tdm-slot-tx-mask = <1 1 1 1 1 1 1 1>; dai-tdm-slot-rx-mask = <1 1 1 1 1 1 1 1>; }; codec { sound-dai = <&ak4458>; prefix = "ak4458"; dai-tdm-slot-num = <8>; dai-tdm-slot-width = <32>; dai-tdm-slot-tx-mask = <1 1 1 1 1 1 1 1>; dai-tdm-slot-rx-mask = <0 0 0 0 0 0 0 0>; }; }; simple-audio-card,dai-link@1 { format = "left_j"; bitclock-master = <&sai1cpu1_slave>; frame-master = <&sai1cpu1_slave>; sai1cpu1_slave: cpu { sound-dai = <&sai1>; dai-tdm-slot-num = <8>; dai-tdm-slot-width = <32>; dai-tdm-slot-tx-mask = <1 1 1 1 1 1 1 1>; dai-tdm-slot-rx-mask = <1 1 1 1 1 1 1 1>; }; codec { sound-dai = <&ak5558>; prefix = "ak5558"; dai-tdm-slot-num = <8>; dai-tdm-slot-width = <32>; dai-tdm-slot-tx-mask = <0 0 0 0 0 0 0 0>; dai-tdm-slot-rx-mask = <1 1 1 1 1 1 1 1>; }; }; }; }; &sai1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai1>; // TODO ! clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; assigned-clocks = <&clk IMX8MM_CLK_SAI1>; assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; assigned-clock-rates = <24576000>; fsl,sai-asynchronous; fsl,sai-mclk-direction-output; // SAI will output the MCLK fsl,dataline = <1 0x01 0x01>; status = "okay"; }; 回复：DAC 和 ADC 位于同一 SAI 上 我的密码配置确实错误！另外，我现在在 RX 同步模式下使用 sai。据我所知，一切都按预期进行！

ISO-26262 ASIL-C 準拠 PIL 試験 (S32G-VNP-GLDBOX による) こんにちは、S26262G-VNP-GLDBOXのISO 32G-VNP-GLDBOX認証とMatlab SimulinkプラグインをPILテストに使用し、ツールチェーンが適格と見なすことができることを証明するためのガイドラインはありますか?MathWorksのようなものがICE認定キットを持っているということですか? Simulink プラグイン: Model-Based Design Toolbox |NXPセミコンダクターズ

IPS 大家好， S32G3参考手册中使用的IPS总线是什么？在多种情况下，“IPS”缩写被用于多种语境中。我正在寻找它的完整形式和规格。在其中一个例子中，我注意到它将“外围总线接口”称为（IPS），这听起来与缩写不符。它是 (IPS) NXP专有的吗？S32G2 S32G3 S32G-VNP-RDB3 S32G-VNP-RDB2 回复：IPS 谢谢您的回复。我很欣赏提供详细信息的方式。继续努力吧。

TEA2017AAT and TEA2016AAT Hi NXP Team, What is the difference between TEA2017AAT and TEA2016AAT? Thanks. Re: TEA2017AAT and TEA2016AAT Hello Arvind, for your additional questions I have open another ticket so the responsible engineering team can follow up with you directly. Have a nice day. Best regards Pavla Re: TEA2017AAT and TEA2016AAT Hi Pavla, And one more doubt Regarding SUPIC Pin - What is exact functionlity of this pin? I can see this statement in datasheet "When start-up is complete and the LLC controller is operating, the LLC transformer auxiliary winding supplies the SUPIC pin. In this operational state, the HV start-up source is disabled."  Do we need to connect SUPIC pin to Aux winding? What happens if will not connect? Regards, Arvind Re: TEA2017AAT and TEA2016AAT Hi Pavla, Thanks for your reply. Which IC we should use? Which one is latest one?   Regards, Arvind Re: TEA2017AAT and TEA2016AAT Hello Arvind, TEA2017 and TEA2016 are pin to pin compatible.  1. you can replace directly, but because the TEA2017 PFC control is average current mode, so the TEA2017 layout check IC pin 4 GND pin need sense near PFC current Res GND (PFC current sense Res also near the Bulk cap GND) as well. When you replace TEA2017 to TEA2016 board need check about the PFC current operation stable or not. If ok than fine.  2. For the TEA2016 and TEA2017 programming pin is not same, so when you replace the TEA2017, you need to change the programming pin as attached.   3. For the mif setting (software setting) is not same the Ringo tool also not same, the TEA2016 (PFC default is DCM/QR) and TEA2017 (PFC default is DCM /QR /CCM). The PFC control behavior is not same  LLC setting is similar, so confirm with your customer as well.  Hope this helps. Have a nice day. Best regards Pavla

How to configure lpuart4 with the correct pads in the device tree for IMX93? I am trying to use uart4 with flow control(cts/rts) , I tried to add the Pin Multiplexing configuration for a qs93 board like you can see below:  pinctrl_uart4: uart4grp { fsl,pins = < MX93_PAD_GPIO_IO19__LPUART4_TX 0x31e MX93_PAD_GPIO_IO24__LPUART4_RX 0x31e >; }; pinctrl_uart4_rtscts: uart4-rtsctsgrp { fsl,pins = < MX93_PAD_GPIO_IO26__LPUART4_CTS_B 0x31e MX93_PAD_GPIO_IO18__LPUART4_RTS_B 0x31e >; }; The Pad names seems to be not correct, known that I determine them from QS93 document, the pins I wanted to use are with the same GPIOs in the pad and for sure support the LPUART4 mentioned alternative functions.  With these configuration, my recipe build fails with: syntax error FATAL ERROR: Unable to parse input tree  How can I determine the correct pad names in this case, or where I can find the correct definition if these pads?  Yocto Project Re: How to configure lpuart4 with the correct pads in the device tree for IMX93? My mistake was that I determined incorrectly the pad names from the documentation, here it is the correct configuration.   pinctrl_uart4: uart4grp { fsl,pins = < MX93_PAD_ENET2_TD0__LPUART4_TX 0x31e MX93_PAD_ENET2_RD0__LPUART4_RX 0x31e >; }; pinctrl_uart4_rtscts: uart4-rtsctsgrp { fsl,pins = < MX93_PAD_ENET2_TD1__LPUART4_RTS_B 0x31e MX93_PAD_ENET2_RD2__LPUART4_CTS_B 0x31e >; };

软件激活失败，服务器错误 我正在尝试激活 S32 Design Studio for Arm，但在线和离线激活均失败，并显示错误消息“ com.acresso.activation.handler.ServerException ” 激活服务器似乎出了问题？

How to save secure data to SE050 Hi all, Currenly, i'm working with secure element SE050.  I readed on SE050's datasheet and found content: "Secured user flash memory up to 50 kB for secure data or key storage". My question: How to save/read my secure data to flash memory of SE050? Thanks. i.MXRT 106x Re: How to save secure data to SE050 Hi @namht , Is it possible to turn on the verbose log level? so I may have the APDU command log for analyzation.  Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: How to save secure data to SE050 I call ex_sss_boot_factory_reset() → Se05x_API_GetFreeMemory() → InjectCertificate → Se05x_API_GetFreeMemory() . Log : App :INFO :mem=32767 App :INFO :Inject certificate example App :INFO :Injecting ECC certificate at 0x00000014 App :INFO :mem=32767 Re: How to save secure data to SE050 Hi @namht , Yes, it is possible so we recommend binging with your host in real application, please kindly refer to https://www.nxp.com/docs/en/application-note/AN12662.pdf for details. Actually the mem size should change, but I am not sure if you have enabled the following definition so the application deleted all custom defined secure objects from the beginning of the demo. Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: How to save secure data to SE050 Hi @Kan_Li  I tried demo of "se05x_InjectCertificate" for save data to SE050 and "se05x_GetCertificate" for read back this data from SE050 successly. Howerver, my secure data can be leak if anyone try  "brute force" keyID for get data, rights? And, I tried a demo of "se05x_Minimal" for gets available memory from secure element. I see before and after Inject Certificate, Se05x_API_GetFreeMemory() return pfreeMem = 32767. Why available memory of SE050 not change?   Re: How to save secure data to SE050 Hi @namht , There is another demo called "se05x_GetCertificate". Please kindly refer to simw-top\demos\se05x\se05x_GetCertificate for details. Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: How to save secure data to SE050 Hi Kan, Thank you for reply. I tried following the example, but i don't know how to read back it again. I tried "sss_key_store_get_key()" and return status = kStatus_SSS_Fail Re: How to save secure data to SE050 Hi @namht , Binary file is a secure object supported by SE050, so you may create a file object at first and store your secure data into it, for example, the device certificate . We provide a demo of se05x_InjectCertificate for that purpose. You may find this demo within the MW: https://www.nxp.com/webapp/Download?colCode=SE05x-PLUG-TRUST-MW&appType=license . Hope that helps, Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

使用 I2c 将 DAC6571 与 RT1020 连接 大家好， 我已使用 I2c 将 DAC6571 与 i.Mx RT1020 处理器连接起来。 我已经使用了 SDK 中的 i2c DMA 示例。 我在 DAC 上写入数据时遇到问题；它的行为非常随机。无法在 DAC 上设置正确的值。 请指导我。 i.MXRT 102x 回复：使用 I2c 将 DAC6571 与 RT1020 连接 谢谢您的回复。 无论我如何配置它都不正确吗？ 回复：使用 I2c 将 DAC6571 与 RT1020 连接 我这样设置。但是不工作 字节数据[3]； 数据[ INDEX0 ] = (value >> 6) & 0x0F; // 10 位值的高 4 位 数据[ INDEX0 ] |= 0x30; // 设置两个零和两个断电位（00 11 XXXX） 数据[ INDEX1 ] = (值 << 2) & MAX_8BIT; // 10 位值的低 6 位，后跟两个无关位