Compile the sample project within MCAL, like S32K14X_MCAL4_2_RTM_1_0_0 Hi,     If you try to compile the sample project within S32K14X_MCAL4_2_RTM_1_0_0, you should take care of the command if you use Linaro.    After you set the environment of compiling and run the command under command window, you should enter     "launch.bat MODE=USER TOOLCHAIN=linaro"    NOT    "launch.bat MODE=USER TOOLCHAIN=LINARO"    The command is case sensitivity.   Hope you can compile the project successfully.  Cheers! Oliver

MC56F83xxx 的引导加载程序实用程序 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> MC56F83xxx是最新的DSC系列，它集成了CAN-FD、USB、增强型DMA等新功能，可用于电机控制、开关模式电源应用。 MC56F83xxx在片上闪存中运行代码，因此引导加载程序的主要任务是在制造过程中或设备生命周期的任何时间使用嵌入式应用程序固件映像更新内部闪存。引导加载程序通过充当从设备并监听主设备可以启动通信的各种外设端口来完成配置。 该文档描述了使用引导加载程序将应用程序代码下载到闪存的过程，例如硬件连接、生成 S-Record 文件、选择 S-Record 文件、blhost 命令，特别是客户可能面临的陷阱。 概述

i.MX 8M Mini SoM Supports Running Linux / Android Measuring 60mm by 49mm, the MYC-C8MMX CPU Module is a high-performance and cost-effective ARM SoM powered by i.MX 8M Mini which is NXP's first embedded multi-core heterogeneous applications processors built using advanced 14LPC FinFET process technology. The MYC-C8MMX CPU Module provides an outstanding embedded solution for Home and Building Control, IOV, Industrial and Medical Instruments, Human Machine Interface (HMI) and more other general purpose industrial and IoT applications which require optimized power consumption while maintaining high-performance. It is a minimum system integrated with CPU, 2GB DDR4, 8GB eMMC, 32MB QSPI Flash, GigE PHY and PMIC. All controller signals are brought out through two 0.8mm pitch 100-pin Expansion Connectors. It is capable of running Linux and Android OS and provided with plenty of software resources.                         MYC-C8MMX CPU Module Top-view                                         MYC-C8MMX CPU Module Bottom-view   MYIR offers MYD-C8MMX development board for evaluating the MYC-C8MMX CPU Module, the base board has taken great media capabilities of the i.MX 8M Mini processor to provide MIPI-DSI, MIPI-CSI, LVDS interfaces and Audio In/Out ports. It also has strong communication connectivity with 2 x USB 2.0 Host ports and 1 x Micro USB 2.0 Host/Device port, Gigabit Ethernet, MicroSD card slot, USB based Mini PCIe interface for 4G LTE Module, WiFi/Bluetooth and NVMe PCIe M.2 2280 SSD Interface. MYIR can offer design services to help customize the base board according to customers’ requirements.                                                    MYD-C8MMX Development Board Top-view                                                     MYD-C8MMX Development Board Bottom-view   MYIR offers commercial and industrial grades options for CPU Modules. More information can be found at: http://www.myirtech.com/list.asp?id=617 Measuring 60mm by 49mm, the MYC-C8MMX CPU Module is a high-performance and cost-effective ARM SoM powered by i.MX 8M Mini which is NXP's first embedded multi-core heterogeneous applications processors built using advanced 14LPC FinFET process technology. The MYC-C8MMX CPU Module provides an outstanding embedded solution for Home and Building Control, IOV, Industrial and Medical Instruments, Human Machine Interface (HMI) and more other general purpose industrial and IoT applications which require optimized power consumption while maintaining high-performance. It is a minimum system integrated with CPU, 2GB DDR4, 8GB eMMC, 32MB QSPI Flash, GigE PHY and PMIC. All controller signals are brought out through two 0.8mm pitch 100-pin Expansion Connectors. It is capable of running Linux and Android OS and provided with plenty of software resources.                         MYC-C8MMX CPU Module Top-view                                         MYC-C8MMX CPU Module Bottom-view   MYIR offers MYD-C8MMX development board for evaluating the MYC-C8MMX CPU Module, the base board has taken great media capabilities of the i.MX 8M Mini processor to provide MIPI-DSI, MIPI-CSI, LVDS interfaces and Audio In/Out ports. It also has strong communication connectivity with 2 x USB 2.0 Host ports and 1 x Micro USB 2.0 Host/Device port, Gigabit Ethernet, MicroSD card slot, USB based Mini PCIe interface for 4G LTE Module, WiFi/Bluetooth and NVMe PCIe M.2 2280 SSD Interface. MYIR can offer design services to help customize the base board according to customers’ requirements.                                                    MYD-C8MMX Development Board Top-view                                                     MYD-C8MMX Development Board Bottom-view   MYIR offers commercial and industrial grades options for CPU Modules. More information can be found at: http://www.myirtech.com/list.asp?id=617

当前APK.apk <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> Android 传感器融合 APK <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> Android 传感器融合 APK 传感器融合

Current APK.apk Android sensor fusion APK Android sensor fusion APK SensorFusion

MC56F83xxx のブートローダユーティリティ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> MC56F83xxxは最新のDSCファミリーであり、CAN-FD、USB、拡張DMAなどの新機能を統合し、モーター制御、スイッチモード電源アプリケーションで使用できます。 MC56F83xxxはオンチップフラッシュでコードを実行するため、ブートローダーの主なタスクは、製造中またはデバイスの寿命中いつでも、組み込みアプリケーションファームウェアイメージで内部フラッシュメモリを更新することです。ブートローダーは、スレーブデバイスとして機能し、マスターが通信を開始できるさまざまな周辺ポートをリッスンすることでプロビジョニングを行います。 このドキュメントには、ブートローダーを使用してアプリケーションコードをフラッシュにダウンロードする手順、たとえば、ハードウェア接続、S-Recordファイルの生成、S-Recordファイルの選択、blhostコマンド、特にお客様が直面する可能性のあるトラップについて説明します。 全般

3-Phase Hall Sensor PMSM Driver for E-Bike and Sensorless Solution for HV Motor-Based on KE02 Description Block Diagram Products Related Documentation Training Related Demos from Communities Description A bicycle with an integrated electric motor and a rechargeable battery, making it an eco-friendly, zero-emission vehicle ideal for smart cities. An important feature of an E-Bike is that it must be reliable and can be used for long periods. Block Diagram Products Category Name 1: Microcontroller Product 1 URL 1 https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/ke-series-cortex-m4-m0-plus/kinetis-ke02-20-mhz-entry-level-microcontrollers-mcus-based-on-arm-cortex-m0-plus-core:KE02 Product 1 Description 1 The Kinetis KE02 includes a powerful array of analog, communication and timing and control peripherals with specific flash memory size and the pin count. The K02 acts as a low-power, high-robustness, and cost-effective microcontroller with one 6-channel FlexTimer/PWM and two 2-channel FlexTimer/PWM. Product 2 URL 1 Arm® Cortex®-M4|Kinetis® K64 120 MHz 32-bit MCUs | NXP  Product 2 Description 1 Kinetis ®  K64-120 MHz, 256 KB SRAM Microcontrollers (MCUs) based on Arm ®  Cortex ® -M4 Core Category Name 2: Gate driver Product 1 URL 1 https://www.nxp.com/products/power-management/motor-and-solenoid-drivers/bldc-h-bridge-stepper/3-phase-brushless-motor-pre-driver:GD3000 Product 1 Description 1 The GD3000 is a gate driver IC for three-phase motor drive applications providing three half-bridge drivers, each capable of driving two N-channel MOSFETs. Category Name 3: LED Driver Product URL 1 https://www.nxp.com/products/power-management/lighting-driver-and-controller-ics/ic-led-controllers/16-channel-fm-plus-ic-bus-57-ma-20-v-constant-current-led-driver:PCA9955BTW Product Description 1 The PCA9955B is an I2C-bus controlled 16-channel constant current LED driver optimized for dimming and blinking 57 mA Red/Green/Blue/Amber (RGBA) LEDs in amusement products. Each LED output has its own 8-bit resolution (256 steps) fixed frequency individual PWM controller that operates at 31.25 kHz with a duty cycle that is adjustable from 0 % to 100 % to allow the LED to be set to a specific brightness value. Category Name 4: Logic USB Type-C Configuration Channel Product URL 1 https://www.nxp.com/products/interfaces/usb-interfaces/usb-type-c-true-plugn-play/usb-pd-phy-and-cc-logic/cc-logic-for-usb-type-c-applications:PTN5150 Product Description 1 PTN5150 is a small thin low power CC Logic chip supporting the USB Type-C connector application with Configuration Channel (CC) control logic detection and indication functions. The PTN5150 enables USB Type-C connector to be used in both host and device ends of the Type-C cable Category Name 5: Current-Limited Power Switch Product URL 1 https://www.nxp.com/products/power-management/load-switches/usb-pd-and-type-c-current-limited-power-switch:NX5P3290UK Product Description 1 The NX5P3290 includes under-voltage lockout, over-temperature protection, and reverse current protection circuits to automatically isolate the switch terminals when a fault condition occurs. Category Name 6: Secure Product 1 URL 1 A71CH | Plug and Trust for IoT | NXP  Product Description 1 Plug and Trust - The fast, easy way to deploy secure IoT connections Category Name 7: NFC Product 1 URL 1 PN5180 | Full NFC Forum-compliant frontend IC | NXP  Product Description 1 Full NFC Forum-compliant frontend IC Category Name 8: GPIO Expander Product 1 URL 1 PCAL6534 | Level translating GPIO Expander | NXP  Product Description 1 Ultra-low-voltage, level translating, 34-bit I2C-bus/SMBus I/O expander   Category Name 8: NFC smartcard Product 1 URL 1 https://www.nxp.com/products/rfid-nfc/mifare-hf/mifare-desfire/mifare-desfire-ev2:MIFARE_DESFIRE_EV2_2K_8K Product Description 1 Secure, contactless multi-application IC with an enhanced feature set for Smart City applications Related Documentation Document URL Title https://www.nxp.com/docs/en/application-note/AN10439.pdf Wafer-level chip-scale package https://www.nxp.com/docs/en/application-note/AN5322.pdf AN5322, TPMS wheel location introduction and main concepts Training Training URL https://community.nxp.com/docs/DOC-341509 Related Demos from Communities URL Kinetis Microcontrollers  MCUXpresso SDK  MCUXpresso Software and Tools  UAV Speed Control with Kinetis KV5x Cortex-M7 MCU and GD3000 Motor Pre-Drivers    Block Diagrams Smart City

現在のAPK.apk <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> AndroidセンサーフュージョンAPK <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> AndroidセンサーフュージョンAPK センサ・フュージョン

RT10xx optimization for LCD performance.pdf The attached document describes how to optimize LCD display performance on RT10xx platform. The content include RT10xx configuration and Emwin setting with LCD parameters. Products Product Category NXP Part Number URL MCU i.MX RT1060 i.MX RT1060 MCU/Applications Crossover MCU | Arm® Cortex®-M7, 1MB SRAM | NXP  MCU i.MX RT1050 i.MX RT1050 MCU/Applications Crossover MCU| Arm® Cortex-M7, 512KB SRAM | NXP  SDK Software Software Development Kit https://mcuxpresso.nxp.com/en/select    Tools NXP Development Board URL MIMXRT1060-EVK i.MX RT1060 Evaluation Kit | NXP  MIMXRT1050-EVK i.MX RT1050 Evaluation Kit | NXP  Was this helpful to you?

Bootloader utility for MC56F83xxx The MC56F83xxx is the latest DSC family, it integrates new features such as CAN-FD, USB, enhanced DMA, can be used in motor control, switch mode power supply applications. The MC56F83xxx runs code in on-chip flash, so the Bootloader’s main task is to update the internal flash memory with an embedded application firmware image during manufacturing, or at any time during the life of the device. The Bootloader does the provisioning by acting as a slave device, and listening to various peripheral ports where a master can start communication. The Doc describes the procedures to use the bootloader to download application code to flash, for example the hardware connection, generating S-Record file, selecting the S-Record file, the blhost commands, especially, the traps customer may face. General

i.MX Design&Tool Lists Design Check Lists: HW Design Checking List for i.MX6DQSDL HW Design Checking List for i.Mx53 Hardware Design Checklist for i.MX28 HW_Design_Checking_List_for_i.MX6SoloX i.MX6UL Hardware design checklist DDR Design Tool: I.MX53 DDR3 Script Aid imx53 DDR stress tester V0.042 i.Mx6DQSDL DDR3 Script Aid MX6DQP DDR3 Script Aid i.Mx6DQSDL LPDDR2 Script Aid i.Mx6SL LPDDR2 Script Aid i.MX6SX DDR3 Script Aid I.MX6UL DDR3 Script Aid i.MX6UL_LPDDR2_Script_Aid i.MX6ULL_DDR3_Script_Aid  i.MX6ULL_LPDDR2_Script_Aid  MX6SLL_LPDDR2_Script_Aid  MX6SLL_LPDDR3_Script_Aid  i.MX6 DDR Stress Test Tool V1.0.3 i.MX6/7 DDR Stress Test Tool V3.00 i.MX8MSCALE DDR Tool Release  i.MX8M DDR3L register programming aid  i.MX 8/8X Family DDR Tools Release Application Notes: MX_Design_Validation_Guide I.MX6 series USB Certification Guides i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus i.MX 8M | i.MX 8M Mini | i.MX 8M Nano i.MX53 i.MX6_All i.MX6DL i.MX6Dual i.MX6DualPlus6QuadPlus i.MX6Quad i.MX6S i.MX6SL i.MX6SoloX i.MX6UL Re: i.MX Design&Tool Lists Hi LinWang Sorry for late reply. I asked to local FAE and It resolved. Thanks! Ko-hey Re: i.MX Design&Tool Lists Hello Ko-hey, I am not the owner of these two pages and they are in private space for NXP internal only. Please ask your local support team for help. Thanks! Re: i.MX Design&Tool Lists Hi LinWang‌ I got a same error which is commented "Unauthorized" with the following two links. MMDC/DDR Resources Target List for SoC, Modules and Software Resource Kits  Do they need permission now ? Ko-hey Re: i.MX Design&Tool Lists Thanks, got it! On Tue, Aug 2, 2016 at 4:54 AM, LinWang Re: i.MX Design&Tool Lists Hi Joe, I try to move the doc into publish space. You can access it after moderator approve the operation. Re: i.MX Design&Tool Lists Thanks for checking - I get the following error, so my guess is the permissions are wrong, preventing the public from viewing it. I've had others check (from different places in the world), and it is broken from them too. Thanks, Joe Unauthorized Access to this place or content is restricted. If you think this is a mistake, please contact your administrator or the person who directed you here. On Mon, Aug 1, 2016 at 9:27 PM, LinWang Re: i.MX Design&Tool Lists Hello engjoe, The link works fine when I tried just now. Please contact local supporter help if you meet problem to access the link. Re: i.MX Design&Tool Lists LinWang, the link for i.MX6UL_LPDDR2_Script_Aid​ is broken. Can you please post a new one? Thank you. Re: i.MX Design&Tool Lists Hi Brian, Please ask local FAE help. Re: i.MX Design&Tool Lists Nice. But I can't access the HW Design Checking List for i.Mx53.:smileycry: Re: i.MX Design&Tool Lists :smileycool:

16-bit SAR ADC calibration 1. How Calibration works There are three main sub-blocks important in understanding how the Kinetis SAR module works.  There is a capacitive DAC, a comparator, and the SAR engine that controls the module. Of those blocks, the DAC is most susceptible to variations that can cause linearity problems in the SAR. The DAC is architected with three sets of binary weighted capacitors arrayed in banks, as in Figure 1. The capacitors that represent the most significant bits of the SAR (B15:B11) are connected directly to the inputs of the comparator. The next bank of five capacitors (B10:B6) is connected to the top plate of the MSB array through an intentionally oversized scaling capacitor. The final six capacitors that makeup the least significant bits of the SAR (B5:B0) are correspondingly connected to the top plate of the middle bank of capacitors through another scaling capacitor. Figure 1. Arrangement of DAC capacitors Only the MSB capacitor bank is calibrated. Because the first scaling capacitor is intentionally oversized, each of the non-calibrated MSB capacitors will have an effective capacitance too small to yield accurate results. However, because they are always too small, we can measure the amount oferror that each of those capacitors would cause individually, and add that back in to the result. Calibration starts with the smallest of the LSB capacitors, B11. The SAR samples Vrefl on all of the capacitors that are lower-than or equal-to the capacitor under test (CUT), while connecting all of the smaller capacitors to Vrefh. The top plate of all of the MSB capacitors is held at VDDA while this happens. After the sampling phase is complete, the top plates of the MSB capacitors are allowed to float, and the bottom plates of the MSBs not under test are connected to Vrefl. This allows charge to redistribute from the CUT to the smaller capacitors. Finally, an 11 bit SAR algorithm (corresponding with the 11 capacitors that are smaller than the MSB array) is performed which produces a result that indicates the amount of error that the CUT has compared to an ideally sized capacitor. This process is repeated for each of the five MSBs on both the plus side and minus side DACs and the five error values that are reported correspond to the five MSBs accordingly. All of these error values are about the same magnitude, with a unit of 16-bit LSBs. See Figure 2 for an example. Figure 2. Example of calibration on bit 11 The DAC MSB error is cumulative. That is, if bit 11 of the DAC is set, then the error is simply the error of that bit. However if bit 12 of the DAC is set, the total error is equivalent tothe error reported on bit 12, plus the error reported on bit 11. For each MSB the error is calculated as below, where Ex is the error found during the calibration for its corresponding MSB bit: When bit 11 of the DAC is set: CLx0 = E0. When bit 12 of the DAC is set: CLx1 = E0+E1. When bit 13 of the DAC is set: CLx2 = E2 + E1 + 2E0. When bit 14 of the DAC is set: CLx3 = E3 + E2 + 2E1 + 4E0. When bit 15 of the DAC is set: CLx4 = E4 + 2E3 + 4E2 + 8E1 + 16E0 Figure 3. Effect of calibration error on ADC response These are the values that are then placed in each of the CLxx calibration results registers. Figure 3 shows how the errors would accumulate if all of the CLxx registers were set to zero. The offset and gain registers are calculated based on these values as well. Because of this, the gain and offset registers calibrate only for errors internal to the SAR itself. Self calibration does not compensate for board or system level gain or offset issues. 2. Recommended Calibration Procedure From the above description it is evident that the calibration procedure is in effect several consecutive analog to digital conversions. These are susceptible to all of the same sources of error of any ADC conversion. Because what is primarily being measured is the error in the size of the MSB capacitors; the recommendation is to configure the SAR in such a way as to make for the most accurate conversions possible in the environment that the SAR is being calibrated in. Noise is the primary cause of run-to-run variation in this process,so steps should be taken to reduce the impact of noise during the calibration process. Such as: All digital IO should be silent and unnecessary modules should be disabled. The Vrefh should be as stable and high a voltage as possible, since higher Vrefh means larger ADC code widths. An isolated Vrefh pin would be ideal. Lacking that, using an isolated VDDA as the reference would be preferable to using VREFO. The clock used should be as noise free as possible, and less than or equal to 6 MHz. For this purpose the order of desirable clock sources for calibration would be OSC > PLL > FLL > ASYNC The hardware averaging should be set to the maximum 32 samples. The Low Power Conversion bit should be set to 0. The calibration should be done at room temperature. The High Speed Conversion and Sample Time Adder will not have much effect in most situations, and the Diff and Mode bits are completely ignored by the calibration routine. The calibration values should be taken for each instance of the SAR on a chip in the above conditions. They should be stored in nonvolatile memory and then written into their appropriate registers whenever the ADC register values are cleared. In some instances, the system noise present will still cause the calibration routine to exhibit greater than desired run-to-run variation. One rule of thumb would be to repeat calibration several times and look at the CLx0 registers. If the value reported in that register varies by more than three, the following procedure can be implemented. Run the calibration routine several times. Twenty to forty times. Place the value of each of the calibration registers into a corresponding array. Perform a bubble sort on each array and find the median value for each of the calibration registers. Use  these median values as described for typical calibration results. Kinetis E Series MCUs Kinetis EA Series MCUs Kinetis K Series MCUs Kinetis L Series MCUs Kinetis V Series MCUs Kinetis W Series MCUs

Example MPC5643L 2b RAM and 2b FLASH ECC error injection CW210 ******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi bit ECC error in * internal SRAM or FLASH (user must choose it in the option at the end of main * function) and how to handle this error with respect to constraints given by * MPC5643L architecture (ECSM/RGM/FCCU relation and ECC error handling through * reset). The example is only possible to run in internal_FLASH target. Power- * -on-reset is required after downloading the code into MCU's flash. The example * displays notices in the terminal window (setting specified below). No other * external connection is required. * ------------------------------------------------------------------------------ * Test HW:         xPC564xLKIT, PPC5643L Cut3 silicon * Target :         internal_FLASH * Fsys:            120 MHz PLL0 * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Terminal:        19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection:  default * ******************************************************************************** ******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi bit ECC error in * internal SRAM or FLASH (user must choose it in the option at the end of main * function) and how to handle this error with respect to constraints given by * MPC5643L architecture (ECSM/RGM/FCCU relation and ECC error handling through * reset). The example is only possible to run in internal_FLASH target. Power- * -on-reset is required after downloading the code into MCU's flash. The example * displays notices in the terminal window (setting specified below). No other * external connection is required. * ------------------------------------------------------------------------------ * Test HW:         xPC564xLKIT, PPC5643L Cut3 silicon * Target :         internal_FLASH * Fsys:            120 MHz PLL0 * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Terminal:        19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection:  default * ******************************************************************************** General

Example MPC5643L Flash_program_simple CW210 ******************************************************************************** * Detailed Description: * Example show simple flash programming routine. During runtime it changes * content of field of constants 'test' (thus located in internal flash). * Also it shows how to relocate code into RAM a data into FLASH (used linker * command file is MPC5643L_my_sections.lcf and MPC5643L_DEBUG_my_sections.lcf). * * Note: For complex tasks use SSD driver (Freescale site for particular device, * Software&Tools/Run-Time Software/Middleware-Device Drivers * * ------------------------------------------------------------------------------ * Test HW:         xPC564xLKIT, PPC5643L Cut3 silicon * Target :         internal_FLASH, RAM * Fsys:            120 MHz PLL0 * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Terminal:        19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection:  default * ******************************************************************************** ******************************************************************************** * Detailed Description: * Example show simple flash programming routine. During runtime it changes * content of field of constants 'test' (thus located in internal flash). * Also it shows how to relocate code into RAM a data into FLASH (used linker * command file is MPC5643L_my_sections.lcf and MPC5643L_DEBUG_my_sections.lcf). * * Note: For complex tasks use SSD driver (Freescale site for particular device, * Software&Tools/Run-Time Software/Middleware-Device Drivers * * ------------------------------------------------------------------------------ * Test HW:         xPC564xLKIT, PPC5643L Cut3 silicon * Target :         internal_FLASH, RAM * Fsys:            120 MHz PLL0 * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Terminal:        19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection:  default * ******************************************************************************** General

BSP安全维护 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 漏洞监控和修复的最佳实践

CommandLineBootloader.20141030.Alpha.zip <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 20141030 アルファ版を Jiunn.Yang@freescale.com でリリース a) FRDM-KL25ZおよびTWR-K60D100Mをサポートします。 b)Xモデム256と1Kをサポートし、Teraterm、http://ttssh2.sourceforge.jp/ によるテスト <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 20141030 アルファ版を Jiunn.Yang@freescale.com でリリース a) FRDM-KL25ZおよびTWR-K60D100Mをサポートします。 b)Xモデム256と1Kをサポートし、Teraterm、http://ttssh2.sourceforge.jp/ によるテスト 日時:CommandLineBootloader.20141030.Alpha.zip <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> こんにちは、みんな、 これはアルファ版ですので、テストして、問題があればお知らせください。 歓声！

ビデオ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> TAD ツールの使用

HOWTO: Create An ISP Project From Example in S32DS for S32 Platform S32DS contains many example projects from which you can learn how S32DS can be used with the help of the Vision SDK to develop vision applications. The example projects contain generated and hand-written code, which utilize the Vision SDK to demonstrate a workflow using S32DS. In this document, the procedure for creating a project from one of the provided ISP examples through to execution on the EVB is detailed. This project was run using S32DS version 3.2 and VSDK version 1.5.0.   1) Launch S32DS 2) Select 'File -> New -> S32DS Project from Example' 3) Select 'isp_h264dec_single_stream' project    In this particular project, the ISP graph diagram is included. If you wish to view it, go to the Project Explorer panel and expand 'isp_h264dec_single_stream_graph'. Then double click on 'ISP data flow : h264dec_single_stream'. The ISP graph diagram will appear in the editor panel. 4) If not in the C/C++ Perspective, switch over by clicking on the icon showed below (Hovering over the correct icon should display 'C/C++'). The current perspective is displayed on the top bar. 5) Select isp_h264dec_single_stream: A53 in the Project Explorer panel 6) Build project for A53  7) Start a debug session using method as described in HOWTO Create A53 Linux Project in S32DS for Vision, beginning at step 9. 😎 Click Resume  The program takes the input H264 encoded image img_1280x960.h264 located in the /home/root/vsdk/data/common folder on the Linux BSP and outputs it on the display The output image should look like below. New Project Wizard - Project Management and Settings SDKs

BSP 的生命周期维护 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 恩智浦网络研讨会：2020年6月2日

示例_MPC5777C-外部_SRAM-测试-S32DS.Power.2017.R1 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> ******************************************************************************** * Detailed Description: * Application performs basic initialization then it initializes EBI for external * SRAM connected to MPC5777C-516DS and test it by write and read of block of * data. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 3N45H * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  jumper J4 on position 1-2 (choosing CS0) *                  EMIOS1 (PortI P16-0) --> USER_LED_1 (P7-1) to see LED blink ******************************************************************************** Revision History: Ver  Date         Author            Description of Changes 0.1  Jun-26-2017  David Tosenovjan  Initial version 0.2  Oct-13-2017  David Tosenovjan  Lower CLKOUT frequency 0.3  Feb-02-2020  David Tosenovjan  Corrected External_SRAM_MMU_init                                     Ported to S32 design studio *******************************************************************************/ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> ******************************************************************************** * Detailed Description: * Application performs basic initialization then it initializes EBI for external * SRAM connected to MPC5777C-516DS and test it by write and read of block of * data. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 3N45H * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  jumper J4 on position 1-2 (choosing CS0) *                  EMIOS1 (PortI P16-0) --> USER_LED_1 (P7-1) to see LED blink ******************************************************************************** Revision History: Ver  Date         Author            Description of Changes 0.1  Jun-26-2017  David Tosenovjan  Initial version 0.2  Oct-13-2017  David Tosenovjan  Lower CLKOUT frequency 0.3  Feb-02-2020  David Tosenovjan  Corrected External_SRAM_MMU_init                                     Ported to S32 design studio *******************************************************************************/ 概述