CAN TJA1145AT/0Z & TJA1145AT/FD/0Z Essentially different Customer feedback they use CAN TJA1145AT/0Z & TJA1145AT/FD/0Z，It was all used according to the CAN FD function, and there were no problems。Therefore, what is the specific difference between FD and FD in model naming。There are still differences from the specifications, as shown in the figure。Thanks！ Re: CAN TJA1145AT/0Z & TJA1145AT/FD/0Z Essentially different Dear Louis, please refer to the section 7.3.2 in the TJA1145A datasheet. Depending on the CFDC bit setting the  TJA1145AT and the TJA1145AT/FD will behave same (CFDC=0=>error counter increments) or (CFDC=1) the TJA1145AT/FD will ignore the CAN FD frames=>error counter decrements. With Best Regards, Jozef

S32K144 MCU seems died (not working) once CHIPCTL register accessed. I got a HardFault_Handler ISR occurred and the MCU seems died as soon as the chip control register (CHIPCTL) was accessed to set the clock out. It happened in both cases of using an external crystal oscillator or a high-speed internal reference clock (FIRC). 1. Environment a. Windows 11 b. S32 Design Studio for ARM version 2.2 c. MCU of the target: S32K144F512M15 2. Test procedure a. clock initialization completed successfully for both cases of using SOSC_CLK and FIRC_CLK. b. working as expected for blinking LED operation with PORT and RTC control without(removing) handling CLOCK OUT function. 3. Problem a. got the HardFault_Handler ISR once accessed the CHIPCTRL register, and MCU not working (exactly endless looping in startup code) ever after when executed a function to handle CLOCK OUT (pin #24 of S32K144512M15 100pin LQFP) b. I got the same MCU problem couple of times while doing the test, and needed to replace the MCU so that my target worked again. 4. My code to access the CHIPCTRL void CLK_clkout() {     // Configure SCG_CLKOUT     // SCG->CLKOUTCNFG = 0x06000000; // Select SPLL_CLK as source of SCG_CLKOUT     SCG->CLKOUTCNFG = 0x03000000; // CLKOUTCNFG[24..27] : Select source of SCG_CLKOUT                                                                   // 0b0001 = SOSC_CLK                                                                   // 0b0011 = FIRC_CLK                                                                   // 0b0110 = SPLL_CLK     //Configure CLKOUT source and divider     SIM->CHIPCTL &= ~  (SIM_CHIPCTL_CLKOUTEN_MASK|SIM_CHIPCTL_CLKOUTDIV_MASK|SIM_CHIPCTL_CLKOUTSEL_MASK); //Clear the relevant fields     SIM->CHIPCTL = SIM_CHIPCTL_CLKOUTSEL(0) //CLKOUT source is SCG_CLKOUT | SIM_CHIPCTL_CLKOUTDIV(0) //CLKOUT is the source signal divided by 1 & ~SIM_CHIPCTL_CLKOUTEN(1); //CLKOUT signal is enabled (0b1) or disabled (0b0, 0 MHz). } Remarks) Problem was occurred for any clock sources and either CLKOUT signal enabled  or disabled. Any comment/recommendation would be appreciated. Thank you.  Re: S32K144 MCU seems died (not working) once CHIPCTL register accessed. Hi@Senlent, I got the clock out issue resolved thanks to your help. However the CHIPCTL register still has not been updated when I stopped at a breakpoint after setting the values to generate CLKOUT signal as expected. But I verified that values in the chip control register updated correctly as attached. Considering the endianness, the CHIPCTL register value= 0x00300D80 i.e. CLKOUTEN= 1, CLOCKOUTDIV= 5, CLKOUTSEL= 8 that is correct.  This ticket would be closed. Thank you so much again. Re: S32K144 MCU seems died (not working) once CHIPCTL register accessed. Hi@uzza9 I made a demo for your reference and i see no problem with the code i provided before. you should stop first then you may see the register value. test result, output clock is 1MHz. Re: S32K144 MCU seems died (not working) once CHIPCTL register accessed. Hi@Senlent, Thank you for your point to the correct way. The  good thing is that no more MCU seems died (not working) thanks to your help. However still CLOCKOUT not working, my observation on status of CHIPCTL register somewhat interesting while running the code you provided. As the attached, CHIPCTL register kept 0x00300000 (i.e. No SRAML retention) even though I was going through step by step on the code. Even the register does not change accordingly when I set CLKOUTDIV(1). I think I should see the CLKOUT signal at the pin of the MCU once the CLKOUT code executed while system clock working. Can you see the register changed accordingly as well as the CLKOUT signal at the pin? Minor remark; I tried with following code I revised according to your point as well as the code you provided. Both did not work. void clkout() { // Configure SCG_CLKOUT // SCG->CLKOUTCNFG = 0x06000000; // Select SPLL_CLK as source of SCG_CLKOUT SCG->CLKOUTCNFG = 0x03000000; // CLKOUTCNFG[24..27] : Select source of SCG_CLKOUT // 0b0001 = SOSC_CLK // 0b0011 = FIRC_CLK // 0b0110 = SPLL_CLK uint32_t regValue; /* CLKOUTEN should be first cleared and then execute sequence */ SIM->CHIPCTL &= ~SIM_CHIPCTL_CLKOUTEN_MASK; regValue = SIM->CHIPCTL; regValue &= ~( SIM_CHIPCTL_CLKOUTEN_MASK | SIM_CHIPCTL_CLKOUTDIV_MASK | SIM_CHIPCTL_CLKOUTSEL_MASK ); /* regValue |= SIM_CHIPCTL_CLKOUTEN(1); regValue |= SIM_CHIPCTL_CLKOUTSEL(0); regValue |= SIM_CHIPCTL_CLKOUTDIV(0); SIM->CHIPCTL = regValue; */ // SIM->CHIPCTL |= SIM_CHIPCTL_CLKOUTEN(1); SIM->CHIPCTL |= SIM_CHIPCTL_CLKOUTSEL(0); SIM->CHIPCTL |= SIM_CHIPCTL_CLKOUTDIV(0); SIM->CHIPCTL |= SIM_CHIPCTL_CLKOUTEN(1); } Re: S32K144 MCU seems died (not working) once CHIPCTL register accessed. Hi@uzza9 When setting the CHIPCTL register, be sure to configure it in the order given in the data sheet: For your reference (From our SDK(RTM)) SCG->CLKOUTCNFG = 0x03000000; uint32_t regValue; /* CLKOUTEN should be first cleared and then execute sequence */ SIM->CHIPCTL &= ~SIM_CHIPCTL_CLKOUTEN_MASK; regValue = SIM->CHIPCTL; regValue &= ~( SIM_CHIPCTL_CLKOUTEN_MASK | SIM_CHIPCTL_CLKOUTDIV_MASK | SIM_CHIPCTL_CLKOUTSEL_MASK ); regValue |= SIM_CHIPCTL_CLKOUTEN(1); regValue |= SIM_CHIPCTL_CLKOUTSEL(0); regValue |= SIM_CHIPCTL_CLKOUTDIV(0); SIM->CHIPCTL = regValue; "b. I got the same MCU problem couple of times while doing the test, and needed to replace the MCU so that my target worked again." I reproduced your problem and I was able to restore the MCU to normal state by using the “mass erase” command

LX2160 two 1-Rank DDR4 DIMM modules with one memory controller (MC1) Hello NXP, We have a custom board with LX2160A CPU. We want to use two 1-Rank DDR4 DIMM modules with one memory controller (MC1), but we are getting error "Invalid cs_in_use value" during boot and only 8GB of 16GB of RAM are available after boot. We also tried to boot with two 2-Rank DIMMs in MC1, there were no errors and all 16GB of RAM were available after boot. The error seems to be coming from findrank() function, where cs_in_use value 0x5 (CS2+CS0) seems to be unsupported. Is configuration with two 1-Rank modules per one MC valid? Or maybe software updates are available that add support for this configuration? DIMM modules that we used: Innodisk M4C0-8GS1LCEM, 8GB, 3200 MT/S, 1-Rank, ECC. LX2160A clocks: CPU 2200, PLAT 700, DDR 1800. Software version: LSDK-21.08. Here is full boot log (attached boot-log.txt) with debug level traces enabled, DDR_DEBUG and DDR_PHY_DEBUG options are also enabled. Re: LX2160 two 1-Rank DDR4 DIMM modules with one memory controller (MC1) Using two 1-rank DDR4 DIMM on LX2160A may be possible, but it has not be validated and we don't have supported configuration. You may try it and see if you can get it to work using the QCVS tool. but we cannot guarantee it because it is not a supported configuration. Re: LX2160 two 1-Rank DDR4 DIMM modules with one memory controller (MC1) Yes, we already used QCVS DDR tool in Code Warrior, it allowed us to improve DDR eye diagrams. DDR memory seems to work stable after these adjustments. The problem is that if we use two 1R DIMM modules in one MC, we get an "Invalid cs_in_use value" error during boot and only one of the two 1R modules seems to be active. If we use two 2R modules in one MC, there are no problems or errors during boot and both modules are active. We want to know if two 1R DIMM modules on one MC is a valid configuration or not. Re: LX2160 two 1-Rank DDR4 DIMM modules with one memory controller (MC1) Please confirm the QCVS has been done. QCVS_DDR_User_Guide Thanks

私のIDEバージョンはS32DS 3.5ですが、S32K1XX RTM 4.0.2をインストールするにはどうすればよいですか? タイトルが言ったように、私のプロジェクトはS32K1xx RTM4.0.2に基づいていますが、今はSDKリソースを見つけるのが難しいです。 History SDKを簡単に見つける方法を教えてください。

How to disable MMU for arm64 platforms like imx8 series I tried to disable MMU before control gives to Linux kernel. So the flow is, U-boot Spl -> ATF -> U-boot -> Bootloader -> Payload -> Linux kernel End of payload we give control to Linux kernel. Before giving control kernel we need to disable MMU. I use the below code to disable MMU and the results, kernel gives warning and hang. // Disable MMU mrs x0, sctlr_el1 // Read the System Control Register (EL1) and x0, x0, #1 // Clear the M (MMU enable) bit msr sctlr_el1, x0 // Write back the modified value to SCTLR_EL1 isb dsb sy ret   Any suggestion on this ? Re: How to disable MMU for arm64 platforms like imx8 series Hello, You can disable from kernel menu config or  variable CONFIG_MMU (default value y)in the Kconfig file. Regards

MC56F8257のサンプルプログラムはどこにありますか? こんにちは、MC56F82xxシリーズのガイドと例はどこにありますか? Re:MC56F8257のサンプルプログラムはどこにありますか? ありがとう、相棒!

i.mxrt1170: CAN Bus trace impedance controller Hi NXP team, we are designing a CAN FD Port (RT1170 +TJA1057BT/0Z) can you tell us is it necessary to control (CANH/CANL) trace impedance as differential signal? And if yes, how many Ohm (120Ohm?) to control or like Single-Ended Signal (50Ohm) is enough Thanks, Huy i.MXRT 105x i.MXRT 106x Re: i.mxrt1170: CAN Bus trace impedance controller Hi Gavin, Thank for your reply We got it Thanks, Huy Re: i.mxrt1170: CAN Bus trace impedance controller Hi @haryanl , Thanks for your interest in NXP MIMXRT series! Yes, and the target impedance is 120 ohm. The schematic you provided is referenced to the correct section. Best regards, Gavin

S32K144 Debugging pins are disabled. How to recover the board? I am using NXP S32K144 IC and while creating its demo project on S32 Design Studio via Autosar MCAL layer during the configuring of Port Driver SWD pins: PTA4: JTAG SWD PTA5: System Reset PTA10: JTAG TDO PTC5: JTAG TDI PTC4: JTAG CLK These are configured as UnusedPort pins and theri debugging fucntionality is removed. Now when i am trying to program them via Jlink, i am getting this error: SWD selected. Executing JTAG -> SWD switching sequence. - Connect Under Reset - SWD selected. Executing JTAG -> SWD switching sequence. - Communication error while accessing MDM-AP. - Connect Under Reset - InitTarget() end - Took 377ms - InitTarget() start - SWD selected. Executing JTAG -> SWD switching sequence. - Connect Under Reset - SWD selected. Executing JTAG -> SWD switching sequence. - Communication error while accessing MDM-AP. - Connect Under Reset - InitTarget() end - Took 374ms - ERROR: Failed to connect. Could not establish a connection to target. - ERROR: Connect failed What should i do now? Is their any way i can recover the chip? or is my chip and board damaged now? Isnt their any other way to get it back? Will flashing the code in it via uart using rappid bootloader, solve the problem? Re: S32K144 Debugging pins are disabled. How to recover the board? This is a completely different topic, it has nothing to do with the SWD/JTAG/Reset_b pins discussed in this thread. BR, Daniel Re: S32K144 Debugging pins are disabled. How to recover the board? So is their any way on how to recover the MCU's which are bricket by CSEc. With PeMicro and Lauterback, they will not get recover via that also? Re: S32K144 Debugging pins are disabled. How to recover the board? No, it cannot recover the MCUs bricked by the CSEc engine. Refer to https://wiki.segger.com/J-Link_Commander or contact SEGGER support, J-link is not an NXP product. Regards, Daniel Re: S32K144 Debugging pins are disabled. How to recover the board? Via this method, the chips which are brick because of CSEc peripheral of S32K144 can those also be recovered? And in the shared link for Jlink, it says to execute halt commands. What Jlink Halt are their which needs to be executed. Can you guide us on that too. Thanks and Regards Kunal Gupta Re: S32K144 Debugging pins are disabled. How to recover the board? Hi @Kunal_Gettobyte, The pins are configured for SWD/JTAG/Reset_b after Power-on reset until they are reconfigured by the application. The debugger will have to halt the execution in this short window. PE Micro have Kinetis_Recovery_Utility.exe With Lauterbach we can use: system.CPU S32K144 wait state.power() system.attach Regarding J-link, this should work: https://wiki.rdu.im/_pages/Notes/HOWTOs/howto-recover-swd-after-disabled-with-jlink.html Regards, Daniel

S32G399A - System timer module frequency Good morning, I have an S32G399-RDB3 board with a setup derived from the GoldVIP package. The M7 binary and the Linux kernel images were changed, but the bootloader configuration is practically the same of the original configuration. I'm using one of the system timer instances to collect measurements, and I wanted to ask whether there is a practical way to read the STM frequency without following the entire chain of clock signals. Thank you. GoldVIP Re: S32G399A - System timer module frequency Perfect, thank you for your help. Re: S32G399A - System timer module frequency hi，Matteo_Zini Thank you for your reply. If you want to know the exact STM timer time, you must know that the XBAR_DIV3_CLK default is 133.33Mhz, the frequency division factor CPS and CMP values. BR Joey Re: S32G399A - System timer module frequency I'm using Linux on the Cortex-A cores, so I'm not sure how to configure it. Anyway, I would just need to understand the frequency to transform the ticks into seconds, not to set it to any specific value. Thank you. Re: S32G399A - System timer module frequency hi,Matteo_Zini Thank you for your reply. There are multiple possible sources of the XBAR_DIV3_CLK clock, so you need to configure the same value of XBAR_DIV3_CLK for the M core and A core, to avoid conflicts. BR Joey Re: S32G399A - System timer module frequency Hi, thank you for the reply. Because for example if you need to do it at runtime, there are multiple possible sources of the XBAR_DIV3_CLK clock and reconstructing the full chain is not trivial. Re: S32G399A - System timer module frequency hi，Matteo_Zini Thank you for contacting us. May I ask why you want to read the STM frequency without following the entire chain of clock signals? In addition, You can refer to the attachment to check the clock of M core STM.

Could not generate UART configuration for S32K388 Hardware: S32K388 Issue Description: I am facing issue during generation of UART config. It's complaining saying LPUART4 and LPUART12 are using same source channel of DMA Method and asking me to configure only one of LPUART4 or LPUART12. But for my application, I need both of the channels to be configured. I made sure that I am using different DMA channels when I configured Rm and Mcl. Is this error with Tresos generator? If not, please help me with identifying the problem here. Thanks. Re: Could not generate UART configuration for S32K388 Hello @Gnanesh, This is a HW limitation. There are many peripherals but not many DMAMUX slots, therefore, some of the DMAMUX sources are routed to more peripharals. Like source 43: That means that if either of the LPUARTs received data, it would trigger both DMA channels and both LPUART DATA registers would be read by the DMA at the same time. Regards, Daniel

S32K311 EMIOS GPT Hi, I am trying to configure timer for 500ms usin EMIOS GPT. How to calculate the compareValue ? Is there any documents available? Re: S32K311 EMIOS GPT Hi @_Leo_ , Thank you for your support. Small doubt, how to derive this 1s -> 120MHz (120,000,000 ticks)? Re: S32K311 EMIOS GPT Hi, Thank you so much for your interest in our products and for using our community. There is the S32K3 RTD Training eMIOS presentation (attached). On the other hand, for GPT frequency of 2Hz (500ms) with eMIOS clock frequency of 120MHz you need 60,000,000 ticks: 1s -> 120MHz (120,000,000 ticks) 2Hz = (1/2)s ->120,000,000 *(1/2) = 60,000,000 ticks But max ticks are 65,534 (16 bits). Using Global Prescaler = 256 (in Emios_Mcl_Ip driver) and Gpt Emios Prescaler = 15 (in Emios_Gpt driver): 1s -> 120MHz/256/15 (31,250 ticks) 2Hz = (1/2)s ->31,250 *(1/2) = 15,625 ticks Please find attached project. This example implement a General Purpose Timer (GPT) with eMIOS (CH_0), such timer generates an interrupt when it reaches to its defined compare value and its respective notification function toggles the on-board blue LED (PTB8). S32DS 3.6 + RTD 5.0.0 (S32K31XEVB-Q100) Hope it helps you. Have a nice day!    

S32G399A STM issue Hi everyone, I'm facing an issue with the STM1 timer. I've configured two counters: Counter_1 running at 1ms for STM0 (CH0) and Counter_2 running at 1us for STM1 (CH0). The STM0 counter works fine, but STM1 is not updating as expected. Instead of updating every 1us, it updates every 15-25s.  Configuration Details: Clock for both STM0 and STM1: 133.33333 MHz Prescaler (PSC) for both: 1 Compare values: 0x208D5 for 1ms (STM0) and 0x85 for 1us (STM1) Interrupt priority: 4 for STM0, 5 for STM1 Re: S32G399A STM issue hi,asj Thank you for your reply. According to the timer's PSC and clock frequency, it is theoretically possible to achieve 1us, if you doubt the reason for performance, you can try to set STM1 larger time, such as 100us or 2ms. BR Joey Re: S32G399A STM issue Hi Joey, Sorry for the late reply. Yes, I'm doing that. My doubt now, is whether a time period of 1us is feasible. This means 1000000 interrupts per second. So, it might lead to a runtime problem. Could you shed some light on this? BR asj Re: S32G399A STM issue hi,asj Sorry for replying so late. Did you try setting Freeze mode to FALSE? Additionally, after the channel interrupt has been handled, clear the channel interrupt flag (CIF). BR Joey Re: S32G399A STM issue Hi Joey, Yes, I am. The CNT value for STM0 (1ms) continuously updates every 1ms, upon reaching CMP value (IRQ assertion is happening properly). But for STM1 (1us), the CMP value only updates after CNT value falls over from FFFFFFFF to 00000000 and then matches the CMP value (IRQ assertion is improper). So, it takes 10-15s for my counter to update its value. Thanks, asj Re: S32G399A STM issue hi,asj Are you using STM0 and STM1 in debug mode, and if so, check to see if the value of CNT reaches the comparison value to enter the interrupt. Also, try setting Freeze mode to FALSE. BR Joey Re: S32G399A STM issue Okay, I can do that, but the thing is if I'm using them both for 1ms, they work. So that's why I had the doubt. Anyways, I'll do it and let you know Do let me know if you find anything from the code Re: S32G399A STM issue hi,asj Thank you for your information. I will try to look at the code for you and find the problem. In addition, The second problem is that I suggest that you do not apply STM0 and only use STM1 to check whether STM1 itself is configured incorrectly. If STM1 works well alone, you should focus on finding configuration problems between the two STMS when they are used. BR Joey Re: S32G399A STM issue This is my STM configuration: static const Stm_Prv_InstanceConfig_tst Stm_Cfg_PbInstanceConfInirba_Stm_Config_acst[STM_CFG_PB_NUMBER_OF_STM_INSTANCES] = { /* STM peripheral instance*/ /* Freeze mode */ /* Prescaler value(range 1 to 256) */ /* Instance configuration for instance STM0*/ { STM_CFG_STM0_INSTANCE, // STM peripheral instance TRUE, // Freeze mode 1, // Prescale value(range 1 to 256) }, /* Instance configuration for instance STM1*/ { STM_CFG_STM1_INSTANCE, // STM peripheral instance TRUE, // Freeze mode 1, // Prescale value(range 1 to 256) }, }; static const Stm_GptChannelConfig_tst Stm_Cfg_GptPbChannelConfigInirba_Stm_Config_acst[STM_CFG_GPT_NUMBER_OF_LOGIC_STM_CHANNELS] = { /* Instance of the STM STM hardware channel */ /* peripheral, STM_REG_STMN_CHm */ /* m = 0, 1, 2, 3 { STM_CFG_STM0_INSTANCE, STM_CFG_STMN_CH0, }, { STM_CFG_STM1_INSTANCE, STM_CFG_STMN_CH0, }, }; This is how I'm setting the compare value: Stm_StartTimer((uint8)  RBA_STM_CFG_STM0_INSTANCE,                           (uint8)  RBA_STM_CFG_STMN_CH0,                           (uint32) 0x208D5);                   // 1ms     //Rework OS timer clock value         // Init OS system timer - STM1 and CH0 Stm_StartTimer((uint8)  RBA_STM_CFG_STM1_INSTANCE,                          (uint8)  RBA_STM_CFG_STMN_CH0,                           (uint32) 0x85);                   // 1us Stm_StartTimer function does the following: /* Read the current counter value */      Stm_Prv_CounterStartValue_au32[HwTimerInstance_u8][HwTimerChannel_u8]= STM_PRV_REG_CNT((HwTimerInstance_u8));      /* Load the compare value,which is the sum of current counter value and timeout value */      STM_PRV_REG_CMP((HwTimerInstance_u8), (HwTimerChannel_u8)) = (uint32)(TimeOutValue_u32+Stm_Prv_CounterStartValue_au32[HwTimerInstance_u8][HwTimerChannel_u8]);      /* Store the timeout value */      Stm_Prv_TimeoutValue_au32[HwTimerInstance_u8][HwTimerChannel_u8]=TimeOutValue_u32;      /* Enable the channel */      STM_PRV_REG_STMCCR_CEN_TIMER_CH_ENABLED((HwTimerInstance_u8), (HwTimerChannel_u8)); The logic for updation of CMP value: /* store current compare value */     Stm_cmp_value_u32=STM_PRV_REG_CMP((HwTimerInstance_u8), (HwTimerChannel_u8));     /* Set the compare value */     STM_PRV_REG_CMP((HwTimerInstance_u8), (HwTimerChannel_u8))=(uint32)(Stm_cmp_value_u32 + Stm_Prv_TimeoutValue_au32[HwTimerInstance_u8][HwTimerChannel_u8]); } And as for the second question, I'm trying to use both STM0 and STM1 for different time intervals, to implement counters for my usecase. Re: S32G399A STM issue Hi，asj Thank you for contacting us. Could you share more information about your code? For example, how do you configure your STM? In addition, is it normal only to use the STM1? BR Joey Re: S32G399A STM issue These are my ISRs where I set the CMP value by adding a "timeout value" (0x85 for 1us), and clear the interrupt flag, these are done inside "Handler": ISR(IsrSTM0) {     Handler((uint8) STM_CFG_STM0_INSTANCE, (uint8) STM_CFG_STMN_CH0);     Os_IncrementCounter_Counter_1();        } ISR(IsrSTM1) {     Handler((uint8) STM_CFG_STM1_INSTANCE, (uint8) STM_CFG_STMN_CH0);     Os_IncrementCounter_Counter_2(); }

i.mx95 lvds HI NXP Teams I am evaluating the I.MX95 for multi-camera and multi-display applications. Since two sets of MIPI-CSI are required simultaneously, DSI cannot be used for the display. I would like to know if the two 1x4 LVDS ports can output different display information separately? What is the supported bitrate and resolution? poyuan Graphics & Display Re: i.mx95 lvds Hello, Yes, the i.MX95 2x 4-lane LVDS display interface capable of 1080p60 resolution. Best regards/Saludos, Aldo. Re: i.mx95 lvds I understand the current status of the I.MX95. Can the two BOE WXGA LVDS panels on the EVK output different information? If I create my own adapter, can it output 1080P, 30FPS information? Re: i.mx95 lvds Hello, Please note that i.MX95 is still in pre-production stage so all information and specifications herein are subject to change without notice. I.MX95 is capable of a 2x 4-lane or 1x 8-lane LVDS display interface capable of 1080p60 resolution. On the EVK there is 2 combinations available either two single-channel LVDS-to-HDMI converter or two BOE WXGA LVDS panel. Best regards/Saludos, Aldo.

S32DS IPCF config When I use S32DS to test IPCF M7,before I update code where can I config IPCF info?Like set address,etc.Thanks Re: S32DS IPCF config Hi, This information is provided under Config Tools, inside the Peripherals tab: Please, let us know.

S32K344 resets every three days or RTC system clock returns to initial value every three days (S32K344) I implemented a function where the RTC system clock was set to an initial value (2025-3-11 15:25:0), and then the current system time was obtained every 0.5 seconds and stored on the SD card. I tested continuously for 7 days, but after 7 days, I found that the logs in the SD card would return to the initial value of 2025-3-11 15:25:0 every time it reached [2025-3-13, 4:41:57]. Is it because the system reset or is it just an issue with RTC? Re: S32K344 resets every three days or RTC system clock returns to initial value every three days I have sent you the code via private message. Re: S32K344 resets every three days or RTC system clock returns to initial value every three days My code size exceeds 25MB, is there any other way to send it to you? Re: S32K344 resets every three days or RTC system clock returns to initial value every three days Hi @SCoder41, Just from the log, I am unable to pinpoint if the issue is mainly the RTC or the MCU. Could you share the code (either here, or by a private message). If not, could you share exactly what the code does?  Also, if the reset source is not a SW reset, (i.e. hardware reset), the counter value will be reset. You must configure either SIRC or SXOSC, and perform SW reset to avoid resetting the counter: Solved: Does the S32K312 RTC support system time keeping at reset? - NXP Community Best regards, Julián

iMX8QM Dual MIPI-DSI 1920x1080p@60 with DS90UB941 Serializer Hello, I have a custom board with a iMX8QM, and need to use a dual link MIPI-DSI for a 1920x1080p@60 LCD screen.  How should the device tree be structured to use two DSI ports for a single LCD panel?  The DS90UB941 Serializer accepts even data on channel 1 and odd data on channel 2.  I've tried structuring my device tree as shown below, but I get DRM errors and the video device is never created.  If I put the panel inside the MIPI node the errors go away, but that seems to only work for single-channel DSI.  How should the device tree be structured to support dual-channel DSI for a LCD? panel1: panel1 { #address-cells = <1>; #size-cells = <0>; status = "okay"; compatible = "raydium,rm67191"; reg = <0>; dsi-lanes = <4>; video-mode = <2>; width-mm = <292>; height-mm = <109>; port@0 { reg = <0>; panel1_input: endpoint { remote-endpoint = <&mipi0_out>; }; }; port@1 { reg = <1>; panel1_input2: endpoint { remote-endpoint = <&mipi1_out>; }; }; }; &mipi0_dphy { status = "okay"; }; &mipi1_dphy { status = "okay"; }; &mipi0_dsi_host { status = "okay"; fsl,clock-drop-level = <2>; ports { port@1 { reg = <1>; mipi0_out: endpoint { remote-endpoint = <&panel1_input>; }; }; }; }; &mipi1_dsi_host { status = "okay"; fsl,clock-drop-level = <2>; ports { port@1 { reg = <1>; mipi1_out: endpoint { remote-endpoint = <&panel1_input2>; }; }; }; }; Re: iMX8QM Dual MIPI-DSI 1920x1080p@60 with DS90UB941 Serializer Hi @joanxie, I'm connecting to the DS90UB941 via I2C and setting the necessary registers in the device tree.  I was under the impression that I would need to output even data on one DSI channel and odd data on the second DSI channel, but after talking with TI it turns out that I can supply a single channel DSI as you suggested and the serializer will automatically adjust based on the PCLK frequency.  Therefore, I think this topic can be closed.  Thank you! Re: iMX8QM Dual MIPI-DSI 1920x1080p@60 with DS90UB941 Serializer how do you connect DS90UB941? I don't find you set this in the dts file, and one mipi dsi can support 148Mhz, why do you need to use dual mipi dsi? and you couldn't combine dual mipi dsi into one to support display Re: iMX8QM Dual MIPI-DSI 1920x1080p@60 with DS90UB941 Serializer Hi @joanxie, yes that is true, but the max pixel clock the TI DS90UB941 serializer can support is 105MHz, so it requires using two DSI channels to support up to 210MHz pixel clock.  For 1920x1080p@60 the pixel clock required is 147.5MHz, so that is why I must split it into two DSI channels. How should the device tree be structured to support this? Re: iMX8QM Dual MIPI-DSI 1920x1080p@60 with DS90UB941 Serializer why do you need to set as this? one mipi dsi can support 1080p@60 already， why do you need to connect with 2 mipi dsi interface?

Program not starting after power on Hi, Kind of a stupid question, but I can seem to find why this doesn't work. I am using a S32K144W. When debugging everything works fine and I can develop my application. However, when I disconnect the debugger (JLink) and power cycle my board, nothing happens. Pressing the reset button doesn't work. The application doesn't start. When I attach my debugger and start the gdb server, the application does run when pressing the reset button. Can you provide any pointer to why this is and how to solve this problem? Thanks! Re: Program not starting after power on Hi @Senlent , Thanks for your reply. After some more testing the issue seemed to be the fact that I went to VLPS power mode. No idea why it works when the debugging is connected. Re: Program not starting after power on Hi@peacefulcarrot I have encountered some similar problems, and the reason for the failure was that the clock did not run properly.You can check if there is any problem with the clock configuration

s32k118 CAN Rx中断 大家好， 我正在使用 s32k118 MCU 并且需要与 CAN 总线连接。我一直使用 CAN_Receive() 函数每 100 毫秒轮询一次 CAN 总线，以从总线中检索任何消息，但不幸的是，我确实错过了很多消息，因为每 100 毫秒总线上就会出现多条消息。 我的最终目标是将所有接收到的消息异步添加到 CAN 消息队列中，以便我可以定期解析这些消息。我希望通过 CAN Rx 中断来实现这一点，只要 MCU 检测到总线上的消息，就会触发该中断。不幸的是，我无法设置这样的 ISR。 我尝试在 CAN0_ORed_0_31_MB_IRQn IRQ 上使用 interrupt_manager 组件设置 ISR。但似乎只有在我调用 main() 函数中的 CAN_Receive()后我的 ISR 才会被触发。这不符合我的要求，因为我希望在 ISR 中专门使用 CAN_Receive() 函数。此外，在触发一次之后，代码似乎陷入不断重复调用 ISR 的状态。 我尝试使用 CAN_InstallEventCallback() 安装回调函数，但同样，只有在调用 CAN_Receive() 或 CAN_Send()后才会调用回调函数。所以，再次看来，我似乎不能依靠回调来捕获来自总线的所有消息。 最后，我使用了 Rx FIFO 功能，该功能确实成功地将所有消息以缓冲区格式添加到邮箱 0。这就是我需要的...除了最多 6 条消息。 我预计一次需要缓冲大约 16 条消息。 为了说明我在轮询、ISR 和回调方面遇到的问题，我附加了一个“CAN_Example”项目。希望它有助于进一步澄清问题。 我如何完成这项任务，即缓冲传入的 CAN 消息以供将来解析？ 回复：s32k118 CAN Rx中断 谢谢，问题解决了！ 似乎我错过的关键点是在每个邮箱上至少调用一次FLEXCAN_DRV_Receive()、 FLEXCAN_DRV_RxFifo() 或 CAN_Receive()，以使回调正常工作。 回复：s32k118 CAN Rx中断 你好@ArushThomas 您可以参考下面链接中的演示，其中展示了如何使用 MB 或 FIFO 中断接收或传输 CAN 帧。 https://community.nxp.com/t5/S32K-Knowledge-Base/S32K1xx-FlexCAN-Mask-Setting-Demo/ta-p/1519753

SNVS LP battery fail detection I'm trying to get the recovery from power fail routines for my new application up and running and I am finding the SNVS LP documentation frustrating. Obviously, I need to know if the RTC value is valid before I decide to write a default value, and I look to the Digital Low-Voltage Detector for this purpose. (I.MX RT1160 reference manual, page 2020). Configuring the reference value for LPLVDR is straightforward, but I am not happy about the references to the LP status register. According to the manual we should clear the low voltage event in this register after setting LPLVDR, yet there is no record of where this bit is in the register. Most bits are unidentified and marked as reserved. From what I can see, this situation is the same for other devices using the SNVS module.  Anyway, if we look into the SNVS_LP_Init() routine in the SDK, the implication is that the low voltage event is bit 8, as defined by SNVS_LPSR_LVD_MASK. But despite what the manual states it is set on initialisation, not cleared. And there is no function or macro to check for a valid state at power up, so what is it we are looking for to know if the battery has failed? Should it remain set after initialisation? Do I just ignore it and check LPLVDR directly? I could just see how it seems to work, but I really need to understand how NXP intended it to work so I can make sure my application is reliable. Regards. Sacha. Re: SNVS LP battery fail detection Thanks Edwin, I have requested access to this documentation. To be fair to NXP, there is a note in the reference manual stating that information on security related bit fields is available in the security reference manual. I just don't see why the SNVS reset state bit would be classed as secure. Besides, it would still be nice to have a macro in the SDK to simply check this state. Regards. Sacha. Re: SNVS LP battery fail detection Hi @Sacha, Please look for a better description of the SNVS registers under the Security Reference Manual, which can be downloaded here (the file is the same for both the RT1160 and RT1170): That said, you will see the SRM states that this bit is 1 on reset, not cleared. After initialization, this bit is cleared with the SNVS_LPSR_LVD_MASK: BR, Edwin. Re: SNVS LP battery fail detection Sorry. I meant bit 3, not bit 8. But my comments/ questions still stand.

Running LIN Demo and Free master together possible? I want to use the LIN demo example and use it to demonstrate on Freemaster, I just got to know that both things use the same LPUART peripheral that inst 2. what to do? Re: Running LIN Demo and Free master together possible? Hi, Thank you so much for your interest in our products and for using our community. For your previous tickets, I assume that you are using S32K144EVB. If not please tell me. In S32K144EVB, LIN Phy is connected to LPUART2, while OpenSDA is connected to LPUART1, the last one is commonly used to connect to FreeMASTER thought the Micro USB connector. On the other hand, you can customize SW to connect FreeMASTER to any LPUART instance or even CAN. Additionally, you can customize your HW to connect LIN Phy to any LPUART instance. Hope it helps you. Have a nice day!