i.MX RT1170 における GPIO 命名の違い（「gpio_mux_io」と「gpio_io」）の説明 こんにちは、 i.MX RT1170 の設定ツールで、GPIO 信号の命名がポート番号によって異なることに気付きました。 GPIOポート1～6の信号は「 gpio_mux_io 」とラベル付けされ、GPIOポート7～13の信号は「 gpio_io 」とラベル付けされます。 この命名法の違いの理由を明確にしていただけますか? この区別は非常に具体的であり、これらの GPIO グループ間に根本的なアーキテクチャ上または機能上の違いがある可能性があることを示唆しています。 技術的な根拠を理解することで、特に電気的特性、MUX 機能、または低電力動作がマターになるデザインの場合、GPIO ポート間で信号を割り当てるときに、より情報に基づいた決定を下すことができます。 特に知りたいのは、以下の点です。 GPIO1～GPIO6とGPIO7～GPIO13が異なるI/Oサブシステムまたはドメインに属しているかどうか 2つのグループがMUXの柔軟性、パッド制御機能、またはデフォルト機能に関して異なる場合 あるグループからピンを選択する場合と他のグループからピンを選択する場合の実用的な設計上の考慮事項や制限があるかどうか この違いを説明するドキュメント参照もいただければ幸いです。 サポートありがとうございます。 よろしくお願いします Re: Clarification on GPIO naming difference (“gpio_mux_io” vs “gpio_io”) on i.MX RT1170 こんにちは@mastupristi 、 これらの GPIO グループ間の主な違いは、各ポートが属する電源ドメインです。これは第2.1.2章の図でより明確に確認できます。RM では「システム バス ダイアグラム」というタイトルです。この図では、ポート 1 ～ 6 は WAKEUPMIX ドメインにあり、ポート GPIO 7 ～ 12 は LPSRMIX ドメインにあり、GPIO 13 は SNVSMIX ドメインの一部です。 さらに、各 GPIO ピンは異なる機能と代替構成をサポートします。RM の第 12.4 章「メモリ マップとレジスタ定義」も確認することを強くお勧めします。各ピンに使用可能なオプションが詳細に説明されています。 GPIO ピンの電気的仕様と制限については、データシートのセクション 4.3「I/O パラメータ」を参照してください。 最後に、設計プロセスをサポートできるハードウェア設計ガイドラインドキュメントもあります。このドキュメントの第 8 章「未使用ピン」には、未使用ピンの処理に関する推奨事項が記載されています。 他にご質問がございましたらお知らせください。 BR ハビブ

Recommended substitute for P89LPC935FDH Hi, We are looking for a recommended substitute for the P89LPC935FDH. Could you please suggest the best alternative that would allow for an easy hardware transition and minimal software changes? Thank you. Re: Recommended substitute for P89LPC935FDH Hello. Thank you for your interest in NXP. Unfortunately, NXP does not offer a drop‑in, pin‑compatible successor for the LPC900 series. The P89LPC935FDH is officially discontinued, and NXP lists no direct replacement.  However, the closest device with minimal firmware porting effort and reasonable hardware modification is: NXP LPC11xx (LPC1100) Series - LPC111x LPC1100 Series: Scalable Entry-Level Microcontrollers (MCUs) Based on Arm Cortex-M0+/M0 Cores | NXP Semiconductors - Small packages (TSSOP‑28, QFN‑28) - Low‑power, inexpensive - Peripherals comparable or superior (ADC, timers, I2C, SPI, UART) - Easy to port 8051‑style logic into ARM Cortex‑M0 - NXP’s intended migration path from P89LPC → LPC11xx LPC1112 / LPC1113 in TSSOP‑28 or HVQFN‑33 packages - ARM Cortex‑M0 (fast, low-power) - SPI, I2C, UART – all present - 10‑bit ADC (LPC1113/14) - GPIO count similar to LPC900 - Small packages (down to 5×5 mm QFN) Best Regards,

How to Maximize Your Power with Aion 2's Class-Specific Skills What Are Class-Specific Skills? Class-specific skills are abilities that are unique to your chosen class in Aion 2. These skills allow you to define your role in battle, whether you're dealing heavy damage, providing support, or absorbing hits for your team. Every class in Aion 2 has its own set of skills that cater to different playstyles and situations. For instance, warriors might have abilities that boost their defense or provoke enemies, while archers focus on dealing damage from a distance with precision and speed. Healers, on the other hand, have supportive spells that can turn the tide of a battle. Knowing how to leverage your class's skill set is essential for getting the most power out of your character. How Can I Maximize My Class-Specific Skills? Maximizing your power with your class-specific skills is more than just learning what each one does. You need to understand when and how to use them effectively. Here are a few tips to get you started: 1. Understand the Cooldowns and Synergies One of the first things you should know about your skills is their cooldowns. Every class has some abilities that are powerful but take a while to recharge. It's important to use these skills at the right time, as timing can mean the difference between winning and losing a fight. Additionally, many classes have skills that synergize with one another. These abilities work well when used in combination, whether it’s a buff that enhances a specific attack or a debuff that makes enemies more vulnerable to your strikes. Understanding these synergies is key to maximizing your overall damage or survivability. For example, if you're playing a mage, using a debuff that reduces an enemy’s magical resistance, followed by a heavy-hitting spell, can increase your damage output significantly. Similarly, tank classes can use taunts and buffs in tandem to maintain aggro while reducing damage taken. 2. Maximizing Utility Skills Class-specific skills are not just about dealing damage; they also include utility abilities like crowd control, mobility, and defensive buffs. Knowing when to use these utility skills is crucial, especially in group content where strategy plays a major role. Crowd Control (CC): Many classes, especially those in support roles, have crowd control abilities like stuns, snares, or knockbacks. Using these at the right time can prevent enemies from overwhelming your team or give you an edge in PvP. Mobility: Some classes have movement abilities that can help you avoid damage or reposition in battle. Using these smartly can prevent you from being caught out of position or out of reach of an enemy. Defensive Skills: Tank and healer classes often have skills that mitigate incoming damage or heal your team. You’ll want to be using these abilities at the right moment to keep yourself and your party alive during tough fights. 3. Master Your Rotation A key part of maximizing your power lies in optimizing your skill rotation. A good rotation uses your class's abilities in the most efficient order, ensuring that your damage is as high as possible without wasting cooldowns. For DPS (damage-dealing) classes, this means making sure you’re constantly hitting with your most effective skills while weaving in debuffs or buffs as necessary. A simple example for a warrior might look like this: Start with a skill that boosts your damage or defense. Follow it with a heavy-hitting attack. Use crowd control if needed to disable enemies. Keep applying buffs and debuffs as necessary. Finish off with your most powerful skill when it’s off cooldown. For healers, your rotation may not involve direct damage, but keeping an eye on your healing abilities and using them in the most efficient order is just as important. It’s vital that you’re not letting anyone in your party drop too low on health while maximizing the healing output. 4. Gear and Skill Synergy Many players overlook the synergy between their skills and their gear. Certain gear items may provide bonuses that enhance the effectiveness of specific skills, such as increasing critical damage or reducing cooldown times. If you're looking to maximize your character’s power, always pay attention to gear that complements your playstyle. For example, if you focus on DPS, look for items that boost your skill power, crit rate, and attack speed. On the other hand, tanks should prioritize gear that increases their defense, health, or taunt effectiveness. It’s also important to make sure your gear aligns with your class's primary attributes so you can truly maximize the effectiveness of your abilities. 5. Buy Aion 2 Kinah Online Sometimes, getting the best gear and leveling up your skills can be time-consuming. If you want to speed up the process or acquire rare items, some players choose to buy Aion 2 Kinah online. This can help you acquire better equipment or purchase materials that may otherwise be difficult to obtain. Just be sure to buy from trusted sources to avoid scams or account issues. 6. Understand Your Class's Weaknesses While maximizing your skills, it’s also important to understand your class's weaknesses. No class is perfect, and every role has its limitations. For example, some classes might be extremely effective at dealing damage but are more vulnerable in terms of defense. Others might have excellent healing abilities but lack high DPS. Knowing when to compensate for these weaknesses in group content or PvP is essential. For example, if you're a healer, you might need to rely on your DPS teammates to keep the enemy distracted while you focus on support. On the other hand, a DPS player might need to watch their positioning carefully to avoid getting hit by strong attacks from enemies. 7. Adapt to the Situation Every battle in Aion 2 is different. Whether you're fighting a boss in a dungeon, raiding with your guild, or engaging in PvP, you'll need to adapt your use of class-specific skills to the situation at hand. This flexibility is key to making the most out of your abilities. For example, while fighting in a dungeon, you may need to prioritize single-target abilities for bosses, while in large-scale PvP, area-of-effect (AoE) abilities might be more useful. Being able to quickly swap between playstyles and skill rotations will make you a stronger and more versatile player. Maximizing your power in Aion 2 isn't just about grinding or obtaining the best gear—it’s about understanding your class-specific skills and learning how to use them in the most efficient way. Mastering your skills, understanding synergies, optimizing rotations, and adapting to different situations will allow you to play at the highest level. Remember to pay attention to your gear’s synergy with your abilities, and if you need a boost, consider options like buying Aion 2 Kinah online to further enhance your experience.

S32E288 MU and MRUs Hello, I am  trying to figure out how exactly does the MU (Messaging Unit) work and how does it link with each cores MRU (Message Receive Unit).  I am  trying to pass flags/messages from the M33 boot core to other R52 cores and as I understand, each core has its own MRU with a number of channels and message buffers per channel. So for example the M33 core has 12 channels with 4 message buffers in the first 4 channels and 2 message buffers in all the other channels (5-12). I can also see the base address (4530_0000h) for the configuration registers, but where are the messages themselves stored or how can they be read? As I understand the MU (Messaging Unit) is supposed to be the interface between any two cores, but then again table 918 makes it seem like only the MUB is supposed to be used by the user/"transmitting core". How do I know where to write the data so that it is received by the MRU of the receiving core? Is there maybe an example I could reference or is this even the intended way for the messaging unit to work? Re: S32E288 MU and MRUs Hello, In the S32Z/E architecture, the Messaging Unit (MU) and Message Receive Unit (MRU) function together as a hardware mailbox system for inter-processor communication (IPC).    How MU and MRU Link Together The communication is directional:  Transmitting Side (MU): The sender (e.g., M33 core) uses the MU to "push" messages. You write to the MU's transmit registers. Receiving Side (MRU): Each receiving core (e.g., R52) has its own dedicated MRU instance. This MRU acts as the "mailbox" that receives and stores the message until the receiving core reads it. The Link: A message written to a specific MU channel by the sender is automatically routed by the hardware interconnect to a corresponding MRU channel on the destination core.    Where Messages are Stored & Read The messages are not stored in general RAM; they are held in hardware registers within the receiving core's MRU:  To Write (Sender): You write your 32-bit data to the TRn (Transmit Register) of the MU. To Write (Sender): You write your 32-bit data to the TRn (Transmit Register) of the MU. To Read (Receiver): The receiving R52 core reads the message from its own MRU's Mailbox (MB) registers. Base Addresses: While the configuration base might be 4530_0000h for one unit, the MRU for a specific R52 core will have its own unique base address in the memory map. You must check the S32Z Reference Manual for the specific MRU instance address assigned to the target R52 core.    How to Target a Specific Core To ensure the data reaches the correct R52 core: Identify the MRU Instance: Each R52 core (or cluster) is typically paired with a specific MRU instance (e.g., MRU_0 for Core 0). Enable the Path: The sender must have permission to write to that specific MRU instance. Channel Mapping: You write to MU_CHx which is hard-wired or configured to trigger an interrupt and populate a buffer in the target MRU_CHy .    Implementation Reference The most robust way to implement this is using the Inter-Platform Communication Framework (IPCF) provided by NXP.  IPCF abstracts the raw MU/MRU register writes into a clean IPC_Send / IPC_Receive API. You can find examples in the S32 Design Studio or within the RTD (Real-Time Drivers) package for S32Z/E.  Regards

CAN‑FD 5 Mbps Support on S32K146 Hello NXP Team, I am working with the S32K146 MCU and would like to confirm the maximum achievable CAN‑FD data-phase bitrate. My setup: MCU: NXP S32K146 (FlexCAN with CAN‑FD enabled) CAN source clock: 80 MHz PLL output Trying to configure CAN‑FD data-phase bitrate = 5 Mbps Re: CAN‑FD 5 Mbps Support on S32K146 Hi, chapter 55.3.11.1 Clock domains and restrictions of the device RM shows equations for calculation of max achievable data phase bitrate. The 5Mbps, you mentioned, is possible. You can use below calculator for bitrate parameter calculation https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/MPC5xxx-S32Kxx-LPCxxxx-CAN-CAN-FD-bit-timing-calculation/ta-p/1119319 BR, Petr

MCXA185VLH USB0_DP and USB0_DM Pins Not Highlighted in MCUXpresso Pins Too Hi,     We are currently working with the MCXA185VLH controller and enabling USB0 functionality using MCUXpresso Config Tools. According to the datasheet, USB0_DM and USB0_DP are assigned to pin 26 and pin 27 respectively (pad type: ANA, IO supply: VDD_USB). However, when USB0 is enabled in the MCUXpresso Pins Tool, these DP and DM pins are not highlighted,Only USB VBUS_DET PIN 22 signal are visible and configurable. Could you please confirm the following Are USB0_DP and USB0_DM fixed-function analog PHY pins that are automatically connected internally and therefore not shown in the pin mux configuration? Is any additional configuration required in MCUXpresso Config Tools to activate these pins, or are they enabled automatically once USB0 peripheral and PHY are initialized in software? Is there any recommended way to verify correct USB PHY pin activation within the tool? We want to confirm that our configuration is correct before proceeding with hardware validation. Thank you for your support. MCXA Package and IO|GPIO USB Re: MCXA185VLH USB0_DP and USB0_DM Pins Not Highlighted in MCUXpresso Pins Too Hi @Darvin, Thanks for your post and apologies the delay reply. Yes, the USB0_DP and USB0_DM are internally connected, that is why in the pinmux table those pins do not have different Pinmux Assignment. No additional configuration is needed.  There is not an official recommendation to verify the USB PHY with the tool. Regarding PCR configuration there is only needed the USB0_VBUS_DET that you are setting. 

PCA2131 RTC 在电池备份模式下的行为 您好， 我们在电池管理系统设计中使用 PCA2131 RTC。当 VDD 电源以 3.3 V 供电时，设备将按预期运行。但是，当 RTC 切换到备用电池模式（3 V 纽扣电池连接到 BAT 引脚）时，不会产生 CLKOUT 信号。 我们希望了解 RTC 在电池备份模式下的行为，特别是 CLKOUT 和中断功能的可用性。我们的要求是在备用电池模式下生成中断以唤醒电池管理系统。 请找到随附的原理图以供参考。 Re: PCA2131 RTC Behavior in Battery Backup Mode 你好 Kalpakg24 很抱歉延迟了，看来您的代理商已经在内部联系了我们，我们已经在提供支持，我们将继续使用该媒介，我希望没有问题。 祝你愉快，好运连连。

imx93 は lpm ドライバを使用するための周波数設定ポイントを取得できません カスタム imx93 SOM の CPU 周波数と DDR 周波数を調整するために、imx93_lpm ドライバーを使用しようとしています。 フォルダー内に「mode」オブジェクトがないため、`echo 1 > /sys/devices/platform/imx93-lpm/mode` を実行しようとしても失敗します。dmesg の出力を読んでいると、lpm ドライバから「DDR 周波数スケーリングをサポートできません」というエラーが発生し、ドライバがプローブに失敗していることがわかります。このエラーは、arm_smccc_smc 呼び出しが 2 未満の周波数設定ポイントを返すことによって発生します。 lpddr4x_timings.cにアクセスできますファイルには 3 つの周波数設定ポイントがあるように見えます。 私の推測では、uboot が spl.c で spl_dram_init を呼び出すと、DDR タイミングは設定されますが、周波数設定ポイント データは Linux による取得のために ARM SMC ストレージに書き込まれません。DDR タイミングを ARM SMC に書き込む例は見当たりません。 Linux でアクセスできるように DDR タイミング データが Arm SMC に保存されていることを確認する方法について説明していただけますか? Re: imx93 cannot get frequency set points to use lpm driver こんにちは@aaronc-nv 、 NXP サポートにお問い合わせいただきありがとうございます。 観察されている動作は、LPM ノードがデバイス ツリーに含まれていない場合に予想されるものです。 この問題を解決するには、i.MX93 EVK で定義されているのと同じ方法で、デバイス ツリーに lpm ノードを追加してください。 &lpm { ld-mode-enabled; }; このノードを追加した後、デバイス ツリーを再構築して再試行してください。 よろしくお願いします、 チャビラ

Copy: S32K3 Question about compatibility module of EB-Tresos and S32DS This post is a copy from here Hello K3 team, I am thinking about how to migrate S32DS module to EB-Tresos for our customer(ANT&SWS) now because the user is using MCAL and Driver for 2 kinds of cores(1 Core : Autosar, Other Core : NON Autosar). There are MCAL, Drivers, OS and Middleware area(Fig.1) but I am not sure exactly which module EB-Tresos supports... I thought EB-Tresos supports the only MCAL but it seems like I am wrong. For instance, EB tresos does not show Siul2 Port(Fig.1). Q1. If the user would like to use Drivers module on EB-Tresos, can the user use this module on EB-Tresos?       In my opininon, the user can use it the only S32DS and combine MCAL configuration generated on EB-Tresos on S32DS.  Q2. How about OS? Is it compatible(Fig.2)? Fig.1 I just compared it. Fig.2. OS module on EB Tresos Regards, Fumi EB TRESOS LICENSES Priority: MEDIUM S32DS Source: NXP Internal Re: Copy: S32K3 Question about compatibility module of EB-Tresos and S32DS Provided answered in original thread

S32G: Qspi_Ip_HyperflashProgram が 2 バイトごとに書き込みコマンドを送信するのはなぜですか? こんにちは、専門家の皆さん CTM: ヴァレオ プラットフォーム: S32G3 モジュール: RTD 5.0.0QLP04 Flsドライバ 顧客から、NOR フラッシュの書き込みスループットが予想よりも大幅に低いという報告がありました。 お客様は、関数Qspi_Ip_HyperflashProgramがデータを 2 バイトずつ送信する理由を知りたい場合があります。これがボトルネックのようです。 このトピックについて助けてくれる専門家はいますか? ご対応ありがとうございます。 レオ RTD Re: S32G: why the Qspi_Ip_HyperflashProgram sends write command for every 2 bytes? こんにちは@Nhi_Nguyen ご協力いただきありがとうございます。しかし、当社のドライバで一度に 2 バイトを書き込むのは、お客様にとって遅すぎるのではないでしょうか?パフォーマンスを向上させるにはどうすればよいでしょうか? BR、 レオ Re: S32G: why the Qspi_Ip_HyperflashProgram sends write command for every 2 bytes? こんにちは@LeoLiAP 、 これは、Hyperbus が以下の 2 種類のデータ送信をサポートしているためです。 ドライバーは、内部バッファに 1 ワードを書き込むこと (コードは各アドレス データに対して 1 ワード) をサポートします。その後、バッファを Fls (Write Buffer) に送信するコマンドを呼び出します。 よろしくお願いいたします。 ニ Re: S32G: why the Qspi_Ip_HyperflashProgram sends write command for every 2 bytes? こんにちは@LeoLiAP 、 2 バイトの書き込みは Hyperbus プロトコルに従うため、これを変更できないことは理解しています。しかし、SW チームは時間を節約するためにコードを改善する予定であり、そのためのチケットは ARTDCMEM-1247 です。 よろしくお願いいたします。 ニ

RTD Half Duplex SPI Hi @VaneB  As you mentioned before I try to RTD for half duplex SPI. When I send to data with using Lpspi_Ip_SyncTransmitHalfDuplex function how could I get data from slave. Lpspi_Ip_AsyncTransmitHalfDuplex(&SLAVE_EXTERNAL_DEVICE, RxSlaveBuffer, NUMBER_OF_BYTES, LPSPI_IP_HALF_DUPLEX_RECEIVE, NULL_PTR); /* Master transmits data in half-duplex mode by sync method */ Lpspi_Ip_SyncTransmitHalfDuplex(&MASTER_EXTERNAL_DEVICE, TxMasterBuffer, NUMBER_OF_BYTES, LPSPI_IP_HALF_DUPLEX_TRANSMIT, TIMEOUT); after that should I write this function  Lpspi_Ip_AsyncTransmitHalfDuplex(&SLAVE_EXTERNAL_DEVICE, RxSlaveBuffer, NUMBER_OF_BYTES, LPSPI_IP_HALF_DUPLEX_TRANSMIT, NULL_PTR); /* Master transmits data in half-duplex mode by sync method */ Lpspi_Ip_SyncTransmitHalfDuplex(&MASTER_EXTERNAL_DEVICE, TxMasterBuffer, NUMBER_OF_BYTES, LPSPI_IP_HALF_DUPLEX_RECEIVE, TIMEOUT); Re: RTD Half Duplex SPI Hi everybody, can somebody share an example to try tx and rx in half mode using 3-wire with registers? I have the same problem and i can't communicate with a SPI half duplex 3-wire sensor. Regards, DP Re: RTD Half Duplex SPI Hi @danielmartynek  I will keep the discussion on the opened case for not duplicating the thread. I guess you can also see the ticket.  Re: RTD Half Duplex SPI Hi @JosephJ, I see the ticket, a colleague of mine is working on this. As I already mentioned in this thread, there is an option to send one frame of 80bits, instead of 10 8bit frames. That means that you can use the RTD without the continous mode. Or you could send 10 8bit frames and use GPIO as the CS, again with the continuous mode disabled. Regards, Daniel Re: RTD Half Duplex SPI Hi @danielmartynek  I opened a case because community support do not provide us the RTD update that supports the 3wire spi communication at continuous mode. You provided us some details how to the update the SDK to support that feature. But it will be a hard task to accomplish that since sdk is provided by RTD team. Even you think that updating the sdk based on that information will not be an easy task. That's why I opened this case. Can you please get in touch with RTD team once again if they can fix this issue in scheduled plan? https://support.nxp.com/s/case/5002p00002vTPqsAAG/3-wire-spi-driver-with-continuous-mode Re: RTD Half Duplex SPI Hi @maximillion, I don't think the SDK can be easily modified. These are SW limitations, it should work in HW, there are these errata though: ERR011097 ERR011089 https://www.nxp.com/docs/en/errata/S32K148_0N20V.pdf To receive 4 8byte frames in half-duplex continous mode, you need these commands: while(LPSPI1->FSR & LPSPI_FSR_TXCOUNT_MASK){} LPSPI1->TCR = LPSPI_TCR_CPHA_MASK |LPSPI_TCR_TXMSK_MASK |LPSPI_TCR_CONT_MASK |LPSPI_TCR_PRESCALE(2) |LPSPI_TCR_PCS(0) |LPSPI_TCR_FRAMESZ(7); while(LPSPI1->FSR & LPSPI_FSR_TXCOUNT_MASK){} LPSPI1->TCR = LPSPI_TCR_CPHA_MASK |LPSPI_TCR_TXMSK_MASK |LPSPI_TCR_CONT_MASK |LPSPI_TCR_CONTC_MASK |LPSPI_TCR_PRESCALE(2) |LPSPI_TCR_PCS(0) |LPSPI_TCR_FRAMESZ(7); while(LPSPI1->FSR & LPSPI_FSR_TXCOUNT_MASK){} LPSPI1->TCR = LPSPI_TCR_CPHA_MASK |LPSPI_TCR_TXMSK_MASK |LPSPI_TCR_CONT_MASK |LPSPI_TCR_CONTC_MASK |LPSPI_TCR_PRESCALE(2) |LPSPI_TCR_PCS(0) |LPSPI_TCR_FRAMESZ(7); while(LPSPI1->FSR & LPSPI_FSR_TXCOUNT_MASK){} LPSPI1->TCR = LPSPI_TCR_CPHA_MASK |LPSPI_TCR_TXMSK_MASK |LPSPI_TCR_CONT_MASK |LPSPI_TCR_CONTC_MASK |LPSPI_TCR_PRESCALE(2) |LPSPI_TCR_PCS(0) |LPSPI_TCR_FRAMESZ(7); /* terminate the transfer */ while(LPSPI1->FSR & LPSPI_FSR_TXCOUNT_MASK){} LPSPI1->TCR = LPSPI_TCR_CPHA_MASK |LPSPI_TCR_PRESCALE(2) |LPSPI_TCR_PCS(0) |LPSPI_TCR_FRAMESZ(7); And you have to read the RX data in the meantime. To transmit data, change TXMSK for RXMASK. Regards, Daniel Re: RTD Half Duplex SPI @danielmartynek Also, is the limitation you are talking about hardware or software? Re: RTD Half Duplex SPI Hi @danielmartynek  "Functions implemented in SDK for LPSPI (RTM 3.0.0 S32 Design Studio 2.2) do not have "native support" for 3-wire. So can we implement 3-wire SPI in continuous mode by making necessary changes at the driver level for RTM3.0.0? Re: RTD Half Duplex SPI Hi @maximillion, Unfortunately, I have been informed that there is not going to be any patch. It will be just listed as a limitation in the User Manual. I'm not sure what the reasons are. Regards, Daniel Re: RTD Half Duplex SPI Hi @danielmartynek, Can't we use TXMSK CONT function in LPSPI driver? I need this in my project won't a new update or patch come out? Re: RTD Half Duplex SPI Hi @maximillion, The RTD team has found some limitations that do not allow the TXMSK CONT function in the LPSPI driver. They will update the UM with a note mentioning that. Regards, Daniel Re: RTD Half Duplex SPI Hi @maximillion, Yes, it looks like it is a bug in RTD. Have you consider using one 80bit frame instead? BR, Daniel Re: RTD Half Duplex SPI How should I handle this issue? Is this issue related to RTD driver isn't it? Re: RTD Half Duplex SPI Hi @maximillion, I don't see any issue with the 3wire mode, but with the Continues mode. I have created the attached simple test project (Master only). 1. CONT = 0 2. CONT = 1 The issue is clearly in the Continuous mode. Regards, Daniel Re: RTD Half Duplex SPI Hi Actually, this project is valid and I worked on this project. I'm not sure why you couldn't test the project. Anyway, I'm in trouble with the 3-wire SPI. I'm waiting for your answer. Re: RTD Half Duplex SPI Hello @maximillion, I'm sorry for the delay, I couldn't get to the testing. You example had a few issues, like both modules have to have one pin selected for both MOSI/MISO and the pin must be set as Input/Output. Anyway, I think there is a bug in the RTD driver. It has been reported to the RTD development team. Once I have sone new information, I will update the thread. Best regards, Daniel Re: RTD Half Duplex SPI Hello @danielmartynek  In the project I uploaded, LPSPI1 was used as master and LPSPI0 as slave. In my project, S32K148 will be master and it will communicate with TFT display, so you can think of LPSPI0 module as TFT display. I need to configure the display with 3 wire spi. Below I have attached a photo of the SPI communication specified in the datashette. Also I attached my logic analyzer screnshoot. Could you please tell me how to read data from slave correctly from master?     Re: RTD Half Duplex SPI I only have 3 Wire Clock, Chip Select, Data. Your project is not 3-wire. I've written so much that your community always suggests another answer. I have attached the project. I only have to use 3 wires. I need to send and receive at MOSI pin. In the example project, I sent and received data between two SPI modules, but in my own project I cannot read data from the slave because the master does not keep the chip select pin continuous while receiving data. Why chip select did not keep continuos? Below picture master send data (LPSPI0) and slave receive data (LPSPI1) after that receive send data and master receive. Why doesn't the pcs pin keep the pin continuous while the master is receiving data? Please review the project.   Re: RTD Half Duplex SPI Hi @maximillion, A simple test project is in this thread: https://community.nxp.com/t5/S32K/S32K314-SPI-flash-implementation/m-p/1617504#M21457 It sends one 8bit frame to the Slave device and reads 3 frames from the Slave device. Regards, Daniel Re: RTD Half Duplex SPI Actually my question is, how can I read the register from the slave. I am sending data as master and how can I receive data from slave. What function should I use to get the data as master from slave

NTAG 5 - Demo App In the Documentation NTAG 5 - Android Application Development (RM00221) there is a Demo Android Application mentioned from NXP. But so far I can't find a Link to the Source Code or the apk Where can I find the Source Code to the Demo App? Best regards Julian Re: NTAG 5 - Demo App done many thanks Re: NTAG 5 - Demo App Hello, as shuja971 pointed out, the requested source code is for the NTAG 5 Explorer app on Play Store that allows changing on voltage and energy harvesting mode. This code is to be used with the white NTAG5 demo boards. Is it possible to provide the source for the NTAG 5 Explorer app? Re: NTAG 5 - Demo App Hi, Hope you're doing well. I checked the source codes available and they don't have enough details. For example, the NTAG 5 Explorer app on Play Store allows changing on voltage and energy harvesting mode while there is no sign of such commands in the source codes or documentation. Can you please help in this regard? Re: NTAG 5 - Demo App I downloaded the mentioned source code of the NTAG 5 development kit, but that is NOT the source code of the mentioned app NTAG 5 Explorer from the Google Play Store! E.g. with the Explorer App I can switch the harvesting mode to various voltages and that works fine, but this feature is not included anywhere in the source code of the development kit. Is it possible to find also the source code of the other demo apps from Play Store (NTAG 5 Explorer, NTAG i2C Demo, NXP TagInfo, NXP Tag Writer, ...) somewhere? Re: NTAG 5 - Demo App You're welcome Re: NTAG 5 - Demo App Great, thank you for the Links Best regards Julian Re: NTAG 5 - Demo App Hello, You can look at the google play store NTAG 5 Explorer - Apps en Google Play  Also, you can find the source code for the application in the following link OM2NTx5332: NTAG 5 development kits | NXP , it is located under the code snippets section. Regards, Estephania

オートモーティブ SW Package マネージャ と NXP Design 製品 List のツールの可用性の違い こんにちは、 オートモーティブ SW Package マネージャ と NXP Design 製品 List でツールと RTD ライブラリの可用性に違いがあるのはなぜですか? たとえば、オートモーティブ SW Package マネージャ には S32 Design Studio 3.5.3 があります。 NXP Design 製品リストにはS32 Design Studio 3.6.6があります。 どのバージョンを使用することをお勧めしますか? ありがとう。 Re: Differences in tool availability between Automotive SW Package Manager and NXP Design Product Li こんにちは@Djuric オートモーティブ ソフトウェア Package Manager では、バンドルは、HVBMS やその他のアプリケーション パッケージなど、特定の実装で適切な機能を保証するために一緒にテストされた特定のソフトウェア バージョンで構成されます。これらのバンドルは、グループとして確実に動作するように設計された検証済みのソフトウェア コンポーネントのセットとして提供されます。 一方、 https://nxp.flexnetoperations.comで利用可能なコンテンツには、検証済みバンドルだけでなく、リリースされたすべてのソフトウェア バージョンが含まれます。 アプリケーションを始めたばかりの場合は、常に最新のソフトウェア バージョンを使用することをお勧めします。 また、各ソフトウェアのリリース ノートをチェックして、どのような依存関係があり、どのバージョンでテストされているかを確認することもできます。これにより、互換性が確保され、統合の問題が軽減されます。 BR、ヴェインB

Dockerコンテナでのモデル推論 こんにちは、コミュニティ # iMX 8MP ハーヴェイ021 モデル推論に関する問題が発生しました。Docker コンテナ内では失敗しますが、ホスト マシンでは動作します。関連する共有ライブラリはすでにコンテナにコピーされており、プログラムは不足している依存関係を報告せずに実行されます。 公式検証プログラムを実行すると、セグメンテーション違反が発生しました。 以下のようにコマンドを実行します。 root@imx8mpevk:~/examples# ./label_image--external_delegate_path=/usr/lib/libvx_delegate.soo 情報: モデル ./mobilenet_v1_1.0_224_quant.tflite がロードされました 情報: 解決済み報告者 情報: Vx デリゲート: allowed_cache_mode が 0 に設定されています。 情報: Vx デリゲート: デバイス番号が 0 に設定されています。 情報: Vx デリゲート: allowed_builtin_code が 0 に設定されています。 INFO: Vx デリゲート: error_during_init が 0 に設定されています。 INFO: Vx デリゲート: error_during_prepare が 0 に設定されています。 INFO: Vx デリゲート: error_during_invoke が 0 に設定されています。 情報: EXTERNAL デリゲートが作成されました。 INFO: EXTERNAL デリゲートを適用しました。 W [HandleLayoutInfer:332]Op 162: デフォルトのレイアウト推論パス。 セグメンテーション違反 gdb デバッグ: Dockerイメージ: ubuntu24.04-arm64 docker コマンド: docker run -it --rm --device=/dev/galcore --device=/dev/mxc_hantro --device=/dev/mxc_hantro_vc8000e --network=host --privileged=true ubuntu:dl_gdb bash ターゲットイメージバージョン: linux6.6.36 フル 対象マシン: i.MX 8mp Re: model inference in docker container こんにちは@noway 、 お元気でお過ごしのことと思います。   2.6.2 章「i.MX Linux プラットフォーム用の Flex Delegate を使用した TensorFlow Lite ライブラリのビルディング」をご覧ください。 2.6.2.2 Docker VMのセットアップ i.MX 機械学習ユーザーズガイド。   これが役に立つことを願っています。   よろしくお願いいたします。 チャビラ Re: model inference in docker container ご回答ありがとうございます。しかし、私は 8mp で Docker を実行していました。私のベースイメージはarm64/v8/ubuntu24.04です

PN7220 Commands For FeliCa Reader/Writer Digital Protocol Requirements Specification Certificaiton We are using NXP PN7221 in our reader. Our reader needs to process Felica cards. Hence, we need to pass the testing specified in the Felica R/W digital card protocol requirements spec at https://www.felicatech.org/readerwriter/pdf/FeliCa_ReaderWriter_Digital_Protocal_Requirements_E_1_23.pdf. Please see tables 3 and 4 on page 18. I am new to the NCI commands used in PN7221. Please let me know what the NCI commands to use for: 1. Poll type F Felica card. 2. Modify the polling parameters such as system code in the poll command. 3. Turn on RF. 4. Turn off RF. 5. The NCI commands to send the Felica commands in table 3 and 4. Thank you, Raymond Re: PN7220 Commands For FeliCa Reader/Writer Digital Protocol Requirements Specification Certificait Hello, this is Fabian, I've been assigned to support your case. Thank you for your interest in our products. As you may have noticed, we don't have any example that can be referred to in order to use PN722x for a proper polling of Felica cards. PN7220 does support Felica cards and, the configurations can be seen in section 19 Annex C: RF protocol configuration indexes. These configurations can be done by using our GUI: NFC Cockpit. But, the implementation for loading the configurations in your own application must be done by the respective development team. Additionally, the use of PN7160 examples as a reference for building the NCI commands will be very useful for your application. This IC also uses NCI 2.0 as well meaning that the commands will be quite similar. Still, is recommended to use Cockpit and, address the PN722x datasheet. Re: PN7220 Commands For FeliCa Reader/Writer Digital Protocol Requirements Specification Certificait Thank you for your reply. Just want to make sure. Please let me know which NXP doc you are referred to:  section 19 Annex C: RF protocol configuration indexes. Re: PN7220 Commands For FeliCa Reader/Writer Digital Protocol Requirements Specification Certificait Sorry, I missed pasting the Document Link: PN722X NFC controller Re: PN7220 Commands For FeliCa Reader/Writer Digital Protocol Requirements Specification Certificait No worries. Thanks again.

Linker file I am trying to port code from cosmic to CodeWarrior 5.2 for HCS12 controller, when I am trying to use #pragma CODE_SEG PAGE_32 to make a function under section PAGE 32 ,only the section is getting updated in map file, starting address remains unchanged. Re: Linker file Hi @Aswin_5232, You did not specify the part number of the MCU. Use something like this instead: Linker: SEGMENTS PAGE_32 = READ_ONLY 0x8000 TO 0xBFFF PAGE 32; END PLACEMENT MyPage32Funcs INTO PAGE_32; END   Main #pragma CODE_SEG MyPage32Funcs void MyFunc(void) { ... } #pragma CODE_SEG DEFAULT Regards, Daniel Any support, information, and technology (“Materials”) provided by NXP are provided AS IS, without any warranty express or implied, and NXP disclaims all direct and indirect liability and damages in connection with the Material to the maximum extent permitted by the applicable law. NXP accepts no liability for any assistance with applications or product design. Materials may only be used in connection with NXP products. Any feedback provided to NXP regarding the Materials may be used by NXP without restriction.

IMX8MPは常にeMMC boot0から起動しますが、eMMcパーティションmmcblk2p1からは起動できません。 こんにちは、 私は SolidRun i.MX8MP ボードを使用しています。デフォルトのイメージ（core-image-inimal-imx8mpsolidrun.wic.zst）がありますSD カードと eMMC の両方にフラッシュされます。ボードを eMMC ユーザー パーティション 1 (mmcblk2p1) から起動したいのですが、 mmcblk2boot0 から起動します。 補足事項 SD カードからの起動: mmc 開発 パーティション #0 に切り替えます。OK mmc1は現在のデバイスです SD カードはユーザー パーティションから正しく起動します。 カーネルは imx8mp-hummingpulse.dtb をロードします U-Boot で行ったカスタム変更 (ボード メッセージ、DTB の選択など) が反映されます。 eMMCからの起動: mmc 開発 パーティション #0 に切り替えます。OK mmc2（パート0）は現在のデバイスです U-Boot は boot0 からロードされます。 デフォルトの DTB は imx8mp-hummingpulse.dtb ではなく imx8mp-cubox.dtb がロードされます。 U-Boot で行った変更がまったく反映されません。 eMMC情報: mmc情報 ブート領域0: 4 MiB ブート領域1: 4 MiB ユーザーエリア: 29.1 GiB ブート領域は書き込み保護されていません U-Boot変数のみを設定しようとしましたが、機能しません setenv mmcdev 2 setenv mmcpart 1 Uboot は引き続き boot0 からロードされます - ユーザー パーティションの変更は無視されます。 起動中に UART コンソールを使用して U-Boot を停止し、boot_targets を印刷します。出力は (mmc1 mmc2 usb pxe dhcp) です。setenv を使用して mmc2 mmc1 usb pxe dhcp に変更し、saveenv で保存します。新しいイメージを再フラッシュした後、boot_targetsを再度確認すると、mmc2 mmc1 usb pxe dhcpがまだ表示されているので、新しいイメージをフラッシュした後も変更が保持されます。 これにより、ROM は常に boot0 を実行し、ユーザー パーティションは実行されないことが確認されます。 eMMC パーティション (mmcblk2p1) から起動する方法はありますか? よろしくお願いします。 Re: IMX8MP always boots from eMMC boot0, cannot boot from eMMc partition mmcblk2p1 こちらのリンクからお読みいただけます。 https://community.nxp.com/t5/forums/replypage/board-id/imx-processors/message-id/243934 eMMC についての理解が不足しています。 Re: IMX8MP always boots from eMMC boot0, cannot boot from eMMc partition mmcblk2p1 こちらのリンクからお読みいただけます。 https://community.nxp.com/t5/i-MX-Processors/Secondary-Boot-on-i-MX6ULL-Hangs-After-Reset/mp/2251161 eMMC についての理解が不足しています。 Re: IMX8MP always boots from eMMC boot0, cannot boot from eMMc partition mmcblk2p1 こんにちは@tusharvernekar 返信が遅くなり申し訳ありません。少し前に春節休暇を取っていましたが、今はオフィスに戻っています。そして私はその質問をよく理解できません。mmcblk2p1 は dtb ファイルとカーネル イメージを配置するために使用される FAT32 パーティションなので、ブートローダーをビルディングせずにこのパーティションに uboot を配置できるということですか?これは私にとってまったく新しいブートプロセスです。SD ブートの場合でもブート方法について詳細を確認して共有していただけますか。 BR

IMX8MP always boots from eMMC boot0, cannot boot from eMMc partition mmcblk2p1 Hi, I am working with a SolidRun i.MX8MP board. I have the default image (core-image-inimal-imx8mpsolidrun.wic.zst) flashed to both SD card and eMMC. I want the board to boot from eMMC user partition 1 (mmcblk2p1) but it boots from mmcblk2boot0 . Observations Booting from SD card: mmc dev switch to partitions #0, OK mmc1 is current device SD card boots correctly from the user partition. Kernel loads imx8mp-hummingpulse.dtb  Custom changes I made in U-Boot (e.g., board messages, DTB selection) are reflected. Booting from eMMC: mmc dev switch to partitions #0, OK mmc2(part 0) is current device U-Boot loads from boot0. Default DTB imx8mp-cubox.dtb is loaded not imx8mp-hummingpulse.dtb. Changes I made in U-Boot are not reflected at all. eMMC info: mmc info Boot area 0: 4 MiB Boot area 1: 4 MiB User area: 29.1 GiB Boot areas not write-protected I tried Setting U-Boot variables alone but its not working setenv mmcdev 2 setenv mmcpart 1 Uboot still loaded from boot0 — user partition changes ignored. I stop U-Boot during startup using the UART console and print boot_targets; the output is (mmc1 mmc2 usb pxe dhcp). I change it to mmc2 mmc1 usb pxe dhcp using setenv and save it with saveenv. After reflashing a new image, I check boot_targets again, and it still shows mmc2 mmc1 usb pxe dhcp, so the changes I made persist even after flashing the new image This confirms that ROM always executes boot0, never the user partition. Is there any way I can boot from eMMC partition(mmcblk2p1) ? Thanks Re: IMX8MP always boots from eMMC boot0, cannot boot from eMMc partition mmcblk2p1 You can read this link. https://community.nxp.com/t5/forums/replypage/board-id/imx-processors/message-id/243934 You lack understanding of eMMC. Re: IMX8MP always boots from eMMC boot0, cannot boot from eMMc partition mmcblk2p1 You can read this link. https://community.nxp.com/t5/i-MX-Processors/Secondary-Boot-on-i-MX6ULL-Hangs-After-Reset/m-p/2251161 You lack understanding of eMMC. Re: IMX8MP always boots from eMMC boot0, cannot boot from eMMc partition mmcblk2p1 Hi @tusharvernekar  Sorry to reply late, I was on holiday for the Spring Festival a while ago, and now I'm back in the office. And I cannot understand the question well. Since mmcblk2p1 is FAT32 partition which is used to put dtb files and kernel Image, do you mean you can put uboot into this partition without building bootloader? It is totally new boot process for me, could you confirm and share me more details about the boot method even in SD boot case. B.R

TJA1145T/FD error frame wake-up issue 当前我使用TJA1145T/FD芯片，将INH引脚连接到mcu唤醒引脚，当前配置特定帧唤醒，比如0x100,功能正常可以唤醒，但是如果总线有错误帧也会唤醒，比如正常250K总线网络接入500K设备，TJA1145T/FD也会拉高INH，请问怎么样屏蔽掉错误帧唤醒功能，只保留特定帧唤醒(有错误帧不拉高INH）,请问有没有方法，感谢您的回答 Re: TJA1145T/FD error frame wake-up issue 亲爱的张先生 否，TJA1145T/FD 不能配置为忽略 CAN 错误帧。 启用选择性唤醒后，设备仍会将某些格式错误的流量（包括比特率不匹配导致的错误帧）视为与唤醒相关的活动，并将 INH 设置为高电平。遗憾的是，没有任何解决方法。   致以最崇高的敬意 约瑟夫

配置未使用 GPIO 端口/引脚的最佳方法 配置未使用的 GPIO 端口或引脚的最佳方法是什么，以降低噪声和功耗等。默认情况下，端口在启动时初始化为高 Z。那么，我们是否需要对其进行配置？ Re: Best way to configure unused GPIO Ports/Pins 感谢您的回答 Re: Best way to configure unused GPIO Ports/Pins 你好，我是@sharonfmc93、 没错，高 Z 是引脚的默认状态，因此无需设置。此外，我们建议将未使用的 GPIO 保持未连接状态或外部连接到 VSS/GND 参考。 有关详细信息，请参阅文章《硬件设计指南》->第7 章：未使用的引脚。 您可以从以下链接中找到应用笔记： S32K3 通用型 MCU — 硬件设计包 BR IsaulO.