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[#1]

S32E288 MU and MRUs

Hello,

I am  trying to figure out how exactly does the MU (Messaging Unit) work and how does it link with each cores MRU (Message Receive Unit). 

I am  trying to pass flags/messages from the M33 boot core to other R52 cores and as I understand, each core has its own MRU with a number of channels and message buffers per channel. So for example the M33 core has 12 channels with 4 message buffers in the first 4 channels and 2 message buffers in all the other channels (5-12). I can also see the base address (4530_0000h) for the configuration registers, but where are the messages themselves stored or how can they be read?

As I understand the MU (Messaging Unit) is supposed to be the interface between any two cores, but then again table 918 makes it seem like only the MUB is supposed to be used by the user/"transmitting core". How do I know where to write the data so that it is received by the MRU of the receiving core?

Is there maybe an example I could reference or is this even the intended way for the messaging unit to work?

Re: S32E288 MU and MRUs

Hello,

In the S32Z/E architecture, the

Messaging Unit (MU) and Message Receive Unit (MRU) function together as a hardware mailbox system for inter-processor communication (IPC). 

How MU and MRU Link Together

The communication is directional: 

• Transmitting Side (MU): The sender (e.g., M33 core) uses the MU to "push" messages. You write to the MU's transmit registers.
• Receiving Side (MRU): Each receiving core (e.g., R52) has its own dedicated MRU instance. This MRU acts as the "mailbox" that receives and stores the message until the receiving core reads it.
• The Link: A message written to a specific MU channel by the sender is automatically routed by the hardware interconnect to a corresponding MRU channel on the destination core. 

Where Messages are Stored & Read

The messages are not stored in general RAM; they are held in hardware registers within the receiving core's MRU: 

• To Write (Sender): You write your 32-bit data to the TRn (Transmit Register) of the MU.
• • To Write (Sender): You write your 32-bit data to the TRn (Transmit Register) of the MU.
  • To Read (Receiver): The receiving R52 core reads the message from its own MRU's Mailbox (MB) registers.
  • Base Addresses: While the configuration base might be 4530_0000h for one unit, the MRU for a specific R52 core will have its own unique base address in the memory map. You must check the S32Z Reference Manual for the specific MRU instance address assigned to the target R52 core. 
  How to Target a Specific Core

  To ensure the data reaches the correct R52 core:

  1. Identify the MRU Instance: Each R52 core (or cluster) is typically paired with a specific MRU instance (e.g., MRU_0 for Core 0).
  2. Enable the Path: The sender must have permission to write to that specific MRU instance.
  3. Channel Mapping: You write to MU_CHx which is hard-wired or configured to trigger an interrupt and populate a buffer in the target MRU_CHy. 

  Implementation Reference

  The most robust way to implement this is using the Inter-Platform Communication Framework (IPCF) provided by NXP. 

  • IPCF abstracts the raw MU/MRU register writes into a clean IPC_Send / IPC_Receive API.
  • You can find examples in the S32 Design Studio or within the RTD (Real-Time Drivers) package for S32Z/E. 

  
  

  Regards