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哪种内存性能高?OCRAM 还是 SDRAM 我通过 16 个引脚的 semc 端口将 sdram( W9825G6KH-5i )连接到 rt1176。 我想知道哪种内存性能较高。 板上的片上 RAM 或 SDRAM。 回复:哪种内存性能高?OCRAM 还是 SDRAM 在内存方面,ITCM 和 DTCM 将是最快的,因为它们以与核心相同的速度运行并且不使用缓存。OCRAM 速度较慢(对于 memcpys 来说慢 3-4 倍,IIRC),因为它必须经过 AXI 总线和缓存。SEMC 可能无法比 OCRAM 更快(因为它使用相同的 AXI 总线和缓存),但确切的速度取决于设置。
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Where can I find MCX comparator SAMPLE/WINDOW input Hi NXP, I am currently trying to use the comparator module in the MCX series. However, I have noticed that the documentation does not provide detailed instructions on how to configure the SAMPLE/WINDOW signal. Although the manual (MCXN 44.3.1, MCXA 41.3.1) note mentions "See the chip configuration section for the source of SAMPLE/WINDOW input." I have not been able to find the relevant description. https://www.nxp.com/webapp/Download?colCode=MCXNX4XRM&location=null https://www.nxp.com/webapp/Download?colCode=MCXAP64M96FS3RM&location=null Could you please assist me in confirming how to proceed with the configuration? If possible, I would greatly appreciate it if you could provide me with some examples. Thank you very much! Analog(ADC|CMP|DAC|OpAmps) MCXA MCXN Re: Where can I find MCX comparator SAMPLE/WINDOW input Hi @Harry_Zhang: Thank you very much! Re: Where can I find MCX comparator SAMPLE/WINDOW input Hi @onejoeluo  About "See the chip configuration section for the source of SAMPLE/WINDOW input." Please check the MCX Nx4x Reference Manual 26  chapter Input Multiplexing (INPUTMUX). Hope this will help you. BR Hang
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Reset led toggling while deploying the project from mbdt Hello NXP team, We are working in dio configuration using mbdt with S32K344 EVB Rev B1. while deploying the code using matlab we are able to see the functionality working but after some time like 3 to 5 sec the board reset LED starts blinking continuously. Unable to find the solution. Can anyone give me some solutions! Attached the project folder with this, kindly do some needful. Thanks & Regards Esakki MBDT @VaneB @Irina_Costachescu @Robin_Shen @Ganapathi_NASH_INDIA @Kavin_raj_mbd  Re: Reset led toggling while deploying the project from mbdt Hi, @Vijay98, Thank you for your interest into Model-Based Design Toolbox for S32K3. It looks like your evaluation board enters into a sequential reset state. Please review the following thread  S32K3X4EVB-T172 with MBD which addresses the same issue. Let us know if your problem persists. Best regards, Dragos Re: Reset led toggling while deploying the project from mbdt Hi esakki, I am also facing the same issue... In s32k344 evb rev A it's working fine but in s32k344 evb rev B1 after flashing for 5 to 10 sec it's working fine after that reset led starts blinking continuously  If you find any solution kindly let me know... then any one resolved this issue let us know Thanks & Regards  KR MBDT S32K3X4EVB-T172  @VaneB @Irina_Costachescu @Robin_Shen 
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安装S32DS 3.5的问题 当我输入许可证并选择在线时,发生了这种情况 回复:安装S32DS 3.5的问题 谢谢!
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S32M LIN スタックのコンパイル エラー S32DS 3.5 と S32M24 RTD 2.0.0 を使用しており、S32K1_S32M24X_LINSTACK_RTM_1_0_2_D2308_updatesite.zipをインストールしています。 マスターとスレーブの例をインポートし、mexファイルのバックスラッシュの問題を修正しました( )、そして、設定コードを生成しました。 どちらのプロジェクトもビルドされません。 スレーブコードに次のエラーがあります。 説明 Resource Path Location Type 'LinIf_Channel_State' undeclared (この関数で最初に使用) lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 520 行目 C/C++ の問題 'LINIF_IDLE' 未宣言 (この関数で最初に使用)。「LINIF_CODE」のことだったの?lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 520 行目 C/C++ の問題 フィールド 'lin_baudrate_adjusted_flg' を解決できませんでした lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 199 行目 セマンティックエラー フィールド 'lin_max_frame_res_timeout_val' を解決できませんでした lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 193 行目 セマンティックエラー フィールド 'lin_protocol_state' を解決できませんでした lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 172 行目 セマンティックエラー フィールド 'lin_protocol_state' を解決できませんでした lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 438 行目 セマンティックエラー フィールド 'lin_protocol_state' を解決できませんでした lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 443 行目 セマンティックエラー フィールド 'lin_protocol_state' を解決できませんでした lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 488 行目 セマンティックエラー フィールド 'lin_virtual_interface' を解決できませんでした lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 128 行目 セマンティックエラー フィールド 'lin_virtual_interface' を解決できませんでした lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 146 行目 セマンティックエラー フィールド 'lin_virtual_interface' を解決できませんでした lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 176 行目 セマンティックエラー フィールド 'lin_virtual_interface' を解決できませんでした lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 181 行目 セマンティックエラー フィールド 'lin_virtual_interface' を解決できませんでした lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 302 行目 セマンティックエラー フィールド 'lin_virtual_interface' を解決できませんでした lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 411 行目 セマンティックエラー フィールド 'lin_virtual_interface' を解決できませんでした lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 489 行目 セマンティックエラー フィールド 'max_idle_timeout_cnt' を解決できませんでした lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 528 行目 セマンティックエラー フィールド 'response_buffer_ptr' を解決できませんでした lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 443 行目 セマンティックエラー フィールド 'response_length' を解決できませんでした lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 438 行目 セマンティックエラー 関数 'OsIf_ResumeAllInterrupts' の暗黙宣言 [-Werror=暗黙の関数宣言] lin_commontl_proto.c/Lin_Master_S32M244_Example_DS/stacks/lin/src 1241 行目 C/C++ の問題 関数 'OsIf_ResumeAllInterrupts' の暗黙宣言 [-Werror=暗黙の関数宣言] lin_commontl_proto.c/Lin_Slave_S32M244_Example_DS/stacks/lin/src 1241 行目 C/C++ の問題 関数 'OsIf_SuspendAllInterrupts' の暗黙宣言 [-Werror=暗黙の関数宣言] lin_commontl_proto.c/Lin_Master_S32M244_Example_DS/stacks/lin/src 1172 行目 C/C++ の問題 関数 'OsIf_SuspendAllInterrupts' の暗黙宣言 [-Werror=暗黙の関数宣言] lin_commontl_proto.c/Lin_Slave_S32M244_Example_DS/stacks/lin/src 1172 行目 C/C++ の問題 make: *** [stacks/lin/lin_dal/src/subdir.mk:20:stacks/lin/lin_dal/src/lin_dal.o]エラー 1 Lin_Slave_S32M244_Example_DS C/C++ の問題 make: *** [stacks/lin/src/subdir.mk:36: stacks/lin/src/lin_commontl_proto.o]エラー 1 Lin_Master_S32M244_Example_DS C/C++ の問題 make: *** [stacks/lin/src/subdir.mk:36: stacks/lin/src/lin_commontl_proto.o]エラー 1 Lin_Slave_S32M244_Example_DS C/C++ の問題 make: *** 未完成の仕事を待っています...。Lin_Master_S32M244_Example_DS C/C++ の問題 make: *** 未完成の仕事を待っています...。Lin_Slave_S32M244_Example_DS C/C++ の問題 シンボル 'LinIf_Channel_State' を解決できませんでした lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 520 行目 セマンティックエラー シンボル 'LINIF_IDLE' を解決できませんでした lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 520 行目 セマンティックエラー マスター・コードのエラーは少なくなります。 説明 Resource Path Location Type 関数 'OsIf_ResumeAllInterrupts' の暗黙宣言 [-Werror=暗黙の関数宣言] lin_commontl_proto.c/Lin_Master_S32M244_Example_DS/stacks/lin/src 1241 行目 C/C++ の問題 関数 'OsIf_SuspendAllInterrupts' の暗黙宣言 [-Werror=暗黙の関数宣言] lin_commontl_proto.c/Lin_Master_S32M244_Example_DS/stacks/lin/src 1172 行目 C/C++ の問題 これらのエラーはどのように解決できますか? Re: S32M LIN スタックのコンパイル エラー ワークスペースから両方のプロジェクトを完全に削除してから、Lin_SlaveプロジェクトとLin_Masterプロジェクトを再インポートしました。コンフィギュレーターを開く前に、元の投稿で説明したLDFソース行のバックスラッシュの問題を修正しました。 その後、コンフィギュレーターを開き、コードを更新して、無事にビルドすることができました。 コンフィギュレーターのこの行が、このコードのすべてのバージョンで一貫して壊れているのはなぜですか?S32K118の実装でも同じ問題があります。 Re: S32M LIN スタックのコンパイル エラー マスターコードとスレーブコードのためにlin_commontl_proto.cにインクルードを追加する必要がありました。 #include 「OsIf_Internal.h」 マスターコードはビルドされますが、スレーブコードにはまだエラーがあります。 1. LINIF_IDLEが定義されていない 2. stacks/lin/lin_dal/src/lin_dal.c:520:23:エラー: 'LinIf_Channel_State' 未宣言
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S32M LIN Stack compilation errors I am using S32DS 3.5 and S32M24 RTD 2.0.0 and installed the S32K1_S32M24X_LINSTACK_RTM_1_0_2_D2308_updatesite.zip. I imported the master and slave examples, fixed the backslash problem in the mex file ( ), and generated the configuration code. Neither project will build. The slave code has these errors: Description Resource Path Location Type 'LinIf_Channel_State' undeclared (first use in this function) lin_dal.c /Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src line 520 C/C++ Problem 'LINIF_IDLE' undeclared (first use in this function); did you mean 'LINIF_CODE'? lin_dal.c /Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src line 520 C/C++ Problem Field 'lin_baudrate_adjusted_flg' could not be resolved lin_dal.c /Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src line 199 Semantic Error Field 'lin_max_frame_res_timeout_val' could not be resolved lin_dal.c /Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src line 193 Semantic Error Field 'lin_protocol_state' could not be resolved lin_dal.c /Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src line 172 Semantic Error Field 'lin_protocol_state' could not be resolved lin_dal.c /Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src line 438 Semantic Error Field 'lin_protocol_state' could not be resolved lin_dal.c /Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src line 443 Semantic Error Field 'lin_protocol_state' could not be resolved lin_dal.c /Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src line 488 Semantic Error Field 'lin_virtual_interface' could not be resolved lin_dal.c /Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src line 128 Semantic Error Field 'lin_virtual_interface' could not be resolved lin_dal.c /Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src line 146 Semantic Error Field 'lin_virtual_interface' could not be resolved lin_dal.c /Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src line 176 Semantic Error Field 'lin_virtual_interface' could not be resolved lin_dal.c /Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src line 181 Semantic Error Field 'lin_virtual_interface' could not be resolved lin_dal.c /Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src line 302 Semantic Error Field 'lin_virtual_interface' could not be resolved lin_dal.c /Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src line 411 Semantic Error Field 'lin_virtual_interface' could not be resolved lin_dal.c /Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src line 489 Semantic Error Field 'max_idle_timeout_cnt' could not be resolved lin_dal.c /Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src line 528 Semantic Error Field 'response_buffer_ptr' could not be resolved lin_dal.c /Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src line 443 Semantic Error Field 'response_length' could not be resolved lin_dal.c /Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src line 438 Semantic Error implicit declaration of function 'OsIf_ResumeAllInterrupts' [-Werror=implicit-function-declaration] lin_commontl_proto.c /Lin_Master_S32M244_Example_DS/stacks/lin/src line 1241 C/C++ Problem implicit declaration of function 'OsIf_ResumeAllInterrupts' [-Werror=implicit-function-declaration] lin_commontl_proto.c /Lin_Slave_S32M244_Example_DS/stacks/lin/src line 1241 C/C++ Problem implicit declaration of function 'OsIf_SuspendAllInterrupts' [-Werror=implicit-function-declaration] lin_commontl_proto.c /Lin_Master_S32M244_Example_DS/stacks/lin/src line 1172 C/C++ Problem implicit declaration of function 'OsIf_SuspendAllInterrupts' [-Werror=implicit-function-declaration] lin_commontl_proto.c /Lin_Slave_S32M244_Example_DS/stacks/lin/src line 1172 C/C++ Problem make: *** [stacks/lin/lin_dal/src/subdir.mk:20: stacks/lin/lin_dal/src/lin_dal.o] Error 1 Lin_Slave_S32M244_Example_DS C/C++ Problem make: *** [stacks/lin/src/subdir.mk:36: stacks/lin/src/lin_commontl_proto.o] Error 1 Lin_Master_S32M244_Example_DS C/C++ Problem make: *** [stacks/lin/src/subdir.mk:36: stacks/lin/src/lin_commontl_proto.o] Error 1 Lin_Slave_S32M244_Example_DS C/C++ Problem make: *** Waiting for unfinished jobs.... Lin_Master_S32M244_Example_DS C/C++ Problem make: *** Waiting for unfinished jobs.... Lin_Slave_S32M244_Example_DS C/C++ Problem Symbol 'LinIf_Channel_State' could not be resolved lin_dal.c /Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src line 520 Semantic Error Symbol 'LINIF_IDLE' could not be resolved lin_dal.c /Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src line 520 Semantic Error The master code has fewer errors: Description Resource Path Location Type implicit declaration of function 'OsIf_ResumeAllInterrupts' [-Werror=implicit-function-declaration] lin_commontl_proto.c /Lin_Master_S32M244_Example_DS/stacks/lin/src line 1241 C/C++ Problem implicit declaration of function 'OsIf_SuspendAllInterrupts' [-Werror=implicit-function-declaration] lin_commontl_proto.c /Lin_Master_S32M244_Example_DS/stacks/lin/src line 1172 C/C++ Problem How can these errors be resolved? Re: S32M LIN Stack compilation errors I deleted both projects completely from my workspace, then re-imported the Lin_Slave and Lin_Master projects. Before opening the configurator, I fixed the backslash problem on the LDF source line mentioned in the original post. I then opened the configurator, updated the code, and was able to build successfully. Why is this line of the configurator consistently broken across all versions of this code? I see the same problem in the S32K118 implementation.  Re: S32M LIN Stack compilation errors I needed to add an include to lin_commontl_proto.c for the master and slave code: #include "OsIf_Internal.h" The master code will build now, but the slave code still has errors: 1. LINIF_IDLE is not defined 2. stacks/lin/lin_dal/src/lin_dal.c:520:23: error: 'LinIf_Channel_State' undeclared 
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S32M LIN 堆栈编译错误 我正在使用 S32DS 3.5 和 S32M24 RTD 2.0.0,并安装了 S32K1_S32M24X_LINSTACK_RTM_1_0_2_D2308_updatesite.zip。 我导入了主从示例,修复了 mex 文件中的反斜杠问题 ( ),并生成配置代码。 两个项目都无法建设。 从站代码有以下错误: 描述 资源路径 位置 类型 'LinIf_Channel_State' 未声明(在此函数中首次使用)lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 第 520 行 C/C++ 问题 “LINIF_IDLE”未声明(在此函数中首次使用);您的意思是“LINIF_CODE”吗?lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 第 520 行 C/C++ 问题 字段“lin_baudrate_adjusted_flg”无法解析 lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 第 199 行语义错误 字段“lin_max_frame_res_timeout_val”无法解析 lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 第 193 行语义错误 字段“lin_protocol_state”无法解析 lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 第 172 行语义错误 字段“lin_protocol_state”无法解析 lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 第 438 行语义错误 字段“lin_protocol_state”无法解析 lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 第 443 行语义错误 字段“lin_protocol_state”无法解析 lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 第 488 行语义错误 字段“lin_virtual_interface”无法解析lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 第 128 行语义错误 字段“lin_virtual_interface”无法解析lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 第 146 行语义错误 字段“lin_virtual_interface”无法解析lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 第 176 行语义错误 字段“lin_virtual_interface”无法解析lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 第 181 行语义错误 字段“lin_virtual_interface”无法解析lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 第 302 行语义错误 字段“lin_virtual_interface”无法解析lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 第 411 行语义错误 字段“lin_virtual_interface”无法解析lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 第 489 行语义错误 字段“max_idle_timeout_cnt”无法解析 lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 第 528 行语义错误 字段“response_buffer_ptr”无法解析 lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 第 443 行语义错误 字段“response_length”无法解析 lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 第 438 行语义错误 函数“OsIf_ResumeAllInterrupts”的隐式声明 [-Werror=implicit-function-declaration] lin_commontl_proto.c/Lin_Master_S32M244_Example_DS/stacks/lin/src 第 1241 行 C/C++ 问题 函数“OsIf_ResumeAllInterrupts”的隐式声明 [-Werror=implicit-function-declaration] lin_commontl_proto.c/Lin_Slave_S32M244_Example_DS/stacks/lin/src 第 1241 行 C/C++ 问题 函数“OsIf_SuspendAllInterrupts”的隐式声明 [-Werror=implicit-function-declaration] lin_commontl_proto.c/Lin_Master_S32M244_Example_DS/stacks/lin/src 第 1172 行 C/C++ 问题 函数“OsIf_SuspendAllInterrupts”的隐式声明 [-Werror=implicit-function-declaration] lin_commontl_proto.c/Lin_Slave_S32M244_Example_DS/stacks/lin/src 第 1172 行 C/C++ 问题 制作:*** [stacks/lin/lin_dal/src/subdir.mk:20:堆栈/lin/lin_dal/src/lin_dal.o]错误 1 Lin_Slave_S32M244_Example_DS C/C++ 问题 制作:*** [stacks/lin/src/subdir.mk:36:stacks/lin/src/lin_commontl_proto.o]错误 1 Lin_Master_S32M244_Example_DS C/C++ 问题 制作:*** [stacks/lin/src/subdir.mk:36:stacks/lin/src/lin_commontl_proto.o]错误 1 Lin_Slave_S32M244_Example_DS C/C++ 问题 make:*** 等待未完成的作业.... Lin_Master_S32M244_Example_DS C/C++ 问题 make:*** 等待未完成的作业.... Lin_Slave_S32M244_Example_DS C/C++ 问题 符号“LinIf_Channel_State”无法解析 lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 第 520 行语义错误 符号“LINIF_IDLE”无法解析 lin_dal.c/Lin_Slave_S32M244_Example_DS/stacks/lin/lin_dal/src 第 520 行语义错误 主代码错误较少: 描述 资源路径 位置 类型 函数“OsIf_ResumeAllInterrupts”的隐式声明 [-Werror=implicit-function-declaration] lin_commontl_proto.c/Lin_Master_S32M244_Example_DS/stacks/lin/src 第 1241 行 C/C++ 问题 函数“OsIf_SuspendAllInterrupts”的隐式声明 [-Werror=implicit-function-declaration] lin_commontl_proto.c/Lin_Master_S32M244_Example_DS/stacks/lin/src 第 1172 行 C/C++ 问题 如何解决这些错误? 回复:S32M LIN 堆栈编译错误 我从工作区中完全删除了这两个项目,然后重新导入了 Lin_Slave 和 Lin_Master 项目。在打开配置器之前,我修复了原始帖子中提到的 LDF 源代码行上的反斜杠问题。 然后我打开配置器,更新代码,并成功构建。 为什么配置器的这一行在该代码的所有版本中都始终出现问题?我在 S32K118 实现中也看到了同样的问题。 回复:S32M LIN 堆栈编译错误 我需要在 lin_commontl_proto.c 中添加一个包含主代码和从代码的内容: #包括“OsIf_Internal.h” 主代码现在可以构建了,但是从属代码仍然有错误: 1. LINIF_IDLE未定义 2. stacks/lin/lin_dal/src/lin_dal.c:520:23:错误:“LinIf_Channel_State”未声明
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i.Mx8MP Fast Auth HAB errors Hello, I'm trying to implement secure boot on an i.MX8MP-based custom platform. The board design is very similar to the i.MX8MP devkit. I want to use the Fast Authentication feature. So far, I've burnt the key hash into the SoC and I got the following HAB errors: u-boot=> hab_status Secure boot disabled HAB Configuration: 0xf0, HAB State: 0x66 --------- HAB Event 1 ----------------- event data: 0xdb 0x00 0x14 0x45 0x33 0x1d 0xc0 0x00 0xca 0x00 0x0c 0x00 0x01 0xc5 0x1d 0x00 0x00 0x00 0x10 0xe8 STS = HAB_FAILURE (0x33) RSN = HAB_INV_KEY (0x1D) CTX = HAB_CTX_COMMAND (0xC0) ENG = HAB_ENG_ANY (0x00) --------- HAB Event 2 ----------------- event data: 0xdb 0x00 0x14 0x45 0x33 0x1d 0xc0 0x00 0xca 0x00 0x0c 0x00 0x01 0xc5 0x1d 0x00 0x00 0x00 0x10 0xe8 STS = HAB_FAILURE (0x33) RSN = HAB_INV_KEY (0x1D) CTX = HAB_CTX_COMMAND (0xC0) ENG = HAB_ENG_ANY (0x00) --------- HAB Event 3 ----------------- event data: 0xdb 0x00 0x14 0x45 0x33 0x1d 0xc0 0x00 0xca 0x00 0x0c 0x00 0x01 0xc5 0x1d 0x00 0x00 0x00 0x10 0xd0 STS = HAB_FAILURE (0x33) RSN = HAB_INV_KEY (0x1D) CTX = HAB_CTX_COMMAND (0xC0) ENG = HAB_ENG_ANY (0x00) --------- HAB Event 4 ----------------- event data: 0xdb 0x00 0x14 0x45 0x33 0x1d 0xc0 0x00 0xca 0x00 0x0c 0x00 0x01 0xc5 0x1d 0x00 0x00 0x00 0x10 0xd0 STS = HAB_FAILURE (0x33) RSN = HAB_INV_KEY (0x1D) CTX = HAB_CTX_COMMAND (0xC0) ENG = HAB_ENG_ANY (0x00) --------- HAB Event 5 ----------------- event data: 0xdb 0x00 0x14 0x45 0x33 0x0c 0xa0 0x00 0x00 0x00 0x00 0x00 0x00 0x91 0xff 0xc0 0x00 0x00 0x00 0x20 STS = HAB_FAILURE (0x33) RSN = HAB_INV_ASSERTION (0x0C) CTX = HAB_CTX_ASSERT (0xA0) ENG = HAB_ENG_ANY (0x00) --------- HAB Event 6 ----------------- event data: 0xdb 0x00 0x14 0x45 0x33 0x0c 0xa0 0x00 0x00 0x00 0x00 0x00 0x00 0x91 0xff 0xe0 0x00 0x00 0x00 0x0c STS = HAB_FAILURE (0x33) RSN = HAB_INV_ASSERTION (0x0C) CTX = HAB_CTX_ASSERT (0xA0) ENG = HAB_ENG_ANY (0x00) --------- HAB Event 7 ----------------- event data: 0xdb 0x00 0x14 0x45 0x33 0x0c 0xa0 0x00 0x00 0x00 0x00 0x00 0x00 0x92 0x00 0x00 0x00 0x00 0x00 0x04 STS = HAB_FAILURE (0x33) RSN = HAB_INV_ASSERTION (0x0C) CTX = HAB_CTX_ASSERT (0xA0) ENG = HAB_ENG_ANY (0x00) --------- HAB Event 8 ----------------- event data: 0xdb 0x00 0x14 0x45 0x33 0x0c 0xa0 0x00 0x00 0x00 0x00 0x00 0x40 0x1f 0xbd 0xc0 0x00 0x00 0x00 0x20 STS = HAB_FAILURE (0x33) RSN = HAB_INV_ASSERTION (0x0C) CTX = HAB_CTX_ASSERT (0xA0) ENG = HAB_ENG_ANY (0x00) --------- HAB Event 9 ----------------- event data: 0xdb 0x00 0x14 0x45 0x33 0x0c 0xa0 0x00 0x00 0x00 0x00 0x00 0x40 0x1f 0xad 0xc0 0x00 0x00 0x00 0x04 STS = HAB_FAILURE (0x33) RSN = HAB_INV_ASSERTION (0x0C) CTX = HAB_CTX_ASSERT (0xA0) ENG = HAB_ENG_ANY (0x00) It looks like my key is invalid. I double checked that I fused the correct keys and it looks good to me. Here is my full procedure, if you see something wrong: PKI tree generation: $ ./keys/hab4_pki_tree.sh Do you want to use an existing CA key (y/n)?: n Key type options (confirm targeted device supports desired key type): Select the key type (possible values: rsa, rsa-pss, ecc)?: rsa-pss Enter key length in bits for PKI tree: 4096 Enter PKI tree duration (years): 5 How many Super Root Keys should be generated? 4 Do you want the SRK certificates to have the CA flag set? (y/n)?: n  SRK table/fuse generation: $ ./linux64/bin/srktool -h 4 -t SRK_1_2_3_4_table.bin -e SRK_1_2_3_4_fuse.bin -d sha256 -c crts/SRK1_sha256_4096_65537_v3_usr_crt.pem,crts/SRK2_sha256_4096_65537_v3_usr_crt.pem,crts/SRK3_sha256_4096_65537_v3_usr_crt.pem,crts/SRK4_sha256_4096_65537_v3_usr_crt.pem Number of certificates = 4 SRK table binary filename = SRK_1_2_3_4_table.bin SRK Fuse binary filename = SRK_1_2_3_4_fuse.bin SRK Fuse binary dump: SRKH[0] = 0xCC68B1A5 SRKH[1] = 0xFC739529 SRKH[2] = 0xC2A266D4 SRKH[3] = 0x565ED742 SRKH[4] = 0xD85265D5 SRKH[5] = 0x2E4D871A SRKH[6] = 0x6AAF0D93 SRKH[7] = 0x21C75F71 Hexdump output: $ hexdump -e '/4 "0x"' -e '/4 "%X""\n"' SRK_1_2_3_4_fuse.bin 0xCC68B1A5 0xFC739529 0xC2A266D4 0x565ED742 0xD85265D5 0x2E4D871A 0x6AAF0D93 0x21C75F71 Fuse reads on target after being burnt: u-boot=> fuse read 6 0 4 Reading bank 6: Word 0x00000000: cc68b1a5 fc739529 c2a266d4 565ed742 u-boot=> fuse read 7 0 4 Reading bank 7: Word 0x00000000: d85265d5 2e4d871a 6aaf0d93 21c75f71 For the signing procedure, you'll find attached my CSF templates and imx-mkimage build logs. I'm using CST version 4.0.0. And for the CSF binaries generation and injection: $ ./linux64/bin/cst -i cst_spl.txt -o cst_spl.bin CSF Processed successfully and signed data available in cst_spl.bin $ ./linux64/bin/cst -i cst_fit.txt -o cst_fit.bin CSF Processed successfully and signed data available in cst_fit.bin $ cp flash.bin signed_flash.bin $ dd if=cst_spl.bin of=signed_flash.bin seek=$((0x36c00)) bs=1 conv=notrunc $ dd if=cst_fit.bin of=signed_flash.bin seek=$((0x59020)) bs=1 conv=notrunc $ sudo dd if=signed_flash.bin of=/dev/sdb bs=1K seek=32 && sync i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: i.Mx8MP Fast Auth HAB errors For its detailed information, recommend to have a reference to the section of SRM.  Regards Harvey Re: i.Mx8MP Fast Auth HAB errors Hello @Harvey021, thanks for your feedback! Do you know if it is written somewhere? I read multiple times the official CST doc and I did not find this information. Re: i.Mx8MP Fast Auth HAB errors Hello @jd-bootlin  The i.MX8MP doesn't support RSA-PSS key for HAB. Suggest to Key Type - RSA. Regards Harvey Re: i.Mx8MP Fast Auth HAB errors After decoding the first HAB event using the HABv4 API document, it looks like the reason is "specified key is identified as a CA key." I double checked my keys and they don't have the CA flag set, I'm a little bit more confused now.
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imx8qm lpddr4 android bsp Hi! I'm trying to flash a board from phytec with imx8qm on board. I've downloaded Android 14 from the nxp page. I tried to run uuu_imx_android_flash.sh script but it keeps failing with error: [HID(W): LIBUSB_ERROR_TIMEOUT (-7) ] SDPS: boot -f imx-boot-imx8qmmek-sd.bin-flash The command was: sudo ./uuu_imx_android_flash.sh -f imx8qm As I understood the error is related to LPDDR4 and DDR4. The board has LPDDR4 and my question is the android build or uboot from the build don't support LPDDR4? Also, tried to flash linux and got the same error.    Re: imx8qm lpddr4 android bsp Hi, Thank you for your answer! Re: imx8qm lpddr4 android bsp Hi, Thank you for your interest in NXP Semiconductor products, The problem is the imx-boot image, there must be differences other than the LPDDR4 because 8QM-MEK has a LPDDR4 memory. The differences in RAM configuration, channels of PMIC, memories, etc. cause failures probing, then failure booting an image specially with this SoC since the resources are managed by SCFW. You have to use PHYTEC release of Android since it requires a lot of partitions and are checksum-ed, with Linux you could adapt working with our RootFS integrating PHYTEC imx-boot, device tree and probably Kernel image, the other option is to use PHYTEC Linux release too. Regards
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OpenCL Number of platforms 0 I'm using Layerscape LS1028ARDB, LSDK v21.08, kernel 5.10.35.  This post is related to https://community.nxp.com/t5/Layerscape/ls1028ardb-OpenCL-clinfo-Number-of-platforms-is-0/m-p/1579037/highlight/true I am trying to make sure my OpenCV application is using OpenCL. I run the following: $ cat /boot/config-5.15.0-1007-ls | grep MXC_GPU_VIV CONFIG_MXC_GPU_VIV=y It looks like use of GPU should be enabled in my kernel build. However, when I run clinfo, I get Number of platforms 0 When I run dmesg | grep -i galcore I see: [    3.750350] galcore f0c0000.gpu: Adding to iommu group 14 [    3.755946] Galcore version 6.4.3.p2.336687 Am I missing something here? Re: OpenCL Number of platforms 0 Thanks, it was because I needed the desktop Ubuntu image instead of main. Re: OpenCL Number of platforms 0 I downloaded LSDK 21.08 pre-built images $ wget https://www.nxp.com/lgfiles/sdk/lsdk2108/firmware_ls1028ardb_sdboot.img $ wget https://www.nxp.com/lgfiles/sdk/lsdk2108/boot_LS_arm64_lts_5.10.tgz $  wget https://www.nxp.com/lgfiles/sdk/lsdk2108/rootfs_lsdk2108_ubuntu_desktop_arm64.tgz Deploy them to SD card. $ flex-installer -i pf -d /dev/sdb $ flex-installer -b boot_LS_arm64_lts_5.10.tgz -f firmware_ls1028ardb_sdboot.img -r rootfs_lsdk2108_ubuntu_desktop_arm64.tgz  -d /dev/sdb Note:/dev/sdb is SD device name on the host PC. Boot from SD card on LS1028ARDB, I got the following information. root@localhost:~# apt-get install clinfo root@localhost:~# clinfo clinfo: /usr/lib/libOpenCL.so.1: no version information available (required by clinfo) Number of platforms 1 Platform Name Vivante OpenCL Platform Platform Vendor Vivante Corporation Platform Version OpenCL 1.2 V6.4.3.p2.336687 Platform Profile FULL_PROFILE Platform Extensions cl_khr_icd Platform Extensions function suffix viv Platform Name Vivante OpenCL Platform Number of devices 1 Device Name Vivante OpenCL Device GC7000UL.6202.0000 Device Vendor Vivante Corporation Device Vendor ID 0x564956 Device Version OpenCL 1.2 Driver Version OpenCL 1.2 V6.4.3.p2.336687 Device OpenCL C Version OpenCL C 1.2 Device Type GPU Device Profile FULL_PROFILE Device Available Yes Compiler Available Yes Linker Available Yes Max compute units 1 Max clock frequency 600MHz Device Partition (core) Max number of sub-devices 0 Supported partition types (n/a) Supported affinity domains (n/a) Max work item dimensions 3 Max work item sizes 512x512x512 Max work group size 512 Preferred work group size multiple 8 Preferred / native vector sizes char 4 / 4 short 4 / 4 int 4 / 4 long 4 / 4 half 0 / 0 (cl_khr_fp16) float 4 / 4 double 0 / 0 (n/a) Half-precision Floating-point support <68: get="" cl_device_half_fp_config="" ="" error="" -30=""> Single-precision Floating-point support (core) Denormals No Infinity and NANs Yes Round to nearest Yes Round to zero Yes Round to infinity No IEEE754-2008 fused multiply-add No Support is emulated in software No Correctly-rounded divide and sqrt operations No Double-precision Floating-point support (n/a) Address bits 32, Little-Endian Global memory size 268435456 (256MiB) Error Correction support Yes Max memory allocation 134217728 (128MiB) Unified memory for Host and Device Yes Minimum alignment for any data type 128 bytes Alignment of base address 2048 bits (256 bytes) Global Memory cache type Read/Write Global Memory cache size 16384 (16KiB) Global Memory cache line size 64 bytes Image support Yes Max number of samplers per kernel 16 Max size for 1D images from buffer 65536 pixels Max 1D or 2D image array size 8192 images Max 2D image size 8192x8192 pixels Max 3D image size 8192x8192x8192 pixels Max number of read image args 128 Max number of write image args 8 Local memory type Global Local memory size 32768 (32KiB) Max number of constant args 9 Max constant buffer size 65536 (64KiB) Max size of kernel argument 1024 Queue properties Out-of-order execution Yes Profiling Yes Prefer user sync for interop Yes Profiling timer resolution 1000ns Execution capabilities Run OpenCL kernels Yes Run native kernels No printf() buffer size 1048576 (1024KiB) Built-in kernels (n/a) Device Extensions cl_khr_byte_addressable_store cl_khr_gl_sharing cl_khr_fp16 cl_khr_global_int32_base_atomics cl_khr_global_int32_extended_atomics cl_khr_local_int32_base_atomics cl_khr_local_int32_extended_atomics NULL platform behavior clGetPlatformInfo(NULL, CL_PLATFORM_NAME, ...) No platform clGetDeviceIDs(NULL, CL_DEVICE_TYPE_ALL, ...) Success [viv] clCreateContext(NULL, ...) [default] Success [viv] clCreateContextFromType(NULL, CL_DEVICE_TYPE_DEFAULT) Success (1) Platform Name Vivante OpenCL Platform Device Name Vivante OpenCL Device GC7000UL.6202.0000 clCreateContextFromType(NULL, CL_DEVICE_TYPE_CPU) No devices found in platform clCreateContextFromType(NULL, CL_DEVICE_TYPE_GPU) Success (1) Platform Name Vivante OpenCL Platform Device Name Vivante OpenCL Device GC7000UL.6202.0000 clCreateContextFromType(NULL, CL_DEVICE_TYPE_ACCELERATOR) No devices found in platform clCreateContextFromType(NULL, CL_DEVICE_TYPE_CUSTOM) No devices found in platform clCreateContextFromType(NULL, CL_DEVICE_TYPE_ALL) Success (1) Platform Name Vivante OpenCL Platform Device Name Vivante OpenCL Device GC7000UL.6202.0000
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S32K1 attach gdbserver without reset Hi, I am trying to attach my debugger (SEGGER J-Link) to a running target to debug it. However, when starting the gdb server, the target seems to reset. Steps to reproduce this issue: 1. Start SEGGER J-Link Remote Server 2. Start gdb server (in WSL2) using the following command: `JLinkGDBServerCLExe -device S32K144W -endian little -if SWD -speed auto -noir -noLocalhostOnly -nologtofile -TelnetPort 19020 -select IP=192.168.x.y -noreset -nohalt` Observer behaviour: When the command is run, the RESET pin is pulled down for 160ms. The running program is stopped (observed by the blinking led that stops). After ~4 seconds, the gdbserver is attached (> `Connected to target`) and the application starts again (led blinking). However, the application was reset, which is not as desired. Any idea to why this would be or what I could do to find the cause? The reset reason seems to be SW reset. The used MCU is a S32K144W on a custom board. Debugging etc works without a problem, the issue I am having is just that I cannot attach to a running target. Re: S32K1 attach gdbserver without reset Hi @danielmartynek , Using the script when starting the gdb server solved the problem. `JLinkGDBServerCLExe -device S32K144W -endian little -if SWD -speed auto -noir -noLocalhostOnly -nologtofile -TelnetPort 19020 -select IP=192.168.x.y -JLinkScriptFile NXP_Kinetis_S32_Attach.JLinkScript -nohalt` Thank you very much and have a nice day! Re: S32K1 attach gdbserver without reset HI @peacefulcarrot, It is necessary that the MCU is in the unlocked state. A special JLink script is needed, which can be found here: https://wiki.segger.com/S32Kxxx#Attach_to_debug_session JLink commander has to be called in following way: C:\Programme\SEGGER\JLink\JLink.exe -JLinkScriptFile NXP_Kinetis_S32_Attach.JLinkScript Then, the MCU is not reset, and access to all memory and registers is possible. Please contact SEGGER support if you have any questions, Regards, Daniel
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S32K144: Is there a way to use FlexIO pin for PWM generation in Simulink Currently trying to figure out how to use a FlexIO pin for PWM generation in Simulink. I don't see any blocks in Simulink for using a FlexIO pin for PWM generation, only for I2C, SPI and UART. Any help would be greatly appreciated.  Re: S32K144: Is there a way to use FlexIO pin for PWM generation in Simulink Thank you for the information Re: S32K144: Is there a way to use FlexIO pin for PWM generation in Simulink Hello @mirali , Unfortunately, in MBDT for S32K1xx, for the FlexIO we do not provide PWM generation blocks. However, such support can be achieved by using custom code in a similar approach described by this article: https://community.nxp.com/t5/NXP-Model-Based-Design-Tools/How-to-use-your-own-C-code-in-our-Toolbox-Battery-Management/ta-p/1119004 I am not sure if the S32K1 SDK, the abstraction layer on which the MBDT for S32K1 generates the hardware access peripherals code has such support for the PWM generation, so in this case you can directly control and achieve such functionality by writing to registers using a similar approach mentioned in the article above. Regards, Marius
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S32K144:SimulinkでPWM生成にFlexIOピンを使用する方法はありますか 現在、SimulinkでPWM生成にFlexIOピンを使用する方法を理解しようとしています。Simulinkには、PWM生成にFlexIOピンを使用するためのブロックは見当たらず、I2C、SPI、およびUARTのみに使用されています。どんな助けでも大歓迎です。 Re:S32K144:SimulinkでPWM生成にFlexIOピンを使用する方法はありますか 教えて頂きありがとうございました
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MIFARE Development Hey there, I´m relativly new in RFID/NFC an got some questions. We´ve got a new costumer. They have already an excisting custom Board which is powered by an ST Frontend. For there current purpose they use Mifare Ultralight. Now they want to get access to several other Tags, e.g: Mifare® Classic®, Ultralight®, Ultralight C®, Plus®, DESFire® EV1, EV2, EV3, ICODE 2, ICODE SLI. I would choose the CLCR663 PLus - IC for the new development. I have watched the Mifare Academy videos, but still don´t know how to solve following problems: 1. Create Application on 3rd party Tags: In my understanding, the Tag owner has to create a new App to the e.g DESfire EV3 Tag. When connecting to the Product, the Product searches for this specific App through AID. But in case of EV3 Tag, the App is secured by an App-Key. Because the Tag owner doesn´t want me to know the Master-Key and i don´t want the owner to know my App-Key. And without the Master-Key, I´m not able to create a new App by my own, when the customer presents the Tag to my Product, or? - Who generates the Key for the App? - Is there a 'Best Practice' in those cases? 2. AES-128 key: If i want to use AES-128 encryption both sides need the same key. If there is a 3rd party Tag, i don´t know the key. Same questions like 1. - Who generates the Key? - Do i have to write the key to the Tag, when I´m able to get access to my App? - Is there a 'Best Practice' in those cases? Best regards Oliver Contact Smart Card Reader ICs Re: MIFARE Development Ok. Thank you. Re: MIFARE Development The detail information is in the full version of datasheet. The datasheet is NDA required and can be downloaded under "Secure" file.  
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I.MX R1170 SEMC SDRAM 在 SRAM 访问期间中断 你好 我将 SDRAM(CS0)和 SRAM(CSX1)连接到 RT1170 的 SEMC。 我发现 CS0 有时为低脉冲而 CSX1 为低,这意味着当 SEMC 正在访问 SRAM 时,SEMC 对 SDRAM 进行了中断访问。 访问 SRAM 时是否可以阻止 SDRAM 访问? 回复:I.MX R1170 SEMC SDRAM 在 SRAM 访问期间中断 是的,如果需要执行刷新,自动刷新仍然会中断 burts 操作。它只是分割突发,以便可以在其间插入自动刷新。 此致, 奥马尔 回复:I.MX R1170 SEMC SDRAM 在 SRAM 访问期间中断 是的,因为自动刷新是定期执行的。不幸的是,我们没有这个具体实现的例子。 此致, 奥马尔 回复:I.MX R1170 SEMC SDRAM 在 SRAM 访问期间中断 SEMC 在发送 AUTO REFRESH 命令之前发送 PRECHARGE ALL 命令来关闭设备上任何打开的页面。因此,如果自动刷新被禁用,则这两个命令都不会被执行。这在 SDRAMCR3[REN] 字段上被禁用。 请注意,如果刷新没有按照 sdram 时序进行,则可能会导致 sdram 上的某些数据丢失。 此致, 奥马尔 回复:I.MX R1170 SEMC SDRAM 在 SRAM 访问期间中断 SDRAM 的哪个特定命令会中断 SRAM 访问? 将 BMCR 设置为 0x81 的目的是避免重新排序命令队列,以便命令按照“先进先出”策略执行。 建议 UT 和 RT 保持不变,将它们更改为内存可能的最高刷新周期可能会减少 SDRAM 的中断,因为我怀疑中断是自动刷新命令。 此致, 奥马尔 回复:I.MX R1170 SEMC SDRAM 在 SRAM 访问期间中断 我认为SDRAM的中断是由于自动刷新命令造成的,因此调整SDRAM刷新的时间对于防止这种情况至关重要。 另外,在 BMRC 寄存器上实施不同的设置可能会有所帮助,我建议设置 0x81 以防止重新排序命令。 此致, 奥马尔
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I.MX R1170 SEMC SDRAM interrupt during SRAM access Hi  I'm connecting SDRAM(CS0) and SRAM(CSX1) to the SEMC of RT1170. I found CS0 sometimes had low pulse while CSX1 was low, which means SEMC had an interrupt access to SDRAM while SEMC was accessing SRAM. Is it possible to prevent SDRAM access while accessing SRAM? Re: I.MX R1170 SEMC SDRAM interrupt during SRAM access Yes, the auto-refresh still interrupts the burts operation if necesary to execute refresh. It just splits the burst so it can insert auto-refresh in between.  Best regards, Omar Re: I.MX R1170 SEMC SDRAM interrupt during SRAM access Hi @Omar_Anguiano  I found other related thread. In this thread, NXP described ">>1. The SDRAM refresh command is inserted between SEMC burst access.". It looks I can prevent SDRAM refresh from interrupting SRAM access while Auto-Refresh is enabled. Which is correct? https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Questions-when-using-SDRAM-and-SRAM-together-on-SEMC/m-p/1366152/highlight/true#M16998 Re: I.MX R1170 SEMC SDRAM interrupt during SRAM access Yes as auto-refresh is executed periodically. Unfortuantely, we don't have an example of this specific implementation.  Best regards, Omar Re: I.MX R1170 SEMC SDRAM interrupt during SRAM access Hi @Omar_Anguiano  Thank you for your support. Do you mean it's impossible to prevent SDRAM refresh from interrupting SRAM access while Auto-Refresh is enabled? Do you have any sample projects where the Auto-Refresh is disabled? Re: I.MX R1170 SEMC SDRAM interrupt during SRAM access The SEMC sends PRECHARGE ALL command to close any opened page on device before sending AUTO REFRESH command. So if the Auto-refresh is disable then both commands will not be executed. This is disabled on SDRAMCR3[REN] field.  Please consider that if refresh is not done with the sdram timings it may cause loosing some data on the sdram.  Best regards, Omar Re: I.MX R1170 SEMC SDRAM interrupt during SRAM access Hi @Omar_Anguiano  >>Which specific command of the SDRAM is interrumping the SRAM access?  I checked the interruption and it was "Precharge All Banks" and "Auto Refresh".  Is it possible to prevent these SDRAM interruptions? Which setting is causing this behavior? Re: I.MX R1170 SEMC SDRAM interrupt during SRAM access Which specific command of the SDRAM is interrumping the SRAM access?  The goal of having BMCR to 0x81 is to avoid re-ordering of the command queue so the commands are executed under "first in first out" policy.  UT and RT are suggested to stay the same, changing them to the highest refresh period possible by the memory might reduce the interruption of SDRAM as I suspect that the interruption is the auto-refresh command.  Best regards, Omar Re: I.MX R1170 SEMC SDRAM interrupt during SRAM access Hi @Omar_Anguiano  >>adjusting the timing of SDRAM refresh is crucial to prevent this. I'm using Auto Refresh so, I tried to adjust SDRAMCR3[31-1], for example changed to UT = RT or UT < RT.  However the result was same, there are still interruption of SDRAM. How can I avoid the interruption?  BMCR are set to 0x81. Re: I.MX R1170 SEMC SDRAM interrupt during SRAM access Hi Thank you for your information. But how can I adjust the timing of SDRAM refresh? Should I change UT[31-24] value?  Currently I set UT[31-24] and RT[23-16] on SDRAMCR3 as same value because NXP recommended.  BMRC registers are 0x81. Re: I.MX R1170 SEMC SDRAM interrupt during SRAM access I believe that the interruption of SDRAM is due to the auto-refresh command, so adjusting the timing of SDRAM refresh is crucial to prevent this. Also implementing different settings on the BMRC registers might be helpful, I suggest the setting of 0x81 to prevent re-ordering of the commands. Best regards, Omar
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Stresstest fails at 3 frequencypoints but passes with 1 frequencypoint, LPDDR4 Hello everyone, I had asked a similar question when i used the mScale DDR Test Tool and that error was resolved when switched to ConfigTool V15. I am currently working on a board bring-up with the following combination of SOC, RAM and Software for the RAM-Stresstest: - i.MX 8M Plus (1600 MHz) + Micron LPDDR4 4GB (MT53D1024M32D4DS) - iMX Config Tool v24.12 I have used the NXP RPA Excel sheet for generating the according ".ds"-file for the Stresstest program. Also using the standard parameters in the "DDR Configuration Sheet" results in the same error.  The question is as following: Why does the Stresstest run smoothly and without errors, even under temperature fluctuations, when chosing 2000 MHz as the single frequency for the test, but fails when i chose the same parameterset, but now with three frequency points enabled. In that case the default, additional 200 MHz and 50 MHz, are tested as well.  Any help is hugely appreciated Greetings Niko i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Re: Stresstest fails at 3 frequencypoints but passes with 1 frequencypoint, LPDDR4 Hello, If selecting a frequency range to test, ensure that the start frequency test is within ±50MHz of the frequency that the DDR initialization script is tuned for and make sure end frequency is no less than start frequency and within 100Mhz of the start frequency. Best regards. Re: Stresstest fails at 3 frequencypoints but passes with 1 frequencypoint, LPDDR4 I have already extensively tested the ODT, PDDS, Vref etc. For our highest target frequency i can get the stresstest running succesfully, without errors, when its the only tested frequency -> i assume our layout is good, because the most critical operating point works. Also in the first test run when 200 and 50 MHz are enabled. Only from the second run errors arrise in the highest frequency operating point as well -> i assume some the firmware or the Config Tool dont work as expected: So you´d test the 2000 MHz/200 MHz and 50 MHz seperately and then just enable the 3 frequencies in the RPA sheet?  Re: Stresstest fails at 3 frequencypoints but passes with 1 frequencypoint, LPDDR4 Hello, It is suggested to run the stress test at the target operating frequency for an extended period of time to verify the DDR performance on the target board. Running the stress test higher/lower than the target operating frequency is not meaningful. The signal waveform may change a lot as the frequency increases/decreases. Therefore, passing the stress test at a frequency higher/lower than the target operating frequency does not necessarily mean that there is more timing margin. To pass the stress test you may need to change: ODTImpedance Desired ODT impedance in Ohm. Valid values for DDR4=240,120,80,60,40. Valid values for LPDDR4=240,120,80,60,40 TxImpedance Write Driver Impedance for DQ/DQS in ohm (Valid values for all DDR type= 240, 120, 80, 60, 48, 40, 34) ATxImpedance Write Driver Impedance for Address/Command (AC) bus in ohm (Valid values for all DDR type = 120, 60, 40, 30, 24, 20) Best regards.
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I.MX SRAMアクセス中のR1170 SEMC SDRAM割り込み こんにちは RT1170のSEMCにSDRAM(CS0)とSRAM(CSX1)を接続しています。 CS0 のパルスが Low で CSX1 のパルスが Low になることがあることがわかったのは、SEMC が SRAM にアクセスしている間に SEMC が SDRAM に割り込みアクセスしていたことを意味します。 SRAMにアクセスしながらSDRAMのアクセスを防ぐことは可能ですか? Re: SRAM アクセス中の R1170 SEMC SDRAM 割り込み I.MX はい、自動更新は、更新を実行するために必要な場合は、バーツ操作を中断します。バーストを分割するだけで、その間に自動更新を挿入できます。 よろしくお願いいたします オマル Re: SRAM アクセス中の R1170 SEMC SDRAM 割り込み I.MX はい、自動更新は定期的に実行されます。残念ながら、この特定の実装の例はありません。 よろしくお願いいたします オマル Re: SRAM アクセス中の R1170 SEMC SDRAM 割り込み I.MX SEMC は、AUTO REFRESH コマンドを送信する前に、デバイス上の開いているページを閉じるために PRECHARGE ALL コマンドを送信します。したがって、自動更新が無効になっている場合、両方のコマンドは実行されません。これは SDRAMCR3[REN] フィールドで無効になっています。 SDRAM のタイミングでリフレッシュが行われないと、SDRAM 上の一部のデータが失われる可能性があることを考慮してください。 よろしくお願いいたします オマル Re: SRAM アクセス中の R1170 SEMC SDRAM 割り込み I.MX SDRAMのどのコマンドがSRAMアクセスを妨害していますか。 BMCR を0x81する目的は、コマンドが「先入れ先出し」ポリシーで実行されるように、コマンド・キューの順序変更を回避することです。 UTとRTは同じままにしておくことをお勧めしますが、メモリによって可能な限り高いリフレッシュ期間に変更すると、中断が自動更新コマンドであると疑われるため、SDRAMの中断を減らすことができます。 よろしくお願いいたします オマル Re: SRAM アクセス中の R1170 SEMC SDRAM 割り込み I.MX SDRAMの中断は自動更新コマンドによるものと考えており、これを防ぐためにはSDRAMの更新タイミングを調整することが重要です。 また、BMRCレジスタに異なる設定を実装すると役立つかもしれませんが、コマンドの並べ替えを防ぐために0x81を設定することをお勧めします。 よろしくお願いいたします オマル
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MC9S12XEP100 Flash burner question MC9S12XEP100. Code Warrior 5.9.0, single chip, absolute assembler. I have a program, similar to the one I wrote using the MC9S12C64, but larger and more complex. I couldn't figure out the flash burner process for that one until I posted the question and Ladislav was able to explain it to me with his C64-FLASH-ASM test program. Using that I was able to get my program to work just fine. Now I am having the same issue using the MC9S12XEP100 processor. I was hoping there would be enough similarities in the process that I could adapt what I learned, but I'm having some difficulties. Is there a test program similar to the C64-FLASH-ASM, but specific to the MC9S12XEP100 in single chip, absolute assembler that I could study and see if I could get that to work? I'm attaching a basic test code that I am using to troubleshoot. Regards, Robert   Re: MC9S12XEP100 Flash burner question Hi Ladislav, Thanks so much for your detailed response. There are still a few minor errors in your comments, but no matter, I'm quite sure I know what you are doing and they really helped. Your screen shots of the memory window were a big revelation to me. I didn't know about the l, g and r suffix. That explains a lot. The spread sheet that compares the equivalent addresses also really helped in my education. I now feel I have a good understanding of what you have done and a better understanding of what the debugger can do. As a result of my new found knowledge I am realizing that I should be using EEPROM emulation. I have some questions about that in a separate thread.  Thanks once more for all your help and patience. Regards, Robert Re: MC9S12XEP100 Flash burner question Hi, I have found my notes contain copy/paste mistakes. I am not sure what are you looking at so more detailed comments. Moreover, I suppose the DFLASH is in erased status before it is written. Moreover, the question is how the RAM content is refreshed in your memory window. You should also check the setup lime it is done for DFLASH. The address 0x2100 is selected by compiler so the array is placed: Buffer[0] is at address 0x2100,0x2101    of a  local address space Buffer[1] is at address 0x2102,0x2103 Buffer[2] is at address 0x2104,0x2105 Buffer[3] is at address 0x2106,0x2106 Finally, it is good to understand local and global address space. The RAM 0x2100 is in local address space 0x2100 and in the global address space 0x0F_E100. Si memory map in attachment. ... and be careful when you show address space ... extension 'G  or 'L. For example 0FE100'G and 2100'L represents the same address from different views.    .... does no exist  .... the variable "buffer" in a local address space  ... the variable "buffer" in a global address space better comments of the original asm code..            ;---------------------------             ;err = DFLASH_Program(0x0000, &buffer[0], 4); //write 4 words to D Flash address 0x10_0000             ; GPAGE (0x10_.... ) is not used in the Addr variable because it is directly used in the DFLASH_Program routine             MOVW  #$0000,Addr  ; address to be written 0x(10)0000~0x(10)0007                        MOVB  #4,Cnt       ; number of words to be written             ;for example data to be written into DFLASH are 0x0123, 0x4567, 0x89AB, 0xCDEF             ; written global DFLASH address is 0x10_0000’G   … for data visualization in a debugger memory             ; window“ ’G ” must be added into memory address             LDX   #Buffer      ; Load the base address of the array into X register, the base address                                              ; is selected by compiler if you do not set exact address             LDD  #$0123      ; Load the hexadecimal value 0x0123 into D register             STD  0,X                ; Store the value at the 0th position of the array;  Buffer[0] = 0x0123             LDD  #$4567      ; Load the value 0x4567 into D register             STD  2,X                ; Store the value at the 1st position of the array;  Buffer[1] = 0x4567             LDD  #$89AB      ; Load the value 0x89AB into D register             STD  4,X                ; Store the value at the 2nd position of the array;  Buffer[2] = 0x89AB             LDD  #$CDEF     ; Load the value 0xCDEF into D register             STD  6,X                ; Store the value at the 3rd position of the array;  Buffer[3] = 0xCDEF             CALL  DFLASH_Program  ; note there is a status of verification in the Err variable after execution of this command             ;---------------------------             ;err = DFLASH_Program(0x0008, &buffer[0], 4); //write 4 words to eeprom address 0x0000             ;… at this place you should check whether Err value is OK to be sure entire write process has             ;     finished correctly. I am not doing it in this example.             ;---------------------------             ; write another set of data to a 8 bites higher address of the DFLASH             ; written global DFLASH address is 0x10_0008’G             MOVW  #$0008,Addr  ; address to be written  0x(10)0008~0x(10)000F                        MOVB  #4,Cnt       ; number of words to be written                        ;for example data to be written into DFLASH are 0xDEAD,0xBEEF,0xC0DE,0xCAFE             LDX   #Buffer      ; Load the base address of the array into X register, the base address                                              ; is selected by compiler if you do not set exact address             LDD  #$DEAD     ; Load the hexadecimal value 0xDEAD into D register             STD  0,X                ; Store the value at the 0th position of the array;  Buffer[0] = 0x0123             LDD  #$BEEF      ; Load the value 0xBEEF into D register             STD  2,X                ; Store the value at the 1st position of the array;  Buffer[1] = 0x4567             LDD  #$C0DE      ; Load the value 0XC0DE into D register             STD  4,X                ; Store the value at the 2nd position of the array;  Buffer[2] = 0x89AB             LDD  #$CAFE     ; Load the value 0xCAFE into D register             STD  6,X                ; Store the value at the 3rd position of the array;  Buffer[3] = 0xCDEF             CALL  DFLASH_Program  ; note there is a status of verifiction in the Err variable after execution of this command             ;---------------------------             ;err = DFLASH_Program(0x0008, &buffer[0], 4); //write 4 words to eeprom address 0x0000             ;… at this place you should check whether Err value is OK to be sure entire write process has             ;     finished correctly. I am not doing it in this example.             ;--------------------------- Best regards, Ladislav Re: MC9S12XEP100 Flash burner question Hi Daniel, Freescale USBDM (from China). I use it successfully to load programs. Does that answer your question? Regards, Robert Re: MC9S12XEP100 Flash burner question Hi Robert, I mean debugger like PE Micro Multilink (with revision), USBDM, ... Re: MC9S12XEP100 Flash burner question Hi Daniel, Code Warrior IDE V5.9.0 Build 5294 Special Edition. Regards, Robert Re: MC9S12XEP100 Flash burner question Hello @roberthiebert, What debugger do you use? The debugger can interpret the data as 0xCAFE because of ECC, for example. Regards, Daniel Re: MC9S12XEP100 Flash burner question I've spent a lot of time stepping through this code and recording all the variable and register states on each step. I think I have a pretty good understanding of what is happening here, but one thing in particular still has me puzzled. In this section of code: LDX #Buffer ; Load the base address of the array into X register LDD #$0123 ; Load the value 0123 into A register STD 0,X ; Store the value at the 0th position of the array X is loaded with $2100, the address of "Buffer" in RAM D is loaded with decimal 0123 Decimal 0123 is copied into the first two bytes of the "Buffer" array at address $2100 in RAM. Now, when I use the debugger to check the contents of RAM address $2100 I see $CA, $FE in the first two bytes, and they never change. Why is this and where are the example words stored? Regards, Robert  Re: MC9S12XEP100 Flash burner question Hi, The topic has already been processes... https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12-X-MCU-Security/ta-p/1111118 https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Unsecuring-MC9S12XEP100MAG/m-p/617603 Best regards, Ladislav Re: MC9S12XEP100 Flash burner question Hi Ladislav, One more thing. I did some more research and I understand that in order for CW to be able to read the D-Flash the FSEC register needs to be set to $FE. I see that your code has done this, but I can't find out where and how you did it. Could you explain how I can do that in my code  please? Regards, Robert Re: MC9S12XEP100 Flash burner question Hi Ladislav, I have made some progress. To make a long story short, I discovered that my controller was secured. I don't know how that happened, but I was able to unsecure it and now your program is working the way you have shown in your last post. Now I am able to study your ASM code to make sure I understand it fully before I try to adapt  it it work in my code. I have one thing that is puzzling me though. If I am understanding you r code correctly, you have placed your test data to be burned to D-Flash, in RAM memory starting at Buffer: (address $2100). But when I look at that address all I ever see is $CA,$FE, repeat.  Why is this? Regards, Robert  Re: MC9S12XEP100 Flash burner question I have the memory set to refresh on halt, but no matter what I do, the memory never changes. I've tried setting breakpoints where I see you have highlighted, but nothing. I tired running the program and halting it at random points. No change. What am I doing wrong? Re: MC9S12XEP100 Flash burner question Hi, Do not step memory functions if the part of memory is displayed in the memory window of the debugger. Set refresh memory when halting First loop Second loop … after erase sector Second loop after writing data Second loop reading the data       Moreover, it is always suitable to disable possible interrupts to do not change registers. Create critical section which is not interrupted using CLI, SEI. Best regards, Ladislav Re: MC9S12XEP100 Flash burner question Hi again Ladislav, After stepping through the program again several times I noticed some other peculiar things. After running the FLASH_ERASE_VERIFY subroutine the returned "err" was $01. Which was expected. However, after any FLASH_PROGRAM subroutine "returned "err" was $40. The FLASH_READ  subroutine seems to work but it doesn't return the var_Data values I expected. It returns $FA, $CF first. $4 second. $BB $B6 third.  $46 $46 forth. The values at address $100000 are $FA, $CF, $00,$04,$BB, $B6, $46, $46. These are not the values that should have been burned to this address if I am understanding the program correctly. The values at address $2100 are $CA,$FE,$CA,$FE,$CA,$FE,$CA,$FE and they don't change. Something seems odd here. Regards, Robert  Re: MC9S12XEP100 Flash burner question Hi Ladislav, Thank you for that excellent attachment. It was just what I was looking for. It runs just fine on my controller, except for one thing. I can't seem to get the debugger to update the memory window, either for the RAM or the D-Flash. I when I single step through the program I expected to see the RAM addresses from $2100 to $2110 update with the appropriate steps. I'm not seeing this. I also expected to see the D-Flash addresses from $10000 to $100010 update as I step through, but I'm not seeing that either. Also, if I run the program and halt it, the memory locations are not updated. Are there some settings in the de-bugger that I don't have set right? Regards, Robert Re: MC9S12XEP100 Flash burner question I am very sorry but I see no issue to rebuilt C to ASM. C shows you principle and this C code is not a object oriented programming. It is simple Ansi C. Here you can see programming of D-Flash. (Not P-Flash, it is a little bit different but in principle very similar) ;************************************************************** ;* This stationery serves as the framework for a * ;* user application. For a more comprehensive program that * ;* demonstrates the more advanced functionality of this * ;* processor, please see the demonstration applications * ;* located in the examples subdirectory of the * ;* Freescale CodeWarrior for the HC12 Program directory * ;************************************************************** ; Include derivative-specific definitions INCLUDE 'derivative.inc' ; export symbols XDEF Entry, _Startup, main ; we use export 'Entry' as symbol. This allows us to ; reference 'Entry' either in the linker .prm file ; or from C/C++ later on XREF __SEG_END_SSTACK ; symbol defined by the linker for the end of the stack ;********************************************************************* OK EQU 0 ERASED EQU 1 NON_ERASED EQU 2 LENGTH_OUT_OF_RANGE EQU 3 ;********************************************************************* ; variable/data section MY_EXTENDED_RAM: SECTION ; Insert here your data definition. Buffer ds.w 4; Err ds.b 1; Addr ds.w 1; Cnt ds.b 1; var_i ds.b 1; var_j ds.b 1; var_Data ds.w 1; ;********************************************************************* ; code section MyCode: SECTION main: _Startup: Entry: ;--------------------------- LDS #__SEG_END_SSTACK ; initialize the stack pointer CLI ; enable interrupts ;--------------------------- EndlessLoop: ;--------------------------- ;EE_Init ... 0x0F //oscillator 16MHz -> divide by 0x0F to achieve FCLK 800kHz - 1.05MHz ;while(FSTAT_CCIF == 0); //wait if command in progress BRCLR FSTAT,#128,*+0 ;abs = 0001 ;FCLKDIV = fdiv; //osc = 16MHz LDAB #$0F STAB FCLKDIV ;--------------------------- ;DFLASH_Erase_Sector(0x0000); //erase first sector (256 bytes) MOVW #$0000,Addr CALL DFLASH_Erase_Sector ;--------------------------- ;err = DFLASH_Erase_Verify(0x0000, 16); //check if 16 words are erased - we will receive ERASED message MOVW #$0000,Addr MOVB #16,Cnt CALL DFLASH_Erase_Verify ; note there is a status of verification in the Err variable after execution of this command ;--------------------------- ;err = DFLASH_Program(0x0000, &buffer[0], 4); //write 4 words to D Flash address 0x0000 MOVW #$0000,Addr ; address to be written MOVB #4,Cnt ; number of words to be written ;for example data to be written into DFLASH are 0123, 4567, 89AB, CDEF LDX #Buffer ; Load the base address of the array into X register LDD #$0123 ; Load the value 0123 into A register STD 0,X ; Store the value at the 0th position of the array LDD #$4567 ; Load the value 4567 into A register STD 2,X ; Store the value at the 1st position of the array LDD #$89AB ; Load the value 89SB into A register STD 4,X ; Store the value at the 2nd position of the array LDD #$CDEF ; Load the value CDEF into A register STD 6,X ; Store the value at the 3rd position of the array CALL DFLASH_Program ; note there is a status of verifiction in the Err variable after execution of this command ;--------------------------- ;err = DFLASH_Program(0x0008, &buffer[0], 4); //write 4 words to eeprom address 0x0000 MOVW #$0008,Addr ; address to be written MOVB #4,Cnt ; number of words to be written ;for example data to be written into DFLASH are 0123, 4567, 89AB, CDEF LDX #Buffer ; Load the base address of the array into X register LDD #$DEAD ; Load the value 0123 into A register STD 0,X ; Store the value at the 0th position of the array LDD #$BEEF ; Load the value 4567 into A register STD 2,X ; Store the value at the 1st position of the array LDD #$C0DE ; Load the value 89SB into A register STD 4,X ; Store the value at the 2nd position of the array LDD #$CAFE ; Load the value CDEF into A register STD 6,X ; Store the value at the 3rd position of the array CALL DFLASH_Program ; note there is a status of verifiction in the Err variable after execution of this command ;--------------------------- ; get written data ;--------------------------- MOVW #$0000,Addr CALL DFLASH_Read STD var_Data MOVW #$0002,Addr CALL DFLASH_Read STD var_Data MOVW #$0004,Addr CALL DFLASH_Read STD var_Data MOVW #$0006,Addr CALL DFLASH_Read STD var_Data ;--------------------------- JMP EndlessLoop ; restart. ;--------------------------- ;********************************************************************* ;DFLASH_Read ;********************************************************************* DFLASH_Read: MOVB #$10, GPAGE LDX Addr GLDD X RTC ;********************************************************************* ;DFLASH_Program ;********************************************************************* DFLASH_Program: ;if((Cnt < 1) || (Cnt > 4)) LDAB Cnt CMPB #1 BCS LBL_DP1 CMPB #4 BLS LBL_DP2 ;return LENGTH_OUT_OF_RANGE; LBL_DP1: MOVB #LENGTH_OUT_OF_RANGE,Err RTC LBL_DP2: ;while(FSTAT_CCIF == 0); //wait if command in progress BRCLR FSTAT,#128,*+0 ;abs = 000e ;FSTAT = 0x30; //clear ACCERR and PVIOL MOVB #$30, FSTAT ;FCCOBIX = 0x00; CLR FCCOBIX ;FCCOB = 0x1110; MOVW #$1110,FCCOB ;FCCOBIX = 0x01; MOVB #$1,FCCOBIX ;FCCOB = address; MOVW Addr,FCCOB ;for(i=2; i<=Cnt+1; i++) //fill appropriate number of words to FCCOB CLRA LDX #Buffer LDAB Cnt INCB STAB var_j ; end variable of cycle LDAA #$2 ; start value of cycle LBL_DP3: ;FCCOBIX = A = 2 to {3,4,5}; STAA FCCOBIX ;FCCOB = *ptr; LDD 2,X+ STD FCCOB LDAA FCCOBIX INCA CMPA var_j BLS LBL_DP3 ;FSTAT_CCIF = 1; //launch command BSET FSTAT,#128 ;while(FSTAT_CCIF == 0); //wait for done BRCLR FSTAT,#128,*+0 ;abs = 004b ;return OK; MOVB OK,Err RTC ;********************************************************************* ;DFLASH_Erase_Verify ;********************************************************************* DFLASH_Erase_Verify: ;while(FSTAT_CCIF == 0); //wait if command in progress BRCLR FSTAT,#128,*+0 ;abs = 0001 ;FSTAT = 0x30; //clear ACCERR and PVIOL MOVB #$30,FSTAT ;FCCOBIX = 0x00; CLR FCCOBIX ;FCCOB = 0x1010; MOVW #$1010, FCCOB ;FCCOBIX = 0x01; MOVB #$1, FCCOBIX ;FCCOB = address; MOVW Addr, FCCOB ;FCCOBIX = 0x02; MOVB #$2, FCCOBIX ;FCCOB = number_of_bytes; MOVB Cnt,FCCOB ;FSTAT_CCIF = 1; //launch command BSET FSTAT,#128 ;while(FSTAT_CCIF == 0); //wait for done BRCLR FSTAT,#128,*+0 ;abs = 002b ;if(FSTAT_MGSTAT == 0) BRCLR FSTAT,#3,*+7 ;abs = 0037 BRA lbl_nonerased ;return ERASED; MOVB #ERASED, Err RTC lbl_nonerased: ;return NON_ERASED; MOVB #NON_ERASED, Err RTC ;********************************************************************* ;void DFLASH_Erase_Sector(unsigned int address) ;********************************************************************* DFLASH_Erase_Sector: ;while(FSTAT_CCIF == 0); //wait if command in progress BRCLR FSTAT,#128,*+0 ;abs = 0001 ;FSTAT = 0x30; //clear ACCERR and PVIOL MOVB #$30, FSTAT ;FCCOBIX = 0x00; CLR FCCOBIX ;FCCOB = 0x1210; MOVW #$1210, FCCOB ;FCCOBIX = 0x01; MOVB #$1, FCCOBIX ;FCCOB = address; MOVW Addr,FCCOB ;FSTAT_CCIF = 1; //launch command BSET FSTAT,#128 ;while(FSTAT_CCIF == 0); //wait for done BRCLR FSTAT,#128,*+0 ;abs = 0022 RTC ;********************************************************************* ;********************************************************************* ;********************************************************************* ;********************************************************************* ;********************************************************************* Re: MC9S12XEP100 Flash burner question I'm still working hard at trying to figure this "C" code out but getting nowhere. The code runs and says that the first 256 bytes in D Flash have been erased at $10_0000, but I don't see that. Then it says that buffer[0] has been written into $0_0000, $10_0008 and $10_0010, But I don't see that either. What am I missing here? Regards, Robert Re: MC9S12XEP100 Flash burner question I'm still not getting anywhere with this. I've tried to figure out the ASM by stepping through the code, but I really have to be able to understand what the program is doing in "C" first. I believe that it partitions the DFlash then erases it all. Then it writes 16 bytes that it had written into RAM into D FLash. I can find the bytes in RAM, but in no place in D Flash can I find where it has written them in.  Any suggestions would be greatly appreciated. Regards, Robert Re: MC9S12XEP100 Flash burner question Hi Ladislav, This is not easy stuff for me, but I was able to load your XEP100-DFLASH-CW47 program into my controller using a USBDM. I believe the program is running correctly. I expected to see the D-Flash address from $10_0000 loaded with $12, $34, $56, $78 $9A, $BC, $DE, $F0, but nothing is there. I also expected to see each of the remainder of the 256 byte sector loaded with $FF.  Perhaps my understanding of how the program is supposed to work is flawed? Regards, Robert Re: MC9S12XEP100 Flash burner question Hi Ladislav, Thanks again for your prompt reply and the files. I am not a "C" engineer and only have a basic knowledge of the language so the disassembly process will be challenging, but I'll give it my best shot. Regards, Robert Re: MC9S12XEP100 Flash burner question Hi, there are no similarities. It is 2 levels higher MCU with different memory organization. In this case I suggest to use DFLASH for data storage. There is no ASM code available but I believe it is not any problem to do it by disassembling C code. If you are C coding engineer it must be easy for you to rebuilt it to asm. Here is a C code and the project is attached. You can go/step through the ASM code in debugger to see how it works. I have also attached C code for PFLASH programming. Nothing easier but it does not require to  perform partitioning of this memory. There are some similarities in addresses but global address must be used for data E/W. Short (4000-7FFF) and PPAGE_Offset addresses are used for program execution. In the case of the MCU it will require more effort to understand how flash is organized and how it works. Moreover, to go from relocatable assembly of the single file project to the absolute assembly is easy. Directive EQU is used for data placement into RAM and ORG is used to place code in given PFLASH space. What is necessary to be understand is that for reading and writing DFLASH the global address must be used. However in the case of this memory it is solved easily because it has higher word (DPAFE ) always 0x10 so it is enough to send to the routine only offset in the range 0000-7FFF and full address is created in routine, for example DFLASH_Program.. I am sorry we do not have any empty space, resources or responsibility for such complex projects … plus in assembler. Best regards, Ladislav Re: MC9S12XEP100 Flash burner question Oops. I forgot to mention that when I try to erase the sectors I get an Access Error code. Regards, Robert Re: MC9S12XEP100 Flash burner question I'll try the attachment again
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S32K1xx:Frequent access to eeprom sends hardfault Hello,     In the development process encountered a problem, frequent access to the S32K118 analog eeprom sent hardfault, I know frequent write eep without delay will occur errors, frequent read will also? The snippet code is as follows:     for (uint8 i = 0; i < 16u; i++)     {         u8slog[i] = *((uint8 *)(0x14000000) + i) ;     } Re: S32K1xx:Frequent access to eeprom sends hardfault Hi @ZEROOO, Reading the FlexRAM does not require any delay, even in the EEE mode, it is just an SRAM. But instead of valid data, the read access can return all 0xFF if there is an ECC error in the backup flash. So, the application should check if the data are valid before they are processed further. Writing does not require any delay per se, it requires the CCIF flag to be set before the FlexRAM in the EEE mode can be written. Regards, Daniel Re: S32K1xx:Frequent access to eeprom sends hardfault Hello, Yes, frequent reads from the S32K118's analog EEPROM, even without writes, can potentially lead to issues and even hard faults. Here's a breakdown of why and how to mitigate it: Understanding the S32K118 Analog EEPROM Not a Standard Memory: The analog EEPROM on the S32K118 is not like standard RAM or flash. It's an emulated EEPROM using flash memory, and it has specific characteristics that must be considered. Limited Endurance: Even read operations can contribute to the wear and tear of the underlying flash memory cells. While reads don't cause the same level of stress as writes, repeated reads over time can still degrade the flash. Access Timing: The analog EEPROM access, especially reads, might require specific timing considerations. If reads are performed too rapidly without allowing sufficient time for the memory to stabilize, it can lead to errors. Bus Conflicts: Very frequent reads can potentially cause bus conflicts or timing issues, especially if other peripherals or processes are also accessing the memory bus. This can manifest as a hard fault. Why Frequent Reads Can Cause Issues Flash Wear (Though Minor): While writes are the primary cause of flash wear, repeated reads can also contribute, albeit to a much lesser extent. The flash memory cells are still subjected to electrical stress during read operations. Timing and Bus Contention: The memory controller needs time to access and retrieve data from the flash memory. If reads are performed too rapidly, it might not be able to keep up, leading to data corruption or bus errors. If other peripherals are also accessing the memory bus, frequent reads can exacerbate bus contention, potentially leading to hard faults. Potential for Software Errors: If the read operation is not handled correctly in the software, it can lead to errors. For example, reading beyond the valid address range or not checking for errors can cause issues. Analyzing Your Code Snippet for (uint8 i = 0; i < 16u; i++) { u8slog[i] = *((uint8 *)(0x14000000) + i); } This code reads 16 bytes sequentially from the analog EEPROM address range starting at 0x14000000. If this code is executed very frequently without any delays, it could contribute to the problems mentioned above. Mitigation Strategies Introduce Delays: Add small delays between read operations to allow the memory controller to stabilize. The necessary delay will depend on the specific characteristics of the S32K118's analog EEPROM. Example:   #include "S32K118.h" // Include header file for delay functions. for (uint8 i = 0; i < 16u; i++) { u8slog[i] = *((uint8 *)(0x14000000) + i); //Add a small delay. for(volatile uint32_t delay = 0; delay < 1000; delay++){} //example delay. } Note that the delay amount will need to be tuned for your specific application. Using a timer based delay is preferable to a simple loop delay. Read Less Frequently: If possible, reduce the frequency of read operations. Cache the data in RAM if it doesn't change frequently. Check for Errors: Implement error checking to detect any read errors. The S32K118 might have status registers or flags that indicate memory access errors. Optimize Bus Usage: Minimize bus contention by optimizing the timing of other peripheral accesses. If possible, use DMA to reduce the CPU load during memory access. Refer to the Datasheet: Consult the S32K118 datasheet and reference manual for specific timing requirements and recommendations for analog EEPROM access. Verify Address Range: Ensure that the address range that you are reading from is valid. Reading from an invalid address range will cause a hardfault.
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