提交NDA申请后一般多久可以签？ 我已经在https://support.nxp.com/s提交了NDA申请（服务申请: 00624736），得到过一次答复说已经提交给法务了，但是过去1周了，没有进一步消息，也不清楚是不通过还是法务还没审核？ 一般签这个NDA需要多长时间呢？

LTE Coexistence with IW416 Hi, Would like to check if LTE Coexistence is supported with IW416? Thanks, Pankaj Re: LTE Coexistence with IW416 hi Weidong, Can you please also calrify the LTE Coexistence for 88W9098 and IW610 chips? Thanks in advance. Thanks, Pankaj Re: LTE Coexistence with IW416 Dear @pankaj , Yes, LTE Coexistence is supported. Below is abstracted from datasheet, check it, please! 1. Coexistence descriptions in datasheet 2. Coexistence overview -- An application note  https://www.nxp.com/products/IW416 If you can't access the document, it means that you don't have access right. It is Secure File. you need these 2 steps to get authentication  from product manager. --NDA with NXP --Applying for access rights. Login nxp website--->My NXP Account--->Secure Files--->Filling out information following guidance---submit --->waiting for approval from product manager. Thanks! Regards, weidong

S32K342チップコアのロックステップステータスを取得する方法 こんにちは： S32K342チップがロックステップチップであることを知りましたが、お客様はこのチップのロックステップステータスを取得することに夢中になっています。機能的なセキュリティ要件があるため、S32K342チップのロックステップ機能がオンになっていることを確認する必要がありますので、このチップのロックステップステータス、レジスタまたはフラッシュメモリに保存されている情報を取得する方法を尋ねたいと思います。                                                                                                                                          最高の後悔。 Re:S32K342チップコアのロックステップステータスを取得する方法 ありがとうございました。これが私が欲しい答えです。 Re:S32K342チップコアのロックステップステータスを取得する方法 Hi@xinglong レジスターをご覧ください:DCM_GPR 「DCMROF19」 レジスタ ビット 29 (ビット LOCKSTEP_EN): 0 = デカップリング・モード 1 = ロックステップ・モード

USB0 host mode downstream ports Hello NXP Experts, on p57, Rev. 2.3 of LPC55S2X_LPC552X datasheet it states the following: Section 7.23.1.2 USB0 host controller: Features: "Two downstream ports" Could you please detail what this means? can two devices be connected to same PHY? where can i find more info either as a code or appnote? Thanks in advance! Re: USB0 host mode downstream ports Hello @diego_charles : Thanks a lot for clarification! Re: USB0 host mode downstream ports Hi @manuela_mendez  Thank you for your reply,  Bascially, the number of downstream ports indicated by the datasheet is the  number of physical downstream ports supported by the USB0 in  host controller mode. Below some screenshots of descriptions and diagrams that I found by checking  the USB 2.0 specification, please take a look at its terminology. Personally, I found this figure more explanatory.  Taking the information from above, I  like to see it this more  practical way: according to the spec and the DS specification , we should be able to connect to the host controller a  HUB with  two devices attached to it. Each device would be a downstream port, which upstreams data. I hope this helps, if you are facing any particular issues with your application and our LPC55xx MCU feel free create another thread and we will be happy to check. Diego

I2C Scanner using Processor Expert for S32K146EVB Hello I am working on I2C Scanner by using S32K146EVB using Processor Expert. I am able to initialize I2C and while reading the Acknowledge, it is giving a problem. I have attached my file for your kind reference.. I hope to hear from you soon.. @VaneB @Senlent  Re: I2C Scanner using Processor Expert for S32K146EVB Hi Nibesh, Sorry for not testing it for you in the previous question I2C Scanner using S32K146EVB-Q144. But as I mentioned there, since the LPI2C_init of S32K146_Project_LPI2C configure MCFGR1[IGNACK] to Ignore NACK by default, and its LPI2C_Transmit uses MTDR[CMD]=5 by default:101b  Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. So you can't judge the acknowledgement by polling MSR[NDF](NACK Detect Flag). Please try to test the following code: void LPI2C_Transmit (uint8_t address)/* Transmit ID and expects an ACK to be returned */ { LPI2C0->MTDR = (0x04<<8)|((address<<1)|0); } LPI2C_DRV_MasterInit(0, &lpi2c1_MasterConfig0, &lpi2c1MasterState); LPI2C0->MCFGR1 |= LPI2C_MCFGR1_AUTOSTOP_MASK; //Automatic STOP Generation        for(i=1; i<127; i++)        { //       LPI2C_DRV_MasterSetSlaveAddr(INST_LPI2C1, i, false);        LPI2C_Transmit(i);        delay(100);         if((((LPI2C0->MSR) & LPI2C_MSR_NDF_MASK) >> LPI2C_MSR_NDF_SHIFT)==true)         {         LPI2C0->MSR &= LPI2C_MSR_NDF_MASK;         LPUART_DRV_SendDataBlocking(INST_LPUART2, Space, sizeof(Space), TIMEOUT);         }         else         { sprintf( Buffer,"0x%X", i); LPUART_DRV_SendDataBlocking(INST_LPUART2, Buffer, sizeof(Buffer), 10000);         }        } Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

NDA 申請を提出してから署名を得るまでに通常はどのくらいの時間がかかりますか? https://support.nxp.com/s に NDA リクエストを送信しました (サービスリクエスト:00624736に申請したところ、法務部に提出済みとの返信をいただきましたが、1週間経っても何の連絡もありません。却下されたのか、法務部がまだ確認していないのか、はっきりしません。 このNDAに署名するには通常どのくらい時間がかかりますか?

USB0 主机模式下行端口 您好，恩智浦专家， 在第 57 页，修订版LPC55S2X_LPC552X 数据表 2.3 版指出以下内容： 第 7.23.1.2 节USB0 主机控制器：功能：“两个下游端口” 你能详细说明一下这是什么意思吗？两个设备可以连接到同一个 PHY 吗？我可以在哪里找到更多信息（例如代码或应用说明）？ 提前感谢！ 回复：USB0 主机模式下行端口 你好@diego_charles ：非常感谢你的澄清！

使用处理器专家的S32K146EVB I2C扫描仪 您好，我正在使用 Processor Expert 使用 S32K146EVB 开发 I2C 扫描仪。 我能够初始化 I2C，但在读取确认时，出现了问题。 我已附上我的文件供您参考。 我希望很快收到您的回复。 @VaneB @Senlent

Network error on s32g QNX7.1 Dear NXP, I am running QNX7.1 on S32G-VNP-RDB2, but there are problems with the network. The NIC dwc0 is identified after the system starts, I configured a valid ip for it. But it can not ping other machines(return info: "ping: sendto: Host is down"), and no machine could ping the board. Could you please suggest, is there any other work that needs to be done here. Thank you for your support. Re: Network error on s32g QNX7.1 Hello, Check with QNX since this works with the NXP BSP, Regards

如何获取S32K342芯片内核的锁步状态 你好： 我了解到S32K342芯片是一款锁步芯片，但我的客户却痴迷于获得这款芯片的锁步状态。因为他们有功能安全的需求，必须保证S32K342芯片的锁步功能是开启的，所以想问一下如何获取这个芯片的锁步状态，寄存器或者闪存中保存的信息。 最好的遗憾。 回复：如何获取S32K342芯片核心的锁步状态 非常感谢。这就是我想要的答案。 回复：如何获取S32K342芯片核心的锁步状态 嗨@兴隆 请查看寄存器：DCM_GPR“DCMROF19” 寄存器位29（位LOCKSTEP_EN）： 0 = 解耦模式 1 = 锁步模式

imx8mq - configure 4gb memory Dear Nxp engineers,  We have a design based on imx8mq with 3GB DDR - it's working fine.  Now we upgrade it to 4gb memory.  I have been following this link to apply the patch.  https://community.nxp.com/t5/i-MX-Processors/LGE-CTO-booting-failure-with-4G-DRAM-with-OPTE/m-p/1223113 In this link if apply patch and disable OP-TEE, according to the discussion in the link, it should work. But my board would still stuck in "Starting Linux..." Could you help to suggest the proper way to configure 4gb ddr? This is my patch: @@ -18,15 +18,12 @@ }; firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; }; memory@40000000 { device_type = "memory"; - reg = <0x00000000 0x40000000 0 0xc0000000>; + reg = <0x0 0x40000000 0 0xc0000000>, + <0x1 0x00000000 0 0x40000000>; }; pcie0_refclk: pcie0-refclk { diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 08bcb399b1f..0f51fb6ceef 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -163,10 +163,11 @@ CONFIG_SHA384=y CONFIG_EFI_VAR_BUF_SIZE=139264 CONFIG_EFI_IGNORE_OSINDICATIONS=y CONFIG_EFI_CAPSULE_AUTHENTICATE=y -CONFIG_OPTEE=y +CONFIG_OPTEE=n CONFIG_CMD_OPTEE_RPMB=y CONFIG_EFI_MM_COMM_TEE=y CONFIG_TEE=y CONFIG_EFI_ESRT=y CONFIG_EFI_HAVE_CAPSULE_UPDATE=y CONFIG_FIT_SIGNATURE=y +CONFIG_NR_DRAM_BANKS=2 \ No newline at end of file diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 567e120e276..70b44999b6d 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -177,6 +177,8 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_2_SIZE 0x40000000 /* */ #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR Re: imx8mq - configure 4gb memory Thanks Pengyong, this issue is resolved by useing ddr tool to generate new timing file Re: imx8mq - configure 4gb memory Hi @wenyong  You can use our DDR Config Tool configuration the ddr MT53E1G32D2FW parameters, Then the tool will generate the new timing.c file which you can use it compile the new uboot flash.bin file to boot your board. https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/config-tools-for-i-mx-applications-processors:CONFIG-TOOLS-IMX B.R Re: imx8mq - configure 4gb memory Hi @wenyong  OK, this can support 4GB DRAM, Please share your DDR datasheet and schematic file. I will help you configurate the DDR parameters. B.R Re: imx8mq - configure 4gb memory Hi pengyong,  We are using PN# MIMX8MQ6CVAHZAB Thanks, Wenyong Re: imx8mq - configure 4gb memory Hi @pengyong_zhang ,  We use MIMX8MQ6CVAHZAB. Re: imx8mq - configure 4gb memory Hi @wenyong  What is your i.MX8MQ SOC Part number? Because only Quad- A53 can support 4GB DRAM. B.R

S32K3 编译枚举，导致地址发生动态偏移 使用S32DS3.4进行编译，出现如下警告： c:/nxp/s32ds.3.4/s32ds/build_tools/gcc_v10.2/gcc-10.2-arm32-eabi/bin/../lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/bin/real-ld.exe: warning: c:/nxp/s32ds.3.4/s32ds/build_tools/gcc_v10.2/gcc-10.2-arm32-eabi/bin/../lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(lib_a-memcmp.o) uses variable-size enums yet the output is to use 32-bit enums; use of enum values across objects may fail c:/nxp/s32ds.3.4/s32ds/build_tools/gcc_v10.2/gcc-10.2-arm32-eabi/bin/../lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/bin/real-ld.exe: warning: c:/nxp/s32ds.3.4/s32ds/build_tools/gcc_v10.2/gcc-10.2-arm32-eabi/bin/../lib/gcc/arm-none-eabi/10.2.0/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(lib_a-memcpy-stub.o) uses variable-size enums yet the output is to use 32-bit enums; use of enum values across objects may fail 此警告导致全局变量发生地址偏移，如何解决此问题？

USB0 ホスト・モード・ダウンストリーム・ポート こんにちはNXPの専門家、 p57、改訂版。LPC55S2X_LPC552Xデータシートの2.3には、次のように記載されています。 セクション 7.23.1.2USB0 ホスト コントローラー: 機能: "2 つのダウンストリーム ポート" これが何を意味するのか、詳しく説明していただけますか?2つのデバイスを同じPHYに接続できますか?コードまたはAppnoteとして、詳細情報はどこで入手できますか? よろしくお願いいたします！ 日時:USB0ホストモードダウンストリームポート こんにちは@diego_charles:説明してくれてありがとう!

Does the MCU on the evaluation board S32K3X4EVB-Q172 support OTA? Hello, On the schematic of the evaluation board S32K3X4EVB-Q172, the MCU model is S32K344_172MAXQFP. In the S32K3XX data sheet, the mode is defined like this: P/S32K3NNXXT0MPASR.  In the S32K3xx reference manual, the OTA functionality is disabled in CUST_DEL Device Life Cycle. My question is, how to know if the MCU in the evaluation board supports OTA? Thanks! Crane     Re: Does the MCU on the evaluation board S32K3X4EVB-Q172 support OTA? Hi Crane, CUST_DEL: Device (that is, NXP IC) delivered to system integrator (that is, NXP’s customer) for ECU manufacturing and initial configuration. That is to say, the chip on your development board also has this life cycle by default. However, the OTA functionality can be enabled.  I suggest you download S32K3XX HSE and OTA Advance Training from secure file. Also take a look at S32K3_OTA_AB_SWAP_Demostration Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

How long does it usually take to get a signature after submitting an NDA application? I have submitted an NDA request at https://support.nxp.com/s ( Service Request: 00624736), and got a reply saying that it has been submitted to the legal department, but a week has passed and there is no further news. It is not clear whether it was rejected or the legal department has not reviewed it yet? How long does it usually take to sign this NDA? Re: 提交NDA申请后一般多久可以签？ Hi @ZDDL  I am sorry for the inconvenience caused. My coworker is already helping you with this situation in the support ticket, so help me by communicating with her directly through that channel. B.R. VaneB

How to set Lpi2c speed of S32K312 in RTD5.0? Hi NXP: we're developing project with S32K312 and getting I2C speed issue. I set Lpi2c parameters by reference manual and getting correct speed 1Mbit/s by GUI(Lpi2c_setting.png),but I measured I2C speed about clock waveform(LA_I2C_waveform.png) about 2.667Mhz. Is it correct? thanks. attachment: I2C_setting_from_reference_manual.png Lpi2c_setting.png clock_ip_referencepoints.png LA_I2C_waveform.png current environment: MCU:S32K312/100pin S32DS Product:3.5.0.202207261815 RTD S32KXX:RTD5.0.0.202407261948 BR Nelson Re: How to set Lpi2c speed of S32K312 in RTD5.0? Yes, I'm afraid you shouldn't select LPI2C_FASTPLUS_MODE with 1 Mbit/s because the reference manual says so. Re: How to set Lpi2c speed of S32K312 in RTD5.0? Hi Robin: I modified I2C parameters from fast+ mode to fast mode in master mode, and GUI show 400000(Baud rate), but I measured speed about 385Khz. it looks like not accurate about GUI value and LA value, thanks. attachment: 20250306-2-I2C_Test_S32K312.7z BR Nelson Re: How to set Lpi2c speed of S32K312 in RTD5.0? Hi Robin: just now, I saw reference manual as you posted information(LPI2C master mode operation supports up to fast Mode = 400KHz), so S32K312 only supports fast mode in master mode(Up to 400Khz). if I want to adjust more than 400Khz, it is invaild for usage, Is it correct? thanks. BR Nelson Re: How to set Lpi2c speed of S32K312 in RTD5.0? Hi Robin: I always use I2C master mode as LPI2C_FASTPLUS_MODE which support 1 Mbit/s.however, I created simple project by GPIO and I2C function and set I2C parameters as current project, and also tested I2C speed is about 888~914Khz on our PCB board. now you can change MCU package of attachment from 100pin to 172pin for your EVB testing,thanks. attachment: 20250306-I2C_Test_S32K312.7z BR Nelson Re: How to set Lpi2c speed of S32K312 in RTD5.0? Sorry for the inconvenience. It would be best if S32 Design Studio would warn you when you select master mode but exceed 400 kbps data rate. S32K3XXRM mentioned: •LPI2C slave mode operation supports up to high speed mode = 3.4MHz (3.4 Mbps data rate; effective data rate reduces according to I2C protocol). •LPI2C master mode operation supports up to fast Mode = 400KHz (400 kbps data rate; effective data rate reduces according to I2C protocol). Re: How to set Lpi2c speed of S32K312 in RTD5.0? Hi Robin: I tried to change Clock_Ip_ReferencePoints from custom(8Mhz) to AIPS_SLOW_CLK(30Mhz), and also changes I2C timing that it calculated I2C baud rate 1000000. but I measured waveform about 864KHz. now I confuse about calculating result of Lpi2c GUI. please help us, thanks. attachment: clock_ip_referencepoints2.png LA_I2C_waveform2.png Lpi2c_setting2.png BR Nelson Re: How to set Lpi2c speed of S32K312 in RTD5.0? Hi Nelson, The LPI2C_CLK comes from AIPS_SLOW_CLK. So would you please configure AIPS_SLOW_CLK in clock_ip_referencepoints.png? Otherwise, the S32 Configuration Tool may use the wrong frequency (80MHz CUSTOM) for calculation. Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

Hardfault handler log saving I.MXRT1020-EVK board.  MCUXpressoIDE 24.12 , SDK_2.x_EVK-MIMXRT1020  2.13.0 When hardfault occurred, I tried to move the previously logged content to flash. This coding-job was based on an example that included Shell among an example using FreeRTOS. 1. fsl_debug_console.c Before delivering the printbuffer to the DbgConsole_Vprintf function, we delivered the same content to the ringbuffer allocated 8KB using pvMalloc so that it can be stored continuously. 2. semihost_hardfault.c In this function, if it is not under the _semihost_return condition of the existing code, jump to a function called hardfault_handler_main in BL.     Hardfault_handler_main call hardfault_log_save_sc. In hardfault_log_save_sc, the logs in the area 8KB assigned to the malloc defined in fsl_debug_console.c were sorted so that they were stored in the 3F0 and 3F1 sectors of flash from the very first log. In RT1020, the 3F0 sector number of flash corresponds to 0x603F_0000 . The reason why I'm posting the question here is. After creating a trigger_hardfault CMD command and function that deliberately attempts to write a value to the null point in the shell volatile int *ptr = (int *)0x00000000; // NULL pointer *ptr = 42; // trigger hardfault If  intentionally causing hardfault. Ease the first sector of hardfault_log_save_sc is successfully executed, but then the second sector erase and dump to Dram -> flash do not work. How do I fix the file semihost_hardfault.c for hardfault handlers in SDK so that I can write what's in DRAM in flash correctly and fall out indefinitely? i.MXRT 102x Re: flash component project I did  double checks.  but  Still  hardfault occures But I change SDK version or RT1020... SDK 2.13 -> SDK 24.12   then  It works fine After comparing two version with diff sw tool,   Now I   guess , previous SDK version Example has problem.  anyway. thanks for your  f/up Re: flash component project Hi @Seongyon_Jeong  I used the latest SDK(v24.12 or v2.16.0) which need IDE v24 to run the same example (evkmimxrt1020_flash_component_nor_flexspi), but both of them all works fine. Please double check from your side. https://github.com/nxp-mcuxpresso/mcux-sdk-examples/tree/5a158afe9cdb70ca449667ed71490afd29655710/evkmimxrt1020/component_examples/flash_component/flexspi_nor  ***NOR Flash Component Demo Start!*** ***NOR Flash Page 0 Read/Write Success!*** ***NOR Flash Page 1 Read/Write Success!*** ***NOR Flash Page 2 Read/Write Success!*** ***NOR Flash Page 3 Read/Write Success!*** ***NOR Flash Page 4 Read/Write Success!*** ***NOR Flash Page 5 Read/Write Success!*** ***NOR Flash Page 6 Read/Write Success!*** ***NOR Flash Page 7 Read/Write Success!*** ***NOR Flash Page 8 Read/Write Success!*** ***NOR Flash Page 9 Read/Write Success!*** ***NOR Flash Page 10 Read/Write Success!*** ***NOR Flash Page 11 Read/Write Success!*** ***NOR Flash Page 12 Read/Write Success!*** ***NOR Flash Page 13 Read/Write Success!*** ***NOR Flash Page 14 Read/Write Success!*** ***NOR Flash Page 15 Read/Write Success!*** ***NOR Flash All Pages Read/Write Success!*** Re: flash component project This is my SDK version for RT1020 EVK     I download two example  from SDK freertos_hello_flash_operation works fine.  But  flash component nor  is not.  Just Only ,  Import SDK example -> select  this example -> finish (no  change,  just default) But.  Build & Download the image Using GUI Flash Tool of MCUXpressoIDE. , and. Nothing.......  so,  I  Enter  debug mode  of this project. then....          I do not  change anything  in this project.  just import & build & down.  but this faced to  Hardfault   directly.....  So,  I tested another project,   they work fine  with Default SDK Example Project state.  I think  the Example project  has problem   Re: Hardfault handler log saving Hi @Seongyon_Jeong  It seems there are some issues about hardFault handle which are developed from your side. Generally speaking, it is out of our support role. Here I would like to give advice that it's hard to handle flash sections, please follow flash_componment_nor_flexspi example to see how to use  Nor_Flash_Erase_Sector Nor_Flash_Read functions. Re: Hardfault handler log saving Ease the first sector of hardfault_log_save_sc is successfully executed   => Erasing the first sector of hardfault_log_save_sc is successfully executed Miss spelling..

FCCU Alarm Interrupt could not be enable under NCF2 and NCF3 Hello, I try to config SPD project for S32K344, and found the "Alarm State Interrupt Enable" could not be check under NCF2 and NCF3 ether in EB or S32DS. Is that mean there is no way to call interrupt eMcemUserAlarmHandler? If so, why it design like that? Interrupt handle is always fast than runtime task. Re: FCCU Alarm Interrupt could not be enable under NCF2 and NCF3 Hello, I see no restriction on micro for such interrupt enable: I have also configured it it design studio with no issues: I see issue in your configuration as you do not enable any timeout for alarm state ( that interrupt), so your device will transition directly into fault state. Best regards, Peter

GD3162 Hi NXP, Please provide a clear difference between Soft Shut down, 2LTO and Segmented Driver in GD3162 as these features are not very much clear and are a blocker for our project. Re: GD3162 Hi Akshat, SSD uses a smaller, programmable constant sink current to switch off the IGBT/SiC. The turn-off time is increased, turn-off speed is reduced and the gate is slowly discharged. This limits the di/dt and dv/dt, reducing voltage spikes and protecting the device. Unlike SSD, the 2LTO first reduces gate drive to an intermediate programable voltage level (for a programmable duration) before fully turning it off. This reduces the peak voltage overshoot across the power device. The segmented drive feature allows to wave shape the turn-off current and modulate the gate impedance during turn-off, for the purposes of mitigating potentially high VCE overshoot. Segmented drive is exclusively a non-fault, non-latching mode of operation during turn-off. More details about all these features can be found in the GD3162 datasheet. BRs, Tomas

Whether the code of KW38 and KW45 is common I am using KW38 now, and the RAM of KW38 is not enough. As far as I know, many software of KW38 and KW45 are compatible, so whether the program of KW38 can be directly run on KW45? I just want to quickly replace it and test how much memory is needed, and verify how much RAM is needed first Product: KW 37|38|39 Re: Whether the code of KW38 and KW45 is common Ok, thank you for your answer Re: Whether the code of KW38 and KW45 is common Hi KW38 and KW45 are not pin compatible, there are some differences in Application structure and APIs used for each device. For development using a new board, and in order to avoid any issues related to the software, I would recommend checking on the Bluetooth Low Energy Application Developer’s Guide Chapter 9 to see how this structures are integrated; also, this document describes the most commonly used APIs and provides code examples applicable to KW45. I would recommend using the SDK examples for KW45 as base for developing your application if you are trying to move to KW45. Best Regards