Clarification Required on FlexCAN Enhanced RX FIFO + DMA Operation on S32K312 Hello , We are currently working on FlexCAN Enhanced RX FIFO with DMA on the S32K312, enhanced FIFOenhanced FIFOenhanced FIFO we are using the rtd v 7.0.1 and would like clarification on several observations and issues we are facing. 1. MEX Configuration Verification Could you please verify the recommended MEX configuration for FlexCAN Enhanced RX FIFO with DMA enabled? We would like to ensure that our configuration follows the intended RTD usage model. 2. Enhanced RX FIFO + DMA Data Loss Observation As suggested in the FlexCAN errata, the following Message Buffers are not used when Enhanced RX FIFO is enabled: MB0–MB7, MB10, MB12, MB20, MB22, MB30, MB32, MB40, MB50, and MB60. Our setup is as follows: Enhanced RX FIFO enabled DMA enabled Watermark configured to 10 entries DMA transfers FIFO data into a software buffer Observed behavior: CAN messages are correctly received into the Enhanced RX FIFO. DMA transfers data successfully until the watermark level is reached. DMA completion interrupt is triggered. After this point, incoming CAN messages are not observed in the expected next FIFO location (11th FIFO entry onwards). Data loss and abnormal FIFO behavior are observed. Could you please explain the expected behavior in this scenario and the likely reason for the observed message loss? 3. FlexCAN_Ip_RxFifo DMA Reconfiguration While debugging the RTD driver, we observed that the FlexCAN_Ip_RxFifo API appears to reconfigure DMA parameters. Specifically: Minor loop count appears to be configured as 16 Transfer size appears to be 4 bytes This results in a total transfer size of 64 bytes (or approximately 68 bytes depending on interpretation), which does not appear to match the Enhanced RX FIFO entry size described in the Reference Manual. Could you clarify the intended operation of this API and the rationale behind these DMA settings? 4. Enhanced RX FIFO Memory Observation Another observation during debugging is that even though DMA appears to transfer data from the FIFO into the software buffer: The FIFO memory region still contains older message IDs. The memory browser appears to show only the first Enhanced RX FIFO element. FIFO locations do not appear to update as expected. A screenshot is attached for reference. Could you explain whether this is expected behavior and how the Enhanced RX FIFO memory should be interpreted during runtime debugging? 5. Structure Size Mismatch We also observed a discrepancy between the RTD structure and the Reference Manual. FlexCAN_Ip_MsgBuffType size in RTD: 78 bytes Enhanced RX FIFO element size according to the Reference Manual: 80 bytes Could you clarify: Why this size difference exists? Whether any packing/alignment considerations are involved? Whether DMA transfers should be configured for 78 bytes or 80 bytes? Intended Use Case Our requirement is to use: Enhanced RX FIFO DMA-based reception No CPU interrupts for message reception The intended behavior is: CAN message arrives in Enhanced RX FIFO. DMA automatically transfers the FIFO entry into a software buffer. No software polling or RX interrupt handling is required for normal operation. The Message Buffers reserved by the Enhanced RX FIFO (MB0–MB7, MB10, MB12, MB20, MB22, MB30, MB32, MB40, MB50, and MB60) are intentionally avoided, while the remaining Message Buffers are used for transmission. Request Could you please provide: Any available example project demonstrating Enhanced RX FIFO with DMA operation. Recommended RTD configuration for this use case. Clarification on whether the RTD currently supports continuous Enhanced RX FIFO reception using DMA without software re-arming. Any bare-metal driver examples implementing Enhanced RX FIFO + DMA reception. Thank you for your support. Re: Clarification Required on FlexCAN Enhanced RX FIFO + DMA Operation on S32K312 Hi,
1. MEX Configuration Verification A: seems your mex does not correspond for the your described setup - watermark is set to 1 - DMA Transfer Config is not need, driver configures DMA by own, unless you want to do own DMA setting and transfers
2. Enhanced RX FIFO + DMA Data Loss Observation A: After DMA completion interrupt, all received messages are read out and the assigned DMA channel is disabled. So if the FlexCAN_Ip_RxFifo is not called again, RXFIFO still accepts messages, again from entry 0, but as DMA is not started again, it does not read out RXFIFO.
3. FlexCAN_Ip_RxFifo DMA Reconfiguration A: what is minor loop count? Driver itself sets minor loop size (NBYTES) as 80 to read up to 64byte payload message plus IDHIT and timestamp info from RXFIFO. So I do not get your calculation, in fact. Maybe share your code
4. Enhanced RX FIFO Memory Observation A: just first Enhanced RX FIFO element area is visible to used, if represents Enhanced FIFO output port address range. It is not advisable to show RXFIFO memory during debugging. For proper FIFO engine operation, the CPU should not access the Enhanced FIFO output port address range during DMA operation, in fact displaying this memory space cause reading of it.
5. Structure Size Mismatch A: FlexCAN_Ip_MsgBuffType does not fully reflect RXFIFO structure. at teh end of transfer a driver read out internal buffer and fill respective fields of user buffer with proper data. As written above DMA should be set to read out 80bytes per single DMA request.
Driver is written in a way you need to rearm DMA (call FlexCAN_Ip_RxFifo) again after DMA is finished and FLEXCAN_EVENT_DMA_COMPLETE event is called.
You can refer to below demo foe enhance RXFIFO and DMA usage, but it is done in RTD400 https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-FlexCAN-Ip-TX-RX-EnhanceRXFIFO-DMA-test-S32DS3-5/ta-p/2015832
BR, Petr
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