Multi Source Translation Content

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 

Multi Source Translation Content

讨论

排序依据:
MPC5777C - Questions about the SRAM access configuration Hello! While reading the "Chapter 24 RAM Controller (PRAMC)" of the MPC5777C Reference Manual, I had the following questions: 1 - What is a 64-bit WRP4 read burst? 2 - What is a 2-1-1-1 response? 3 - What is the purpose of the late-write buffer, since there is the possibility of performing write bursts? Does the late-write buffer merges single beat write transactions into a multi beat bursted transaction? 4 - The PRAMC offers the possibility to add an optional read wait-state to register RAM read data prior to returning it on the system bus. What does "register RAM read data means"? Where this data would be registered? In which scenario adding a wait state to the read accesses would be beneficial? 5 - Does the PRAMC or the SRAM have a row buffer to store the last accessed row in the memory array? DRAMs have this resource, but I am not sure if SRAMs have this as well. 6 - DRAMs follows the JEDEC standard to define its commands, such as the activate command (ACT) and the Column Address Strobe (CAS) command. Does the MPC5777C SRAM follow this standard, and thus, work with the same commands? Best regards, Matheus Re: MPC5777C - Questions about the SRAM access configuration 2) Core cycles 3) No, it is not about speed. Data are putted off to late write buffer when another SRAM write is in progress. Pay attention to section 24.4.2.1 64-bit writes 4) I think it is just generic module description. This option works, but as there is no requirement, I don't see any benefit. Re: MPC5777C - Questions about the SRAM access configuration 2) These cycles refer to the clock cycles of the core or the cycles of the PRAMC? 3) So the late write buffer is a memory faster than SRAM? If so, by which technology is the late-write buffer made? 4) The Reference Manual says that one of the PRAMC features is to have "Configurable read access timing (zero or one wait-state programmable) allowing use in large range of frequency targets". If there is no requirement to use this optional wait state, why does the RM says that the optional wait state allows use in a large range of frequency targets? Re: MPC5777C - Questions about the SRAM access configuration 1) 4-beat wrapping burst. Wrapping mean that firstly wanted data are read first. If you need Word2 for instance, sequence is as follows: Word2 - Word3 - Word0 - Word1 2) First data are read is 2 cycles (Word2 in example above), then 1 cycle per word (Word3 - Word0 - Word1) 3) Late write buffer allows not to wait until end of write cycle. From CPU side data are just written to SRAM and terminated. Physically store to SRAM is performed later. 4) It mean 1 clock cycle is added (there is a buffer there), but I don’t see any benefit. As I know there is no requirement to use it. 5, 6) No it static RAM, not dynamic. It works differently.
查看全文
RT1166 PWM同步 当我配置同一个子模块的PWM_A和PWM_B时,PWM_A1和PWMA_2的边沿对齐,PWM_B1和PWM_B2的边沿对齐。但是,PWM_A 与 PWM_B 不对齐。有没有办法对齐所有四个通道的输出?
查看全文
The FS23 example only has S32K344, but no S32K312? Hi When I import the example, I only see the K344 version. What should I do if I need to use it on K312? Re: The FS23 example only has S32K344, but no S32K312? Hi Can I use the tool to import the K312 project and automatically adapt it, or do I need to create a new project and configure everything to imitate the K344 routine?
查看全文
MCIMX6Q的bsp包 你好,我想请问一下MCIMX6Q的芯片有没有类似于MCIMX6ULL这样的简易bsp包,而不是LINUX环境下的bsp包,我想尝试在MCIMX6Q下运行非LINUX的其他实时操作系统(RT-thread系统),这样的bsp包对于移植来说有很大的帮助。 回复: MCIMX6Q的bsp包 详细信息我通过电子邮件发送给您,请检查。 回复: MCIMX6Q的bsp包 仍然建议您使用Linux BSP,以便您可以轻松使用它。 适用于 i.MX 应用处理器的嵌入式 Linux | NXP 半导体
查看全文
MTBF - TJA1051 Hello, I am doing MTBF calculation of my project. I need reliability data of TJA1051 or TJA1057 as it is now recommended Is it possible to have these data? Thanks in advance. Re: MTBF - TJA1051 Hello Alaric, we do not provide this kind of information to the email address you are contacting us from. Please register with your company email address and then you can request this information via support ticket. Thank you for your kindly understanding. Kind Regards Romana
查看全文
Unable to get RSTP streaming working imx8mp Using the imx8mp evkit with IMX-OS08A20 accessory card. Bitbake imx-image-full and got the camera working with-in the gopoint demos. Am trying to stream the camera over rtsp and view the stream from PC VLC over the network. On the server imx ran: gst-variable-rtsp-server -p 9001 -u "v4l2src device=/dev/video2 ! video/x-raw,width=640,height=480 ! v4l2h264enc ! rtph264pay name=pay0 pt=96" Shows: Pipeline set to: ( v4l2src device=/dev/video2 ! video/x-raw,width=640,height=480 ! v4l2h264enc ! rtph264pay name=pay0 pt=96 )... Stream ready at rtsp://127.0.0.1:9001/stream Then I tried to retrieve the stream from another device over the network, it does not work, but on the server side i see a new line everytime i tried to connect from the client ====== V4L2ENC: 1.24.7 build on Oct 23 2024 09:43:13. ====== ====== V4L2ENC: 1.24.7 build on Oct 23 2024 09:43:13. ====== ====== V4L2ENC: 1.24.7 build on Oct 23 2024 09:43:13. ====== So I tried to load the stream from the imx system itself with: GST_DEBUG=3 gst-launch-1.0 rtspsrc location=rtsp://127.0.0.1:9001/stream ! queue ! rtph264depay ! v4l2h264dec ! autovideosink and GST_DEBUG=3 gst-launch-1.0 rtspsrc location=rtsp://192.168.100.219:9001/stream ! queue ! rtph264depay ! v4l2h264dec ! autovideosink I see the same response as above on the server side. Client side logs : root@imx8mpevk:~# GST_DEBUG=3 gst-launch-1.0 rtspsrc location=rtsp://127.0.0.1:9001/stream ! queue ! rtph264depay ! v4l2h264dec ! autovideosink Setting pipeline to PAUSED ... ====== V4L2DEC: 1.24.7 build on Oct 23 2024 09:43:13. ====== Pipeline is live and does not need PREROLL ... Progress: (open) Opening Stream Pipeline is PREROLLED ... Prerolled, waiting for progress to finish... Progress: (connect) Connecting to rtsp://127.0.0.1:9001/stream Progress: (open) Retrieving server options Progress: (open) Retrieving media info 0:00:00.198607035 1940 0xffffa0000d20 WARN rtspsrc gstrtspsrc.c:7097:gst_rtspsrc_send: error: Unhandled error 0:00:00.198669410 1940 0xffffa0000d20 WARN rtspsrc gstrtspsrc.c:7097:gst_rtspsrc_send: error: Service Unavailable (503) ERROR: from element /GstPipeline:pipeline0/GstRTSPSrc:rtspsrc0: Unhandled error Additional debug info: /usr/src/debug/gstreamer1.0-plugins-good/1.24.7.imx/gst/rtsp/gstrtspsrc.c(7097): gst_rtspsrc_send (): /GstPipeline:pipeline0/GstRTSPSrc:rtspsrc0: Service Unavailable (503) ERROR: pipeline doesn't want to preroll. Setting pipeline to NULL ... 0:00:00.199138163 1940 0xffffa0000d20 WARN rtspsrc gstrtspsrc.c:8584:gst_rtspsrc_open: can't get sdp 0:00:00.199200289 1940 0xffffa0000d20 WARN rtspsrc gstrtspsrc.c:6515:gst_rtspsrc_loop: we are not connected Not sure what is happening and how to proceed. Any advice greatly appreciated. Yocto Project Re: Unable to get RSTP streaming working imx8mp Managed to fix this, using v4l2src device=/dev/video3 instead. Re: Unable to get RSTP streaming working imx8mp what bsp version do you test? let me reproduce this
查看全文
RT1166 PWM Synchronization When I configure PWM_A and PWM_B of the same submodule, the edges of PWM_A1 and PWMA_2 are aligned, and so are the edges of PWM_B1 and PWM_B2. However, PWM_A is not aligned with PWM_B. Is there a way to align the outputs of all four channels? Re: RT1166 PWM Synchronization Hi @tbonkers , Thanks for your interest in the NXP MIMXRT product, I would like to provide service for you. In IMXRT1160RM refence manual chapter 72.3.2.3 Counter Synchronization. https://www.nxp.com/webapp/Download?colCode=IMXRT1160RM It describe PWM Counter Synchronization, Please refer to this.     Wish it helps you. If you still have question about it, please kindly let me know. Wish you a nice day! Best Regards MayLiu
查看全文
无法使 RSTP 流工作 imx8mp 使用带有 IMX-OS08A20 附件卡的 imx8mp 评估套件。Bitbake imx-image-full 并使相机在 gopoint 演示中工作。 我正在尝试通过 rtsp 传输摄像机并通过网络查看来自 PC VLC 的流。 在服务器上 imx 运行: gst-variable-rtsp-server -p 9001 -u "v4l2src device=/dev/video2 ! video/x-raw,width=640,height=480 ! v4l2h264enc ! rtph264pay name=pay0 pt=96" Shows: Pipeline set to: ( v4l2src device=/dev/video2 ! video/x-raw,width=640,height=480 ! v4l2h264enc ! rtph264pay name=pay0 pt=96 )... Stream ready at rtsp://127.0.0.1:9001/stream 然后我尝试通过网络从另一个设备检索流,但它不起作用,但在服务器端,每次我尝试从客户端连接时,我都会看到一条新线 ====== V4L2ENC: 1.24.7 build on Oct 23 2024 09:43:13. ====== ====== V4L2ENC: 1.24.7 build on Oct 23 2024 09:43:13. ====== ====== V4L2ENC: 1.24.7 build on Oct 23 2024 09:43:13. ====== 因此我尝试使用以下命令从 imx 系统本身加载流: GST_DEBUG=3 gst-launch-1.0 rtspsrc location=rtsp://127.0.0.1:9001/stream ! queue ! rtph264depay ! v4l2h264dec ! autovideosink and GST_DEBUG=3 gst-launch-1.0 rtspsrc location=rtsp://192.168.100.219:9001/stream ! queue ! rtph264depay ! v4l2h264dec ! autovideosink 我在服务器端看到与上面相同的响应。 客户端日志: root@imx8mpevk:~# GST_DEBUG=3 gst-launch-1.0 rtspsrc location=rtsp://127.0.0.1:9001/stream ! queue ! rtph264depay ! v4l2h264dec ! autovideosink Setting pipeline to PAUSED ... ====== V4L2DEC: 1.24.7 build on Oct 23 2024 09:43:13. ====== Pipeline is live and does not need PREROLL ... Progress: (open) Opening Stream Pipeline is PREROLLED ... Prerolled, waiting for progress to finish... Progress: (connect) Connecting to rtsp://127.0.0.1:9001/stream Progress: (open) Retrieving server options Progress: (open) Retrieving media info 0:00:00.198607035 1940 0xffffa0000d20 WARN rtspsrc gstrtspsrc.c:7097:gst_rtspsrc_send: error: Unhandled error 0:00:00.198669410 1940 0xffffa0000d20 WARN rtspsrc gstrtspsrc.c:7097:gst_rtspsrc_send: error: Service Unavailable (503) ERROR: from element /GstPipeline:pipeline0/GstRTSPSrc:rtspsrc0: Unhandled error Additional debug info: /usr/src/debug/gstreamer1.0-plugins-good/1.24.7.imx/gst/rtsp/gstrtspsrc.c(7097): gst_rtspsrc_send (): /GstPipeline:pipeline0/GstRTSPSrc:rtspsrc0: Service Unavailable (503) ERROR: pipeline doesn't want to preroll. Setting pipeline to NULL ... 0:00:00.199138163 1940 0xffffa0000d20 WARN rtspsrc gstrtspsrc.c:8584:gst_rtspsrc_open: can't get sdp 0:00:00.199200289 1940 0xffffa0000d20 WARN rtspsrc gstrtspsrc.c:6515:gst_rtspsrc_loop: we are not connected 不确定发生了什么以及如何进行。非常感谢任何建议。 Yocto Project 回复:无法让 RSTP 流工作 imx8mp 设法修复此问题,改用 v4l2src device=/dev/video3。 回复:无法让 RSTP 流工作 imx8mp 你测试的是哪个 bsp 版本?让我重现一下
查看全文
RSTPストリーミングをimx8mpで動作させることができません imx-OS08A20 アクセサリカードと imx8mp evkit の使用。Bitbake imx-image-full を使用して、カメラを gopoint デモで動作させるようにしました。 rtsp経由でカメラをストリーミングし、ネットワーク経由でPCVLCからのストリームを表示しようとしています。 サーバー上で imx は次のように実行しました。 gst-variable-rtsp-server -p 9001 -u "v4l2src device=/dev/video2 ! video/x-raw,width=640,height=480 ! v4l2h264enc ! rtph264pay name=pay0 pt=96" Shows: Pipeline set to: ( v4l2src device=/dev/video2 ! video/x-raw,width=640,height=480 ! v4l2h264enc ! rtph264pay name=pay0 pt=96 )... Stream ready at rtsp://127.0.0.1:9001/stream 次に、ネットワーク経由で別のデバイスからストリームを取得しようとしましたが、機能しませんが、サーバー側では、クライアントから接続しようとするたびに新しい行が表示されます ====== V4L2ENC: 1.24.7 build on Oct 23 2024 09:43:13. ====== ====== V4L2ENC: 1.24.7 build on Oct 23 2024 09:43:13. ====== ====== V4L2ENC: 1.24.7 build on Oct 23 2024 09:43:13. ====== だから私はimxシステム自体からストリームをロードしようとしました: GST_DEBUG=3 gst-launch-1.0 rtspsrc location=rtsp://127.0.0.1:9001/stream ! queue ! rtph264depay ! v4l2h264dec ! autovideosink and GST_DEBUG=3 gst-launch-1.0 rtspsrc location=rtsp://192.168.100.219:9001/stream ! queue ! rtph264depay ! v4l2h264dec ! autovideosink サーバー側でも上記と同じ応答が表示されます。 クライアント側のログ: root@imx8mpevk:~# GST_DEBUG=3 gst-launch-1.0 rtspsrc location=rtsp://127.0.0.1:9001/stream ! queue ! rtph264depay ! v4l2h264dec ! autovideosink Setting pipeline to PAUSED ... ====== V4L2DEC: 1.24.7 build on Oct 23 2024 09:43:13. ====== Pipeline is live and does not need PREROLL ... Progress: (open) Opening Stream Pipeline is PREROLLED ... Prerolled, waiting for progress to finish... Progress: (connect) Connecting to rtsp://127.0.0.1:9001/stream Progress: (open) Retrieving server options Progress: (open) Retrieving media info 0:00:00.198607035 1940 0xffffa0000d20 WARN rtspsrc gstrtspsrc.c:7097:gst_rtspsrc_send: error: Unhandled error 0:00:00.198669410 1940 0xffffa0000d20 WARN rtspsrc gstrtspsrc.c:7097:gst_rtspsrc_send: error: Service Unavailable (503) ERROR: from element /GstPipeline:pipeline0/GstRTSPSrc:rtspsrc0: Unhandled error Additional debug info: /usr/src/debug/gstreamer1.0-plugins-good/1.24.7.imx/gst/rtsp/gstrtspsrc.c(7097): gst_rtspsrc_send (): /GstPipeline:pipeline0/GstRTSPSrc:rtspsrc0: Service Unavailable (503) ERROR: pipeline doesn't want to preroll. Setting pipeline to NULL ... 0:00:00.199138163 1940 0xffffa0000d20 WARN rtspsrc gstrtspsrc.c:8584:gst_rtspsrc_open: can't get sdp 0:00:00.199200289 1940 0xffffa0000d20 WARN rtspsrc gstrtspsrc.c:6515:gst_rtspsrc_loop: we are not connected 何が起こっているのか、どのように進めればよいのかわかりません。どんなアドバイスでも大歓迎です。 Yocto Project Re:RSTPストリーミングをimx8mpで動作させることができません 代わりに v4l2src device=/dev/video3 を使用して、これを修正することができました。 Re:RSTPストリーミングをimx8mpで動作させることができません どのBSPバージョンをテストしますか?これを再現させてください
查看全文
RT1166 PWM同期 同じサブモジュールのPWM_AとPWM_Bを設定すると、PWM_A1とPWMA_2の端が整列し、PWM_B1とPWM_B2の端も整列します。ただし、PWM_A は PWM_B と一致していません。4つのチャンネルすべての出力を揃える方法はありますか?
查看全文
FS23 の例には S32K344 しかありませんが、S32K312 はありませんか? こんにちは サンプルをインポートすると、K344バージョンしか表示されません。K312で使用したい場合はどうすればいいですか? Re: FS23 の例には S32K344 しかありませんが、S32K312 はありませんか? こんにちは このツールを使用して K312 プロジェクトをインポートし、自動的に適応させることができますか? それとも、新しいプロジェクトを作成し、K344 ルーチンを模倣するようにすべてを構成する必要がありますか?
查看全文
FS23示例只有S32K344,没有S32K312的吗 Hi 导入示例的时候只看到K344的版本,如果我需要在K312上使用需要怎么去做呢 Re: FS23示例只有S32K344,没有S32K312的吗 Hi@Maker007 如果你当前的工程只是需要添加SBC的驱动,你可以导入你当前的工程然后在组件里面添加SBC组件进行配置即可,不需要所有的东西都从头开始配置。 Re: FS23示例只有S32K344,没有S32K312的吗 Hi 可以直接使用工具导入K312的工程自动适配吗,还是说需要新建一个工程,所有的东西去模仿K344例程去配置 Re: FS23示例只有S32K344,没有S32K312的吗 Hi@Maker007 参考S32K344的例程直接创建一个新的工程,这几乎不用你做更多的修改,对照着配置就可以。
查看全文
Ethernet RGMII pins cannot be reassigned as GPIO Hi, We are using DART-MX8M-PLUS development kit, along with our custom board based on iMX8MP. In order to use ADC connected on i2c5 bus, we need pins that are originally used for ethernet RGMII (ENET1_RGMII*) as a part of ethernet device named as fec, within the imx8mp-var-dart-dt8mcustomboard.dts device tree file:   &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; phy-mode = "rgmii"; phy-handle = <&ethphy1>; status = "okay"; }; ... pinctrl_fec: fecgrp { fsl,pins = < MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x00 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x00 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x00 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x00 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x00 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x00 >; };   In order for pins SAI1_TXD1 and SAI1_RXD5 to be used for our ADC, I've removed shown fec entry from device tree, as well as those RGMII pins definitions. After that, i2c device was added, as well as desired pins, in the following way:   &i2c5{ clock-frequency = <400000>; pinctrl-names = "default", "gpio", "adc"; pinctrl-0 = <&pinctrl_i2c5>; pinctrl-1 = <&pinctrl_i2c5_gpio>; pinctrl-2 = <&pinctrl_adc>; scl-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; status = "okay"; adc@2f { compatible = "adi,ad7091r5"; reg = <0x2f>; }; }; ... pinctrl_adc: adcgpiogrp { fsl,pins = < MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x1c2 MX8MP_IOMUXC_SAI1_RXD5__GPIO4_IO07 0x1c2 >; }; After the boot, I can see that those changes are present in the system by running the following command:   cat /sys/kernel/debug/pinctrl/pinctrl-handles ... device: 30ad0000.i2c current state: default state: default type: MUX_GROUP controller 30330000.pinctrl group: i2c5grp (21) function: pinctrl (0) type: CONFIGS_PIN controller 30330000.pinctrl pin MX8MP_IOMUXC_HDMI_DDC_SCL (144)config 000001c2 type: CONFIGS_PIN controller 30330000.pinctrl pin MX8MP_IOMUXC_HDMI_DDC_SDA (145)config 000001c2 state: gpio type: MUX_GROUP controller 30330000.pinctrl group: i2c5gpiogrp (25) function: pinctrl (0) type: CONFIGS_PIN controller 30330000.pinctrl pin MX8MP_IOMUXC_HDMI_DDC_SCL (144)config 000001c2 type: CONFIGS_PIN controller 30330000.pinctrl pin MX8MP_IOMUXC_HDMI_DDC_SDA (145)config 000001c2 state: adc type: MUX_GROUP controller 30330000.pinctrl group: adcgpiogrp (26) function: pinctrl (0) type: CONFIGS_PIN controller 30330000.pinctrl pin MX8MP_IOMUXC_SAI1_TXD1 (95)config 000001c2 type: CONFIGS_PIN controller 30330000.pinctrl pin MX8MP_IOMUXC_SAI1_RXD5 (89)config 000001c2 ... The problem is that setting GPIO value using libgpiod doesn't reflect on those pins. I've connected those pins to the oscilloscope and neither in the case of development board nor of our custom board the change can be seen. I've even tried toggling those values from the Uboot but, again, with no success. I'd like to add that using gpioinfo or cat /sys/kernel/debug/gpio commands don't show that those pins are used by any device. In order to debug the problem, I've tried to use other SAI1 pins and I've noticed that only those which are related to the ethernet RGMII cannot be controlled; if I define other pins in the same way, the value can be changed. Therefore, I'd like to ask, could you know what might be the cause of the problem? Are ethernet RGMII pins somehow hardwired to the appropriate SAI1 pins or the problem comes from somewhere else? Regards, Dragan Re: Ethernet RGMII pins cannot be reassigned as GPIO Hi @Chavira, Yes, this solved our problem, we can control GPIO pins with libgpiod library. Thanks a lot! Regards, Dragan Re: Ethernet RGMII pins cannot be reassigned as GPIO Hi @idragan! I attached two modifications. with the first one you should be able to use the gpios using the gpio commands (gpioset, gpioget, gpioinfo) With the second one you should be able to use the gpios usingthe next commands: $ echo 0 >> /sys/class/leds/ /brigthness $ echo 1 >> /sys/class/leds/ /brigthness I will wait for your update. Best Regards! Chavira Re: Ethernet RGMII pins cannot be reassigned as GPIO Hi @Chavira, Thanks for the fast response! Sure, I'm attaching dts file we're using. As for the pins, yes, we'd like to use SAI1_TXD1, SAI1_RXD5 and SAI1_RXD4 (which is currently not present in this device tree). Regards, Dragan Re: Ethernet RGMII pins cannot be reassigned as GPIO Hi @idragan! Thank you for contacting NXP Support! Can you share the device tree of your development board? The pins that you want to use as a GPIOS are the SAI1_TXD1 and SAI1_RXD5? Best Regards! Chavira
查看全文
Read multiple analog signals. S32k396 Hello. I am reading the potentiometer input present on the S32X-MB via the PTD1 input (P0_ChanNum0). Now, I am configuring, within the same signal group, the reading of the next input (PTD0, which corresponds to P1_ChanNum1) by reading a bus in Simulink. To do this, I have added another signal in the same group and assigned it the appropriate pin number in the PORT. When running the code, I observe an analog signal on the variable Group0_Channel0 (via Freemaster), but a zero on the Group0_Channel1 signal, which indicates that either the input is not being initialized correctly, it is not being read, or I am not accessing it correctly using a demux in Simulink.   Any idea? Thanks Example Models Re: Read multiple analog signals. S32k396 Hi @MaMM  MBDT integrates the RTD (Real-Time Drivers) for configuration and access to the hardware (peripherals, pins, clocks, interrupts). For more details on configuration parameters, and functions implemented by our blocks, you could check the RTD User Manual for the component you would like to use, and also the AUTOSAR driver standard (RTD MCAL layer is AUTOSAR compatible). For the ADC, and other blocks as well, you could access this documentation I am referring to by clicking on the Help button of the Simulink block, and navigating to the Code Generation section, like illustrated below For configuration examples, you could check the configuration projects that we are delivering together with our application examples.  Moreover, in case of the ADC, PWM, CAN, UART and DIO, we have also put together some articles on our MBDT NXP Community, that provide a more detailed insight into the available parameters, and settings. Maybe you would find them useful as well. Here is the link to the ADC one, but the others are available under the Beginner's Guide for Model-Based Design Toolbox section on our main page. Hope this helps you. Please let us know in case additional information is required. Thanks, Irina Re: Read multiple analog signals. S32k396 Hello Irina, Thanks for the information. You were right; that part was missing. Now it works perfectly! Anyway, is there any kind of user manual for the tool that includes configuration examples? That way, we wouldn’t have to ask these kinds of questions all the time. Currently, based on the examples, we configure our needs, but sometimes a configuration is missing, as has been the case. BR. Re: Read multiple analog signals. S32k396 Hello @MaMM  You have mentioned in your previous posted that you have added the new signal in the same group, however the attached image shows only its enablement inside the AdcHwUnit settings. Could we please double check if the additional channel has also been added to the Adc0Group_0 - AdcGroupDefinition?   Thanks, Irina Re: Read multiple analog signals. S32k396 Hello Irina. Thanks for your response. As you mentioned, on the MB, the pin is P17[5]. Anyway, even if nothing is connected, it should still be providing a reading. Currently, the value read is always zero, which makes me think that something is missing in the initialization. That is, some configuration might be needed to indicate that there are two signals instead of one, or something along those lines. It seems like the data is not being loaded at that position, and as a result, it constantly reads zero. In any case, I have wired the signal to the other input (which goes to P19[1]), and obviously, nothing is displayed. Any idea if something might be missing? Re: Read multiple analog signals. S32k396 Hello @MaMM  From the description provided, your software configuration seems complete - adding the additional Adc Channel to the group, and inside the corresponding Adc Hw Unit should be enough. Also, the Simulink implementation should provide the correct results, as I have just tested the implementation on my end as well. Could you please check the hardware connections for this use case? As far as I see from the schematics, PTD0, on the EVB, is routed to the J56B[87] pin. On the MB, the J56B[87] pin is labeled as PBC_GPIO[22], accessible on the PortBC[5] pin. Hence, your signal to be converted needs to be fed to PortBC[5], unless other hardware modifications were made to this default setup. Hope this helps, Irina
查看全文
OTP 镜像寄存器图 主题请求提供 PF5020 OTP 镜像寄存器映射图文档 您好, 我们目前正在研究 PF5020 PMIC 与恩智浦控制器之间的通信。在审查 PF5020 数据表期间,我们无法找到有关 OTP 镜像寄存器映射的详细信息,包括与 OTP 配置相关的寄存器地址和引脚级说明。 我们需要的输出电压为 1.1 伏和 1.8 伏和 3.3 伏 请问是否有单独的文件提供这些信息?这对我们在系统中正确解释和配置 OTP 相关设置至关重要。 如果您能提供指导或分享任何相关文件,我们将不胜感激。 提前谢谢! 希瓦尼 Re: OTP mirror register map 您好, PF5020 数据表第 16.1 节提供了完整的 OTP 镜像寄存器图,包括 -寄存器地址 -配置字段,例如:用于降压输出电压的 OTP_vswx OTP_V LDOX 用于 LDO 输出电压 OTP_SWX_s eq 用于上电排序 OTP_SWX_PDGRP 用于断电分组 OTP_SWXILIM 用于限流设置 OTP_SWXUV_TH 和 OTP_SWXOV_TH 用于 UV/OV 阈值 VDDOTP 引脚决定设备是否从以下位置加载配置: -OTP 熔丝(当 VDDOTP = GND 时) -硬接线默认值(当 VDDOTP = V1P5D 时) TBBEN 引脚启用 “先试后买” (TBB) 模式,允许在承诺进行熔丝编程之前临时配置和测试 OTP 设置。 请记住,客户不允许在生产中使用 OTP 编程。只有恩智浦或授权合作伙伴(数量较少)才能执行此操作。在开发过程中,您可以使用 KITPF502xSKTEVM。 要为 1.1V、1.8V 和 3.3V 电压配置 PF5020,您需要 - 将 OTP_VSWx 或 OTP_VSWND1 设置为 1.1V 和 1.8V 的适当值 - 根据电流要求,将 OTP_VLDO1 或 OTP_VSWND1 设置为 3.3V 这些值可在 OTP 镜像寄存器中可编程,可以在提交之前在 TBB 模式下进行测试。 BRs, Tomas
查看全文
Simultaneous use of Ethernet and camera on the FRDM-MXCN947 board In MCXNx4x, SmartDMA can be used to implement the Camera interface. According to the MCXNx4x DataSheet, the Pinmux Assignments of Ethernet and SmartDMA conflict. For this reason, I thought that Ethernet and Camera could not be used at the same time. However, the FRDM-MCXN947 Board User Manual (UM12018) states the following: > If Ethernet functionality is still desired while using the camera, an alternative workaround is to move the SJ16 and SJ26 jumpers from their default position. Is there any way to use Ethernet and camera at the same time? Development Board MCXN Re: Simultaneous use of Ethernet and camera on the FRDM-MXCN947 board Hi @dubian1shu  I have rechecked the content of the document and confirmed that there is an issue with the description in the document. We will make timely changes to the document. SmartDMA (EZH_CAMERA) and Ethernet (ENET) can be used at the same time, but you need to find some pins that are not shared for the camera to use. You can refer to this article. MCX N947: Simultaneous Implementation of Ethernet and Camera Functions - NXP Community Hope this will help you. BR Hang Re: Simultaneous use of Ethernet and camera on the FRDM-MXCN947 board Thanks for checking and replying @Harry_Zhang  Since SmartDMA supports P1_X and P3_X, I understand that MCXNx4x can use SmartDMA and Ethernet functions at the same time. But can I use SmartDMA and Ethernet functions using FRDM-MCXN947? J9 (Camera Header) of FRDM-MCXN947 has seven pins that conflict with Ethernet pins. The solution for P1_4 described in the FRDM-MCXN947 board user manual (UM12018) only solves one of them, and does not mention the other six conflicts. For example, P1_5, P1_13, and P1_15 are in conflict between SmartDMA and Ethernet. As far as I can see from the schematic document (SCH-90818), there seems to be no solution to resolve this conflict. Is there a way to use SmartDMA (EZH_CAMERA) and Ethernet (ENET) at the same time on FRDM-MCXN947? Re: Simultaneous use of Ethernet and camera on the FRDM-MXCN947 board Hi @dubian1shu  I checked the MCXNx4x DataSheet, there are indeed some pins Ethernet and SmartDMA conflicting. But if you want to use the Ethernet and SmartDMA at the same time. you can choose some pins that do not conflict with Ethernet and SmartDMA. For example, you can choose the P3_X as the SmartDMA pin, and choose the P1_X as the Ethernet pin. And move the jumper referring to the FRDM-MCXN947 Board User Manual (UM12018). Hope this will help you. BR Hang
查看全文
S32K312 PLL_LOL Problem Hi NXP,     We found S32K312 will reset while  doing (ESD)Air discharge ±15kV test. And we found reset reason is PLL_LOL. Then we use NXP S32K312EVB-Q172 to do the same test, it will reset too.    We try to change GM_SET register to improve crystal diver strength,but it has no improvement. And we try to set DCMRWP3[9] to 1, S32K will not reset when PLL_LOL,but mcu will stop, only reset can recover it.    We need S32K3 keep running while the ESD test. Can cpu clock switch to FIRC while PLL_LOL? Could you give me some suggestions,Thanks! Re: S32K312 PLL_LOL Problem Hi Daniel,     Thanks,disable automatic level controller can slove this problem. Re: S32K312 PLL_LOL Problem What do you mean by higher-power oscillator? Did you disable the automatic level controller (FXOSC_CTRL[ALC_D] = 1)? BR, Daniel Re: S32K312 PLL_LOL Problem Hi @danielmartynek ,   Thanks for your reply. CMU is disable and I am sure the reset reason is PLL Loss of Lock. When PLL LOL,MCU will reset. When set DCMRWP3[9] to 1, mcu will not reset while PLL LOL but mcu will stop running. Thus we cannot change the system clock back to FIRC when PLL LOL. We try to replace the Crystal Oscillator with a higher-power one, it seems better. Re: S32K312 PLL_LOL Problem Hi @zhengjianfei1, Are you sure the FXOSC is that cause of the PLL Loss of Lock? Do you have the FXOSC clock monitor enabled? It could be just the PLL. Is the lastmile regulator enabled? You could try to change the system clock back to FIRC within the interrupt. MUX_0_CSC[SAFE_SW] = 1 Regards, Daniel
查看全文
i.MX95 上的 dm-eiq-genai-flow 演示器需要电路板支持包版本 嗨,团队、 我正在探索 i.MX95 平台上的 dm-eiq-genai-flow-demonstrator(GenAI Flow),它在 Yocto 环境中运行。请您澄清一下: 1.端到端运行演示版的最低要求是哪个电路板支持包(例如 L6.12.20_2.0.0)? 2.此电路板支持包是否包含支持 LLM 推理 (RAG) 的所有必要元素,例如更新的 Neutron 委托、TfLite 运行时和工具? 3.这个演示中还有其他推荐的 Yocto 元层或图像配方(例如 meta-eiq-genai)吗? 预先感谢您的真知灼见! 致以最崇高的敬意, Varshil Gandhi Re: BSP Version Required for dm-eiq-genai-flow-demonstrator on i.MX95 你好 Varshil, 谢谢你的提问。 让我试着回答他们: 1.该代码包最初是为第一季度的 电路板支持包。 L6.12.3-1.0.0 制作的,适用于 i.MX95 修订版 Ax。 2。本第一季度的 电路板支持包。 不直接包括在 LLM 推断中利用中子所必需的内容。这就是该代码包提供元层的原因。 3.这个 meta-eiq-genai-flow 元层提供了添加 Onnxruntime 中子执行提供程序的可能性,以加速 Neutron 上的 LLM 操作并释放一些 CPU 资源,以及内核和 Neutron Fw 的相关补丁/文件。请注意,我们在这个项目中使用的是 onnxruntime 而不是 TF 精简版。 话虽如此,第二季度电路板支持包。(例如L6.12.20_2. 0.0)将于今天发布。它支持 i.MX95 的 B0 版本,但没有 Neutron 上的 LLM 加速,只有 CPU 模式可以运行。 谢谢,并致以最崇高的敬意、 皮埃尔
查看全文
S32K3xx SpiBaudrateConfigRef set Hi, Configuration Components for SDK Peripheral Drivers— LPSPI: 1. Lpspi → SpiExternalDevice → SpiUseBaudrateConfig → SpiBaudrateConfigRef? What is the purpose of this setting, and how do you configure it? 2. What is the difference between SpiUseBaudrateConfig and SpiCalculatedBaudRate for SPI baud rate selection? 3. I need a user-friendly way to configure the SPI baud rate. How can I do that? Regards, Karmegan C Re: S32K3xx SpiBaudrateConfigRef set Hi @daniel_ll, I've sent you a private message regarding this issue. Re: S32K3xx SpiBaudrateConfigRef set Hi Julián, Do you have a link to the Jira bug? And/or more info about in what RTD release this will be fixed? Facing the same issue with RTD 5.0.0 Re: S32K3xx SpiBaudrateConfigRef set Hi @karmegancjk I've confirmed with the internal team, and this is a bug. It is planned to be fixed in the next RTD release. Best regards, Julián Re: S32K3xx SpiBaudrateConfigRef set Hi @karmegancjk, Apparently, only the MCAL Spi component generates a valid SpiBaudRateConfigRef value. I did not notice this since I was basing the project in MCAL and not IP: I think this is not intended, so for now, either configure the SPI component without the "UseBaudrateConfig" parameter or with the MCAL component to generate the reference. I will ask internally to see if this is expected behavior. Best regards, Julián Re: S32K3xx SpiBaudrateConfigRef set Hi, I am not able to assign SpiBaudrateConfig_0 to SpiBaudrateConfigRef in Lpspi Driver. IDE : S32DS 3.5.13. RTD : R22_11 V4.0.0. How do I set the path of SpiBaudrateConfig_0 in SpiBaudrateConfigRef? Re: S32K3xx SpiBaudrateConfigRef set Hi @karmegancjk, All of the configuration parameters are described inside the respective driver user manual. Under "C:\NXP\S32DS.3.6.1\S32DS\software\PlatformSDK_S32K3\RTD\Spi_TS_T40D34M50I0R0\doc" you can find RTD_SPI_UM.pdf.  1. SpiBuadrateConfigRef is the reference node used in order to calculate the Spi baud rate. 2. SpiUseBaudrateConfig uses the reference node, SpiCalculatedBaudRate uses the following formula: SpiCalculatedBaudrate = Function clock / (SpiPrescalerValue * (SpiScaler + 2)) 3. You can use the existing example "Spi_Transfer_S32K344" to use as base. Also, chapter 3.6.13 of the previously mentioned file shows how to configure baud rate: Best regards, Julián
查看全文
S32G-VNP-RDB32 (SJA1110) 交换机中的寄存器访问 你好, 我想把值写进寄存器你能不能给我一个完整的地址来 读写地址 名称访问RESET描述 8Ch DYN_BE_LKP_ ENTRY0 R/W 0h (ffffFFe h) 8ch 之前的基址是什么?比如它会有 0x3fc0008c 所以在这个动态入口表中我们会有完整的地址你能不能给我 8Ch DYN_BE_LKP_ ENTRY0 R/W 0h (fffffF eh) 90h DYN_BE_LKP_ ENTRY1 R/W 0h 94h DYN_BE_LKP_ ENTRY2 R/W 0h 98h DYN_BE_LKP_ R/W 0h 98h DYN_BE_LKP_ ENTRY3 R/W 0h 9Ch DYN_BE_LKP_ ENTRY4 R/W 0h a0h a0h DYN_BE_LKP_ ENTRY5 R/W 0h A4H DYN_BE_LKP _CTRL R/W 0h (ff800000H) 你能不能给我提供在寄存器中配置动态条目的完整地址? 以及需要在 SJA1110 Switch 中实现此功能的地方 Re: Register Access in S32G-VNP-RDB32 (SJA1110) Switch 你好@Atkinson、 我知道这乍看起来可能并不简单,但实际上这个概念非常简单。 最终的寄存器地址取决于访问方法--是通过 AHB 在内部访问 M7 内核,还是通过 SPI_AP 接口从外部访问。基本地址因接入点而异。 寄存器地址使用 UM11107 表 2 中提供的基地址计算。例如,对于交换机子系统,SPI_AP 访问的基地址为0x00000000 ,AHB 访问的基地址为0xFF000000 。 在这种情况下,通过 AHB 访问寄存器0x8C (DYN_BE_LKP_ENTRY0)时,寄存器会变成0xFF00008C 。 现在,可能会让人感到困惑的地方来了:SDK 驱动程序定义了以下内容: #define SJA1110_L2_ART_LE_ADDR(0x3fc00023) /**< l2ArtLockedEntry 寄存器的地址 *   SWITCH_DRV_Write 例程将地址左移 2 位 (<< 2),用于内部 (AHB) 访问。对于 SPI 传输(级联开关设置中使用),不应用移位。因此,0x3fc00023 << 2 的结果是0xFF00008C。   我希望通过上面的解释,现在有感知了。   顺祝商祺! 帕维尔
查看全文