Hello!
While reading the "Chapter 24 RAM Controller (PRAMC)" of the MPC5777C Reference Manual, I had the following questions:
1 - What is a 64-bit WRP4 read burst?
2 - What is a 2-1-1-1 response?
3 - What is the purpose of the late-write buffer, since there is the possibility of performing write bursts? Does the late-write buffer merges single beat write transactions into a multi beat bursted transaction?
4 - The PRAMC offers the possibility to add an optional read wait-state to register RAM read data prior to returning it on the system bus. What does "register RAM read data means"? Where this data would be registered? In which scenario adding a wait state to the read accesses would be beneficial?
5 - Does the PRAMC or the SRAM have a row buffer to store the last accessed row in the memory array? DRAMs have this resource, but I am not sure if SRAMs have this as well.
6 - DRAMs follows the JEDEC standard to define its commands, such as the activate command (ACT) and the Column Address Strobe (CAS) command. Does the MPC5777C SRAM follow this standard, and thus, work with the same commands?
Best regards,
Matheus
2) Core cycles
3) No, it is not about speed. Data are putted off to late write buffer when another SRAM write is in progress. Pay attention to section 24.4.2.1 64-bit writes
4) I think it is just generic module description. This option works, but as there is no requirement, I don't see any benefit.
3) So the late write buffer is a memory faster than SRAM? If so, by which technology is the late-write buffer made?
4) The Reference Manual says that one of the PRAMC features is to have "Configurable read access timing (zero or one wait-state programmable) allowing use in large range of frequency targets". If there is no requirement to use this optional wait state, why does the RM says that the optional wait state allows use in a large range of frequency targets?
1) 4-beat wrapping burst. Wrapping mean that firstly wanted data are read first. If you need Word2 for instance, sequence is as follows: Word2 - Word3 - Word0 - Word1
2) First data are read is 2 cycles (Word2 in example above), then 1 cycle per word (Word3 - Word0 - Word1)
3) Late write buffer allows not to wait until end of write cycle. From CPU side data are just written to SRAM and terminated. Physically store to SRAM is performed later.
4) It mean 1 clock cycle is added (there is a buffer there), but I don’t see any benefit. As I know there is no requirement to use it.
5, 6) No it static RAM, not dynamic. It works differently.