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asoc-simple-card:升级到内核 6.18.x 后出现解析错误 您好, 这是我为内核 6.6.52 编写的工作 DT: / { codec: max98357a@0{ compatible = "maxim,max98357a"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&sdmode_en>; sdmode-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; status = "okay"; }; sound { compatible = "simple-audio-card"; simple-audio-card,name = "SAI3 MAX98357A"; simple-audio-card,format = "i2s"; simple-audio-card,widgets = "Speaker","Speakers"; simple-audio-card,routing = "Speakers","Speaker"; simple-audio-card,bitclock-master = <&cpu_dai>; simple-audio-card,frame-master = <&cpu_dai>; cpu_dai: simple-audio-card,cpu { sound-dai = <&sai3>; clocks = <&clk IMX8MP_CLK_SAI3>; clock-names = "mclk"; //system-clock-frequency = <&clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <32>; }; codec_dai: simple-audio-card,codec { sound-dai = <&codec>; //clocks = <&clk IMX8MP_CLK_SAI3>; }; }; }; &sai3{ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; #sound-dai-cells = <0>; clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, <&clk IMX8MP_AUDIO_PLL2_OUT>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; assigned-clocks = <&clk IMX8MP_CLK_SAI3>, <&clk IMX8MP_AUDIO_PLL1>, <&clk IMX8MP_AUDIO_PLL2>; assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>, <&clk IMX8MP_AUDIO_PLL1_OUT>; // Try common MCLK rates that divide well to 48 kHz multiples // Option A: 24.576 MHz (very common for MAX98357A + 48 kHz) assigned-clock-rates = <24576000>, // PLL2 for 48 kHz <22579200>; // PLL1 for 44.1 kHz // Option B (if 44.1 kHz needed later): use PLL1 + 22579200 //assigned-clock-rates = <22579200>; fsl,sai-asynchronous; fsl,sai-mclk-direction-output; status = "okay"; }; 升级到内核 6.18.20 后,SAI3 无法探测,而且我的声卡也无法工作。 启动日志显示: 平台声音:延迟探测待处理:asoc-simple-card:解析错误 从内核 6.6.52 到 6.18.x,DT 语法有哪些变化?我没有找到任何相关信息。我该如何调查解析错误? i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Linux Yocto Project Re: asoc-simple-card: parse error after upgrading to kernel 6.18.x 你好, 能否请您分享一下您的dmesg日志? 顺祝商祺! Re: asoc-simple-card: parse error after upgrading to kernel 6.18.x 嗨,豪尔赫, dmesg 日志和运行设备树(./dtc -I fs -O dts /proc/device-tree > /tmp/running.dts)随附的。 Re: asoc-simple-card: parse error after upgrading to kernel 6.18.x 您好, 我向前迈出了一步。启用内核配置选项 CONFIG_IMX_AIPSTZ=y 后,声卡设备即可使用。 由于 sai3 节点是 aips5 的子节点,因此我还需要在设备树中启用 aips5: &aips5 { status = "okay"; }; 现在我收到以下错误信息: [ 13.081746] fsl-sai 30c30000.sai: ASoC error (-110): at snd_soc_dai_hw_params() on sai-tx-rx [ 13.090223] sai-tx-rx-HiFi: ASoC error (-110): at __soc_pcm_hw_params() on sai-tx-rx-HiFi speaker-test -c 2 -r 48000 -t sine 2>&1 | head -20 [ 31.368187] fsl-sai 30c30000.sai: ASoC error (-110): at snd_soc_dai_hw_params() on sai-tx-rx [ 31.376682] sai-tx-rx-HiFi: ASoC error (-110): at __soc_pcm_hw_params() on sai-tx-rx-HiFi Unable to set hw params for playback: Connection timed out speaker-test 1.2.11 Playback device is default Stream parameters are 48000Hz, S16_LE, 2 channels Sine wave rate is 440.0000Hz Rate set to 48000Hz (requested 48000Hz) Buffer size range from 24 to 131072 Period size range from 12 to 16383 Periods = 4 Setting of hwparams failed: Connection timed out Re: asoc-simple-card: parse error after upgrading to kernel 6.18.x 我明白了,声音正常了。 我的内核配置: CONFIG_SND_IMX_SOC=m CONFIG_SND_IMX_SOC=m CONFIG_SND_SOC_FSL_SAI=m CONFIG_SND_SOC_FSL_UTILS=m CONFIG_IMX_AIPSTZ=y 设备树部分: /{ codec: max98357a@0{ compatible = "maxim,max98357a"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&sdmode_en>; sdmode-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; status = "okay"; }; sound { compatible = "simple-audio-card"; status = "okay"; simple-audio-card,name = "SAI3 MAX98357A"; simple-audio-card,format = "i2s"; simple-audio-card,widgets = "Speaker", "Speaker Ext"; simple-audio-card,routing = "Speaker Ext", "Speaker"; simple-audio-card,bitclock-master = <&cpu_dai>; simple-audio-card,frame-master = <&cpu_dai>; cpu_dai: simple-audio-card,cpu { sound-dai = <&sai3>; clocks = <&clk IMX8MP_CLK_SAI3>; clock-names = "mclk"; //system-clock-frequency = <&clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <32>; }; codec_dai: simple-audio-card,codec { sound-dai = <&codec>; }; }; }; &sdma2 { status = "okay"; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; }; &aips5 { status = "okay"; }; &audio_blk_ctrl { status = "okay"; assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, <&clk IMX8MP_AUDIO_PLL2>; assigned-clock-rates = <393216000>, <361267200>; }; &sai3{ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; #sound-dai-cells = <0>; assigned-clocks = <&clk IMX8MP_CLK_SAI3>; assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; assigned-clock-rates = <12288000>; clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>, <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; dma-names = "rx", "tx"; fsl,sai-asynchronous; fsl,sai-mclk-direction-output; status = "okay"; }; 设备树基础文件为 imx8mp.dtsi
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MPC564xL用RAppID Initのライセンス RAppIDがダウンロードされましたが、情報には以下のようにE0002と表示されています。これはどういう意味ですか?
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KE1 ECC RAM Single Bit Corrrection Have a few questions regarding ECC. I am currently using the MCM_LMFAR to determine where the ECC triggered a fault and then using that address to read then write back to correct it. Questions: 1. Does the ECC have the ability to autocorrect bits? Or do I really need to perform this read/write to address to correct? 2. If there is not autocorrect, will I need to compensate for byte alignment when performing my read/write correction mechanism? Currently I am performing a 4-byte read/write at the address denoted by the MCM_LMFAR. I feel like this is dangerous as I am not sure the MCM_LMFAR will always show a 4-byte aligned address. Re: KE1 ECC RAM Single Bit Corrrection Hello @sean_dvorscak , Thank you for your post. Could you please let me know which specific device in the KE1 family you are using? This will help me locate the relevant documentation more accurately or perform validation using the same device. BR Celeste Re: KE1 ECC RAM Single Bit Corrrection It's a KE18F512VLH16. Thanks for your help. Re: KE1 ECC RAM Single Bit Corrrection One more question actually. The automatic HW ECC correction functionality is enabled by default? I don't really see any bits in the MCM registers that would suggest it's a feature that can be disabled/enabled. Re: KE1 ECC RAM Single Bit Corrrection Hello @sean_dvorscak , Thanks for your reply. So for your questions: 1. Does the ECC have the ability to autocorrect bits? Or do I really need to perform this read/write to address to correct? ->> Yes, ECC does support hardware correction for single-bit errors. So you should not need a software read/write sequence to obtain corrected data.  2. If there is not autocorrect, will I need to compensate for byte alignment when performing my read/write correction mechanism? Currently I am performing a 4-byte read/write at the address denoted by the MCM_LMFAR. I feel like this is dangerous as I am not sure the MCM_LMFAR will always show a 4-byte aligned address. ->> If implementing an optional scrub, please align the access according to the actual access size or scrub granularity, not blindly to the raw MCM_LMFAR value. Also don't use a fixed 4-byte access unless you first align the address appropriately and confirm the access size is valid. In fact, For multi-bit / non-correctable ECC events , do not assume a read/write can repair the data, you should treat it as data corruption and recover from a known-good source or reinitialize the affected memory as appropriate. Hope it helps. BR Celeste --------------------------------------------------------------------------------------------------------------------- Note: If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! --------------------------------------------------------------------------------------------------------------------- Re: KE1 ECC RAM Single Bit Corrrection Thanks for the confirmation and info. And yes, I am handling uncorrectable bit errors differently. Re: KE1 ECC RAM Single Bit Corrrection Yes, ECC checking/generation is enabled by default after reset. Re: KE1 ECC RAM Single Bit Corrrection Have more follow up questions. Does the hardware correct the data within the Memory Cell, or only on the Read Out Data? Example from AN5335, is the Read-out Data being corrected from 0->1? That would mean we need to write back the corrected value to RAM to actually clear it. We are concerned if the data in the RAM memory cell is not corrected, a single bit error could degrade to a double bit error. Re: KE1 ECC RAM Single Bit Corrrection Hello @sean_dvorscak , I noticed that this thread has already been closed. To help us better track and follow up on this issue, could you please create a new post? Thank you for your cooperation.   BR Celeste
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etpu 曲轴读取信号-mpc5775e 您好, 我正在尝试使用CodeWarrior eTPU 功能集 (AN4907)在MPC5775E上使用 eTPU CRANK 功能。 根据 AN4907,当 CRANK 功能分配给通道 0 时,输入信号应通过TCRCLK连接。因此,我将外部曲轴信号连接到 EVB 上的TCRCLK 输入(J122,引脚 12) 。在引脚工具中相应地配置引脚,并启用角度模式(TBCR.AM) 。 然而,CRANK 函数始终检测不到任何输入信号。状态始终保持在SEEK(状态 = 0) ,齿计数器保持为零,并且不记录齿周期。 我已经核实了以下内容: 外部信号存在,可以作为 GPIO 正确读取。 CRANK 功能分配给发动机 A,通道 0 。 该引脚配置为TCRCLK 。 TBCR.AM已启用。 CRANK 通道已成功初始化,并具有高优先级。 尽管如此,eTPU 似乎并未检测到任何输入转换。 有没有人遇到过类似的问题,或者知道在 MPC5775E 上使用TCRCLK作为 CRANK 输入是否需要任何额外的配置? 我已附上我的项目供您参考。 若能得到任何帮助,我将不胜感激。 谢谢! Re: etpu crank-reading signal-mpc5775e 你好, 你体内可能存在活性IGF1。 我认为默认情况下过渡检测是禁用的,所以不会有信号通过。必须启用 IGF 旁路才能处理信号。 顺祝商祺! Peter
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S32DS.3.xIDEウイルスのチェックと削除 S32DS.3.5 IDEのインストールと更新中に、Alyacのウイルスチェックが出て削除しました。これらの症状は以前から知られていたものですか?その原因を突き止める解決策はあるのでしょうか? Re: S32DS.3.x IDE virus checked and deleted こんにちは、 正直に言うと、このようなメッセージを見たのは私にとって初めてのことです。インストーラーが破損しているか、ウイルス対策ソフトに問題がある可能性があります。 Re: S32DS.3.x IDE virus checked and deleted ランサムウェアが検出され、メッセージが削除されました
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etpu crank-reading signal-mpc5775e Hi, I am trying to use the eTPU CRANK function on an MPC5775E using the CodeWarrior eTPU Function Set (AN4907). According to AN4907, when the CRANK function is assigned to Channel 0, the input signal should be connected through TCRCLK. Therefore, I connected my external crank signal to the TCRCLK input (J122, pin 12) on the EVB. The pin is configured accordingly in the Pins Tool, and Angle Mode (TBCR.AM) is enabled. However, the CRANK function never detects any input signal. The state always remains in SEEK (state = 0), the tooth counters remain zero, and no tooth periods are logged. I have already verified the following: The external signal is present and can be read correctly as a GPIO. The CRANK function is assigned to Engine A, Channel 0. The pin is configured for TCRCLK. TBCR.AM is enabled. The CRANK channel is initialized successfully and has high priority. Despite this, the eTPU does not seem to detect any input transitions. Has anyone experienced a similar issue or knows if there is any additional configuration required for using TCRCLK as the CRANK input on the MPC5775E? I have attached my project for reference. Any help would be greatly appreciated. Thank you. Re: etpu crank-reading signal-mpc5775e Hello, You have probably active IGF1. I believe the transition detection is disabled by default, so no signal will pass through. The IGF bypass must be enabled in order for the signal to be processed. Best regards, Peter
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如何在 S32 Design Studio 中安装 S32K144EVB SDK 你好, 今天,我安装了 S32 Design Studio 来评估S32K144EVB板。我想运行一个小测试,但是阅读手册后发现,当我创建一个新的应用程序项目时,当我点击“SDK”按钮时,并没有出现任何 S32 SDK。 如何为我的开发板安装 SDK 谢谢。 Re: How install S32K144EVB SDK in S32 Design Studio 嗨@ptcaos 首先,您需要下载与您的 S32DS IDE 兼容的软件版本。支持的 IDE 版本在软件的发行说明文档中指定。 在这个例子中,我将使用适用于 S32K1 设备的最新 RTD 版本: 下载 S32K1_S32M24x_RTD_R21-11_3.0.0_D2503_DesignStudio_updatesite.zip。该软件包可在“S32K1 实时驱动程序→ 汽车软件 - S32K1_S32M24x - Cortex-M 实时驱动程序 → S32K1_S32M24x 实时驱动程序 AUTOSAR R21-11 版本 3.0.0”下找到。 在 S32 设计工作室 3.6.x 版本中,导航至帮助 → S32DS 扩展和更新。 在 S32DS 扩展和更新窗口中,单击右下角的“添加更新站点” 。 选择 .zip 文件文件是之前下载的。添加后,该代码包,软件包将出现在可用扩展和更新列表中。 选择要安装的软件包,然后单击“安装/更新” 。 接受许可协议,然后单击“完成”。 安装成功后,S32DS 将提示您重新启动 IDE 以使更改生效。 重要提示:创建新项目时,请确保选择与已安装的 RTD 软件包兼容的工具链版本。例如,RTD 3.0.0使用 NXP GCC 10.2.0 进行开发和测试。此信息可在相应的版本说明文档中找到。 BR,VaneB Re: How install S32K144EVB SDK in S32 Design Studio 剧透 (高亮部分可供阅读) 你好@VaneB 我已经安装了 S32K1_S32M24X 实时驱动程序版本 3.0.0QLP07 按照您描述的步骤操作,但是当我创建一个“新的 S32DS 应用程序项目”时,却找不到 SDK。 我附上了两张截图:一张是在处理器选择菜单中截取的,另一张是在按下“SDK”按钮后截取的。 谢谢。 您好,我已经安装了 S32K1_S32M24X 实时驱动程序 3.0.0 版。QLP07 按照您描述的步骤操作,但在创建“新的 S32DS 应用程序项目”时,没有可用的 SDK。我附上了两张截图:一张是在处理器选择菜单中截取的,另一张是在按下“SDK”按钮后截取的。谢谢。 Re: How install S32K144EVB SDK in S32 Design Studio 你好@ptcaos , 我遇到了完全相同的问题, @VaneB建议的解决方案对我也有效。 我安装了NXP GCC for Arm Release 版本 10.2 build 1728 ,然后在创建项目时,选择了GCC 10.2作为工具链。之后, RTD 3.0.0 就作为 SDK 选项出现了。 因此,关键在于仅仅安装 RTD 是不够的——还需要安装并选择兼容的 GCC 10.2 工具链。 感谢NXP技术支持提供的解决方案! Re: How install S32K144EVB SDK in S32 Design Studio 嗨@ptcaos 请安装 NXP GCC for Arm Release 版本 10.2 build 1728。 这样就应该使 RTD 版本达到 3.0.0。创建新项目时,只要选择 GCC 10.2 作为项目的工具链,即可将其作为 SDK 选项使用。
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KE1 ECC RAM 单比特纠错 关于ECC,我有一些问题。 我目前使用 MCM_LMFAR 来确定 ECC 触发故障的位置,然后使用该地址读取并写回以纠正故障。 问题: 1. ECC 是否具备自动纠错功能?或者我真的需要对地址进行读/写操作才能纠正错误吗? 2. 如果没有自动纠错功能,我在执行读/写纠错机制时是否需要补偿字节对齐问题?目前我正在对 MCM_LMFAR 指示的地址执行 4 字节的读/写操作。我觉得这样做很危险,因为我不确定 MCM_LMFAR 是否总是显示 4 字节对齐的地址。 Re: KE1 ECC RAM Single Bit Corrrection 你好@sean_dvorscak , 感谢您的帖子。 请问您使用的是KE1系列中的哪一款具体设备? 这将有助于我更准确地找到相关文档,或使用同一设备进行验证。 BR 塞莱斯特 Re: KE1 ECC RAM Single Bit Corrrection 它是 KE18F512VLH16。 感谢您的帮助。 Re: KE1 ECC RAM Single Bit Corrrection 你好@sean_dvorscak , 感谢您的回复。 所以,对于你的问题: 1. ECC 是否具备自动纠错功能?或者我真的需要对地址进行读/写操作才能纠正错误吗? 是的,ECC确实支持硬件纠正单比特错误。因此,您无需使用软件读/写序列即可获得校正后的数据。 2. 如果没有自动纠错功能,我在执行读/写纠错机制时是否需要补偿字节对齐问题?目前我正在对 MCM_LMFAR 指示的地址执行 4 字节的读/写操作。我觉得这样做很危险,因为我不确定 MCM_LMFAR 是否总是显示 4 字节对齐的地址。 ->> 如果要实施可选的清理操作,请根据实际访问大小或清理粒度来调整访问权限,而不是盲目地根据原始 MCM_LMFAR 值来调整。此外,除非您先正确对齐地址并确认访问大小有效,否则不要使用固定的 4 字节访问。 事实上,对于多位/不可纠正的 ECC 事件,不要假设读/写操作可以修复数据,而应将其视为数据损坏,并从已知良好的源进行恢复,或根据情况重新初始化受影响的内存。 希望对您有所帮助。 BR 塞莱斯特 --------------------------------------------------------------------------------------------------------------------- 注:如果此帖解答了您的问题,请点击“接受为解决方案”按钮。谢谢你! --------------------------------------------------------------------------------------------------------------------- Re: KE1 ECC RAM Single Bit Corrrection 感谢您的确认和信息。 是的,我对无法纠正的比特错误采取了不同的处理方式。 Re: KE1 ECC RAM Single Bit Corrrection 还有一个问题。 自动硬件纠错功能默认启用吗?我没有在 MCM 寄存器中看到任何可以表明这是一个可以禁用/启用的功能的位。 Re: KE1 ECC RAM Single Bit Corrrection 是的,RESET后默认启用ECC校验/生成功能。 Re: KE1 ECC RAM Single Bit Corrrection 还有一些后续问题。 硬件是校正存储单元内的数据,还是只校正读取的数据? 例如,根据 AN5335,读取数据是否已从 0 到 > 1 进行校正?这意味着我们需要将更正后的值写回 RAM 才能真正清除它。 我们担心,如果 RAM 存储单元中的数据没有得到纠正,单比特错误可能会演变成双比特错误。 Re: KE1 ECC RAM Single Bit Corrrection 你好@sean_dvorscak , 我注意到这个帖子已经关闭了。为了帮助我们更好地跟踪和跟进此问题,请您创建一个新帖子好吗?感谢您的合作。   BR 塞莱斯特
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S32 design Studio I am trying to install S32 design studio v2.0. When I install S32 design studio v2.0 it send request.xml I take this file to license request for Activation.xml I store this on to my computer. When I get back to the install it has timeout and will not let me add the Activation.xml file. How do I do this is the time they allow? Re: S32 design Studio Hi,  in your activation request is missing Unique Machine ID. Without this ID the S32DS can't be activated. Your very first attempt on different PC machine contains such ID and the activation was ok.  The Missing machine UID often occurs when you are using Virtual Machine. In some cases the OS security policy block S32SD to obtain such ID from OS. You can try to backup content of c:\ProgramData\FLEXnet\ folder, delete it and try the installation again. 
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asoc-simple-card: parse error after upgrading to kernel 6.18.x Hi, here is my working DT for Kernel 6.6.52: / { codec: max98357a@0{ compatible = "maxim,max98357a"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&sdmode_en>; sdmode-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; status = "okay"; }; sound { compatible = "simple-audio-card"; simple-audio-card,name = "SAI3 MAX98357A"; simple-audio-card,format = "i2s"; simple-audio-card,widgets = "Speaker","Speakers"; simple-audio-card,routing = "Speakers","Speaker"; simple-audio-card,bitclock-master = <&cpu_dai>; simple-audio-card,frame-master = <&cpu_dai>; cpu_dai: simple-audio-card,cpu { sound-dai = <&sai3>; clocks = <&clk IMX8MP_CLK_SAI3>; clock-names = "mclk"; //system-clock-frequency = <&clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <32>; }; codec_dai: simple-audio-card,codec { sound-dai = <&codec>; //clocks = <&clk IMX8MP_CLK_SAI3>; }; }; }; &sai3{ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; #sound-dai-cells = <0>; clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, <&clk IMX8MP_AUDIO_PLL2_OUT>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; assigned-clocks = <&clk IMX8MP_CLK_SAI3>, <&clk IMX8MP_AUDIO_PLL1>, <&clk IMX8MP_AUDIO_PLL2>; assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>, <&clk IMX8MP_AUDIO_PLL1_OUT>; // Try common MCLK rates that divide well to 48 kHz multiples // Option A: 24.576 MHz (very common for MAX98357A + 48 kHz) assigned-clock-rates = <24576000>, // PLL2 for 48 kHz <22579200>; // PLL1 for 44.1 kHz // Option B (if 44.1 kHz needed later): use PLL1 + 22579200 //assigned-clock-rates = <22579200>; fsl,sai-asynchronous; fsl,sai-mclk-direction-output; status = "okay"; }; After moving to kernel 6.18.20 SAI3 is not probing and I got no sound-card. The boot log shows: platform sound: deferred probe pending: asoc-simple-card: parse error What changes in the DT syntax from kernel 6.6.52 to 6.18.x? I didn't find anything relevant. How can I investigate the parse error? i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Linux Yocto Project Re: asoc-simple-card: parse error after upgrading to kernel 6.18.x Hello, Could you please share your dmesg log? Best regards. Re: asoc-simple-card: parse error after upgrading to kernel 6.18.x Hi Jorge, dmesg log and running device tree (./dtc -I fs -O dts /proc/device-tree > /tmp/running.dts) attached. Re: asoc-simple-card: parse error after upgrading to kernel 6.18.x Hi, I have moved one step forward. After enabling the kernel configuration option CONFIG_IMX_AIPSTZ=y, the sound card device is now available. Because  sai3 node is a sub node of aips5 I also had to enable aips5 in my devicetree: &aips5 { status = "okay"; }; Now I got the following error messages: [ 13.081746] fsl-sai 30c30000.sai: ASoC error (-110): at snd_soc_dai_hw_params() on sai-tx-rx [ 13.090223] sai-tx-rx-HiFi: ASoC error (-110): at __soc_pcm_hw_params() on sai-tx-rx-HiFi speaker-test -c 2 -r 48000 -t sine 2>&1 | head -20 [ 31.368187] fsl-sai 30c30000.sai: ASoC error (-110): at snd_soc_dai_hw_params() on sai-tx-rx [ 31.376682] sai-tx-rx-HiFi: ASoC error (-110): at __soc_pcm_hw_params() on sai-tx-rx-HiFi Unable to set hw params for playback: Connection timed out speaker-test 1.2.11 Playback device is default Stream parameters are 48000Hz, S16_LE, 2 channels Sine wave rate is 440.0000Hz Rate set to 48000Hz (requested 48000Hz) Buffer size range from 24 to 131072 Period size range from 12 to 16383 Periods = 4 Setting of hwparams failed: Connection timed out Re: asoc-simple-card: parse error after upgrading to kernel 6.18.x I got it, sound is working. My kernel configs: CONFIG_SND_IMX_SOC=m CONFIG_SND_IMX_SOC=m CONFIG_SND_SOC_FSL_SAI=m CONFIG_SND_SOC_FSL_UTILS=m CONFIG_IMX_AIPSTZ=y The devicetree part: /{ codec: max98357a@0{ compatible = "maxim,max98357a"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&sdmode_en>; sdmode-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; status = "okay"; }; sound { compatible = "simple-audio-card"; status = "okay"; simple-audio-card,name = "SAI3 MAX98357A"; simple-audio-card,format = "i2s"; simple-audio-card,widgets = "Speaker", "Speaker Ext"; simple-audio-card,routing = "Speaker Ext", "Speaker"; simple-audio-card,bitclock-master = <&cpu_dai>; simple-audio-card,frame-master = <&cpu_dai>; cpu_dai: simple-audio-card,cpu { sound-dai = <&sai3>; clocks = <&clk IMX8MP_CLK_SAI3>; clock-names = "mclk"; //system-clock-frequency = <&clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <32>; }; codec_dai: simple-audio-card,codec { sound-dai = <&codec>; }; }; }; &sdma2 { status = "okay"; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; }; &aips5 { status = "okay"; }; &audio_blk_ctrl { status = "okay"; assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, <&clk IMX8MP_AUDIO_PLL2>; assigned-clock-rates = <393216000>, <361267200>; }; &sai3{ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; #sound-dai-cells = <0>; assigned-clocks = <&clk IMX8MP_CLK_SAI3>; assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; assigned-clock-rates = <12288000>; clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>, <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; dma-names = "rx", "tx"; fsl,sai-asynchronous; fsl,sai-mclk-direction-output; status = "okay"; }; The devicetree base is imx8mp.dtsi
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S32 Design Studio 我正在尝试安装 S32 设计工作室 v2.0。安装 S32 设计工作室 v2.0 时,它会发送 request.xml 文件。我将此文件用于获取激活许可请求,并将其存储在我的计算机上。当我返回安装程序时,它超时了,不允许我添加 Activation.xml 文件。我该如何在规定的时间内完成这件事? Re: S32 design Studio 你好, 您的激活请求中缺少唯一机器 ID。如果没有这个ID,S32DS就无法激活。您第一次在不同的电脑上尝试激活时使用了这样的ID,并且激活成功。 当您使用虚拟机时,经常会出现缺少机器 UID 的情况。在某些情况下,操作系统安全策略会阻止 S32SD 从操作系统获取此类 ID。您可以尝试备份 c:\ProgramData\FLEXnet\ 文件夹的内容,然后将其删除并重新尝试安装。
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etpu クランク読み取り信号-mpc5775e こんにちは、 私はCodeWarrior eTPU Function Set (AN4907)を使用してMPC5775EでeTPU CRANK機能を使用しようとしています。 AN4907によると、CRANK機能が チャネル0に割り当てられた場合、入力信号は TCRCLK経由で接続されるべきです。そこで、外部クランク信号をEVBの TCRCLK入力(J122、ピン12) に接続しました。ピンはピンツールで適切に設定され、角度モード(TBCR.AM)が有効になっています。 しかし、CRANK機能は入力信号を一切検出しません。状態は常にSEEK(状態=0)のままであり、歯カウンターはゼロのままで、歯周期は記録されません。 私は既に以下の事項を確認済みです。 外部信号は存在し、GPIOとして正しく読み取ることができます。 CRANK機能は エンジンA、チャンネル0に割り当てられています。 このピンはTCRCLK用に設定されています。 TBCR.AMが有効になっています。 CRANKチャネルは正常に初期化され、高い優先度を持ちます。 それにもかかわらず、eTPUは入力遷移を一切検出していないようだ。 同様の問題を経験された方、またはMPC5775EでTCRCLKをCRANK入力として使用するために追加の設定が必要かどうかをご存知の方はいらっしゃいますか? 参考までに、私のプロジェクトを添付しました。 どんなご支援でも大変感謝いたします。 よろしくお願いします。 Re: etpu crank-reading signal-mpc5775e こんにちは、 おそらく、あなたは活性型のIGF-1を持っているでしょう。 トランジション検出はデフォルトで無効になっているので、信号は通過しないと思います。信号を処理するには、IGFバイパスを有効にする必要があります。 よろしくお願いいたします。 ピーター
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Using HCI_VENDOR_CONFIG_TX_POWER on KW47 and MCXW72 Bluetooth LE Devices When performing Bluetooth LE RF testing on KW47 and MCXW72 devices, it may be necessary to configure the transmitter output power through a vendor-specific HCI command. NXP's Test Tool provides a convenient way to send HCI commands during Direct Test Mode (DTM) validation and characterization. Although the Test Tool is still commonly referenced in documentation and application workflows, it is no longer actively maintained. As a result, the default HCI command XML definitions included with the tool do not correctly support the vendor-specific Tx power command required by KW47 and MCXW72 devices. The default Test Tool XML does not correctly define the vendor-specific HCI_VENDOR_CONFIG_TX_POWER command for KW47 and MCXW72 devices. As a result, the command is not available in the GUI. Edit BLE HCI 5.0 1.6.1.xml (typically located in C:\nxp\Test Tool 12.9.2.2\Xml) and replace the command definition with the XML snippet provided in this article. Alternatively, replace the original XML file with the updated file attached to this article. Vendor_Commands HCI_VENDOR_CONFIG_TX_POWER HCI_VENDOR_CONFIG_TX_POWER Desc. OgB: FD OcB: 2D 01 3F 012D tx_power tx_power Desc 1 tInt 00 00 Channel type Desc 1 tInt 00 00 NotUsed Not Used 2 tInt 00 00 ​ After updating the XML file and restarting Test Tool, HCI_VENDOR_CONFIG_TX_POWER should appear in the GUI. HCI_VENDOR_CONFIG_TX_POWER command parameters: tx_power[1]: Supported values are 0x00 (0 dBm), 0x07 (7 dBm), and 0x0A (10 dBm). Channel[1]: Supported values are 0x00 (applies to advertising channels) and 0x01 (applies to non-advertising channels). NotUsed[2]: Reserved parameter. Always set this field to 0x0000.
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CAN-FD maximum baud rate on KW47 and MCXW72 The clock tolerance for CAN FD at high baud rates is generally considered to be tight compared to lower baud rates, meaning that the clock frequency needs to be very precise to ensure reliable communication; this is due to the high data rate requiring precise bit timing. CAN generally requires crystal or PLL clock source due to accuracy requirements, on KW45/7 that is limited to 32 MHz crystal (SOSC) since there is no PLL available. However, the FRO192 (FIRC) can be fine trimmed to the SOSC crystal as reference, in a closed loop configuration. When operating in closed loop the FRO192 accuracy is +/-0.25%. The FRO192 when operating in open loop (default) will not be accurate enough for CAN-FD (+/-3%). Closed loop operation is enabled while SCG0→FIRCCSR[FIRCTRUP] = 1 and SCG0→FIRCCSR[FIRCTREN] =1. The auto trim continues as long as those bits are set (for example if change in temperature causes the FRO192clock frequency to drift). Once locked, only the fine trim bits would be updated on subsequent corrections. Refer to code snippet below for correct clock configuration: #include "clock_config.h" #include "fsl_clock.h" const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN = { .freq = 32000000U, /* System Oscillator frequency: 32000000Hz */ .monitorMode = kSCG_SysOscMonitorDisable, /* System OSC Clock Monitor is disabled */ .enableMode = kSCG_SoscEnable, /* System OSC Enable */ }; const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN = { .divSlow = (uint32_t)kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */ .divBus = (uint32_t)kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */ .divCore = (uint32_t)kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */ .src=(uint32_t)kSCG_SysClkSrcFirc, /* Fast IRC is selected as System Clock Source */ }; static const scg_firc_trim_config_t FircTrimConfig_BOARD_BootClockRUN = { .trimMode = kSCG_FircTrimUpdate, /* FIRC trim is enabled and trim value update is enabled */ .trimsrc=kSCG_FircTrimSrcSysOsc, /* Trim source is System OSC */ .trimDiv = 31U, /* Divided by 32 */ .trimCoar = 0U, /* Trim value, see Reference Manual for more information */ .trimFine = 0U, /* Trim value, see Reference Manual for more information */ }; const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN = { .enableMode = kSCG_FircEnable, /* Fast IRC is enabled */ .range = kSCG_FircRange96M, /* 96 Mhz FIRC clock selected */ .trimConfig = &FircTrimConfig_BOARD_BootClockRUN, }; /* Unlock FIRC and SOSC control status registers */ CLOCK_UnlockFircControlStatusReg(); CLOCK_UnlockSysOscControlStatusReg(); /* Init FIRC */ CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN); /* Set SCG to FIRC mode */ CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN); /* Wait for clock source switch finished */ do { CLOCK_GetCurSysClkConfig(&curConfig); } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src); /* Initializes SOSC according to board configuration */ (void)CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockRUN); /* Set the XTAL0 frequency based on board settings */ CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockRUN.freq); /* For 6 mbps baud rate requires FRO192M as FlexCAN source clock */ CLOCK_SetIpSrc(kCLOCK_Can0, kCLOCK_IpSrcFro192M); CLOCK_SetIpSrcDiv(kCLOCK_Can0, kSCG_SysClkDivBy1); The maximum supported baud rate for KW47 and MCXW72 devices is 6 Mbps. Although higher rates may be achievable on some SoCs, 6 Mbps is the highest baud rate supported by the device clock specifications.  For simplicity, the FlexCAN driver APIs can be used to configure the CAN FD baud rate, as shown in the following code snippet: #include "fsl_flexcan.h" #define EXAMPLE_CAN CAN0 #define USE_CANFD (1) #define RX_MESSAGE_BUFFER_NUM (0) #define TX_MESSAGE_BUFFER_NUM (1) #define BYTES_IN_MB kFLEXCAN_64BperMB /* For 6 Mbps use case. FRO192 must be selected as clock source */ #define EXAMPLE_CAN_CLK_FREQ CLOCK_GetFreq(kCLOCK_ScgFircClk) #define USE_IMPROVED_TIMING_CONFIG (1) flexcan_config_t flexcanConfig; /* Get FlexCAN module default Configuration. */ /* * flexcanConfig.clksrc=kFLEXCAN_ClkSrc0; * flexcanConfig.bitRate = 1000000U; * flexcanConfig.bitRateFD = 2000000U; * flexcanConfig.maxMbNum = 16; * flexcanConfig.enableLoopBack = false; * flexcanConfig.enableSelfWakeup = false; * flexcanConfig.enableIndividMask = false; * flexcanConfig.disableSelfReception = false; * flexcanConfig.enableListenOnlyMode = false; * flexcanConfig.enableDoze = false; */ FLEXCAN_GetDefaultConfig(&flexcanConfig); /* Manually override default CAN FD config to 1 Mbps for nominal rate and 6 Mbps for data rate */ flexcanConfig.bitRate = 1000000U; flexcanConfig.bitRateFD = 6000000U; #if (defined(USE_IMPROVED_TIMING_CONFIG) && USE_IMPROVED_TIMING_CONFIG) flexcan_timing_config_t timing_config; memset(&timing_config, 0, sizeof(flexcan_timing_config_t)); if (FLEXCAN_FDCalculateImprovedTimingValues(EXAMPLE_CAN, flexcanConfig.bitRate, flexcanConfig.bitRateFD, EXAMPLE_CAN_CLK_FREQ, &timing_config)) { /* Update the improved timing configuration*/ memcpy(&(flexcanConfig.timingConfig), &timing_config, sizeof(flexcan_timing_config_t)); } #endif FLEXCAN_FDInit(EXAMPLE_CAN, &flexcanConfig, EXAMPLE_CAN_CLK_FREQ, BYTES_IN_MB, true); Note: The maximum supported CAN baud rate for KW47 and MCXW72 devices is 2 Mbps. While higher rates may be achievable under certain conditions, operation above 2 Mbps is outside the supported specification and is not recommended for applications in the field. 
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请求协助:S32 Design Studio for ARM 许可证续订错误 尊敬的恩智浦技术支持团队: 你好, 我写信请求支持,因为我在尝试续订 S32 Design Studio for S32 的许可证时遇到了错误。 以下是我的驾照详情和收到的错误信息: < License Information > < Error Message > 请问如何解决此问题并成功延长/续订许可证? 感谢您抽出时间提供帮助。 顺祝商祺! 成秀贤 Re: Request for Assistance: S32 Design Studio for ARM License Renewal Error @jiri_kral 许可证现已激活并运行正常。 感谢您的帮助! BRs, 宋 Re: Request for Assistance: S32 Design Studio for ARM License Renewal Error 你好, 请再次尝试激活。我归还了旧的驾照。
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请求提供 i.MX RT1176 双核以太网示例(每个核心一个以太网接口) 您好,NXP团队, 我目前正在 使用 MCUXpresso IDE v11.9.1(版本 2170,2024-04-19) 开发 i.MX RT1176 评估板 。 我想知道 NXP 是否提供任何多核示例项目,以演示如何使用 Cortex-M7 和 Cortex-M4 内核以及独立的以太网接口。 我的需求如下: 以太网端口 1应由Cortex-M7内核初始化和管理。 以太网端口 2应由Cortex-M4内核初始化和管理。 两个以太网接口应在其各自的内核上同时独立运行。 如果需要进行核心间通信(例如 RPMsg 或 MU),我希望能够提供一些示例或文档来解释推荐的方法。 我搜索了 MCUXpresso SDK 示例,但没有找到符合此用例的项目。 请问您能否告知我以下信息: NXP 是否有官方的多核示例演示如何在 M7 内核上使用一个以太网控制器,在 M4 内核上使用另一个以太网控制器? 如果有这样的示例,能否请您分享一下项目,或者提供相应的 SDK 示例名称或代码库链接? 如果没有这样的例子,您能否建议在 i.MX RT1176 上实现此配置的推荐架构? 任何参考项目、应用笔记或文档都将不胜感激。 感谢您的支持。 顺祝商祺! 阿拉文德·托加拉利 Re: Request for Dual-Core Ethernet Example on i.MX RT1176 (One Ethernet per Core) 尊敬的@Aravind_Togaralli , 遗憾的是,目前还没有官方示例能够证明 Cortex-M7 和 Cortex-M4 可以同时运行独立的以太网接口。 然而,推荐的架构是保持两个以太网子系统完全独立: 将一个以太网控制器(例如 ENET/ENET_QOS)分配给 CM7,将另一个分配给 CM4。 每个核心都应该维护自己的 MAC 驱动程序、PHY 控制、lwIP 协议栈、netif 实例、DMA 描述符、数据包缓冲区、中断和网络配置。 仅在需要时才使用 RPMsg-Lite、MU 或共享内存进行核心间控制和状态通信。 在开发过程中,可以考虑使用 RDC/XRDC2 来隔离两个内核之间的以太网外设和内存资源。 对于以太网 DMA 缓冲区,请确保所选内存区域可被相应的 CPU 和以太网 DMA 主设备访问。 建议的实施方案如下: 从一个可运行的RT1170多核示例开始。 使用标准的 lwIP 示例在 CM7 上启动以太网。 使用第二个以太网控制器在 CM4 上启动以太网。 验证两个以太网接口是否同时运行且无进程间通信 (IPC)。 如有需要,添加 RDC/XRDC2 隔离。 仅当应用程序需要核心间交互时才引入 RPMsg-Lite 或 MU/共享内存通信。 您可能还会发现应用笔记AN13264很有帮助,因为它为 RT1170 多核应用程序开发提供了指导和建议。 顺祝商祺! 张雪莉
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CSIデモ問題 こんにちは、 こちらはQuectelのFAEチームのブライアンです。 9月に開催されるNXPの展示会に向けて、CSI関連のデモをいくつか準備する予定です。デモの例について少し助けていただけますか? 例えば、モーション検知に似た例がいくつかありましたが、ボード上で取得したCSIデータをどのように分析し、活用すればよいのか教えていただきたいです。 rw610とrw612があります 私のメールアドレス:[email protected] Re: CSI demo question こんにちは、 @BryanNiu RW610とRW612はどちらもCSIをサポートしています。 すでにデフォルトのSDKリリースにデモが入っています:wifi_cli例です。 wifi_cliアプリケーションはCSIの生成および収集の設定に使用されます。このアプリケーションはSDKリリースに含まれています。CSIデータを生成するには、Wi-FiデバイスにWi-fi_cliアプリケーションをフラッシュし、以下のコマンドを実行します。 wlan-set-csi-param-header wlan-set-csi-filter wlan-csi-cfg wlan-auto-null-tx 詳細については以下をご覧ください: AN14281: FreeRTOSのチャネルステートインフォメーション(CSI) | NXPセミコンダクターズ この件に関して他に懸念があれば教えてください。もしなければ、このスレッドの解決策として私の回答をマークしてください。 よろしくお願いいたします。 Christine。 Re: CSI demo question こんにちは、 @Christine_Li さん。 情報ありがとうございます。SDKの基本的なwifi_cli例を成功裏に実行しました。 さらに一歩進んで、CSIデータを分析してデモを開発したいと考えています。RW61x上でCSIモーション検知を行うための以下のリポジトリを見つけました。このデモは弊社のモジュールと互換性がありますか? https://github.com/nxp-appcodehub/dm-motion-detection-using-wifi-csi-on-rw61x あるいは、似たようなデモをおすすめできますか? よろしくお願いします。 ブライアン Re: CSI demo question こんにちは、 @BryanNiu 共有リンクで言及されているデモも、FRDM-RW612向けに設計されています。 ですので、はい、FRDM-RW612では動作するはずです。 RW612モジュールを使用している場合でも、同様に動作するはずです。 しかしSDKバージョンでは、少し古いSDK 25.09.00を使っています。現在、最新のSDKバージョンはSDK 26.06.00です。 最新のSDK 26.06.00と、私が提供したANに従って、CSIのRW612についての詳細を知りたい方はぜひ試してみてください。 この件に関して他に懸念があれば教えてください。 よろしくお願いいたします。 Christine。
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S32 设计工作室许可证续期 订单号:128143961 有效期至:2026年6月22日 产品:S32 Design Studio for ARM v2018 R1 激活码:3E1F-50E5-6F93-F06F Re: S32 Design Studio License Renewal 你好, 现在已扩展。 顺祝商祺! Peter
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禁用 MPU 时 SRAM 的 S32K 默认属性 您好,NXP技术团队, 我想知道当S32K芯片的MPU未启用时,SRAM的默认属性是什么?具体来说,SRAM 默认设置中的“共享”和“缓存”属性分别是什么? 我查阅了 ARMv7-m 架构参考手册,其中指出 SRAM 的设备类型为“device”,这似乎意味着整个 SRAM 是可共享的且不可缓存的。请看下图。 回到我的项目,该项目使用了 MWCT2016s(即当 MPU 未启用时,S32K312) 的 HSE 功能异常,需要配置 MPU 将 SRAM 区域设置为可共享且不可缓存。但是,在使用 S32K322 的项目中,当 MPU 未启用时,HSE 功能正常。 因此,我想知道在未启用 MPU 的情况下 S32K 芯片的 SRAM 属性,或者是否存在其他设置会影响 SRAM 属性,从而导致两个项目之间的差异? Re: S32K default attribute of SRAM when disable MPU 嗨@Johnson97 , 它使用默认内存映射: https://developer.arm.com/documentation/dui0646/c/Cortex-M7-Peripherals/Optional-Memory-Protection-Unit/MPU-Control-Register?lang=en “当 ENABLE 位设置为 0 时,系统使用默认内存映射。这与未实现 MPU 的情况具有相同的内存属性,参见表 2.11。默认内存映射适用于特权软件和非特权软件的访问。 https://developer.arm.com/documentation/dui0646/c/The-Cortex-M7-Processor/Memory-model/Behavior-of-memory-accesses?lang=en#CHDBJAJD 如表 2.11 和表 2.12 所示,SRAM 的存储器类型为普通型、不可共享型、WBWA 型。 此致, 丹尼尔
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[S32N55 / HSE2] Debug Card Request — HSE_DEBUG_INVALID_DEBUG_DOMAIN_MAP_ERR Hi, Following up on S32N55 (HSE2) Secure Debug. CRS(APP) challenge-response authentication now works (final response 0x4A4A4A4A). I am now on the debug card request (HSE_DEBUG_CMD_CARD_REQUEST), and it returns: HSE_DEBUG_INVALID_DEBUG_DOMAIN_MAP_ERR ((hseDebugError_t)0x20) — "invalid debug domain map in debug card." What I send (per your earlier feedback): Packet2 Debug Domain Signal List: array style, List[22..26] = 0x01 each (CRS: Cortex-M7, PCIe, CRS NoC/CAN NoC, CANXL0-1, CANXL2-3), all other bytes 0x00. Packet3 enabledDebugDomainMap (uint64_t): 0x07C00000 as advised (bits 22-26). AuthScheme: macAlgo = HSE_MAC_ALGO_CMAC = 0x11. AuthTag: AES256-CMAC over the card info, authLen = 16. What I have tried for enabledDebugDomainMap (uint64_t, 8 bytes on the wire): Little-endian: 00 00 C0 07 00 00 00 00 → 0x20 Big-endian: 00 00 00 00 07 C0 00 00 → 0x20 bit27 (0x08000000, matching AUTH target 0x1B) → 0x20 All return the same 0x20. Questions: 1. For CRS, what is the exact enabledDebugDomainMap (uint64_t) value HSE expects, and in what wire byte order? 2. Must enabledDebugDomainMap (Packet3 bitmask) be consistent with the Debug Domain Signal List (Packet2, array List[22..26])? What is the exact relationship? 3. The RM example states "domain 1,3 enabled → 0x00..A0." Could you clarify the domain-to-bit mapping so I can compute the CRS value? 4. Does HSE validate the domain map before verifying the AuthTag? I want to confirm whether 0x20 indicates only the domain map is wrong, or whether other fields (e.g. the AuthTag / signed data range) could also be causing HSE to stop at this point. I also want to confirm the signed data range for the card AuthTag: I currently compute AES256-CMAC over the card info fields (authKeyRef + reserved0 + ownerId + authScheme + signal list + domain map + UID list). Is this the correct data to sign? Best regards, Re: [S32N55 / HSE2] Debug Card Request — HSE_DEBUG_INVALID_DEBUG_DOMAIN_MAP_ERR Hello, @EddiePark  Thanks for your post. 1. It is pleased to hear that the phase1 has been passed without issues.2.  For your phase2 queries, I am still checking with it for a more clear description, and would reply you later if there are any valuable updates To make it aligned, would you mind sharing with me the latest logs and corresponding scripts used again, which could be shared via message as usual. BR Chenyin  
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