Code is slower executing from tightly-coupled (ITC) memory As an experiment, I tagged a fairly costly function with __RAMFUNC(SRAM_ITC) To my surprise, it ran about 10% slower. Could anyone share any insight on why that might be? This is on an iMXRT1062, running from flash (XIP) if not running from ITC. i.MXRT 106x Re: Code is slower executing from tightly-coupled (ITC) memory Hello @expertsleepers, The FPU setting for all M7 cores of the iMXRT family should be FPv5-D16. The only exception is the iMXRT1011, here it must be FPv5-SP-D16. For the M4 and M33 cores it is also FPv5-SP-D16. The reason why it is not faster in the ITCM than when executing from the flash is that the function is probably so small that it fits completely into the cache. However, if the code base increases in size, cache trashing occurs. This means that the speed at which the function is executed is no longer deterministic. Regards Re: Code is slower executing from tightly-coupled (ITC) memory Hello @expertsleepers, If the function to be called is a maximum of four megabytes “away” in the address range, a direct jump “BL” can be used without veneer. Regards Re: Code is slower executing from tightly-coupled (ITC) memory This was indeed it. The full situation was: The code uses a lot of double precision maths. The project was set to use a single precision floating point ABI, and so was full of function calls instead of .f64 operations. When the code was put in ITCM every one of those function calls went through a veneer. Having selected a double precision ABI, the function is now twice as fast and doesn't slow down when in ITCM. It doesn't get any faster either, but I'm sure there are more mundane reasons for that. 🙂 I find it odd that the project was created with the wrong ABI - it was created from a iMXRT1062 template. This thread was useful regarding the FP ABI: https://community.nxp.com/t5/i-MX-RT/FPU-Type-options-for-MCUXpresso-for-double-precision-floating/m-p/1231125/highlight/true#M12674 Re: Code is slower executing from tightly-coupled (ITC) memory Ah yes, it could be that. Just to be clear, are function calls from ITC to other ITC functions still fast? Re: Code is slower executing from tightly-coupled (ITC) memory Hello @expertsleepers, does the code you execute from the ITCM call functions that are located in flash or SDRAM/OCRAM? These are now more expensive because the compiler inserts a veneer function. When calling Std-Lib functions, it is also not quite obvious where they are located. Regards Re: Code is slower executing from tightly-coupled (ITC) memory But would that not also be true if the function was executing from flash? The function accesses OC SRAM and external DRAM. Both will cause waits, I'm sure, but I can't see how that would make ITC slower than XIP. Re: Code is slower executing from tightly-coupled (ITC) memory It is possible that the function has some routine that expects data contained on another memory inducing some wait states to the execution. Best regards, Omar Re: Code is slower executing from tightly-coupled (ITC) memory I understand. Following this topic. Re: Code is slower executing from tightly-coupled (ITC) memory Unfortunately the code in question is part of a very large project. I'd have to try to isolate it into a fresh project - which of course may not exhibit the same behaviour. I'll post if I manage to create a small test case. Re: Code is slower executing from tightly-coupled (ITC) memory Interesting. Would you be able to provide a test case? I'd like to reproduce this behaviour.

リンクアドレスとプログラム実行時間の関係 リンクアドレスが異なると、同じプログラムの実行時間が変わります。それらの間の関係は何ですか?プログラムの最適な実行を確保する方法は? 日時:リンクアドレスとプログラム実行時間の関係 わかりました。ありがとう。 日時:リンクアドレスとプログラム実行時間の関係 こんにちは、センレント、 ご提案ありがとうございます! マップファイルの特徴は、以下の通りです。section(".func_mem_area")で関数を指定します。この領域の開始アドレスを変更すると、実行時間が異なります。 また、0x00001410~0x0000141Fなどのアドレスで同じ関数を指定するタイミングも異なります。 0x00001410 [54US] 0x00001412 [75US] 0x00001414 [85US] 0x00001418 [54US] アライメントやアドレスがプログラムの実行時間に与える影響について説明していただけますか? 次に、マップ・ファイルとテスト関数を示します。 *(.func_mem_area) .func_mem_area 0x00001410 0x1c ./Sources/main.o 0x00001410 DelayTest void CODE_AREA DelayTest(uint32_tサイクル) { uint16_tインデックス= 0u、indey = 0u; for(indey = 0u; indey < cycles; indey++) { for(インデックス = 0u; インデックス < 255u; インデックス++) { /*遊ぶ。*/ } } } SysTickを遅延に使用すると、アドレス変更による影響が少なくなります。 お返事をお待ちしております。

How to compile have cargo build within a meta-layer I was following this example on inheriting cargo.bbclass and compiling a simple project: https://www.youtube.com/watch?v=aPsMuSU-Btw However, I got following error: ``` NOTE: Executing Tasks ERROR: my-test-0.1-r0 do_compile: ExecutionError('/opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/temp/run.do_compile.24257', 101, None, None) ERROR: Logfile of failure stored in: /opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/temp/log.do_compile.24257 Log data follows: | DEBUG: Executing shell function do_compile | NOTE: Using rust targets from /opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/rust-targets/ | NOTE: cargo = /opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/recipe-sysroot-native/usr/bin/cargo | NOTE: cargo build -v --frozen --target aarch64-poky-linux-gnu --release --manifest-path=/opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/git//Cargo.toml | error: the lock file /opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/git/Cargo.lock needs to be updated but --frozen was passed to prevent this | If you want to try to generate the lock file without accessing the network, remove the --frozen flag and use --offline instead. | WARNING: /opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/temp/run.do_compile.24257:185 exit 101 from '"cargo" build -v --frozen --target aarch64-poky-linux-gnu --release --manifest-path=/opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/git//Cargo.toml "$@"' | WARNING: Backtrace (BB generated script): | #1: oe_cargo_build, /opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/temp/run.do_compile.24257, line 185 | #2: cargo_do_compile, /opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/temp/run.do_compile.24257, line 157 | #3: do_compile, /opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/temp/run.do_compile.24257, line 152 | #4: main, /opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/temp/run.do_compile.24257, line 198 ERROR: Task (/opt/yocto/imx-6.6.3-1.0.0-build/sources/meta-my-test/recipes-cargo/install/my-test_0.1.bb:do_compile) failed with exit code '1' NOTE: Tasks Summary: Attempted 5745 tasks of which 5743 didn't need to be rerun and 1 failed. ``` I had run `bitbake -f my-test core-image-minimal`. BBLAYERS was appended as well. Simply: How to compile and install a Rust program into iMX93EVK ? Re: How to compile have cargo build within a meta-layer Good Re: How to compile have cargo build within a meta-layer I am a fool, more precisely a newbie. The repo I was referring to (https://gitlab.com/pbarker.dev/rust/print-rand) had no Cargo.lock file. I ran it manually on my machine copied file over and voila! The path the repo was downloaded was `/opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/git/` by default. Well I can override that somehow. This was a non-issue. Well hopefully helps other noobs out in the future. Edit: Some other pitfalls: * `IMAGE_INSTALL` did not work in my case, but `CORE_IMAGE_EXTRA_INSTALL` allowed me to add custom layer's bb files to `bitbake core-image-minimal` build. Recipe name is irrelevant for all I can tell. * On first run, I encountered missing crate hashes. Luckily the fix is printed on. Adding those with a `.inc` file beside the `.bb` file was sufficient to get over it without modifying .bb file `cargo bitbake` command generates. Re: How to compile have cargo build within a meta-layer cbugk-dannie cbugk-dannie Contributor I BTW, this line in the original post tells me cargo itself is functional: ``` error: the lock file /opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/git/Cargo.lock needs to be updated but --frozen was passed to prevent this ``` What I am missing is not knowing how to use the default Yocto behaviour of --frozen with an ordinary cargo project. But I suppose this is outside of the scope of NXP. Still, ou guys commented on having scripts and all on some other posts on this forum. So thought worth a shot, would appreciate any such tips if any. Re: How to compile have cargo build within a meta-layer Firstly, thanks. I get following error when added `DEPENDS += " meta-rust "` to bb file. I thought `meta-rust` was absorbed into `oe-core`, so do I really need it on nanbield? ``` Loading cache: 100% |########################################################################################################################| Time: 0:00:00Loaded 5451 entries from dependency cache. NOTE: Resolving any missing task queue dependencies ERROR: Nothing PROVIDES 'meta-rust' (but /opt/yocto/imx-6.6.3-1.0.0-build/sources/meta-my-test/recipes-my/company/my-test_0.1.bb DEPENDS on or otherwise requires it) ERROR: Required build target 'my-test' has no buildable providers. Missing or unbuildable dependency chain was: ['my-test', 'meta-rust'] Summary: There were 2 ERROR messages, returning a non-zero exit code. ``` Edit: I also added it as another echo of `BBLAYERS` in imx-setup-release.sh and to manifest of repo tool. However, nanbield is not compatible with this modus operandi: ```ERROR: Layer rust-layer is not compatible with the core layer which only supports these series: nanbield (layer is compatible with mickledore honister hardknott gatesgarth kirkstone)``` Re: How to compile have cargo build within a meta-layer Hello, Rust is not include in the default BSP, you have to add it to yocto. https://interrupt.memfault.com/blog/rust-in-yocto Regards

代码在紧耦合（ITC）内存中执行速度较慢 作为实验，我标记了一个相当昂贵的函数 __RAMFUNC(SRAM_ITC) 令我惊讶的是，它的运行速度慢了约 10%。有人可以分享一下为什么会发生这种情况吗？ 这是在 iMXRT1062 上，如果不是从 ITC 运行，则从闪存 (XIP) 运行。 i.MXRT 106x 回复：代码在紧耦合（ITC）内存中执行速度较慢 你好@expertsleepers ， iMXRT 系列所有 M7 内核的 FPU 设置应为 FPv5-D16。唯一的例外是 iMXRT1011，这里必须是 FPv5-SP-D16。 对于 M4 和 M33 核心，它也是 FPv5-SP-D16。 在 ITCM 中执行速度不如从闪存执行速度快的原因是，该函数可能太小，以至于完全可以放入缓存中。 然而，如果代码库规模增加，就会发生缓存破坏。这意味着函数执行的速度不再确定。 此致 回复：代码在紧耦合（ITC）内存中执行速度较慢 你好@expertsleepers ， 如果要调用的函数在地址范围内最多“远离”四兆字节，则可以使用直接跳转“BL”，而无需任何修饰。 此致 回复：代码在紧耦合（ITC）内存中执行速度较慢 确实如此。 完整的情况是： 该代码使用了大量双精度数学。 该项目设置为使用单精度浮点 ABI，因此充满了函数调用，而不是 .f64运营。 当代码放入 ITCM 时，每个函数调用都经过了一层修饰。 选择双精度 ABI 后，该功能现在的速度提高了一倍，并且在 ITCM 中不会减慢速度。它也没有变得更快，但我确信这其中有更多平凡的原因。 🙂 我发现奇怪的是，该项目是使用错误的 ABI 创建的 - 它是从 iMXRT1062 模板创建的。 对于 FP ABI 来说，这个线程很有用： https://community.nxp.com/t5/i-MX-RT/FPU-Type-options-for-MCUXpresso-for-double-precision-floating/mp/1231125/highlight/true#M12674 回复：代码在紧耦合（ITC）内存中执行速度较慢 啊，是的，可能是这样。 只是为了清楚起见，从 ITC 到其他 ITC 函数的函数调用是否仍然很快？ 回复：代码在紧耦合（ITC）内存中执行速度较慢 你好@expertsleepers ， 您从 ITCM 执行的代码是否调用位于闪存或 SDRAM/OCRAM 中的函数？由于编译器插入了饰面函数，因此这些现在更加昂贵。 当调用 Std-Lib 函数时，它们的位置也不太明显。 此致 回复：代码在紧耦合（ITC）内存中执行速度较慢 但如果该函数是从闪存执行的，那么情况不也是如此吗？ 该函数访问 OC SRAM 和外部 DRAM。我确信两者都会导致等待，但我不明白这怎么会使 ITC 比 XIP 慢。 回复：代码在紧耦合（ITC）内存中执行速度较慢 该函数可能有一些例程需要另一个内存中包含的数据，从而导致执行时出现一些等待状态。 此致， 奥马尔 回复：代码在紧耦合（ITC）内存中执行速度较慢 我明白。关注这个话题。 回复：代码在紧耦合（ITC）内存中执行速度较慢 不幸的是，有问题的代码是一个非常大的项目的一部分。我必须尝试将其隔离到一个新的项目中 - 当然它可能不会表现出相同的行为。如果我设法创建一个小测试用例，我会发布。 回复：代码在紧耦合（ITC）内存中执行速度较慢 有趣的。您能提供一个测试用例吗？我想重现这种行为。

The relationship between link address and program execution time With different link addresses, the execution time of the same program will change. What is the relationship between them? How to ensure optimal execution of programs? Re: The relationship between link address and program execution time OK, thanks. Re: The relationship between link address and program execution time Hi@NewbieStudy 1. Below is the delay function you set. I don’t know how you tested the execution time of this function. Is there any error? 2. This function is affected by the system clock. The clock has jitter, which will also cause the execution time to be different even for the same function. 3. This function may be affected by system interrupts, resulting in differences in execution time. 4. The function storage address is not aligned: The Cortex-M7 core can handle unaligned accesses by hardware (but I don't know how it works). Usually, variables should be naturally aligned because these accesses are slightly faster than unaligned accesses.  The above are some of my thoughts, I can’t think of more. Re: The relationship between link address and program execution time Hi, Senlent, Thank you for your suggestion! The characteristics of the map file are as follows. I specify the function in section(".func_mem_area"), modify the starting address of this area, and the execution time is different. The times for specifying the same function at addresses such as 0x00001410~0x0000141F are also different. 0x00001410    [54us] 0x00001412   [75us] 0x00001414   [85us] 0x00001418   [54us] Can you help explain the impact of alignment or address on program execution time?  The following is the map file and test function： *(.func_mem_area) .func_mem_area 0x00001410 0x1c ./Sources/main.o 0x00001410 DelayTest void CODE_AREA DelayTest(uint32_t cycles) { uint16_t index = 0u, indey = 0u; for(indey = 0u; indey < cycles; indey++) { for(index = 0u; index < 255u; index++) { /* do nothing. */ } } } If I use SysTick for delay, it is less affected by address changes. Looking forward to your reply. Re: The relationship between link address and program execution time Hi@NewbieStudy Changes in the link address will cause some changes in the location where the code is stored in flash, which may lead to some differences in execution speed.I can't go into your question in depth. The following are some optimization suggestions for improving performance of S32K3. I hope this will be helpful to you. https://community.nxp.com/t5/S32K-Knowledge-Base/S32K3xx-How-to-optimization-APP-code-for-get-more-high/ta-p/1763126 As following have some suggestions:  1. Most of user code allocate to P-Flash and enable I-Cache 2. Allocate system stack to D-TCM and enable D-Cache 3. Execute code frequently allocate to I-TCM. E.g., ISRs etc. 4. OS' task stack allocate to D-TCM 5. vector table allocate to D-TCM Please note: 1. Due to enable D-Cache, other masters(E.g., DMA, HSE, another APP cores) access theses area of cacheable will be impact. So, theses area need to allocate to non-cacheable area. 2. If another master(E.g., DMA, HSE and another APP cores) access the D-TCM need to over back door. E.g., core1/DMA/HSE access core0' DTCM needed to over backdoor. 

UART Communication clock Hello NXP Community, I hope this message finds you well. I am currently working with the RD-HVBMSCTBUN board and I'm facing some difficulties with UART communication. As we are working on new projects from scratch, we have been referring to examples for guidance, but we haven't had much success so far. After posting several questions and searching for information online, we were finally able to send data using UART and see the output on Putty. However, we now want to incorporate an operating system (FreeRTOS) into our project. Here's where we encountered a problem. The UART example provided uses a clock frequency of 48MHz and FIRC, but most FreeRTOS usecases and other resources suggest using a clock frequency of 160MHz and the PLL. So ,when we changed the clock to 160MHz, we started receiving bizarre characters instead of the expected data. I'm not sure why the UART + FreeRTOS is not working or how to correctly change the UART clock to support 160MHz. I have attempted it myself, but unfortunately, it didn't work (of course we use slow-clock as we are using LPUART1). If anyone in the community has any insights into what might be going wrong or possible solutions to this issue, I would greatly appreciate your help. Your expertise and guidance would be invaluable to us in resolving this problem and continuing our project smoothly. Thank you all in advance for your time and assistance. Re: UART Communication clock My solutions is : Switch to the PLL clock, enable it in peripherals, and ensure that the PLL is locked. FreeRTOS relies on the PLL clock for proper operation.   Re: UART Communication clock Hi, does a demo example run properly if not using FreeRTOS, just after updating clock option? Try to measure TXD data to see what bitrate is really set. Maybe you can try to measure AIPS_SLOW_CLK on CLKOUT0_RUN pin. BR, Petr

メタレイヤー内で cargo をビルドする方法 私はこの例に従って、cargo.bbclassを継承し、簡単なプロジェクトをコンパイルしていました。 https://www.youtube.com/watch?v=aPsMuSU-Btw しかし、私は次のエラーを得ました: ``` メモ: タスクの実行 エラー: my-test-0.1-r0do_compile: ExecutionError('/opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/temp/run.do_compile.24257',101、なし、なし) エラー:障害のログファイルが/ opt / yocto / imx-6.6.3-1.0.0-build / build_fsl-imx-wayland / tmp / work / armv8a-poky-linux / my-test / 0.1 / temporary / log.do_compile.24257に保存されています。 ログデータは次のとおりです。 |DEBUG: シェル関数 do_compile を実行しています |注:/opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/rust-targets/の錆ターゲットを使用 |注:cargo = /opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/recipe-sysroot-native/usr/bin/cargo |注:cargo build -v --frozen --target aarch64-poky-linux-gnu --release --manifest-path=/opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/git//Cargo.toml |エラー:ロックファイル/ opt / yoc / imx-6.6.3-1.0.0-build / build_fsl-imx-wayland / tmp / work / armv8a-poky-linux / my-test / 0.1 / git / Cargo.lockを更新する必要がありますが、これを防ぐために--frozenが渡されました |ネットワークにアクセスせずにロックファイルを生成したい場合は、--frozenフラグを削除して、代わりに--offlineを使用してください。 |警告: /opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/temp/run.do_compile.24257:185「"cargo"ビルド-v」から101を終了 --frozen --target aarch64-poky-linux-gnu --release --manifest-path=/opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/git//Cargo.toml "$@"' |警告:バックトレース(BB生成スクリプト): |#1:oe_cargo_build、/ opt / yocto / imx-6.6.3-1.0.0-build / build_fsl-imx-wayland / tmp / work / armv8a-poky-linux / my-test / 0.1 / temp / run.do_compile.24257、185番線 |#2:cargo_do_compile、/ opt / yocto / imx-6.6.3-1.0.0-build / build_fsl-imx-wayland / tmp / work / armv8a-poky-linux / my-test / 0.1 / temp / run.do_compile.24257、157番線 |#3:do_compile、/ opt / yocto / imx-6.6.3-1.0.0-build / build_fsl-imx-wayland / tmp / work / armv8a-poky-linux / my-test / 0.1 / temp / run.do_compile.24257、152番線 |#4:メイン、/ opt / yocto / imx-6.6.3-1.0.0-build / build_fsl-imx-wayland / tmp / work / armv8a-poky-linux / my-test / 0.1 / temperature / run.do_compile.24257、198番線 エラー:タスク（/opt/yocto/imx-6.6.3-1.0.0-build/sources/meta-my-test/recipes-cargo/install/my-test_0.1.bb:do_compile)終了コード '1' で失敗しました 注: タスクの概要: 5745 個のタスクを試行し、そのうち 5743 個を再実行する必要がなく、1 個が失敗しました。 ``` 私は 'bitbake -f my-test core-image-minimal' を実行しました。BBLAYERSも追加されました。 簡単に言うと、RustプログラムをiMX93EVKにコンパイルしてインストールする方法は? Re:メタレイヤー内でcargoをビルドする方法をコンパイルする方法 よし Re:メタレイヤー内でcargoをビルドする方法をコンパイルする方法 私は愚か者で、より正確には初心者です。私が参照していたリポジトリ（https://gitlab.com/pbarker.dev/rust/print-randCargo.lockファイルがありませんでした。私はそれを私のマシンで手動で実行しました、ファイルをコピーしました、そして出来上がり! リポジトリがダウンロードされたパスは、デフォルトでは「/opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/git/」でした。まあ、どうにかしてそれを上書きすることができます。これは問題ではありませんでした。まあ、うまくいけば、将来他の初心者を助けることができます。 編集:いくつかの他の落とし穴: * 私の場合、「IMAGE_INSTALL」は機能しませんでしたが、「CORE_IMAGE_EXTRA_INSTALL」を使用すると、カスタムレイヤーのbbファイルを「bitbake core-image-minimal」ビルドに追加できました。レシピの名前は私が知る限り関係ありません。 * 最初の実行で、クレートのハッシュが欠落していることがわかりました。幸いなことに、修正は印刷されています。'.bb' ファイルの横に '.inc' ファイルがあるものを追加すると、.bb を変更せずにそれを乗り越えるのに十分でしたfile 'cargo bitbake' コマンドが生成されます。 Re:メタレイヤー内でcargoをビルドする方法をコンパイルする方法 CBUK-ダニー CBUK-ダニー 寄稿者 I ところで、元の投稿のこの行は、貨物自体が機能していることを示しています。 ``` エラー:ロックファイル/ opt / yoc / imx-6.6.3-1.0.0-build / build_fsl-imx-wayland / tmp / work / armv8a-poky-linux / my-test / 0.1 / git / Cargo.lockを更新する必要がありますが、これを防ぐために--frozenが渡されました ``` 私が欠けているのは、通常の貨物プロジェクトでデフォルトのYocto動作--frozenを使用する方法がわからないことです。 しかし、これはNXPの範囲外だと思います。それでも、ouの人たちは、スクリプトを持っていることや、このフォーラムの他のいくつかの投稿にすべてコメントしました。だから、試してみる価値があると思ったので、もしあればそのようなヒントをいただければ幸いです。 Re:メタレイヤー内でcargoをビルドする方法をコンパイルする方法 まず、ありがとう。 bbファイルに'DEPENDS += " meta-rust "'を追加すると、次のエラーが発生します。「メタ錆」が「oe-core」に吸収されると思っていたので、本当にnanbieldに必要ですか? ``` キャッシュの読み込み: 100% |########################################################################################################################|Time: 0:00:00依存関係キャッシュから 5451 エントリをロードしました。注:欠落しているタスクキューの依存関係の解決エラー:何も「meta-rust」を提供しません(ただし、 /opt/yocto/imx-6.6.3-1.0.0-build/sources/meta-my-test/recipes-my/company/my-test_0.1.bbそれに依存するか、それ以外の場合はそれを必要とします) エラー: 必要なビルド ターゲット 'my-test' にはビルド可能なプロバイダーがありません。 欠落している、または構築できない依存関係チェーンは: ['my-test', 'meta-rust'] 概要: 2 つの ERROR メッセージがあり、ゼロ以外の終了コードが返されました。 ``` 編集:私はまた、imx-setup-release.sh の「BBLAYERS」の別のエコーとして、およびリポジトリツールのマニフェストに追加しました。ただし、nanbieldはこの手口と互換性がありません。 '''エラー:レイヤーrust-layerは、これらのシリーズのみをサポートするコアレイヤーと互換性がありません:nanbield(レイヤーはmickledore honister hardknott gatesgarth kirkstoneと互換性があります)'''

RTE Real Time Driver Hi There, I need some informations about Real Time Enviroment (RTE) SchM_ .c, present in S32k RTDs. In particular,  I noticed that, instead of a  simple "enable interrupt/disable interrupt" -critical section approach, a more complex one is used: in particular:  SchM_Enter_ _ _EXCLUSIVE_AREA_ () and SchM_Exit_ _ _EXCLUSIVE_AREA_ ()  methods are implemented (where is the driver name and is an incrementing number 1) could you explain me the ratio under this implementation ? How have I use these functions in my code  ? Why the suddivision for and for 2) If I use this in application, which / ones shall I use? shall I check the implemented ones, in the RTD, before choosing one?, Best Regards. Fabio Re: RTE Real Time Driver Hello, NXP provides stubs for AUTOSAR SchM integration. If you are targeting AUTOSAROS, these will need to be replaced by the BSW integrator. These numbers do not have a meaning other than indicating which register/variable accesses are being protected - See the Integration Manual for the respective module: In the most simple case, this can simply disable/enable interrupts. See the Baremetal implementation. In the FreeRTOS case, these map to taskENTER_CRITICAL() and taskEXIT_CRITICAL() but this will be updated in the future as this is not sufficient for critical sections in interrupt context. Best, Bryan

如何在元层中编译 Cargo Build 我按照这个例子继承了 cargo.bbclass 并编译了一个简单的项目： https://www.youtube.com/watch?v=aPsMuSU-Btw 但是，我收到以下错误： ``` 注意：执行任务 错误：my-test-0.1-r0do_compile:执行错误（'/opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/temp/run.do_compile.24257'，101，无，无） 错误：故障日志文件存储在：/opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/temp/log.do_compile.24257 日志数据如下： | DEBUG：执行 shell 函数 do_compile | 注意：使用来自 /opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/rust-targets/ 的 rust 目标 | 注意：cargo = /opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/recipe-sysroot-native/usr/bin/cargo | 注意：cargo build -v --frozen --target aarch64-poky-linux-gnu --release --manifest-path=/opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/git//Cargo.toml | 错误：锁定文件 /opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/git/Cargo.lock 需要更新，但已传递 --frozen 以防止发生这种情况 | 如果您想尝试在不访问网络的情况下生成锁定文件，请删除 --frozen 标志并改用 --offline。 |警告：/opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/temp/run.do_compile.24257:185从'“cargo”build -v --frozen --target aarch64-poky-linux-gnu --release --manifest-path=/opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/git//Cargo.toml“$@”'退出101 | 警告：回溯（BB 生成的脚本）： | #1: oe_cargo_build, /opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/temp/run.do_compile.24257,第 185 行 | #2:cargo_do_compile,/opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/temp/run.do_compile.24257，第 157 行 | #3: do_compile,/opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/temp/run.do_compile.24257，第 152 行 | #4:主要的，/opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/temp/run.do_compile.24257，第 198 行 错误：任务（/opt/yocto/imx-6.6.3-1.0.0-build/sources/meta-my-test/recipes-cargo/install/my-test_0.1.bb:do_compile）失败，退出代码为“1” 注意：任务摘要：尝试了 5745 项任务，其中 5743 项无需重新运行，1 项失败。 ``` 我已经运行了“bitbake -f my-test core-image-minimal”。BBLAYERS 也被附加。 简单来说：如何编译并安装 Rust 程序到 iMX93EVK 中？ 回复：如何在元层中编译 Cargo Build 好的 回复：如何在元层中编译 Cargo Build 我是一个傻瓜，更确切地说是一个新手。我所指的 repo（ https://gitlab.com/pbarker.dev/rust/print-rand ）没有 Cargo.lock 文件。我在我的机器上手动运行了复制的文件，瞧！ 下载 repo 的路径默认为“/opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/git/”。好吧，我可以以某种方式覆盖它。这不是一个问题。希望将来能帮助其他新手。 编辑：其他一些陷阱： * 在我的情况下，“IMAGE_INSTALL”不起作用，但“CORE_IMAGE_EXTRA_INSTALL”允许我将自定义层的 bb 文件添加到“bitbake core-image-minimal”构建中。据我所知，食谱名称无关紧要。 * 第一次运行时，我遇到了丢失的板条箱哈希值。幸运的是，修复方法已经打印出来了。在 `.bb` 文件旁边添加 `.inc` 文件就足以解决这个问题，而无需修改 .bb文件 `cargo bitbake` 命令生成。 回复：如何在元层中编译 Cargo Build cbugk-dannie cbugk-dannie 贡献者 I 顺便说一句，原帖中的这一行告诉我货物本身是可以运行的： ``` 错误：锁定文件 /opt/yocto/imx-6.6.3-1.0.0-build/build_fsl-imx-wayland/tmp/work/armv8a-poky-linux/my-test/0.1/git/Cargo.lock 需要更新，但已传递 --frozen 以防止发生这种情况 ``` 我所不知道的是不知道如何在普通的货物项目中使用默认的 Yocto 行为 --frozen。 但我认为这超出了 NXP 的范围。不过，你们还是在这个论坛的其他一些帖子上对脚本和所有内容发表了评论。所以认为值得一试，如果有任何这样的建议我将不胜感激。 回复：如何在元层中编译 Cargo Build 首先，谢谢。 当将 `DEPENDS += " meta-rust "` 添加到 bb 文件时，出现以下错误。我以为 `meta-rust` 已经被吸收到 `oe-core` 中了，那么在 nanbield 上我真的需要它吗？ ``` 加载缓存：100% |##############################################################################################################################| 时间：0:00:00从依赖缓存加载了 5451 个条目。注意：解决任何缺失的任务队列依赖关系错误：没有提供“meta-rust”（但/opt/yocto/imx-6.6.3-1.0.0-build/sources/meta-my-test/recipes-my/company/my-test_0.1.bb取决于或需要它）错误：所需的构建目标“my-test”没有可构建的提供程序。 缺失或无法构建的依赖链为：['my-test', 'meta-rust'] 摘要：有 2 条错误消息，返回非零退出代码。 ``` 编辑：我还将其作为 imx-setup-release.sh 中“BBLAYERS”的另一个回显添加到 repo 工具的清单中。然而，nanbield 与这种运作方式不兼容： ```错误：rust-layer 层与仅支持以下系列的核心层不兼容：nanbield（该层与 mickledore honister hardknott gatesgarth kirkstone 兼容）```

初心者にはどのIDEを使用しますか? iMXRT1010またはiMXRT1064ボードの新しいプロジェクトを開始する場合、初心者に最適なIDEはどれですか? これはMCUXpressですか、それともVSCodeですか(VSCode拡張用のMCUXpressを使用)。 それとも同じですか?私はしばらくの間これを見つけようとしましたが、まだ確信が持てません。 MCUXpress for VSCodeはZephyrがベースだって本当ですか? Zephyrは初心者でも簡単に習得できますか? MCUXpressでは、Zephyrと比較して周辺機器がより適切にサポートされていますか? 新しい環境を学ぶことは気になりません。しかし、何時間も学んだ後で、別のものを学ぶ必要があることを知りたくありません。 Re:初心者にはどのIDEを使用しますか? ディエゴさん、長い回答をありがとうございました!ようやく違いがわかりました。 VSCodeルートは新しい働き方であるように私には思えます。MCUXpresso SDKは今後10年ほど存続しますか?では、MCUXpresso SDKを使用して新しいプロジェクトを開始するのはまだ賢明ですか?

S32K344中FlexCAN1传输的问题 我启用了默认的FlexCAN_Ip_Example_S32K344中的引脚配置工具，以在正常模式下观察PTA7引脚上的CAN0 Tx输出。我能够在示波器上看到数字 CAN 信号。 但是当我将输出端口从 PTA7 更改为 PTB1 时，我在示波器上看不到任何信号。 我也尝试将 CAN0 改为 CAN1，但仍然只能看到来自 PTA7 端口的信号。 有什么原因导致我无法从 PTA7 以外的任何端口观察到 CAN 信号，因为在原理图中 PTA7 和 PTB1 都可以有 CAN0_Tx 信号。 我正在使用 S32K3X4EVB-T172 板并附加了该项目。 回复：S32K344中FlexCAN1传输的问题 我有 PCAN-USB CAN 解码器，当 CAN0 Tx 引脚为 PTA7 时可以正常接收消息，但当我将其更改为 PTB1 时，我没有收到任何消息。CAN0 中只能使用 1 个引脚进行传输吗？

IMXRT1021 flexCAN not receiving after physical CAN bus issue Hi, I am using an IMXRT1021 with flexCAN on a 1mbit CAN bus (existing product that has had CAN added in a recent edition). This mostly works well, and CAN is sending and receiving without issue. However if there is a physical event on the CAN bus (such as a large noise spike, or the CAN bus lines being shorted) the CAN module seems to get stuck, not being able to send or receive. If this happens it is mostly in CAN_STATE_ERROR_PASSIVE, but sometimes can be CAN_STATE_ERROR_BUS_OFF. When this happens, the scoping the CAN bus shows it is idle, and the registers are as follows: the CAN status to our CAN callback is 0x14be (kStatus_FLEXCAN_ErrorStatus) FLEXCAN_GetStatusFlags() gives 0x40118 (ERROR_PASSIVE | RX_WRN | SYNCH) CAN_PERIPHERAL->IFLAG1 = 0 CAN_PERIPHERAL->ESR2 0x6000 (same as before it goes into this state) CAN_PERIPHERAL->DBG1 = 0x2000032 (counting through 0x1000032, 0x2000032, 0x4000032 etc) CAN_PERIPHERAL->DBG2 = 0x3e (same as before the issue) a DeInit and ReInit of the CAN peripheral doesn't fix this, and most concerningly nor does a soft reset of the processor. Only a power cycle recovers things. After a soft reset, the state is : the CAN status to our CAN callback is 0x0 FLEXCAN_GetStatusFlags() gives 0x0 CAN_PERIPHERAL->IFLAG1 = 0 CAN_PERIPHERAL->ESR2 0x6000  CAN_PERIPHERAL->DBG1 = 1000001 CAN_PERIPHERAL->DBG2 cycles through 0, 0xb700, 0xa000, 0x9000 This is using a MAX33015EATB CAN transceiver, and the bus is terminated with split-y termination 120 ohms at both physical ends of the bus. Please ask if any more details are needed. I would very much appreciate some help with this. Thank you i.MXRT 102x Re: IMXRT1021 flexCAN not receiving after physical CAN bus issue Hi @PeteA , Thanks for the information! You may put the CAN PHY reset code in the ISR to handle the event of CAN_STATE_ERROR_PASSIVE or CAN_STATE_ERROR_BUS_OFF, and you may change the pin mux of  CAN tx line to set up a toggling on it. Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: IMXRT1021 flexCAN not receiving after physical CAN bus issue It doesn't unfortunately. However I have established that the CAN transceiver (MAX33015EATB ) has fault management, and can go into an error state if it detects an error condition.  This is very likely to be the cause (unfortunately the fault pin is not broken out so it is difficult to scope to check, but in my attempts at testing it appeared to be asserted). This can be reset by toggling the CAN tx line, but I've just got to work out how to do this Thank you for the help Re: IMXRT1021 flexCAN not receiving after physical CAN bus issue Hi @PeteA , Will the device go back to error active state after some time? Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

How does host device (IDE: MCUXPresso, KEIL MDK, IAR) pass information to Jlink? Hi, I have recently been involved in making flash loader for iMXRT1176 which uses hyperflash (MIMXRT1176-GEORGE_S26HL512T) over FLEXSPI peripheral. Unfortunately, the default FlexSPI NOR ROM API seems not to support this version of hyperflash (similar version is present on RT1050-EVKB but it is an older one, CYPRESS S26KS512SDPBHI020) along with my configuration. Despite the fact that pinout used for my hyperflash is identical to the one suggested in the ROM API, but that is issue I handled by implementing my own low level driver for hyperflash and I just don't use the ROM API for FLEXSPI as it does not work. Now to the point. I'm trying to figure out this whole jlink related mechanism that takes a bunch of bytes that in a whole is a final application that was previously compiled for the microcontroller which in turn is to be executed from non-volatile memory after power up of the board. 1.) I already know that Jlink is able to download application image to any non-volatile memory (from which code can be executed) only if there is a proper xml device configuration like one below: and on top of that there must exist proper flash_loader.elf that is to be passed into Loader field in the xml device configuration above. This flash_loader.elf must have a proper memory sections defined there code, data and deviceDescription will be placed, like described here: SEGGER Flash Loader - SEGGER Wiki   2.) When one executes image load command via jlink, it loads flash_loader.elf to RAM of the uC and from there it can execute the functions as defined in the OPEN CMSIS FLASH LOADER standard Algorithm Functions (open-cmsis-pack.github.io) Now what I lack in understanding is the following. How does the Jlink or IDE using Jlink pass the chunks of data to the Flash Program function from the CMSIS loader standard above, without any intermediate interface? flash_loader.elf does not have any main file, so there is no like starting space for code, it must be enforsed somehow to pass the data into the specific functions from API that require it. I know that MCUXpresso uses something called Mailbox and messages that pass on commands and data, which are defined in a project called LPCXFlashDriverLib where  void ServiceMessages(Mailbox_t *msg) is defined and according to the description:  "ServiceMessages.c is flash driver file is intended to function in conjunction with host debug " Questions: 1.)But how does it work for other IDEs like IAR or KEIL MDK? 2.) How does it work for pure Jlink (used without any IDE) as executed via command line? 3.) Is there some dedicated RAM buffer memory dedicated to storing the data so that no intermediate interface is needed, and the application loaded into RAM can just take the data from that specific RAM memory location placed by Jlink firmware? Sorry for the long post 🙂 Re: How does host device (IDE: MCUXPresso, KEIL MDK, IAR) pass information to Jlink? I've just found out on the keil website the following link Programming External Flash with STM32 Devices (keil.com) It contains the whole procedure of creating the flash loader for STM32, but it does not really matter for the topic in question. The essential part that basically explains the procedure was shown on the image below: For more details, see the link above. Best regards, Michal Re: How does host device (IDE: MCUXPresso, KEIL MDK, IAR) pass information to Jlink? Hi @mimlo , I am sorry but as keil and iar are 3rd party tools we don't have such details as you asked, please kindly check with keil and iar for further support.  https://www.iar.com/knowledge/support/request-technical-support https://www.keil.com/support/ Thanks for your patience and understanding! Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

Problem in FlexCAN1 transmit in S32K344 I enabled the pins configuration tool in the default FlexCAN_Ip_Example_S32K344 to observe the CAN0 Tx output on the PTA7 pin in the normal mode. I was able to see the digital CAN signals on the oscilloscope. But when I changed the output port from PTA7 to PTB1, I couldn't see any signals on the oscilloscope. I also tried changing CAN0 to CAN1, but still I can only see signals from the PTA7 port. Is there any reason why can't I observe CAN signals from any ports other than PTA7 becuase in schematics both PTA7 and PTB1 can have CAN0_Tx signal. I am using S32K3X4EVB-T172 board have attached the project. Re: Problem in FlexCAN1 transmit in S32K344 Hi @sagar991, Sorry for the misunderstanding, only pins PTA6 & PTA7 are connected to the PHY on board: If you need to use another pin for transmission, they need to be rerouted. Best regards, Julián Re: Problem in FlexCAN1 transmit in S32K344 I have PCAN-USB CAN decoder which receives messages normally when CAN0 Tx pin is PTA7, but when I change it to PTB1, I don't receive any messages. Can only 1 pin be used in CAN0 for transmitting ? Re: Problem in FlexCAN1 transmit in S32K344 Hi @sagar991, Are you testing this with two S32K344 boards?  In order to see the signals for the transmissions, you will need another CAN node in the bus (either another MCU or CAN analyzer). Best regards, Julián.

Which IDE to use for newbie? When starting a new project for a iMXRT1010 or iMXRT1064 board which IDE is best for a newbie? Is this MCUXpress or VSCode (with MCUXpress for VSCode extension). Or are they the same? I tried to find this out for a while now, but still am not sure. Is it true that MCUXpress for VSCode is based on Zephyr? Is Zephyr easier to learn for a newbie? Are peripherals better supported in MCUXpress compared to Zephyr? I do not mind learning a new environment. But I do not want to find out after hours of learning that I need to learn a different one. Re: Which IDE to use for newbie? Thanks a lot Diego for the extended answer! I now finally understand the difference. It seems to me that the VSCode route is the new way of working. Will MCUXpresso SDK stay around for the next 10 years or so? So is it still wise to start new projects with MCUXpresso SDK? Re: Which IDE to use for newbie? Hi @simmania  I hope that you are doing well! VS code is a vanilla IDE featuring our MCUXpresso VS code extension released the past year  while the MCUXpresso IDE is  an eclipse Based IDE with a first release on 2017. Both are still supported and in constant develop. Following this idea, there is more documentation and articles where the MCUXpresso IDE is involved than the VS code extension, as it was released first. For example, you will find application notes from us that implement the IDE to build projects. Also, more people is experienced on this IDE, which is the opposite to the VS code, which is relatively new. Take for example the Erich Styger blog. He created already a ton of articles for the MCUXpresso IDE, and I am sure he will also integrate VS code. Btw, I highly recommend his blog https://mcuoneclipse.com/ I learned a lot from him. Maybe Erich already has an article or will create one on this topic, as he is a university professor keeping up to date every semester.  Is it true that MCUXpresso for VSCode is based on Zephyr? The VS code extension is not based on Zephyr. It provides support for compiling and debugging Zephyr repositories, as  well our MCUXpresso SDK repository containing our BareMetal and other RTOS examples and drivers.  Is Zephyr easier to learn for a newbie? Compared to other RTOs? Like FreeRTOS? Good question, I would say that it is easier to get started with FreeRTOS as  a bare minimum requirement you need to learn RTOS Kernel services and specific APIs. Zephyr is quite more complex, and it is not only an RTOS  it integrates more stuff, and it is not only necessary to know about kernel services. Something really interesting from Zephyr is that integrates the concept of Device tree, inherited from Linux. The Device tree takes to a new level the system integration and the SOC, as it describes in a huge human readable file the entire system: memory map, external devices, external memories and more.  With the VS code you need to install github repositories to get an example running. Below an example or set the location of your already existing repo. Below a picture of how you can install the RT1064 SDK. With the MCUXpresso IDE you can also install the SDK repos, but, this is not a popular option. The popular way is to drag and drop install SDKs from https://mcuxpresso.nxp.com/en or installing them directly from the IDE.  Are peripherals better supported in MCUXpresso compared to Zephyr? A simple answer is yes. but let me provide details. First to check Zephyr support for your board ( Zephyr targets boards and then specific SOCs). For example lets browse the RT1010 page https://docs.zephyrproject.org/latest/boards/nxp/mimxrt1010_evk/doc/index.html As you can see, at this time, not all the peripherals are supported for the RT1010. When we say that a peripheral is supported is because the Zephyr RTOS HAL layers let you to use those peripherals with ease without having to worry about their low-level implementation, as you would do directly using our SDK drivers.  The SDK provides support for all the RT1010 peripherals, and the MCUXpresso IDE integrates build in our MCUXpresso Config Tools. The config tools can be used to create initialization code for peripherals, clocks, and pins. You may use the config tools to generate code when using Zephyr, but what is the point to init LPUART if the Zephyr RTOS already lets you do this?  Another factor to consider is the debug tools included into the MCUXpresso IDE. The IDE lets you to do more than simply write code and debug it. It in integrates features for trace, RTOS debug, .map viewer and many more, please refer to the MCUXpresso User Guide.  There are more details like the linker management, which is a more advanced topic, but in some moment, you will find out that you will need to put code or variables on a certain place. With the IDE linker management is easier. In summary, the MCUXpresso IDE have many years already in the market so you will find more documentation, articles, source code, and posts in this community compared to the VS code. If you consider that the quantity of resources helps you pick the IDE. In my own perspective I am already familiar with the IDE, but the current trend is to get familiar with Zephyr and use more integration with git repositories. Best regards,  Diego

IMXRT1170 の両方のコアでのクロックとピンの初期化 親愛なるフォーラム、 すべてのマルチコアの例(IMXRT1170 SDK)でclock_config.c同じクロックの多くを 2 回初期化します (CM7 で初期化し、CM4 コアで 2 回目)。pin_mux.cについても同じことが言える場合がありますドキュメントによると、CM7コアが最初に実行されますが、なぜCM4は同じジョブを再度実行する必要がありますか? multicore/evkmimxrt1170_hello_world_cm4 clock_config.c の例: /* Configure ADC1 using OSC_RC_48M_DIV2 */ rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg); 次に、multicore/evkmimxrt1170_hello_world_cm7 clock_config.cから: /* Configure ADC1 using OSC_RC_48M_DIV2 */ rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg); いくつかのケースでプリプロセッサのifdefが見られました。 しかし、さらに奇妙なことに、いくつかの例では、CM4はCM7の時計にも触れます。multicore/evkmimxrt1170_hello_world_cm4 clock_config.c から: /* Module clock root configurations. */ /* Configure M7 using ARM_PLL_CLK */ rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); 1. CM4から同じクロック初期化を削除しても安全ですか、それとも何か他のことが起こっていますか? 2. なぜすべての例が同じクロックを2回初期化するためにこの規則を保持しているのですか? 3. CM4(後で実行される)がCM7クロックを変更すると、未定義の動作が発生する可能性がありますか? 4.自動生成されたclock_config.cを使用する場合の最善のアプローチは何ですかおよびpin_mux.cマルチコアシステム用のMCUXpresso Config Toolsから? よろしくお願いします。 Re: IMXRT1170 の両方のコアでのクロックとピンの初期化 OK Re: IMXRT1170 の両方のコアでのクロックとピンの初期化 これについて何かコメントはありますか? @kerryzhou @_Leo_ @howard_liu @Hui_Ma @KelvinQi 

Jetson (arm64/aarch64) 用 ZLG USBCAN-II ドライバーのヘルプ こんにちは、皆さん Jetson プラットフォームで作業しており、CAN 通信に ZLG USBCAN-II デバイスを使用しています。ZLGドライバのダウンロードページ(https://manual.zlg.cn/web/#/146)に行ってきましたが、しかし、ドライバーはAMD64アーキテクチャでのみ使用でき、arm64またはaarch64のバージョンはないようです。 ここにいる誰かが同様の問題に直面しているか、Jetson(arm64 / aarch64)にドライバーをインストールする方法について提案がありますか?どんな助けやポインタでも大歓迎です! よろしくお願いいたします！ 日時:Jetson(arm64 / aarch64)用のZLG USBCAN-IIドライバーのヘルプ https://community.nxp.com/t5/FreeMASTER/Help-with-ZLG-USBCAN-II-Driver-for-Jetson-arm64-aarch64/m-p/1991351 の複製として終了する

新手该使用哪个 IDE？ 当为 iMXRT1010 或 iMXRT1064 板启动新项目时，哪个 IDE 最适合新手？ 这是 MCUXpress 还是 VSCode（带有 MCUXpress 用于 VSCode 扩展）。 或者它们是一样的？我尝试了一段时间来找出答案，但仍然不确定。 MCUXpress for VSCode 是否基于 Zephyr？ 对于新手来说 Zephyr 是否更容易学习？ 与 Zephyr 相比，MCUXpress 是否对外设提供更好的支持？ 我不介意学习新的环境。但我不想在学习了几个小时之后才发现我需要学习不同的课程。 回复：新手应该使用哪个 IDE？ 非常感谢 Diego 的详细回答！我现在终于明白了其中的区别。 在我看来，VSCode 路线是一种新的工作方式。MCUXpresso SDK 会在未来 10 年左右继续存在吗？那么使用 MCUXpresso SDK 启动新项目仍然明智吗？

IMXRT1170 中两个核心的时钟和引脚初始化 亲爱的论坛， 我们注意到，在所有多核示例（IMXRT1170 SDK）中，clock_config.c对许多相同的时钟进行两次初始化：第一次在 CM7 上，第二次在 CM4 核心上。有时也可以这样说 pin_mux.c根据文档，CM7 核心首先运行，为什么 CM4 要再次执行同样的工作？ 来自 multicore/evkmimxrt1170_hello_world_cm4 clock_config.c 的示例： /* Configure ADC1 using OSC_RC_48M_DIV2 */ rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg); 然后从 multicore/evkmimxrt1170_hello_world_cm7 clock_config.c 中： /* Configure ADC1 using OSC_RC_48M_DIV2 */ rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg); 在某些情况下，我们看到了预处理器 ifdef： 但更奇怪的是，在一些例子中，CM4 甚至触及 CM7 时钟。来自 multicore/evkmimxrt1170_hello_world_cm4 clock_config.c： /* Module clock root configurations. */ /* Configure M7 using ARM_PLL_CLK */ rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); 1. 从 CM4 中删除相同的时钟初始化是否安全，或者是否存在其他问题？ 2. 为什么所有示例都遵循这个惯例，即对相同的时钟进行两次初始化？ 3. 当 CM4（稍后运行）更改 CM7 时钟时，是否可能出现未定义的行为？ 4. 使用自动生成的clock_config.c时的最佳方法是什么和 pin_mux.c来自多核系统的 MCUXpresso 配置工具？ 此致， 回复：IMXRT1170 中两个核心的时钟和引脚初始化 确认 回复：IMXRT1170 中两个核心的时钟和引脚初始化 对此有何评论？ @kerryzhou @_Leo_ @howard_liu @Hui_Ma @KelvinQi

Clocks and pin initialisation on both cores in IMXRT1170 Dear Forum, We've noticed that in all multi-core examples (IMXRT1170 SDK) clock_config.c initialises many of the same clocks twice: on CM7 and second time on CM4 core. Sometimes the same can be said about pin_mux.c According to the docs, CM7 core runs first, why should CM4 do the same job again? Example from multicore/evkmimxrt1170_hello_world_cm4 clock_config.c: /* Configure ADC1 using OSC_RC_48M_DIV2 */ rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg);  Then from multicore/evkmimxrt1170_hello_world_cm7 clock_config.c: /* Configure ADC1 using OSC_RC_48M_DIV2 */ rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg); We saw preprocessor ifdefs for some cases: But even weirder, on some examples CM4 touches even CM7 clocks. From multicore/evkmimxrt1170_hello_world_cm4 clock_config.c: /* Module clock root configurations. */ /* Configure M7 using ARM_PLL_CLK */ rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); 1. Is it safe to remove same clock initialisation from CM4 or is there something else going on? 2. Why all examples keeps this convention to initialise same clocks twice? 3. Is it possible to get undefined behaviour when CM4 (which runs later) changes CM7 clocks? 4. What is the best approach when using auto-generated clock_config.c and pin_mux.c from MCUXpresso Config Tools for multicore systems? Regards, Re: Clocks and pin initialisation on both cores in IMXRT1170 Ok Re: Clocks and pin initialisation on both cores in IMXRT1170 Hi @Juozas , Any clocks don't need initializing twice. The clock configuring code is there but the second core never calls it. You can check the main() function of second core. Regards, Howard Re: Clocks and pin initialisation on both cores in IMXRT1170 Any comments on this? @kerryzhou @_Leo_ @howard_liu @Hui_Ma @KelvinQi