外部频率和占空比输入测量 大家好， 我想在我的定制板 i.mx.rt1176 上测量外部频率输入和占空比。我没有找到应用说明或示例代码。有没有什么资源可以帮助我开始编写代码？ 顺祝商祺！ 巴士里·卡亚

如何协作完成一个项目？版本控制/git 我和另外两名开发人员组成的团队正在快速掌握 MCUXpresso 的 vsCode 扩展。 我们已经完成了所有设置步骤，并成功在我们的 i.MXRT1050 开发板上运行示例代码。 我们的问题是，我们希望在 github 上合作开展一个新项目。 因此，我克隆了 RT1050 的“新项目” repo，做了一些小改动，然后将项目文件夹推送到我们的 repo。 我们似乎遇到了两个问题： - 如果 .vscode并且 armgcc 文件夹是共享的，那么项目的 CMake 文件中的所有路径都是来自我计算机的绝对路径。因此我们的其他开发人员在尝试构建时会遇到错误。 - 如果将这些文件添加到 gitignore，导入项目时会缺少主板的所有支持文件，因此项目也无法编译。 我们已经在另一台开发人员的计算机上构建了这个项目，并使用了一些 hack-y 解决方案。（复制__repo__ ，.vsCode，和 armgcc 文件夹（来自同名项目，位于我们随后删除并克隆我们自己的项目的同一位置），但这不是正确的方法。 设置该功能的步骤是什么？我的 .gitignore 中应该包含什么？以及需要采取哪些步骤来从存储库设置项目？ 回复：如何合作完成一个项目？版本控制/git 谢谢！这个解决方案有效，我们现在正在一起开展这个项目。 回复：如何合作完成一个项目？版本控制/git 你好@halfordC ， 请参阅下面使项目可在 Git 中共享所需的一些更改： 在你的项目中，在 .vscode 下文件夹（应保存在 Git 中）中有一个名为 mcuxpresso-tools.json 的文件，其中包含两个绝对路径：“toolchainPath”和“path”（在“sdk”节点下）。 您可以引用环境变量来确保这些路径在不同的计算机上起作用。 例如：“toolchainPath”：“ ${env:ARMGCC_PATH} ”——其中 ARMGCC_PATH 是指向工具链的环境变量。 ide_overrides.cmake 可以添加到。gitignore，因为它是由构建过程重新生成的。 应将生成构建工件的文件夹添加到。gitignore 也是如此。 希望这些步骤有所帮助。 谢谢！ Dragos。

MUX_0_CSC only use FIRC clock? Hello, While referring to the document on generating clocks for the S32K314, I came across a question. [Figure1] In [Figure1], it states that MUX_0_CSC receives either PLL_PHI0_CLK or FIRC_CLK as its input. [Figure2] However, in [Figure2], the explanation for the SELCTL bit of MSC_0_CSC only indicates that FIRC can be selected. So, does this mean that MUX_0_CSC cannot use PLL_PHI0_CLK as a clock source? Re: MUX_0_CSC only use FIRC clock? thank you! Re: MUX_0_CSC only use FIRC clock? Hi@studyseok8466 Please refer to latest datasheet , "S32K3xx Reference Manual, Rev. 9, 07/2024".

Using the memmove function provided by the libc99 library gives an error result in S32 DS USING 5744 Hi NXP experts, Recently we are using mpc5744 with S32 Design Studio for Power Architecture Version 2017.R1 to compile the project. Now we are facing a memmove function problem. The project in the attachment is modified based on "hello world" and can reproduce the issue we encountered. We defined a 40-byte array of type U8 as the data source, used 0x4001268e as the data destination, called the memmove function to copy data, but found that the last 6 bytes of the destination data were not copied correctly. Upon analyzing the standard C code, we discovered that the issue might be related to the macro replacement of deref_auto_inc in __copy_long_mem.c. The memmove.o included in libc99.a should have enabled #define deref_auto_inc(p) *++(p), but it was incorrectly enabled as #define deref_auto_inc(p) *(p)++. We want to confirm if this issue is caused by a bug in the default lib library provided by s32DS or an default method we have usd. We also found in the map file that the memmove function is not compiled from the C source code but rather uses library functions from libc99.a. This means that we cannot solve this problem by modifying the C source code, is that correct? How should we go about resolving this issue then? We are in urgent need of your help. Project is attached. Thanks!!!  Thanks! Re: Using the memmove function provided by the libc99 library gives an error result in S32 DS USING Hi,  I already put answer to your original thread - https://community.nxp.com/t5/MPC5xxx/mpc5744-facing-a-memmove-function-bug/m-p/1850679#M25343 

プロジェクトで協力して取り組むには?バージョン管理 / git 私と他の2人の開発者のチームは、MCUXpressoのvsCode拡張機能に追いついています。 すべてのセットアップ手順を完了し、i.MXRT1050 開発ボードでサンプル コードを実行することに成功しました。 私たちの問題は、githubの新しいプロジェクトに協力して取り組みたいということです。 そこで、RT1050 の "新しいプロジェクト" リポジトリを複製し、いくつかの小さな変更を加え、プロジェクト フォルダーをリポジトリにプッシュしました。 2つの問題に遭遇したようです。 - .vscode の場合armgccフォルダが共有されている場合、プロジェクトのCMakeファイル内のすべてのパスは、私のコンピューターからの絶対パスです。そのため、他の開発者がビルドしようとするとエラーが発生します。 - これらのファイルが gitignore に追加されている場合、プロジェクトのインポートにはボードのすべてのサポート ファイルがないため、プロジェクトもコンパイルできません。 私たちは、いくつかのハックのような解決策を使用して、別の開発者のコンピューター上に構築するプロジェクトを持っています。( __repo__、.vsCode、そして、同じ名前のプロジェクトからarmgccフォルダを、その後、自分のプロジェクトを削除してクローンしたのと同じ場所にあります)、これはこれを行う正しい方法ではありません。 これを設定する手順は何ですか?私の.gitignoreには何が必要ですか、また、リポジトリからプロジェクトを設定するには、どのような手順を実行する必要がありますか? Re:プロジェクトで協力して取り組むには?バージョン管理 / git 感謝！この解決策が功を奏し、今では全員が一緒にプロジェクトに取り組んでいます。 Re:プロジェクトで協力して取り組むには?バージョン管理 / git こんにちは@halfordC、 プロジェクトを Git で共有可能にするために必要な変更を以下に示します。 プロジェクト内の .vscodeフォルダ (Git に保存する必要があります) には、"toolchainPath" と "path" ("sdk" ノードの下) の 2 つの絶対パスを含む mcuxpresso-tools.json というファイルがあります。 環境変数を参照して、これらのパスが異なるコンピューターで機能することを確認できます。 例: "toolchainPath": "${env:ARMGCC_PATH}" – ここで、ARMGCC_PATHはツールチェーンを指す環境変数です。 ide_overrides.cmake を に追加できます。gitignore は、ビルド プロセスによって再生成されます。 ビルド成果物が生成されるフォルダは、.gitignoreも。 これらの手順がお役に立てば幸いです。 ありがとうございます ドラゴス。

S32K312 Core Clock Hello. I found clock configuration table in Reference Manual Table 145. Is it limitation or just example? I want to set Core Clock = 60 MHz, is it okay? Best Regards, Sean Sung Re: S32K312 Core Clock Hello @Robin_Shen  Thank you for reply. Best Regards, Sean Sung Re: S32K312 Core Clock Hi There is a NOTE in S32K3XXRM: The frequencies in the table above are maximum frequencies for a specific clock. However, any clock frequency selected must adhere to the same clock divider ratios shown in System clocking configurations.   So it is possible to set Core Clock to 60MHz, but you need to pay attention to modifying the divider of other clocks.   Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

Daul vcom fatFS USB OTG1 I'm using the MIMXRT1170-EVKB starter kit and I would to know if OTG USB layer able to handle both vcom and usb host fatFS on the same port? I'm trying to get both working at the same time, using the same port with freeRTOS. Thanks in advance for any clarification 回复： Daul vcom fatFS USB OTG1 Hi @PaoloRB , Thanks for your interest in NXP MIMXRT series! It is possible to switch between device and host roles using the same USB port. The pin_detect example provided in the SDK can be a start: Best regards, Gavin

External Frequence and Duty Input Measurement Hello Everyone, I want to measure external frequency input and duty cycle on my custom board i.mx.rt1176. I did not find application note or example code. Is there any source that help me to start writing my code? Best Regards, Basri KAYA Re: External Frequence and Duty Input Measurement Hi @Bkaya  Thank you very much for your patience.  The QTIMER is limited to work with the BUS_CLK_ROOT, given the fact that you are already using the maximum prescaler value, I would think that testing with reducing the frequency of the bus clock could have been an option.  Another way to measure with such low frequecy would be using low clock reference like the RTC.  Diego Re: External Frequence and Duty Input Measurement Hi @diego_charles, Thank you. I read the frequency input. I changed the divider to 128 so i can measure between 20-10.000 Hz. I did not measure below 20 Hz. Is there a way to do it ?  Best Regards, Basri KAYA Re: External Frequence and Duty Input Measurement Hi @Bkaya  Thank you for reaching us and for your patience.  I think you could use the QTIMER peripheral for this purpose. There is input capture demo on the SDK (qtmr_inputcapture_outputpwm_cm7) this could help you as a starting point to measure frequency.  As one of my colleagues mention the QTIMER could also help you to measure duty cycle.  See this post PWM duty cycle measurement on RT105x for a more detailed idea.  I hope this still could help you.  Diego.

How to work on a project collaboratively? Version control / git Me, and a team of 2 other developers are getting up to speed on the vsCode extension for MCUXpresso.  We've done all the setup steps, and have had success running example code on our i.MXRT1050 development boards.  Our issue, is that we would like to work collaboratively on a new project in github. So, I cloned the "new project" repo for the RT1050, made a few small changes, and pushed the project folder to our repo.  We seem to have run into 2 problems:  - If the .vscode and armgcc folder is shared, then all of the paths in the CMake file for the project are the absolute paths from my computer. So our other devs get errors when they try to build.  - If these files are added to the gitignore, importing the project is missing all the support files for the board, and so project is also not able to compile.  We have got the project to build on another devs computer with some hack-y solutions. (copying the __repo__, .vsCode, and armgcc folder from a project of the same name, in the same location that we then deleted and cloned our own project into), but this can't be the correct way to do this.  What are the steps to set this up? What should I have in my .gitignore, and what steps need to be taken to set up a project from a repository? Re: How to work on a project collaboratively? Version control / git Thanks! This solution worked, we are now all working on the project together.  Re: How to work on a project collaboratively? Version control / git Hi @halfordC,  Please find below some changes needed to make the project shareable in Git: In your project, under .vscode folder (which should be saved in Git), there is a file called mcuxpresso-tools.json that contains two absolute paths: “toolchainPath” and "path" (under “sdk” node).          You can refer environment variables to make sure these paths work on different computers.          Ex:  "toolchainPath": "${env:ARMGCC_PATH}" – where ARMGCC_PATH is an environment variable that points to a toolchain. ide_overrides.cmake can be added to . gitignore as it is regenerated by the build process. Folders where the build artifacts are generated should be added to . gitignore too. Hope these steps help. Thanks, Dragos.

Daul vcom fatFS USB OTG1 MIMXRT1170-EVKBスターターキットを使用していますが、OTG USBレイヤーが同じポートでvcomとusbホストの両方のfatFSを処理できるかどうか知りたいですか? 私はfreeRTOSで同じポートを使用して、両方を同時に動作させるようにしようとしています。 ご説明をよろしくお願いいたします

外部周波数およびデューティ入力測定 みなさん カスタムボードi.mx.rt1176で外部周波数入力とデューティサイクルを測定したいです。アプリケーションノートやサンプルコードは見つかりませんでした。コードを書き始めるのに役立つソースはありますか? よろしくお願いいたします。 バスリ・カヤ

IMX8ULPIEC SAI interfase Good day to all. I have a task of programming SAI interface for i.mx 8 under m-33 core. I figured out that SAI0 and SAI1 are suitable for me, but I can't figure out from the IO Muxing pins I need. Alternative function for I2S? For example PTA1 witch Output7 function(I2S0_RX_FS)  will work as FS for SAI0 with User Defined Protocol? i.MX8ULP Re: IMX8ULPIEC SAI interfase This is what I needed, thank you! Re: IMX8ULPIEC SAI interfase Hello @Sandroom  I hope you are doing very well. Please refer to the SDK of the i.MX8ULP. You can download it from MCUXpresso SDK. Check the SAI examples under SDK_2_16_000_EVK-MIMX8ULP/boards/evkmimx8ulp/driver_examples/sai/interrupt_transfer. There is a File called pin_mux.c. There are defined the mux odtions for the pads including PTA1. void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M33[cm33] */ IOMUXC_SetPinMux(IOMUXC_PTA0_I2S0_RX_BCLK, 0U); IOMUXC_SetPinConfig(IOMUXC_PTA0_I2S0_RX_BCLK, IOMUXC_PCR_DSE_MASK); IOMUXC_SetPinMux(IOMUXC_PTA1_I2S0_RX_FS, 0U); IOMUXC_SetPinConfig(IOMUXC_PTA1_I2S0_RX_FS, IOMUXC_PCR_DSE_MASK); IOMUXC_SetPinMux(IOMUXC_PTA10_LPUART1_TX, 0U); IOMUXC_SetPinConfig(IOMUXC_PTA10_LPUART1_TX, IOMUXC_PCR_PE_MASK | IOMUXC_PCR_PS_MASK); IOMUXC_SetPinMux(IOMUXC_PTA11_LPUART1_RX, 0U); IOMUXC_SetPinConfig(IOMUXC_PTA11_LPUART1_RX, IOMUXC_PCR_PE_MASK | IOMUXC_PCR_PS_MASK); IOMUXC_SetPinMux(IOMUXC_PTA2_I2S0_RXD0, 0U); IOMUXC_SetPinMux(IOMUXC_PTA4_I2S0_MCLK, 0U); IOMUXC_SetPinConfig(IOMUXC_PTA4_I2S0_MCLK, IOMUXC_PCR_OBE_MASK | IOMUXC_PCR_DSE_MASK); IOMUXC_SetPinMux(IOMUXC_PTA7_I2S0_TXD0, 0U); IOMUXC_SetPinConfig(IOMUXC_PTA7_I2S0_TXD0, IOMUXC_PCR_DSE_MASK); IOMUXC_SetPinMux(IOMUXC_PTA8_PTA8, 0U); IOMUXC_SetPinConfig(IOMUXC_PTA8_PTA8, IOMUXC_PCR_OBE_MASK); IOMUXC_SetPinMux(IOMUXC_PTA9_PTA9, 0U); IOMUXC_SetPinConfig(IOMUXC_PTA9_PTA9, IOMUXC_PCR_OBE_MASK); } Best regards, Salas.

S32G3 RDB3 uboot hwconfig for example 4 in bsp41 Hi, I am trying to configure GMAC0, PFE0/1/2 to SGMII, SGMII, and RGMII, respectively, as described in Example 4 of the Ethernet Enablement User Guide. In that document, the hwconfig is specified as: setenv hwconfig "pcie0:mode=sgmii,clock=ext,fmhz=100,xpcs_mode=0;pcie1:mode=sgmii,clock=ext,fmhz=125,xpcs_mode=both" However, it seems that the format has changed in BSP 41. I made the necessary changes according to the BSP 41 User Guide and got the following: => print hwconfig hwconfig=serdes0:mode=pcie&xpcs0,clock=ext,fmhz=100;pcie0:mode=rc;xpcs0_0:speed=1G,an=0;serdes1:mode=xpcs0&xpcs1,clock=ext,fmhz=125;xpcs1_0:speed=1G;xpcs1_1:speed=1G This corresponds to serdes 0 in mode 1 and serdes 1 in mode 3. But, according to the BSP 41 User Guide, mode 1 is only mentioned for serdes 1. Could you please clarify how I should set the hwconfig in my case to match the configuration I need? Thanks, XD Re: S32G3 RDB3 uboot hwconfig for example 4 in bsp41 Hello @XD, Sorry for the late response I was doing some investigation, to answer your questions, in MODE1, this means using GMAC in SGMII in PHY lane 1, the output will be in the following pins: Let me know if this information solves all your questions and if the description matches the behavior in your HW. Re: S32G3 RDB3 uboot hwconfig for example 4 in bsp41 Hi @alejandro_e , Thank you for the detailed explanation. If we select mode 1 on SERDES0, GMAC0 will be mapped to PHY Lane 1. Does this mean the Ethernet MAC mapping to the XPCS table will change, placing GMAC0 on SERDES0 and XPCS1? I want to confirm that our hardware design correctly connects GMAC0 to the appropriate PCIe lanes in this mode 1 configuration. Thanks, XD Re: S32G3 RDB3 uboot hwconfig for example 4 in bsp41 Hello @XD,  Following the reference manual, you can configure GMAC0 in either lane 0 or 1 [page 2760, S32G3 Reference Manual, Rev. 4, 02/2024]: Be also aware of the XPCS (Physical Coding Sublayer) mapping, in the same page of the reference manual: About the routing, yes there could be pins changes depending on the software configuration, to avoid confusion in the interpretation please check the schematics, [S32G-VNP-RDB3-DESIGN-FILES] in page 6 you can see the block diagram and a table for the configuration,  knowing the dip switch configuration and tracking back the muxes to the S32G you can : For example., PFE_MAC2 can be in two ping groups: Let me know if this information answers your questions. Re: S32G3 RDB3 uboot hwconfig for example 4 in bsp41 Hi @alejandro_e , Thank you for your prompt response and clarification. I have a follow-up question. In the Ethernet Enablement User Guide, Example 4 shows GMAC0 using SerDes0 Lane 0. However, in our case, the hwconfig sets GMAC0 to SerDes0 Lane 1 (which I believe also aligns with Example 4). Could you clarify which lane GMAC0 should use in this setup? Additionally, if we use a different configuration, are there any physical changes we need to make? We are currently in the custom board design stage and would like to confirm if this lane change is solely a software configuration or if hardware modifications, such as rerouting connections, are required. Our board does not have a DIP switch. Thanks, XD Re: S32G3 RDB3 uboot hwconfig for example 4 in bsp41 Hello @XD, I have confirmed that table 7 in page 49 of the BSP41 user manual is incorrect. SerDes 0 can be configured in mode 1 as described in the examples I mentioned. Best regards,  Alejandro  Re: S32G3 RDB3 uboot hwconfig for example 4 in bsp41 Hello @XD, Thanks for the detailed description of your problem.  My understanding is that you want to achieve the following configuration [page 2760, S32G3 Reference Manual, Rev. 4, 02/2024]: Which will output GMAC0, PFE_EMAC0 and PFE_EMAC1. As you mentioned, the table 7 in the BSP41 manual only mentions Serdes 1 in mode 1, this might be an error in the documentation, Since in the next subsection 7.2.2.1 Example configurations [page 50 and 51, Linux BSP 41.0 User Manual for S32G3 platforms] you can see mode one is also configured for SerDes 0: I will have to confirm with the internal team if it is an error. and you can also see SerDes 1 in mode 3: Following these two examples the correct configuration is: serdes0:mode=pcie&xpcs0,clock=ext,fmhz=100;pcie0:mode=rc;xpcs0_0:speed=1G,an=0;serdes1:mode=xpcs0&xpcs1,clock=ext,fmhz=125;xpcs1_0:speed=1G,an=0;xpcs1_1:speed=1G As you can see, with this configuration you get Serdes 0 (serdes@40480000) in mode 1 and Serdes 1 (serdes@44180000) in mode 3: U-Boot 2022.04+g4744d0e2c8+p0 (May 27 2024 - 09:33:20 +0000) SoC: NXP S32G399A rev. 1.1 CPU: ARM Cortex-A53 r0p4 @ max 1300 MHz Model: NXP S32G399A-RDB3 DRAM: 3.5 GiB Core: 306 devices, 25 uclasses, devicetree: board MMC: FSL_SDHC: 0 Loading Environment from MMC... OK s32cc_serdes_phy serdes@40480000: Using mode 1 for SerDes subsystem s32cc_serdes_phy serdes@40480000: Unstable RX detected on XPCS0 pci_s32cc pcie@40400000: Configuring as RootComplex pci_s32cc pcie@40400000: Failed to get link up In: serial@401c8000 Out: serial@401c8000 Err: serial@401c8000 Board revision: RDB3 Revision F PCIe: BusDevFun VendorId DeviceId Device Class Sub-Class __________________________________________________________________________ pcie@40400000 RootComplex | `-- 01:00.00 0x1957 0x4300 Bridge device 0x04 Net: eth0: ethernet@4033c000 Found PFE version 0x0101 (S32G3) pfeng pfeng-base: Uploading CLASS firmware pfeng pfeng-base: EMAC0 block was initialized pfeng pfeng-base: EMAC1 block was initialized pfeng pfeng-base: EMAC2 block was initialized pfeng pfeng-base: Enabling the CLASS block pfeng pfeng-base: PFE Platform started successfully (mask: 7) s32cc_serdes_phy serdes@44180000: Using mode 3 for SerDes subsystem s32cc_serdes_phy serdes@44180000: Unstable RX detected on XPCS1 s32cc_serdes_phy serdes@44180000: Unstable RX detected on XPCS0 , eth1: pfe0, eth2: pfe1, eth3: pfe2 Hit any key to stop autoboot: 0 => => printenv hwconfig hwconfig=serdes0:mode=pcie&xpcs0,clock=ext,fmhz=100;pcie0:mode=rc;xpcs0_0:speed=1G,an=0;serdes1:mode=xpcs0&xpcs1,clock=ext,fmhz=125;xpcs1_0:speed=1G,an=0;xpcs1_1:speed=1G => xpcs list Registered XPCS instances: | ID | SerDes instance | XPCS | | 0 | serdes@40480000 | 0 | | 1 | serdes@44180000 | 1 | | 2 | serdes@44180000 | 0 | => In the mentioned section you will also see how to configure the switch 17 and switch 8 to obtain the desired result in your RDB3. For more details about the switches configuration you can check the RDB3 schematics [S32G-VNP-RDB3-DESIGN-FILES] in page 6: As you are probably aware for this configuration you will need to reconfigure the SJA110, for which you need the SJA1110 SDK and it requires to sign an NDA. For this I can recommend contacting your FAE/DFAE/NXP representative so he/she may help you enabling this product in you account. Let me know if this information solved your question. 

Possibility to add an additional code generator? Hi  I was wondering whether it is possible to generate additional .c/.h files with the MCUXpresso Config Tool? So what I have in mind, the MCUXpresso Config Tool already generates very nice pin_mux.h header files including all the symbols for PORTs and GPIOs. E.g. for the GPIO where my red LED is connected to: #define BOARD_INITPINS_LED_RED_GPIO GPIO0  /*!<@brief GPIO peripheral base pointer */ With that I would like to generate an additional header file containing same symbols as in pin_mux.h, but with a typecast: #define LED_RED_PORT (GPIO::Port*)BOARD_INITPINS_LED_RED_GPIO I fear MCUXpresso Config Tool isn't that flexible. But what do you think, are there any other good approaches/tools to generate such header files each time I run the code generator in MCUXpresso Config Tool? Best, THE0 Re: Possibility to add an additional code generator? Hi @Harry_Zhang  Thank you very much for your feedback. I think the approach using a post-processing script should work well. BR The0 Re: Possibility to add an additional code generator? Hi @The0  You’re right that the MCUXpresso Config Tool doesn’t have built-in flexibility to generate additional customized .c or .h files with the kind of modifications you’re describing, such as adding typecasts or additional symbols based on the ones in pin_mux.h. However, you can still achieve this by setting up a custom post-processing script that runs after the code generation. After running the MCUXpresso Config Tool, use a script (Python, Bash, etc.) to read the generated pin_mux.h file, extract the relevant symbols, and create your additional header file (custom_pin_mux.h or similar). BR Hang

Check the performance of the pfe0 interface Hi Sir, The bitrate of the pfe0 interface should be around 900 Mbit/sec, but it was approximately 650 Mbit/sec. How can I identify the bottleneck when transferring data through the pfe0 interface? Best regards, Jeff Re: Check the performance of the pfe0 interface Hello, @Jeff-CF-Huang  Thanks for your reply. From my experiece, firstly check the interrupts uses in your test, in this specific test, they are PFE0 and DMA, find the correponding irq number, and check if the affinity is supported under /proc/irq/XXX/smp_affinity. you may reference the following link for further reading: https://docs.redhat.com/en/documentation/red_hat_enterprise_linux_for_real_time/7/html/tuning_guide/interrupt_and_process_binding#Interrupt_and_process_binding From my test, if not doing any tuning, the iperf test would reach 1G line rate after 5-20 seconds, due the irqbalance's help. If there are multiple tasks in the system, then maybe keep using irqbalance is still a good choice, since irq binding may impact other tasks running in the system. BR Chenyin Re: Check the performance of the pfe0 interface Hi Chenyin, Thank you for your suggestion. Could you explain how to bind hardware resources to a specific core or group of cores? Best regards, Jeff Huang Re: Check the performance of the pfe0 interface Hello, @Jeff-CF-Huang  Thanks for you reply. I have reproduced the issue with your script while running for several times, there may be 700-800 Mbps for 5-20 seconds during a 100 seconds test. I looked into the issue, in my opinion, it may caused by heavy load of irq handling during the test, A53 is not very powerful,  while doing iperf benchmark,   there would be huge number of irqs to one core. Once enabling the ADC, there also be many irqs, if when the irqs are handled on one core, the benchmark results may be impact, but since the irqbalance is enabled by default, after several seconds, the irqs may be balanced to other cores, the load of cores that impact the TCP performance would be decreased so that the rest of testing results may keep reaching the line rate. If it is worried that the network throughput would be impacted, I suggest binding the corresponding irqs(PFE0) to a dedicated core, to avoid other impact of the system load. BR Chenyin BR Chenyin Re: Check the performance of the pfe0 interface Hi Chenyin, Thanks for your reply. After checking, the issue is not easily reproducible. I’ve tried the following commands that are most likely to raise the situation. #!/bin/bash echo 1 > /sys/bus/iio/devices/iio:device1/scan_elements/in_voltage4_en echo 4096 > /sys/bus/iio/devices/iio:device1/buffer/length echo 1 > /sys/bus/iio/devices/iio:device1/buffer/enable echo 1 > /sys/bus/iio/devices/iio:device0/scan_elements/in_voltage4_en echo 4096 > /sys/bus/iio/devices/iio:device0/buffer/length echo 1 > /sys/bus/iio/devices/iio:device0/buffer/enable echo 0 > /sys/bus/iio/devices/iio:device1/buffer/enable echo 1 > /sys/bus/iio/devices/iio:device1/buffer/enable echo 0 > /sys/bus/iio/devices/iio:device0/buffer/enable echo 1 > /sys/bus/iio/devices/iio:device0/buffer/enable iperf3 -c 192.168.1.20 -t 100 Best regards, Jeff Huang Re: Check the performance of the pfe0 interface Hello, @Jeff-CF-Huang  Sorry that I did not reproduce the issue from my side, the logs are attached for your reference. May I know if there are additional setings for trigger such issue? BR Chenyin Re: Check the performance of the pfe0 interface We are working with the S32G399 and BSP40, and using iperf3 as the client. If we don't enable the ADC, the rate can reach approximately 950 Mbit/sec. The below command is how to enable adc. echo 1 > /sys/bus/iio/devices/iio:device1/scan_elements/in_voltage4_en echo 4096 > /sys/bus/iio/devices/iio:device1/buffer/length echo 1 > /sys/bus/iio/devices/iio:device1/buffer/enable Re: Check the performance of the pfe0 interface Hello, @Jeff-CF-Huang  Thanks for you post. May I know if you are working with S32G2 or G3? which version BSP you are using for the performance benchmark? Would you please share  more information? I just tested the TCP performance on RDB2 with BSP42, it could achieve the line rate of 1G port. BR Chenyin

What is VRC_CTRL? Hello I have a question regarding the power management section of the S32K314 MCU. [Figure1] In [Figure 1], it appears that VRC_CTRL is the signal responsible for determining whether to supply 1.5V to the internal core. My question is, does VRC_CTRL enter the BASE through GPIO, or is it input as a different waveform? Thank you for your help! Re: What is VRC_CTRL? Thank you!! Re: What is VRC_CTRL? Hi @malove , No, it is an analog signal which controls base of external BJT, as it is depicted on your picture. Best regards, Pavel Re: What is VRC_CTRL? Thank you @PavelL  If I am using VRC_CTRL, is the output of VRC_CTRL PWM? Re: What is VRC_CTRL? Hi @malove , if VRC_CTRL is not used (please refer to S32K3XXRM rev9 chapter 42.7.3 PMC Configuration Register (CONFIG), bits LMBCTLEN and LMEM), the pin can be used as PTE13.  Best regards, Pavel

WiFi chip detection problem Hello all,  I have a custom board based on iMX8MP with U-Blox Maya-W266 wifi module integrated. (Schematic diagram snippets attached).  SD2_X pins from U-Blox are connected to GPIO2 port of iMX8MP as shown below: After booting the board, I followed instructions from "Getting Started with NXP-based Wireless Modules on i.MX 8M Quad EVK Running Linux OS" to bring up the wifi module: However, I do not see any related messages in dmesg command output. I verified the configurations of wifi_mod_para.conf to be correct. Also, the firmware binary file is present inside nxp directory. I have no idea on what to check for in further steps. I am not sure whether modifications in device tree are needed since the hardware designs are basically identical to the im8mp-evk design.   Any guidance would be of great help. Thank you!! Re: WiFi chip detection problem Hello I listed SDIO interface check items here. Please compare with your design.  Re: WiFi chip detection problem Hi @shaun_wu  I tested the signals in SDIO line. The clock seems fine. But the command is not correct. It needed to be 0 but it is something else. So, I guess the settings in device tree I am using is still wrong.   Re: WiFi chip detection problem I have added the details. Since I am using dts file decompiled from dtb file, the symbols you mentioned are converted into corresponding hex values.  I tried to compile this dts into dtb by commenting out the lines that were not shown in your device tree. The compiler showed some errors, so I had to include those lines.  Hex values in pinctrl-X belong to following: Even with this entry in device tree, the problem still exits. Since there is only one parameter in the device tree you suggested, I tried removing the second parameter. I still get the same result. Re: WiFi chip detection problem Hello @bgaurav1718  Please try add this node to your dts. &usdhc2 { assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; assigned-clock-rates = <400000000>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-1 = <&pinctrl_usdhc3_100mhz>; pinctrl-2 = <&pinctrl_usdhc3_200mhz>; bus-width = <8>; non-removable; status = "okay"; }; Best Regards Shaun Re: WiFi chip detection problem usdhc2 is at address 30b50000. It is aliased as mmc1. So, mmc1 is probably where the WiFi module is connected. But there is only one message in kernel log related to mmc1: [ 3.312631] mmc1: SDHCI controller on 30b50000.mmc [30b50000.mmc] using ADMA Re: WiFi chip detection problem I installed a new image and looked through its device tree.  usdhc1 is mapped to mmc@30b40000, usdhc2 is mapped to mmc@30b50000, usdhc3 is mapped to mmc@30b60000. I think this is what the device tree configuration is supposed to be. Still I get the same message [ 2.107370] mmc2: new HS400 Enhanced strobe MMC card at address 0001 NOTE: I was reading an this article related to the issue. There, it mentions following: Regarding the schematic, I have attached an image in original question. The pins from UBlox are connected to SD2_xxxx pins of the processor.  These pins belong to USDHC2. Re: WiFi chip detection problem Hello @bgaurav1718  You could check shematic. Best Regards Shaun Re: WiFi chip detection problem We are using a custom board with UBlox WiFi module soldered onto the board. So, I don't think hot swapping is feasible here. Do you have any other ways I could possibly try? Re: WiFi chip detection problem Hello @bgaurav1718  1. I think mmc2 is not sdio interface you used. It is used for boot. You device didn't detected Wi-Fi card. There is a simply way to double check, our sd interface support hot swap. You could pullout when board running, see if mmc2 shows sd card removed.  2. I cant find any sd node from your device tree, could you double check on your side? You could go to our github to check 8mp example devise treelinux-imx/arch/arm64/boot/dts/freescale/imx8mp-evk.dts at lf-6.6.y · nxp-imx/linux-imx · GitHub. A sdio node should like following:  &usdhc3 { assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; assigned-clock-rates = <400000000>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-1 = <&pinctrl_usdhc3_100mhz>; pinctrl-2 = <&pinctrl_usdhc3_200mhz>; bus-width = <8>; non-removable; status = "okay"; }; Best Regards Shaun Re: WiFi chip detection problem After struggling with a frustrating WiFi chip detection problem, I decided to take a break and called Ukraine Cleaners for house cleaning in Edmonds. They did an amazing job, leaving my home spotless and stress-free. Definitely lifted my spirits! Re: WiFi chip detection problem I don't think WiFi module is connected to other sd interfaces. Device tree is attached below: Re: WiFi chip detection problem [ 2.024245] mmc2: SDHCI controller on 30b60000.mmc [30b60000.mmc] using ADMA [ 2.103390] mmc2: new HS400 Enhanced strobe MMC card at address 0001   --> Sorry I misunderstand your post, you are right this is not we expected. Could you share dts you used? And could you double confirm which sd interface you are using?   Best Regards Shaun  Re: WiFi chip detection problem Hello @bgaurav1718  I didn't see the log you shared, could you reshare? I see the card was detected, it was detected as sdio card, not sd card. Thats what we expected. No problem. Best Regards Shaun Re: WiFi chip detection problem The module is detected as SD card. I have added snippet from kernel log above. Also, no mlan0 and uap0 interfaces are available. Re: WiFi chip detection problem Hello @bgaurav1718  Could you check with following cmd: dmesg       #check driver and firmware loading  ifconfig -a #check if maln0 uap0 interface enabled Best Regards Shaun Re: WiFi chip detection problem UPDATE: I found following messages in kernel log.  [ 2.024245] mmc2: SDHCI controller on 30b60000.mmc [30b60000.mmc] using ADMA [ 2.103390] mmc2: new HS400 Enhanced strobe MMC card at address 0001 However, it is supposed to be detected as: mmc1: new ultra high speed DDR50 SDIO card at address 0001

[SLN-SVUI-IOT] Is `sln_svui_iot_r2.zip` support only MCUXpresso 11.8.1 ? and VIT dear qct I use MCUXpresso IDE v11.9.0 now. so Can Above work without any issue on MCUXpresso IDE v11.9.0 ? Is it absolutely necessary to use MCUXpresso 11.8.1 and MCUXpresso RT1060 EVKB 2.14.0 SDK ? and  When I get `VIT_Model_en.h` the  using VIT(https://vit.nxp.com/), How do I apply this file? Is there any documentation for it? Thanks, Bryan Re: [SLN-SVUI-IOT] Is `sln_svui_iot_r2.zip` support only MCUXpresso 11.8.1 ? and VIT thanks for your helps~ Re: [SLN-SVUI-IOT] Is `sln_svui_iot_r2.zip` support only MCUXpresso 11.8.1 ? and VIT Hi @bryan_hong  I appreciate your interest on our voice solution projects. In theory, you should be able to use MCUXpresso IDE v11.9.0. For first time evaluation I recommend using the SDK version used for the relase of a project, if everything goes well, you can migrate to a latest SDK version. If you are getting any troubles feel free to let us know.  Regarding the integration of the VIT_Model_en.h. Please refer to the How to integrate the new model in sln_svui_iot_local_demo? section of the SLN-SVUI-IOT User Manual. Thank you for your patience, I hope this helps! Diego Diego

How to modify the DDR configuration of S32G-VNP-RDB3 HI NXP, What do I need to do to modify the DDR configuration of S32G-VNP-RDB3? Do you have any relevant guidance documents? Re: How to modify the DDR configuration of S32G-VNP-RDB3 HI @chenyin_h  According to the website you provided, I can find the document now. Thank you! Re: How to modify the DDR configuration of S32G-VNP-RDB3 Hello, @DRAVE  Thanks for your reply You may find the document from the following link: https://community.nxp.com/t5/NXP-Designs-Knowledge-Base/S32G-DDR-customization-application-doc/ta-p/1399896 Note that it is not formal documents that released from NXP.com, this article is a training and auxiliary document. it is not a substitute for the official document. BR Chenyin Re: How to modify the DDR configuration of S32G-VNP-RDB3 HI @chenyin_h , I found the website https://community.nxp.com/t5/NXP-Designs-Knowledge-Base/S32G-ATF-customization-application-doc/ta-p/1450561#_Toc102056740 There are ATF DDR configuration instructions available. On page 36 of the S32G_ATF_BSP32/V1-20220550.pdf document. I cannot find the "S32_内存配置与测试应用手册_V4_xxxxxxxx.pdf". Can you help me find it? thank you! Re: How to modify the DDR configuration of S32G-VNP-RDB3 Hello, @DRAVE  Thanks for the post. For DDR related modification, I suggest firstly reading the chapter 37 of S32G RM for detailed reference. For code level, the ddr related code is part of the TF-A, you may check the code under drivers/nxp/ddr from: https://github.com/nxp-auto-linux/arm-trusted-firmware BR Chenyin

S32K312 ADC scan mode with DMA transfer hello,  I'm using s32ds3.5,RTD4.0, I want use ADC scan and get results by DMA, is there any application notes or example?  Re: S32K312 ADC scan mode with DMA transfer Hi, seems there is no such example directly.  But various triggering concept examples are shown below, but without DMA https://community.nxp.com/t5/S32K-Knowledge-Base/RTD400-LLD-K344-ADC-SW-HW-trigger/ta-p/1966179 Some examples with DMA implemented... https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-PIT-BTCU-ADC-1-BCTU-ADC-DATA-REG-DM... https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-PIT-BTCU-parallel-ADC-FIFO-DMA-DS3-... BR, Petr