FS26 のデータシートを提供できますか? こんにちは、 FS26 のデータシートを提供できますか?

NTAG5: Read UID via I2C ? Hi ! Is there a way to get the UID of the NTAG5 Link Chip via the I2C Interface ?  best regards  Re: NTAG5: Read UID via I2C ? Hello @rfid_profi  It seems not available for I2C interface. Because INVENTORY and SELECT commands are Supported by NFC interface.

UART3 on i.MX 8M Mini Hi, I try to use UART3 on i.MX 8M Mini LPDDR4 EVKB M4 core but I'm not getting any signals. I'm using the evkmimx8mm_iuart_interrupt_transfer example. I edited pin_mux.c: IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U); IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX, IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | IOMUXC_SW_PAD_CTL_PAD_FSEL(2U)); IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U); IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX, IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | IOMUXC_SW_PAD_CTL_PAD_FSEL(2U)); I also had to edit the function BOARD_BootClockRUN() in clock_config.c: CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10); CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U); CLOCK_EnableClock(kCLOCK_Uart3); And I of course changed the definitions in main.c: #define DEMO_UART UART3 #define DEMO_UART_CLK_FREQ \ CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart3)) / \ (CLOCK_GetRootPostDivider(kCLOCK_RootUart3)) / 10 The Boot Switches are in Download Mode and I'm uploading the code via J-Link. I also configured UART3 in RDC. Therefore should UART3 be accessible with the M4, right? I connected Pin 8, which should be UART3 TX, from the Expansion Connector J1003 on an oscilloscope to detect signals but I can't see anything. What am I missing here? i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: UART3 on i.MX 8M Mini This worked for me as well , But I want to ask why we have done this. Re: UART3 on i.MX 8M Mini I could fix the issue by using the correct PinMux configuration. Instead of IOMUXC_UART3_RXD_UART3_RX  and IOMUXC_UART3_TXD_UART3_TX I'm using IOMUXC_ECSPI1_SCLK_UART3_RX and IOMUXC_ECSPI1_MOSI_UART3_TX now. Thank you for your help! Re: UART3 on i.MX 8M Mini do you dts has this? if yes, you need set to "disabled," pls double check it linux-imx/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi at lf-6.6.y · nxp-imx/linux-imx · GitHub &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; assigned-clocks = <&clk IMX8MM_CLK_UART3>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; fsl,uart-has-rtscts; status = "okay"; }; Re: UART3 on i.MX 8M Mini There's no dts when the switches are in Download mode. So UART3 should be free to use. Re: UART3 on i.MX 8M Mini could you confirm if your dts doesn't use uart3? if linux side uses this, you need disable this firstly, I don't know how your SW is, you can check it by yourself

请问 FS26 datasheet 能提供吗 hi， 请问 FS26 datasheet 能提供吗 Re: 请问 FS26 datasheet 能提供吗 HI Bert 您直接可以下载： FS26 | Safety System Basis Chip with Low Power, for ASIL D Systems | NXP Semiconductors

i.MX 8M Plus Cortex A53 Bare Metal Programming Hi Team, We are planning to do bare metal programming on i.MX 8M Plus Cortex A53 Processor.  1. Do we have bare metal support for cortex A-35 on the i.MX 8M Plus processor? If so, please share me related document links and sample projects.  2. If bare metal programming is not supported, can we run FreeRTOS on cortex A-35 on the i.MX 8M Plus processor. If so, please share me related document links and sample projects.  Regards, Anand Kumar D Re: i.MX 8M Plus Cortex A53 Bare Metal Programming Hello Zhiming, Thank You! for the support.  We have VAR-SOM-MX8M-PLUS System on Module Eval Kit with us and we will do some trials with it following the guidelines provided in the links.  Regards, Anand Kumar D Re: i.MX 8M Plus Cortex A53 Bare Metal Programming Hello, Please refer zephyrproject and it's source code. https://docs.zephyrproject.org/latest/develop/getting_started/index.html https://github.com/zephyrproject-rtos/zephyr Best Regards, Zhiming

Kernal build is failed for android bsp 12 showing FAILED: load BTF from vmlinux: Invalid argument I have tried to build the bsp of android 12 for imx-8mn evk board with lunch 61 but i got following error TEE_LOAD_ADDR=0x56000000 ATF_LOAD_ADDR=0x00960000 VERSION=v2 ./print_fit_hab.sh 0x60000 evk.dtb 0x40200000 0x5B000 0xEFEA8 0x402EFEA8 0x14AEA8 0xBE38 0x960000 0x156CE0 0xA0D0 make[1]: Leaving directory '/home/[email protected]/android_build/vendor/nxp-opensource/imx-mkimage' ===================Finish building imx8mn-evk-uuu:imx8mn_evk_android_uuu_defconfig =================== MODPOST vmlinux.symvers MODINFO modules.builtin.modinfo GEN modules.builtin LD .tmp_vmlinux.btf BTF .btf.vmlinux.bin.o LD .tmp_vmlinux.kallsyms1 KSYMS .tmp_vmlinux.kallsyms1.S AS .tmp_vmlinux.kallsyms1.S LD .tmp_vmlinux.kallsyms2 KSYMS .tmp_vmlinux.kallsyms2.S AS .tmp_vmlinux.kallsyms2.S LD vmlinux BTFIDS vmlinux FAILED: load BTF from vmlinux: Invalid argument make[2]: *** [/home/[email protected]/android_build/vendor/nxp-opensource/kernel_imx/Makefile:1247: vmlinux] Error 255 make[2]: *** Deleting file 'vmlinux' make[2]: Leaving directory '/home/[email protected]/android_build/out/target/product/evk_8mn/obj/KERNEL_OBJ' make[1]: *** [Makefile:237: __sub-make] Error 2 make[1]: Leaving directory '/home/[email protected]/android_build/vendor/nxp-opensource/kernel_imx' make: *** [/home/[email protected]/android_build/device/nxp/common/build/kernel.mk:197: /home/[email protected]/android_build/out/target/product/evk_8mn/obj/KERNEL_OBJ/arch/arm64/boot/Image.lz4] Error 2 make: Leaving directory '/home/[email protected]/android_build' full log while running the ./imx-make.sh is attached Android Re: Kernal build is failed for android bsp 12 showing FAILED: load BTF from vmlinux: Invalid argumen Hello, Please use Ubuntu18.04 to compile Android12. Best Regards, Zhiming Re: Kernal build is failed for android bsp 12 showing FAILED: load BTF from vmlinux: Invalid argumen => Can you try to delete /home/[email protected]/android_build/out/target/product/evk_8mn/obj/KERNEL_OBJ and rebuild it again? Ans : Already tried the build multiple times after make clean => Are you using Ubuntu18.04? Ans : No , Ubuntu 22.04.5 LTS => Did you install the gcc here : 1. Prepare the build environment for U-Boot and Linux kernel ? Ans : yes Re: Kernal build is failed for android bsp 12 showing FAILED: load BTF from vmlinux: Invalid argumen Hello, Can you try to delete /home/[email protected]/android_build/out/target/product/evk_8mn/obj/KERNEL_OBJ and rebuild it again? Are you using Ubuntu18.04? Did you install the gcc here : 1. Prepare the build environment for U-Boot and Linux kernel ? Best Regards, Zhiming

NXP LS1043A 配置 LPUART 实现 RS485 半双工串行通信 你好，我正在尝试配置 LS1043A 中的 LPUART3，以使用 2 线模式进行 RS485 半双工操作。我必须涵盖以下场景： 1. RS485半双工回波接收传输的数据 2. RS485 半双工，无回声，因此没有传输数据的接收 操作将在这两种模式之间切换并正确同步。您能提供上述两种场景的LPUART寄存器配置吗？ QorIQ LS1设备 回复：NXP LS1043A 配置 LPUART 进行 RS485 半双工串行通信 非常感谢您的回复！ 回复：NXP LS1043A 配置 LPUART 进行 RS485 半双工串行通信 请参阅附件的lpuart设备驱动程序。

ADC ChannelType 我想知道S32K3XX的ADC中，P、S、MA、X这些通道后缀的含义是什么，在手册中哪个地方有详细的描述呢？

NXP LS1043A RS485半二重シリアル通信用にLPUARTを構成 こんにちは、私は2線式モードを使用してRS485半二重動作のLS1043AでLPUART3を構成しようとしています。私は次のシナリオをカバーする必要があります: 1. 送信されたデータを受信するためのエコーバック付きRS485半二重 2.エコーバックなしのRS485半二重により、送信データの受信がなくなります 操作はこれらのモード間で切り替えられ、適切に同期されます。上記の 2 つのシナリオで LPUART レジスタの構成を提供できますか。 QorIQ LS1デバイス Re:NXP LS1043A RS485半二重シリアル通信用のLPUARTを構成する ご回答いただき、誠にありがとうございます! Re:NXP LS1043A RS485半二重シリアル通信用のLPUARTを構成する 添付のlpuartデバイスドライバを参照してください。

NXP LS1043A configure LPUART for RS485 half-duplex serial communication Hi, I am trying to configure LPUART3 in LS1043A for RS485 half-duplex operation using 2-wire mode. I have to cover following scenarios: 1. RS485 half duplex with echo back to receive the transmitted data 2. RS485 half duplex without echo back so that there is no receive of transmitted data The operation will be switched between both these modes and is properly synchronized. Can you provide the configuration of LPUART registers for the above two scenarios? QorIQ LS1 Devices Re: NXP LS1043A configure LPUART for RS485 half-duplex serial communication Thank you very much for your response! Re: NXP LS1043A configure LPUART for RS485 half-duplex serial communication Please refer to the attached lpuart device driver.

i.MX 8M Plus Cortex A53 ベアメタルプログラミング こんにちはチーム、 私たちは、8M Plus Cortex A53プロセッサでベアメタルプログラミングを行う予定です i.MX。 1. i.MX 8M PlusプロセッサのCortex A-35のベアメタルサポートはありますか?もしそうなら、関連ドキュメントのリンクとサンプルプロジェクトを共有してください。 2.ベアメタルプログラミングがサポートされていない場合、i.MX 8M PlusプロセッサのCortex A-35でFreeRTOSを実行できますか。もしそうなら、関連ドキュメントのリンクとサンプルプロジェクトを共有してください。 よろしくお願いします。 アナンド・クマールD Re:i.MX 8M Plus Cortex A53ベアメタルプログラミング こんにちは、Zhiming、 ありがとうございます！サポートのために。 VAR-SOM-MX8M-PLUS System on Module Eval Kitを使用しており、リンクに記載されているガイドラインに従っていくつかの試用を行います。 よろしくお願いします。 アナンド・クマールD

i.MX 8M Plus Cortex A53 裸机编程 大家好， 我们计划在 i.MX 8M Plus Cortex A53 处理器上进行裸机编程。 1. 我们是否为 i.MX 8M Plus 处理器上的 Cortex A-35 提供裸机支持？如果有，请与我分享相关文档链接和示例项目。 2.如果不支持裸机编程，我们可以在i.MX 8M Plus处理器上的cortex A-35上运行FreeRTOS吗？如果有，请与我分享相关文档链接和示例项目。 此致， 阿南德·库马尔 回复：i.MX 8M Plus Cortex A53 裸机编程 志明你好， 谢谢！的支持。 我们拥有 VAR-SOM-MX8M-PLUS 系统模块评估套件，我们将按照链接中提供的指南对其进行一些试验。 此致， 阿南德·库马尔

尝试批量擦除后无法连接到S32K118 大家好，NXP 团队和其他人。 我正在使用 S32k118 CSEc 并尝试了 AN5401 提供的示例 1：配置部件和加载密钥。我在 DebugRAM 配置中运行了该项目，可以对 MCU 进行分区并设置密钥。我没有对密钥设置任何保护，但是当我下次尝试擦除整个芯片时，我收到了保护字节已设置的消息。当我继续时，它不断抛出相同的消息并最终失败。 以下是 JLink 的输出： 正在连接... - 通过 USB 连接到探针/编程器设备 0 - 探针/编程器固件：J-Link Ultra V5 编译于 2024 年 2 月 19 日 15:14:38 探头/编程器序列号：505002010 -选择设备“S32K118（允许安全）”。 - 目标接口速度：4000 kHz（固定） - VTarget = 3.305V - InitTarget() 开始 - 已选择 SWD。执行 JTAG -> SWD 切换序列。 - 设备现在将不再安全。 - 停止 CPU 时超时。 - InitTarget() 结束 - 耗时 4.33 秒 - 找到 ID 为 0x0BC11477 的 SW-DP - DPIDR：0x0BC11477 - CoreSight SoC-400 或更早版本 - 扫描 AP 地图以查找所有可用的 AP - AP[2]: 由于已到达 AP 地图末尾，因此停止 AP 扫描 - AP[0]: AHB-AP (IDR: 0x04770031) - AP[1]: JTAG-AP (IDR: 0x001C0020) - 迭代 AP 映射以找到要使用的 AHB-AP - AP[0]: 已跳过。无法读取 CPUID 寄存器 - AP[1]：已跳过。不是 AHB-AP - 连接到 CPU 失败。重置下执行连接。 - DPIDR：0x0BC11477 - CoreSight SoC-400 或更早版本 - 扫描 AP 地图以查找所有可用的 AP - AP[2]: 由于已到达 AP 地图末尾，因此停止 AP 扫描 - AP[0]: AHB-AP (IDR: 0x04770031) - AP[1]: JTAG-AP (IDR: 0x001C0020) - 迭代 AP 映射以找到要使用的 AHB-AP - AP[0]: 已跳过。无法读取 CPUID 寄存器 - AP[1]：已跳过。不是 AHB-AP - 在 Coresight 设置中找不到核心 我也尝试了这里建议的序列https://community.nxp.com/t5/S32K/Unbricking-S32K146/mp/937227： J-Link>r0 J-Link>swdwritedp 2,0x01000000 写入 DP 寄存器 2 = 0x01000000 J-Link>swdreadap 0 读取 AP 寄存器 0 = 0x00000000 J-Link>swdreadap 0 读取 AP 寄存器 0 = 0x00000037 J-Link>swdreadap 1 读取AP寄存器1 = 0x00000037 J-Link>swdreadap 1 读取 AP 寄存器 1 = 0x00000000 J-Link>解锁 Kinetis 找到 ID 为 0x0BC11477 的 SWD-DP 解锁设备...确定 但我仍然无法连接 我尝试过连接 SEGGER Jlink 和 Onboard Pemicro - 结果是一样的。你能解释一下为什么会发生这种情况以及我该如何克服这个问题并避免将来再发生这种情况吗？谢谢。 回复：尝试批量擦除后无法连接到S32K118 谢谢你的回答。 但是 s32k1-RM rev14.1 中的“36.5.12.2.1 使用后门密钥访问取消保护 MCU”部分又如何呢？有帮助嗎？或者 Jlink 命令“解锁 Kinetis”尝试执行该操作？

Failed to connect to s32k118 after mass erase attempt Hello, NXP team and others. I am working with the S32k118 CSEc and tried the Example-1: Configure Part and Load Keys, provided by AN5401. I ran the project in DebugRAM config and could partition MCU and set the keys. I haven't set any protection to the keys but when next time I tried to Erase the whole chip I got the message that the protection bytes are set. When I proceed it keeps throwing the same message and eventually fails. Here is the output from JLink: Connecting ... - Connecting via USB to probe/ programmer device 0 - Probe/ Programmer firmware: J-Link Ultra V5 compiled Feb 19 2024 15:14:38 - Probe/ Programmer S/N: 505002010 - Device "S32K118 (ALLOW SECURITY)" selected. - Target interface speed: 4000 kHz (Fixed) - VTarget = 3.305V - InitTarget() start - SWD selected. Executing JTAG -> SWD switching sequence. - Device will be unsecured now. - Timeout while halting CPU. - InitTarget() end - Took 4.33s - Found SW-DP with ID 0x0BC11477 - DPIDR: 0x0BC11477 - CoreSight SoC-400 or earlier - Scanning AP map to find all available APs - AP[2]: Stopped AP scan as end of AP map has been reached - AP[0]: AHB-AP (IDR: 0x04770031) - AP[1]: JTAG-AP (IDR: 0x001C0020) - Iterating through AP map to find AHB-AP to use - AP[0]: Skipped. Could not read CPUID register - AP[1]: Skipped. Not an AHB-AP - Attach to CPU failed. Executing connect under reset. - DPIDR: 0x0BC11477 - CoreSight SoC-400 or earlier - Scanning AP map to find all available APs - AP[2]: Stopped AP scan as end of AP map has been reached - AP[0]: AHB-AP (IDR: 0x04770031) - AP[1]: JTAG-AP (IDR: 0x001C0020) - Iterating through AP map to find AHB-AP to use - AP[0]: Skipped. Could not read CPUID register - AP[1]: Skipped. Not an AHB-AP - Could not find core in Coresight setup I also tried the sequence as suggested here https://community.nxp.com/t5/S32K/Unbricking-S32K146/m-p/937227 : J-Link>r0 J-Link>swdwritedp 2,0x01000000 Write DP register 2 = 0x01000000 J-Link>swdreadap 0 Read AP register 0 = 0x00000000 J-Link>swdreadap 0 Read AP register 0 = 0x00000037 J-Link>swdreadap 1 Read AP register 1 = 0x00000037 J-Link>swdreadap 1 Read AP register 1 = 0x00000000 J-Link>unlock Kinetis Found SWD-DP with ID 0x0BC11477 Unlocking device...O.K. But then I still cannot connect I have tried connecting with SEGGER Jlink and Onboard Pemicro - the result is the same. Could you explain why it happened and how can I overcome this and avoid in the future? Thanks. Re: Failed to connect to s32k118 after mass erase attempt Hello @dmitry_buchynski, It would have to be implemented in the application SW first. https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K144-Verify-Backdoor-Access-Key-S32DS1-3/ta-p/1102820 Also, the partitioning along with the CSEc keys can be removed, and the CSEc example shows how. But again, such a code would have to be in the MCU already. Regards, Daniel Re: Failed to connect to s32k118 after mass erase attempt Thanks for the answer. But what about section '36.5.12.2.1 Un-securing the MCU using backdoor key access' from s32k1-RM rev14.1? Is it of any help? Or Jlink command "unlock Kinetis" tries to perform exactly that? Re: Failed to connect to s32k118 after mass erase attempt Hello @dmitry_buchynski, If the CSEc key space is allocated by the Program Partition command, the debugger cannot use Mass erase anymore. https://www.nxp.com/docs/en/application-note/AN12130.pdf Section 3.2.5.2 Mass erase and CSEc considerations. Then, the debugger can erase the MCU by sectors only. In this case, however, the MDM-AP Status[2] register shows that the MCU is secure (FSEC[SEC] = secure). That means the previous erasing by sectors/programming must have failed, leaving on the flash configuration field in this secure state. I'm afraid there is nothing we can do to recover it at this point. Regards, Daniel

大量消去を試みた後、s32k118に接続できませんでした こんにちは、NXPチームなど。 私はS32k118 CSEcを使用しており、AN5401が提供するExample-1:パーツキーとロードキーの設定を試しました。DebugRAM構成でプロジェクトを実行し、MCUをパーティション分割してキーを設定することができました。キーに保護を設定していませんが、次にチップ全体を消去しようとすると、保護バイトが設定されているというメッセージが表示されました。続行すると、同じメッセージがスローされ続け、最終的には失敗します。 JLinkからの出力は次のとおりです。 接続。。。 - プローブ/プログラマデバイス0にUSB経由で接続 - プローブ/プログラマーファームウェア:J-Link Ultra V5 コンパイル済み Feb 19, 2024 15:14:38 - プローブ/プログラマS / N:505002010 - デバイス「S32K118 (ALLOW SECURITY)」が選択されました。 - 目標インターフェース速度:4000kHz(固定) - VTarget = 3.305V - InitTarget() の開始 - SWD が選択されました。JTAG -> SWDスイッチングシーケンスを実行しています。 - これでデバイスのセキュリティが解除されます。 - CPU の停止中にタイムアウトします。 - InitTarget() 終了 - 4.33 秒かかりました - ID 0x0BC11477のSW-DPが見つかりました - DPIDR:0x0BC11477 - CoreSight SoC-400以前 - APマップをスキャンして、使用可能なすべてのAPを見つける - AP[2]: AP マップの末尾に達したため、AP スキャンを停止しました - AP[0]:AHB-AP(IDR:0x04770031) - AP[1]:JTAG-AP(IDR:1 0x001C0020) - APマップを反復処理して、使用するAHB-APを見つける - AP[0]:スキップしました。CPUID レジスタを読み取れませんでした - AP[1]: スキップしました。AHB-APではありません - CPU への接続に失敗しました。リセット状態で接続を実行しています。 - DPIDR:0x0BC11477 - CoreSight SoC-400以前 - APマップをスキャンして、使用可能なすべてのAPを見つける - AP[2]: AP マップの末尾に達したため、AP スキャンを停止しました - AP[0]:AHB-AP(IDR:0x04770031) - AP[1]:JTAG-AP(IDR:1 0x001C0020) - APマップを反復処理して、使用するAHB-APを見つける - AP[0]:スキップしました。CPUID レジスタを読み取れませんでした - AP[1]: スキップしました。AHB-APではありません - Coresightセットアップでコアが見つかりませんでした ここで提案されているように、シーケンスも試してみ ました https://community.nxp.com/t5/S32K/Unbricking-S32K146/m-p/937227: Jリンク>R0 J-Link>swdwritedp 2,0x01000000 DPレジスタの書き込み 2 = 0x01000000 J-リンク>swdreadap 0 APレジスタの読出し0 = 0x00000000 J-リンク>swdreadap 0 APレジスタの読出し0 = 0x00000037 J-リンク>swdreadap 1 APレジスタの読出し1 = 0x00000037 J-リンク>swdreadap 1 APレジスタの読出し1 = 0x00000000 J-Link>ロック解除 Kinetis ID が 0x0BC11477 の SWD-DP が見つかりました デバイスのロック解除...わかりました しかし、それでも私は接続できません SEGGER JlinkとOnboard Pemicroで接続してみましたが、結果は同じです。なぜそれが起こったのか、そしてどうすればこれを克服し、将来回避できるのか説明していただけますか?感謝。 Re:大量消去を試みた後、s32k118に接続できませんでした 答えをありがとう。 しかし、s32k1-RM rev14.1のセクション「36.5.12.2.1バックドアキーアクセスを使用したMCUの保護解除」はどうですか?何かお役に立てますか?それとも、Jlinkコマンドの「Kinetisのロックを解除」はまさにそれを実行しようとしますか?

Where we can find Chip configuration information Where can we find the chip configuration information for NXP S32K1xx Microcontrollers Re: Where we can find Chip configuration information Hi@gkunalupta PDB is an internal module of the chip, and it has no external pins connected to it directly. PDB needs to be connected to external pins through the TRGMUX module. In the previous answer, I have told you the location of S32K1xx_Trigger_Muxing.xlsx Re: Where we can find Chip configuration information And where can i find information for device chip configuration details  to know about PDB Pulse out pin Re: Where we can find Chip configuration information Hi@gkunalupta S32K1xx_Trigger_Muxing.xlsx can be found in S32K-RM's attachments. Re: Where we can find Chip configuration information I want to know where can i finds chip specific details, for trigger inputs details which are mentioned: I want to know about trigger inputs, for that on datasheet it is written that find information on chip configuration details. Where can i find that??? Re: Where we can find Chip configuration information Hi@gkunalupta Could you describe your problem in more detail? Do you want the datasheet for s32k1 or something else? Re: Where we can find Chip configuration information Also from where can i found information on which pin to use for pulse-out?

PDB Interrupt in S32K144 how to enable How to enable the interrupt in PDB module of S32K144 MCU via Autosar RTD of 2108 Re: PDB Interrupt in S32K144 how to enable Hi, Thank you so much for your interest in our products and for using our community. There is no PDB example with autosar mcal, but you could refer to the following community thread: https://community.nxp.com/t5/S32K/ADC-project-using-MCAL/td-p/1616331 Hope it helps you. Have a nice day! Re: PDB Interrupt in S32K144 how to enable Also, in Channel Configuration. I cant select channel Index value of 0 for anothe channel. So how i am supposed multiple channels via PDB for ADC?

NTAG 424 Tamper encryption Hi, need help with NTAG424 TT: enabling tamper function with key 0 (or 1,2,3,4 doesn't care) using SetConfiguration option 07 i get 9100 as response so seems everyting ok. But in the NDEF message the mirroring of TT is always in clear as the key remains at E as the default value. I tried with my Python app and with TagExplore, result is the same. Any hint? Mario Re: NTAG 424 Tamper encryption Im having the same problem! Can you help me? How did you solve it?? Re: NTAG 424 Tamper encryption Thanks Daniel, with several try and fix i managed to have the TTStatus encrypted in NDEF. Mario Re: NTAG 424 Tamper encryption Thanks Daniel, reading better the datasheet, TTStatuskey is not used to encrypt the tamper status in NDEF but as authentication to issue the GetTTStatus command. Unfortunately i dont' find how to encrypt TTStatus in NDEF: i red on AN12196 that is possible using the EncData but don't know how. Moreover fig. 3 and 4 at page 9 show the encryption of TTStatus OR Static data, i'd like to have both if possible Thanks, Mario Re: NTAG 424 Tamper encryption Hi  could you please let me know your detail steps, so I can reproduce your issue on my side with RFIDDiscover? Regards Daniel

一种消除电流控制细化的方法。 我想请教一下关于 S32K344 无传感器 FOC 的问题（见下面的示例代码）。 C:\NXP\MC_DevKits\MCSPTE1AK344\sw\MCSPTE1AK344_PMSM_FOC_2Sh_ll 尽管 MOSFET 的开关频率为 20 kHz，但电流控制似乎以 10 kHz 执行。 参照源代码，似乎函数 Bctu_FIFO1_WatermarkNotification() 以 10 kHz 执行（在示波器上观察到 PTC24）。 我希望以与开关频率相同的频率执行电流控制。我该如何修改它？

A method to eliminate current control thinning. I would like to ask for your guidance regarding the sensorless FOC of the S32K344 (see the sample code below). C:\NXP\MC_DevKits\MCSPTE1AK344\sw\MCSPTE1AK344_PMSM_FOC_2Sh_ll Despite the MOSFET switching frequency being 20 kHz, it seems that the current control is being executed at 10 kHz. Referring to the source code, it appears that the function Bctu_FIFO1_WatermarkNotification() is executed at 10 kHz (observed PTC24 on an oscilloscope). I would like to execute the current control at the same frequency as the switching frequency. How can I modify this? Re: A method to eliminate current control thinning. Hi, Thank you so much for your interest in our products and for using our community. You could refer to the MCTPTX1AK324, where the PWM frequency is 10KHz, and the FOC fast loop calculation frequency is 10KHz too. But now the execution frequency of function BCTU FIFO notification is 30KHz, due to there being three PMSM motors, that share the same interrupt routine (for more details, please refer to UG10052 and its SW example). Hope it helps you. Have a nice day!