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IPMSM 的免费试用版 这里有人有为IPMSM开发FOC并从零开始在TI C2000微控制器上实现的经验吗?我正在研究基于0d轴和MTPA控制的30W IPMSM电机控制方案。如果有经验或想和我合作的人,请私信我。我是在兼职做这件事。
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The configured baud rate does not match that of the PC When I configure the S32K311 microcontroller's serial port to a baud rate of 115200 for debugging with a PC, the data appears garbled;I had to change it to 230400 to enable normal communication. Additionally, when I set breakpoints, I cannot see the actual values, which makes debugging very difficult. I hope this can be resolved. I am using S32 Design Studio for S32 Platform 3.6.1 and RTD_R21-11_4.0.0. Re: 配置的波特率与PC端不一致 Hi @LJH 1 I don't see any obvious errors. Please use an oscilloscope or logic analyzer to capture the data transmission rate from the MCU; this should help pinpoint the issue. It might be a problem with the MCU's baud rate.
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我尝试在 FRDM-MCXN947 上运行 Zephyr HTTP 服务器(日本博客) スクリーンショット 2026-06-11 15.39.32.png 0. 这篇文章是关于什么的? 传统上,在使用嵌入式微控制器的网络功能时,首先要弄清楚“如何让它工作”。你需要找到目标微控制器供应商提供的SDK和示例代码,然后根据其API编写代码。由于每个微控制器的API都不同,每次想做类似的事情时,往往都得从头开始研究。网络功能涉及很多知识,例如初始化TCP协议栈和使用套接字API,我相信很多人都经历过还没来得及编写自己的应用程序就因为这些知识而感到力不从心的情况。 Zephyr OS 或许能解决这些问题。Zephyr 作为一款实时操作系统 (RTOS),提供了一套标准的 API,其主要优势在于,一旦掌握了使用方法,同一段代码就能在不同的开发板上运行。在众多可用的示例代码中,也包括我们将要讨论的HTTP 服务器示例,而且它的运行出乎意料地简单。 本文提供了在 NXP FRDM-MCXN947评估板上运行 HTTP 服务器示例的分步指南。示例运行后,您将能够通过 PC 的 Web 浏览器访问 FRDM-MCXN947,并使用页面上的按钮打开/关闭板上的 LED 灯。 目标: 通过浏览器访问 FRDM-MCXN947 上的 HTTP 服务器,并使用页面上的“LED 开”和“LED 关”按钮控制 LED。 在阅读本文之前 这假设 Zephyr 构建环境已经安装,并且您熟悉 west build 和 west flash 的基本操作。 如果您要从设置环境开始,可以参考 Zephyr 官方网站上的“入门指南”,或者观看指导视频,该视频可让您使用 MCUXpresso for VSC 轻松进行设置。 让我们开始吧!请参阅“MCUXpresso 与 VS Code 和 Zephyr OS”。 目录 0. 这篇文章是关于什么的? 1. 你需要准备什么 1.1 硬件 1.2 软件(必须安装) 2. 准备工作:激活环境变量 3. 配置 prj.conf(指定 IP 地址) 3.1 使用静态 IP 地址时 3.2 使用 DHCP(自动获取 IP 地址) 3.3 当PC与主板直接一对一连接时 4. 建造 4.1 对于静态 IP 地址 4.2 使用 DHCP 时 5. 写信给董事会 6. 运行检查 6.1 使用串口终端检查 IP 地址 6.2 通过浏览器访问 参考资料 1. 你需要准备什么 1.1 硬件 产品名称 备注 FRDM-MCXN947评估板 Zephyr 文档 USB 连接线(包含在上述 FRDM 板中) 这样就把主板上的 J17 连接器连接到了 PC。 LAN 线缆 这样就把主板上的以太网接口连接到了网络上。 1.2 软件(必须安装) 最新 Zephyr 开发环境(西部,Zephyr SDK)   2. 准备工作:激活环境变量 这次,我们将使用 macOS 终端屏幕上的命令进行操作。 打开终端后,首先执行以下两个命令。 首先,激活Python执行环境: source ~/zephyrproject/.venv/bin/activate 如果使用 MCUXpresso for VSC 安装 bin/activate 的位置与标准位置不同。 在 macOS 上,它位于 ~/.mcuxpressotools/.venv_3_14/ 中。 在 Windows 系统中,它位于 C:\Users\<ユーザ名>\.mcuxpressotools\.venv_3_12\Scripts 中。 *使用 Windows PowerShell 时,所使用的命令和文件名与 Linux 和 macOS 上的命令和文件名有所不同,因此请在继续操作之前参阅“入门指南”。 接下来,我们将设置构建 Zephyr 所需的环境变量。该命令允许您从任何文件夹构建 Zephyr: source ~/zephyrproject/zephyr/zephyr-env.sh 接下来,导航到示例文件夹: cd ~/zephyrproject/zephyr/samples/net/sockets/http_server   3. 配置 prj.conf(指定 IP 地址) 此文件夹中的 prj.conf 文件包含网络设置。请根据您的连接类型从以下三种方法中选择一种。 部分 连接类型 IP设置方法 第 3.1 节 通过路由器连接到局域网 手动配置静态IP地址。 第 3.2 节 通过路由器连接到局域网 通过 DHCP 自动获取资源(简单) 第 3.3 节 使用一根网线将电脑和主板直接连接起来。 为电脑和主板都设置静态IP地址。 参考:IP 地址:静态和 CHCP スクリーンショット 2026-06-11 16.22.14.png 3.1 使用静态 IP 地址(通过路由器) 此方法需要通过路由器连接到局域网,并为开发板分配一个固定的 IP 地址。请在文本编辑器中打开 prj.conf ,并根据您的网络环境修改以下两行代码。 更改前(默认): CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.0.2.1" CONFIG_NET_CONFIG_MY_IPV4_GW="192.0.2.2" 更改后(例如): CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.168.1.100" CONFIG_NET_CONFIG_MY_IPV4_GW="192.168.1.1" 设置项目 意义 CONFIG_NET_CONFIG_MY_IPV4_ADDR 要分配给电路板的 IP 地址(指定路由器子网内与其他设备不重叠的地址)。 CONFIG_NET_CONFIG_MY_IPV4_GW 网关(路由器)的 IP 地址。如果您仅从同一局域网内的电脑访问它,则并非绝对必要。 这里没有指定子网掩码,但在我测试的环境中,它被设置为 255.255.255.0 。 本文以“192.168.1.100”为例,请根据您的网络环境进行更改。 3.2 使用 DHCP(自动获取 IP 地址) 将 FRDM-MCXN947 连接到路由器(无线路由器)时,它可以自动从路由器获取 IP 地址。为此,请对 prj.conf 进行以下更改: CONFIG_NET_DHCPV4=y # 追加 CONFIG_NET_CONFIG_MY_IPV4_ADDR="" # 空文字列に変更 或者,您可以选择不编辑 prj.conf ,而是使用稍后描述的构建命令指定配置文件(参见第 4.2 节)。 3.3 当PC与主板直接一对一连接时 它还可以通过一根网线将PC和FRDM-MCXN947直接连接,无需路由器。在这种情况下,由于没有DHCP服务器,您需要在PC和开发板上手动设置静态IP地址。 关键点有以下两点: 在同一子网内,为PC和主板分配不同的IP地址。 由于它不会连接到互联网,因此不需要网关设置(或者任何值都可以接受)。 以下是一个设置示例: 主题 IP地址 子网掩码 PC(有线 LAN 适配器) 192.168.100.1 255.255.255.0 FRDM-MCXN947 192.168.100.2 255.255.255.0 (自动设置) 在电路板侧,按照 3.1 节中的方法编辑 prj.conf 。使用上表中的值时的示例设置: CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.168.100.2" CONFIG_NET_CONFIG_MY_IPV4_GW="192.168.100.1" PC端有线LAN适配器的IP地址需要在操作系统设置界面手动设置: macOS:前往“系统偏好设置”→“网络”→选择您的有线 LAN 适配器→将“IP 设置”更改为“手动”,然后输入地址 192.168.100.1 和子网掩码 255.255.255.0 Windows:转到“控制面板”→“网络和共享中心”→“更改适配器设置”→右键单击有线 LAN 适配器→“属性”→“Internet 协议版本 4 (TCP/IPv4)”→选择“使用下面的 IP 地址”并输入相同的信息。 如果启用了 DHCP ,则连接路由器的标准配置(3.2 节)会更简单,因为它不需要更改电脑的 IP 设置。直接连接适用于在没有路由器的环境中进行测试,或者当您不想更改电脑的网络设置时。 4. 建造 设置完成后,继续进行构建(编译和链接)。 工作目录为“~/zephyrproject/zephyr/samples/net/sockets/http_server”。 4.1 如果您拥有静态 IP 地址,或者如果您已将系统配置为在 prj.conf 中使用 DHCP 使用以下命令构建它。 west build -p auto -b frdm_mcxn947/mcxn947/cpu0 4.2 使用 DHCP 时 prj.conf 要在不编辑文件的情况下启用 DHCP,请运行以下命令: west build -p auto -b frdm_mcxn947/mcxn947/cpu0 -- -DEXTRA_CONF_FILE="overlay-dhcpv4.conf" -DEXTRA_CONF_FILE="overlay-dhcpv4.conf" 这将导致在构建过程中将启用 DHCP 的配置文件添加到 prj.conf 中。 在此配置中,如果未启用 DHCP 服务器,则默认设置 prj.conf 中写入的静态 IP 地址。   5. 写信给董事会 构建完成后,将其写入电路板。 使用 USB 电缆将板载J17(USB)连接器(位于以太网连接器左侧)连接到您的 PC,并将LAN 电缆连接到以太网连接器。 IMG_1415.JPG 运行以下命令: west flash 编写过程完成后,董事会将开始运作。   6. 运行检查 6.1 使用串口终端检查 IP 地址 打开串口终端(如 Tera Term、PuTTY 或 VS Code 的串口监视器),选择 FRDM-MCXN947 端口,并将波特率设置为115200 。 市面上有多种类型的串口终端,您可以根据自己的喜好选择使用哪一种。有关其安装和使用方法,请参阅相关文章。 uart:~$ 看到提示符后,输入以下命令: net iface 将显示网络设置列表。如果您指定了静态 IP 地址,则会显示该值;如果您使用了 DHCP,则会显示路由器分配的 IP 地址,请检查该地址。 スクリーンショット 2026-06-11 14.18.15.png 如果错过了启动日志, 可以通过按下开发板上的 SW1(RESET) 按钮重启开发板。重启后,您也可以立即查看输出中的 IP 地址。 スクリーンショット 2026-06-11 14.17.59.png 6.2 通过浏览器访问 在浏览器地址栏中输入已确认的 IP 地址并访问它(在本例中为 http://192.168.1.100 )。 如果工作正常,屏幕上将显示“ LED 开”和“ LED 关”按钮。按下这些按钮即可打开/关闭 FRDM-MCXN947 上的绿色 LED 指示灯。 スクリーンショット 2026-06-11 15.33.47.png IMG_1419.JPG 参考资料 【Zephyr ®系列】第一部分:最近流行的 Zephyr OS 究竟是一款怎样的操作系统?(日语博客) 【Zephyr ®系列】第二部分:首次构建与测试(日语博客) Zephyr 项目入门指南 让我们开始吧!使用 MCUXpresso 和 VS Code 构建 Zephyr OS(视频教程) 试用 UI:Zephyr OS 上的 GUI Guider 示例代码(日本博客) 变更历史记录: 2026-06-16:第一版 ========================= 我们目前无法回复此帖子“评论”部分留下的评论。 由此给您带来的不便,我们深表歉意。如有任何疑问,请参考“NXP 技术问题 - 如何联系我们(日语博客)”。 (如果您已经是恩智浦的分销商或与恩智浦有业务关系,您可以直接咨询您的代表。) 本指南将逐步讲解如何在 FRDM-MCXN947 上运行 Zephyr HTTP 服务器示例,并通过 PC 浏览器控制板上的 LED 灯亮灭。它支持通过路由器建立固定 IP/DHCP 连接,也支持使用单根网线将 PC 与开发板直接连接。如果已安装 Zephyr 构建环境,您只需几条命令即可完成从编辑配置文件到构建和烧录固件的整个过程,从而验证其运行情况。 (预计时间:15 分钟 *假设已安装 Zephyr 开发环境并熟悉 PC 网络) スクリーンショット 2026-06-11 15.39.32.png 以太网 介绍 MCX 日本博客
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Zephyr HTTP ServerをFRDM-MCXN947で動かしてみた (日本語ブログ) スクリーンショット 2026-06-11 15.39.32.png 0. この記事は? 組み込みマイコンでネットワーク機能を使うとき,従来は「まずどうやって動かすか」から調べる必要がありました.使いたいマイコンのベンダーが提供するSDKやサンプルコードを探し,そのAPIに合わせてコードを書く——マイコンが変わればAPIも変わるため,同じようなことをやるにも毎回一から調べ直すことになりがちです.ネットワーク機能ともなれば,TCPスタックの初期化やソケットAPIの使い方など覚えることも多く,「肝心の自分のアプリを書く前に力尽きる」という経験をした方も少なくないのではないでしょうか. Zephyr OSはそういった悩みへの一つの答えになりえます.ZephyrはRTOSとして標準的なAPIを提供しており,一度使い方を覚えれば異なるボードでも同じコードが動くのが大きな強みです.そして豊富に用意されているサンプルコードの中には,今回取り上げるHTTPサーバーのサンプルも含まれており、思った以上に簡単に動かせました. この記事では,そのHTTPサーバーサンプルをNXPのFRDM-MCXN947評価ボードで動作させる手順をステップ・バイ・ステップで解説します.サンプルを動かすと,PCのWebブラウザからFRDM-MCXN947にアクセスして,ページ上のボタンでボード上のLEDをON/OFFできるようになります. ゴール: ブラウザからFRDM-MCXN947上のHTTPサーバーにアクセスし,ページ上の「LED on」「LED off」ボタンでLEDを制御する. この記事を読む前に Zephyrのビルド環境がすでにインストール済みであり, west build や west flash の基本操作に慣れていることを前提としています. 環境の構築から始める場合は,Zephyrの公式サイトの「Getting Started Guide」や,MCUXpresso for VSCを使って簡単にセットアップが行えるガイド動画「 さぁはじめよう!MCUXpresso VS Code で Zephyr OS」を参照ください. 目次 0. この記事は? 1. 用意するもの 1.1 ハードウェア 1.2 ソフトウェア(インストール済みであること) 2. 事前準備:環境変数のアクティベート 3. prj.conf の設定(IPアドレスの指定) 3.1 固定IPアドレスを使う場合 3.2 DHCPを使う場合(IPアドレスを自動取得する) 3.3 PCとボードを直接1対1で接続する場合 4. ビルド 4.1 固定IPアドレスの場合 4.2 DHCPを使う場合 5. ボードへの書き込み 6. 動作確認 6.1 シリアルターミナルでIPアドレスを確認する 6.2 ブラウザからアクセスする 参考資料 1. 用意するもの 1.1 ハードウェア 品名 備考 FRDM-MCXN947評価ボード Zephyrドキュメント USBケーブル (上記FRDMボードに同梱) ボードのJ17コネクタとPCを接続するもの LANケーブル ボードのEthernetコネクタをネットワークに接続するもの 1.2 ソフトウェア(インストール済みであること) 最新のZephyr開発環境(west,Zephyr SDK)   2. 事前準備:環境変数のアクティベート 今回はmac OSのターミナル画面より,コマンドベースで作業を進めていきます. ターミナルを開いたら,最初に以下の2つのコマンドを実行しておきます. まず,Python実行環境をアクティベート(有効化)します: source ~/zephyrproject/.venv/bin/activate MCUXpresso for VSCでインストールした場合 bin/activate の場所が標準と異なります. macOSであれば ~/.mcuxpressotools/.venv_3_14/ にあります。 Windowsであれば C:\Users\<ユーザ名>\.mcuxpressotools\.venv_3_12\Scripts にありました. *Windows PowerShellを使用する場合には,Linux,macOS,とはコマンドや使用するファイル名が異なるので,「Getting Started Guide」を参照の上,進めてください. 続いて,Zephyrのビルドに必要な環境変数を設定します.このコマンドにより,任意のフォルダからZephyrのビルドが行えるようになります: source ~/zephyrproject/zephyr/zephyr-env.sh 次に,サンプルのフォルダへ移動します: cd ~/zephyrproject/zephyr/samples/net/sockets/http_server   3. prj.conf の設定(IPアドレスの指定) このフォルダ内の prj.conf ファイルには,ネットワーク設定が記述されています.接続形態に合わせて以下の3つの方法から選んでください. 節 接続形態 IP設定方法 3.1節 ルーター経由でLANに接続 固定IPアドレスを手動設定 3.2節 ルーター経由でLANに接続 DHCPで自動取得(手軽) 3.3節 PCとボードをLANケーブル1本で直結 PCとボード両方に固定IPを設定 参考: IPアドレス: 固定とCHCP スクリーンショット 2026-06-11 16.22.14.png 3.1 固定IPアドレスを使う場合(ルーター経由) ルーター経由でLANに接続し,ボードに固定のIPアドレスを割り当てる方法です. prj.conf をテキストエディタで開き,以下の2行を自分のネットワーク環境に合わせて書き換えます. 変更前(デフォルト): CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.0.2.1" CONFIG_NET_CONFIG_MY_IPV4_GW="192.0.2.2" 変更後(例): CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.168.1.100" CONFIG_NET_CONFIG_MY_IPV4_GW="192.168.1.1" 設定項目 意味 CONFIG_NET_CONFIG_MY_IPV4_ADDR ボードに割り当てるIPアドレス(ルーターのサブネット内で他の機器と重複しないアドレスを指定) CONFIG_NET_CONFIG_MY_IPV4_GW ゲートウェイ(ルーター)のIPアドレス.同一LAN内のPCからアクセスするだけであれば必ずしも必要ではありません サブネットマスクはここでは指定しませんが,試した環境では 255.255.255.0 が設定されました. この記事では例として「192.168.1.100」を使います.お使いのネットワーク環境に合わせて変更してください. 3.2 DHCPを使う場合(IPアドレスを自動取得する) FRDM-MCXN947をルータ(ワイヤレス・ルータ)に接続する場合,ルータからIPアドレスを自動取得できます.これには prj.conf に次の変更を加えます: CONFIG_NET_DHCPV4=y # 追加 CONFIG_NET_CONFIG_MY_IPV4_ADDR="" # 空文字列に変更 あるいは prj.conf を編集せず,後述のビルドコマンドで設定ファイルを追加指定する方法もあります(4.2節参照). 3.3 PCとボードを直接1対1で接続する場合 ルーターを介さず,PCとFRDM-MCXN947をLANケーブル1本で直接つなぐ構成でも動作させることができます.この場合はDHCPサーバーがいないため,PCとボードの両方に固定IPアドレスを手動で設定します. ポイントは次の2点です: PCとボードに,同じサブネット内の異なるIPアドレスを割り当てる インターネットには接続しないため,ゲートウェイの設定は不要(あるいは任意の値でかまわない) 設定例を示します: 対象 IPアドレス サブネットマスク PC(有線LANアダプタ) 192.168.100.1 255.255.255.0 FRDM-MCXN947 192.168.100.2 255.255.255.0 (自動設定) ボード側は3.1節と同じ要領で prj.conf を編集します.上の表の値を使う場合の設定例: CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.168.100.2" CONFIG_NET_CONFIG_MY_IPV4_GW="192.168.100.1" PC側の有線LANアダプタのIPアドレスは,OSの設定画面から手動で設定します: macOS:「システム設定」→「ネットワーク」→ 有線LANアダプタを選択 →「IPの設定」を「手入力」に変更し,アドレス 192.168.100.1 ,サブネットマスク 255.255.255.0 を入力 Windows:「コントロールパネル」→「ネットワークと共有センター」→「アダプターの設定の変更」→ 有線LANアダプタを右クリック→「プロパティ」→「インターネットプロトコルバージョン4 (TCP/IPv4)」→「次のIPアドレスを使う」を選択し,同様に入力 DHCPが使える環境であれば ルーターに接続する通常の構成(3.2節)の方が,PCのIP設定変更が不要で手軽です.直接接続は,ルーターがない場所での動作確認や,PCのネットワーク設定を変えたくない場面で役立ちます. 4. ビルド 設定が完了したら,ビルド(コンパイルとリンク)を行います. 作業ディレクトリは「~/zephyrproject/zephyr/samples/net/sockets/http_server」です. 4.1 固定IPアドレスの場合,またはDHCPを使う設定を prj.conf で行った場合 つぎのコマンドでビルドします. west build -p auto -b frdm_mcxn947/mcxn947/cpu0 4.2 DHCPを使う場合 prj.conf を編集せずにDHCPを有効にするには,次のコマンドを実行します: west build -p auto -b frdm_mcxn947/mcxn947/cpu0 -- -DEXTRA_CONF_FILE="overlay-dhcpv4.conf" -DEXTRA_CONF_FILE="overlay-dhcpv4.conf" により,DHCPを有効にする設定ファイルが prj.conf に追加された形でビルドされます. この設定ではDHCPサーバが有効でない場合, prj.conf に書かれた固定IPがデフォルトで設定されます.   5. ボードへの書き込み ビルドが完了したら,ボードに書き込みます. ボードのJ17(USB)コネクタ(Ehthernetコネクタに向かって左側)をUSBケーブルでPCに接続し,EthernetコネクタにはLANケーブルを接続しておきます. IMG_1415.JPG 次のコマンドを実行します: west flash 書き込みが完了すると,ボードが動作を開始します.   6. 動作確認 6.1 シリアルターミナルでIPアドレスを確認する シリアルターミナル(Tera Term,PuTTY,VS Code の Serial Monitor など)を開き,FRDM-MCXN947のポートを選択してボーレートを115200に設定します. シリアルターミナルにはいくつもの種類があり,好きなものが使えます.これらのインストールと使い方については別記事を参照ください. uart:~$ というプロンプトが表示されたら,次のコマンドを入力します: net iface ネットワーク設定の一覧が表示されます.固定IPを指定した場合はその値が,DHCPを使った場合はルーターから割り振られたIPアドレスが表示されるので,そのアドレスを確認してください. スクリーンショット 2026-06-11 14.18.15.png 起動時のログを見逃した場合 ボード上のSW1(RESET)ボタンを押すとボードが再起動します.再起動直後の出力でもIPアドレスを確認できます. スクリーンショット 2026-06-11 14.17.59.png 6.2 ブラウザからアクセスする 確認したIPアドレスをブラウザのアドレスバーに入力してアクセスします(今回の例では http://192.168.1.100 ). 正しく動作していれば,「LED on」「LED off」のボタンを含むページが表示されます.これらのボタンを押すと,FRDM-MCXN947の緑色のLEDがON/OFFします. スクリーンショット 2026-06-11 15.33.47.png IMG_1419.JPG 参考資料 [Zephyr® シリーズ] 第1回 最近流行りのZephyr OSってどんなOS?(日本語ブログ) [Zephyr® シリーズ] 第2回 はじめてのビルドと実機動作(日本語ブログ) Zephyr Project Getting Started Guide さぁはじめよう!MCUXpresso VS Code で Zephyr OS (ガイド動画) Zephyr OSでUI: GUI Guiderサンプルコードを実行してみる (日本語ブログ) 変更履歴: 2026-06-16:初版 ========================= 本投稿の「Comment」欄にコメントをいただいても,現在返信に対応しておりません. お手数をおかけしますが,お問い合わせの際には「NXPへの技術質問 - 問い合わせ方法 (日本語ブログ)」をご参照ください. (既に弊社NXP代理店,もしくはNXPとお付き合いのある方は,直接担当者へご質問いただいてもかまいません.) ZephyrのHTTPサーバーサンプルをFRDM-MCXN947で動かし,PCのブラウザからボード上のLEDをON/OFFする手順をステップ・バイ・ステップで解説します.ルーター経由での固定IP/DHCP接続に加え,PCとボードをLANケーブル1本で直結する構成にも対応しています.Zephyrのビルド環境がインストール済みであれば,設定ファイルの編集からビルド・書き込みまで,コマンド数本で動作を確認できます. (作業時間:15分 *Zephyr開発環境インストール済,PCネットワークに慣れていれば) スクリーンショット 2026-06-11 15.39.32.png Ethernet introduction MCX 日本語ブログ
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I tried running Zephyr HTTP Server on FRDM-MCXN947 (Japanese blog) スクリーンショット 2026-06-11 15.39.32.png 0. What is this article about? When using network functionality with embedded microcontrollers, traditionally, you had to start by figuring out "how to make it work." You'd have to find the SDK and sample code provided by the vendor of the microcontroller you wanted to use, and then write code according to its API. Since the API changes with each different microcontroller, you often end up having to research everything from scratch every time you want to do something similar. With network functionality, there's a lot to learn, such as initializing the TCP stack and using the socket API, and I'm sure many people have experienced running out of steam before they could even write their own application. Zephyr OS can be one solution to these problems. Zephyr provides a standard API as an RTOS, and a major advantage is that once you learn how to use it, the same code will run on different boards. Among the abundant sample code available, there is also the HTTP server sample that we will be discussing, and it was surprisingly easy to get running. This article provides a step-by-step guide on how to run the HTTP server sample on the NXP FRDM-MCXN947 evaluation board. Once the sample is running, you will be able to access the FRDM-MCXN947 from your PC's web browser and turn the LEDs on the board ON/OFF using buttons on the page. goal: Access the HTTP server on the FRDM-MCXN947 from your browser and control the LEDs using the "LED on" and "LED off" buttons on the page. Before reading this article This assumes that the Zephyr build environment is already installed and that you are familiar with the basic operations of west build and west flash . If you're starting from setting up the environment, you can refer to the " Getting Started Guide " on the Zephyr official website, or the guide video that allows you to easily set it up using MCUXpresso for VSC. Let's get started! See "MCUXpresso with VS Code and Zephyr OS". table of contents 0. What is this article about? 1. What you will need 1.1 Hardware 1.2 Software (must be installed) 2. Preparation: Activate environment variables 3. Configuring prj.conf (specifying the IP address) 3.1 When using a static IP address 3.2 Using DHCP (Automatically obtaining an IP address) 3.3 When connecting the PC and the board directly on a one-to-one basis 4. Build 4.1 In the case of a static IP address 4.2 When using DHCP 5. Writing to the board 6. Operation check 6.1 Check the IP address using the serial terminal 6.2 Accessing from a browser Reference materials 1. What you will need 1.1 Hardware Product name remarks FRDM-MCXN947 Evaluation Board Zephyr Documentation USB cable (included with the FRDM board mentioned above) This connects the board's J17 connector to the PC. LAN cable This connects the board's Ethernet connector to the network. 1.2 Software (must be installed) Latest Zephyr development environment (west, Zephyr SDK)   2. Preparation: Activate environment variables This time, we'll proceed using commands from the macOS Terminal screen. Once you open the terminal, first execute the following two commands. First, activate the Python execution environment: source ~/zephyrproject/.venv/bin/activate If installed using MCUXpresso for VSC The location of bin/activate is different from the standard. On macOS, it's located in ~/.mcuxpressotools/.venv_3_14/ . On Windows, it was located in C:\Users\<ユーザ名>\.mcuxpressotools\.venv_3_12\Scripts . *When using Windows PowerShell, the commands and filenames used will differ from those on Linux and macOS, so please refer to the " Getting Started Guide " before proceeding. Next, we'll set the environment variables required to build Zephyr. This command will allow you to build Zephyr from any folder: source ~/zephyrproject/zephyr/zephyr-env.sh Next, navigate to the sample folder: cd ~/zephyrproject/zephyr/samples/net/sockets/http_server   3. Configuring prj.conf (specifying the IP address) The prj.conf file in this folder contains network settings. Please choose from the following three methods according to your connection type. section Connection type IP setting method Section 3.1 Connect to the LAN via a router Manually configure a static IP address. Section 3.2 Connect to the LAN via a router Automatic acquisition via DHCP (easy) Section 3.3 Connect the PC and the board directly with a single LAN cable. Set a static IP address for both the PC and the board. Reference: IP Address: Static and CHCP スクリーンショット 2026-06-11 16.22.14.png 3.1 Using a static IP address (via a router) This method involves connecting to the LAN via a router and assigning a fixed IP address to the board. Open prj.conf in a text editor and rewrite the following two lines to match your network environment. Before change (default): CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.0.2.1" CONFIG_NET_CONFIG_MY_IPV4_GW="192.0.2.2" After the change (example): CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.168.1.100" CONFIG_NET_CONFIG_MY_IPV4_GW="192.168.1.1" Setting items meaning CONFIG_NET_CONFIG_MY_IPV4_ADDR The IP address to assign to the board (specify an address within the router's subnet that does not overlap with other devices). CONFIG_NET_CONFIG_MY_IPV4_GW The IP address of the gateway (router). This is not strictly necessary if you are only accessing it from a PC within the same LAN. The subnet mask is not specified here, but in the environment I tested, it was set to 255.255.255.0 . This article uses "192.168.1.100" as an example. Please change it to match your network environment. 3.2 Using DHCP (Automatically obtaining an IP address) When connecting the FRDM-MCXN947 to a router (wireless router), it can automatically obtain an IP address from the router. To do this, make the following changes to prj.conf : CONFIG_NET_DHCPV4=y # 追加 CONFIG_NET_CONFIG_MY_IPV4_ADDR="" # 空文字列に変更 Alternatively, you can choose not to edit prj.conf and instead specify the configuration file using the build command described later (see Section 4.2 ). 3.3 When connecting the PC and the board directly on a one-to-one basis It can also be operated by directly connecting the PC and the FRDM-MCXN947 with a single LAN cable, without using a router. In this case, since there is no DHCP server, you will need to manually set a static IP address on both the PC and the board. The key points are the following two: Assign different IP addresses to the PC and the board within the same subnet . Since it will not connect to the internet, gateway settings are not required (or any value is acceptable). Here is an example of the settings: subject IP address Subnet mask PC (wired LAN adapter) 192.168.100.1 255.255.255.0 FRDM-MCXN947 192.168.100.2 255.255.255.0 (Automatic setting) On the board side, edit prj.conf in the same way as in Section 3.1. Example settings when using the values from the table above: CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.168.100.2" CONFIG_NET_CONFIG_MY_IPV4_GW="192.168.100.1" The IP address of the wired LAN adapter on the PC side is set manually from the OS settings screen: macOS: Go to "System Preferences" → "Network" → Select your wired LAN adapter → Change "IP Settings" to "Manual" and enter the address 192.168.100.1 and subnet mask 255.255.255.0 Windows: Go to "Control Panel" → "Network and Sharing Center" → "Change adapter settings" → Right-click on the wired LAN adapter → "Properties" → "Internet Protocol Version 4 (TCP/IPv4)" → Select "Use the following IP address" and enter the same information. If DHCP is available , the standard configuration of connecting to a router (Section 3.2) is easier as it does not require changing the PC's IP settings. Direct connection is useful for testing in locations without a router or when you don't want to change the PC's network settings. 4. Build Once the setup is complete, proceed with the build (compilation and linking). The working directory is "~/zephyrproject/zephyr/samples/net/sockets/http_server". 4.1 If you have a static IP address, or if you have configured the system to use DHCP in prj.conf Build it with the following command. west build -p auto -b frdm_mcxn947/mcxn947/cpu0 4.2 When using DHCP prj.conf To enable DHCP without editing the file, run the following command: west build -p auto -b frdm_mcxn947/mcxn947/cpu0 -- -DEXTRA_CONF_FILE="overlay-dhcpv4.conf" -DEXTRA_CONF_FILE="overlay-dhcpv4.conf" This will result in the configuration file for enabling DHCP being added to prj.conf during the build process. In this configuration, if the DHCP server is not enabled, the static IP address written in prj.conf will be set by default.   5. Writing to the board Once the build is complete, write it to the board. Connect the board's J17 (USB) connector (to the left of the Ethernet connector) to your PC using a USB cable, and connect a LAN cable to the Ethernet connector . IMG_1415.JPG Run the following command: west flash Once the writing process is complete, the board will start operating.   6. Operation check 6.1 Check the IP address using the serial terminal Open a serial terminal (such as Tera Term, PuTTY, or VS Code's Serial Monitor), select the FRDM-MCXN947 port, and set the baud rate to 115200 . There are several types of serial terminals available, and you can use whichever you prefer. Please refer to separate articles for information on their installation and usage. uart:~$ When you see the prompt, enter the following command: net iface A list of network settings will be displayed. If you specified a static IP address, that value will be displayed; if you used DHCP, the IP address assigned by the router will be displayed, so please check that address. スクリーンショット 2026-06-11 14.18.15.png If you miss the startup log, you can restart the board by pressing the SW1 (RESET) button on the board. You can also check the IP address in the output immediately after restarting. スクリーンショット 2026-06-11 14.17.59.png 6.2 Accessing from a browser Enter the confirmed IP address into your browser's address bar and access it (in this example, http://192.168.1.100 ). If it is working correctly, a page containing " LED on " and " LED off " buttons will be displayed. Pressing these buttons will turn the green LED on/off on the FRDM-MCXN947. スクリーンショット 2026-06-11 15.33.47.png IMG_1419.JPG Reference materials [Zephyr ® Series] Part 1: What kind of OS is the recently popular Zephyr OS? (Japanese Blog) [Zephyr ® Series] Part 2: First Build and Testing (Japanese Blog) Zephyr Project Getting Started Guide Let's get started! Zephyr OS with MCUXpresso and VS Code (Guided Video) Trying out UI: GUI Guider sample code on Zephyr OS (Japanese blog) Change history: 2026-06-16: First Edition ========================= We are currently unable to respond to comments left in the "Comment" section of this post. We apologize for the inconvenience, but please refer to "Technical Questions to NXP - How to Contact Us (Japanese Blog)" when making an inquiry. (If you are already an NXP distributor or have a business relationship with NXP, you may ask your representative directly.) This guide provides a step-by-step explanation of how to run the Zephyr HTTP server sample on the FRDM-MCXN947 and turn the LEDs on the board ON/OFF from a PC browser. It supports both fixed IP/DHCP connections via a router and direct connections between the PC and the board using a single LAN cable. If the Zephyr build environment is already installed, you can verify operation from editing the configuration file to building and flashing with just a few commands. (Estimated time: 15 minutes *Assuming Zephyr development environment is installed and you are familiar with PC networking) スクリーンショット 2026-06-11 15.39.32.png Ethernet Introduction MCX Japanese Blog
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Exporting YOLO Models for NXP i.MX Platforms In this post, we will review the YOLO model export process for three popular NXP families: i.MX8MP, i.MX93, and i.MX95. These processors are increasingly used in edge AI applications such as smart vision, industrial automation, robotics, and intelligent HMI systems. Although they all support machine learning deployment, the export path, supported runtimes, and hardware acceleration options may differ depending on the device. The purpose of this guide is to provide a clearer starting point for developers who want to take a trained YOLO model and prepare it for execution on these i.MX platforms. Whether your workflow targets CPU, NPU. YOLO Model Export Workflow for i.MX Processors 1) Install Ultralytics Install or upgrade the Ultralytics package from PyPI: pip install -U ultralytics 2) Export the YOLO Model (TFLite INT8) Export your trained YOLO model to TensorFlow Lite (TFLite) format with INT8 quantization: yolo export model= .pt format=saved_model quantize=8 Example: yolo export model=yolov8n.pt format=saved_model quantize=8 Notes: The model must be exported in TFLite format and fully INT8 quantized. After the export process, a directory named " _saved_model" Inside this directory, you should use the following file as the input for the converter called " _full_integer_quant.tflite "  This is the fully quantized INT8 model required for NPU deployment. Using any other file from the export directory may result in compatibility issues or prevent proper NPU acceleration. After obtaining the *_full_integer_quant.tflite file, you can proceed with the needed conversion workflow to generate the final model optimized for execution on the NPU. For additional valid export options, please refer to the official Ultralytics documentation: https://docs.ultralytics.com/modes/export/ At this stage: The model can run on CPU for: i.MX8MP i.MX93 i.MX95 On i.MX8MP, this TFLite model can also be deployed to the NPU using the appropriate delegate. 3) i.MX93  Compile for Ethos-U NPU (Vela) For i.MX93, an additional compilation step is required to use the Ethos-U NPU. Run the Vela compiler to convert the TFLite model into an optimized format: vela .tflite --output-dir Notes: This step generates a model optimized for the Ethos-U NPU. The resulting output files are required for deployment using the NPU delegate on the i.MX93 platform. Please ensure that the model complies with the Ethos-U operator constraints, as only supported operations can be accelerated by the NPU. This command can be executed directly on the i.MX93 target, or alternatively by using the eIQ Toolkit (please refer to the eIQ Converter documentation for more details). 4)  i.MX95 Convert Model Using Neutron SDK For i.MX95, the model must be converted using the Neutron Converter, depending on the BSP version installed on your board. .\neutron-converter.exe ` --input " .tflite" ` --target imx95 ` --output " .tflite" ` --optimization-level OOpt Notes: The Neutron toolchain prepares the model for i.MX95 NPU acceleration. Supported formats and flags may vary depending on the Neutron SDK version. Always verify compatibility with your BSP release. You can check the compatibility details of the Neutron SDK in the "docs" folder of your downloaded Neutron SDK package. 5) Benchmark the Model After exporting and converting the model, you can validate performance using benchmarking tools. Typical options include: TFLite benchmark tool (CPU / delegate): benchmark_model --graph= .tflite --num_threads=X 6) Results iMX8MP CPU root@imx8mpevk:~# /usr/bin/tensorflow-lite-2.19.0/examples/benchmark_model --graph=yolov8n_full_integer_quant.tflite --mum_threads=4 INFO: STARTING! WARN: Unconsumed cmdline flags: --mum_threads=4 INFO: Log parameter values verbosely: [0] INFO: Graph: [yolov8n_full_integer_quant.tflite] INFO: Signature to run: [] INFO: Loaded model yolov8n_full_integer_quant.tflite INFO: Created TensorFlow Lite XNNPACK delegate for CPU. INFO: The input model file size (MB): 3.42652 INFO: Initialized session in 86.368ms. INFO: Running benchmark for at least 1 iterations and at least 0.5 seconds but terminate if exceeding 150 seconds. INFO: count=1 curr=1029584 p5=1029584 median=1029584 p95=1029584 INFO: Running benchmark for at least 50 iterations and at least 1 seconds but terminate if exceeding 150 seconds. INFO: count=50 first=986237 curr=985536 min=983921 max=993982 avg=985863 std=1497 p5=984152 median=985947 p95=986715 INFO: Inference timings in us: Init: 86368, First inference: 1029584, Warmup (avg): 1.02958e+06, Inference (avg): 985863 INFO: Note: as the benchmark tool itself affects memory footprint, the following is only APPROXIMATE to the actual memory footprint of the model at runtime. Take the information at your discretion. INFO: Memory footprint delta from the start of the tool (MB): init=11.207 overall=40.918 root@imx8mpevk:~# NPU root@imx8mpevk:~# /usr/bin/tensorflow-lite-2.19.0/examples/benchmark_model --graph=yolov8n_full_integer_quant.tflite --num_threads=4 --external_delegate_path=/usr/lib/libvx_delegate.so INFO: STARTING! INFO: Log parameter values verbosely: [0] INFO: Num threads: [4] INFO: Graph: [yolov8n_full_integer_quant.tflite] INFO: Signature to run: [] INFO: #threads used for CPU inference: [4] INFO: #threads used for CPU inference: [4] INFO: External delegate path: [/usr/lib/libvx_delegate.so] INFO: Loaded model yolov8n_full_integer_quant.tflite INFO: Vx delegate: allowed_cache_mode set to 0. INFO: Vx delegate: device num set to 0. INFO: Vx delegate: allowed_builtin_code set to 0. INFO: Vx delegate: error_during_init set to 0. INFO: Vx delegate: error_during_prepare set to 0. INFO: Vx delegate: error_during_invoke set to 0. INFO: EXTERNAL delegate created. INFO: Explicitly applied EXTERNAL delegate, and the model graph will be completely executed by the delegate. INFO: The input model file size (MB): 3.42652 INFO: Initialized session in 39.515ms. INFO: Running benchmark for at least 1 iterations and at least 0.5 seconds but terminate if exceeding 150 seconds. INFO: count=1 curr=16831746 p5=16831746 median=16831746 p95=16831746 INFO: Running benchmark for at least 50 iterations and at least 1 seconds but terminate if exceeding 150 seconds. INFO: count=50 first=67167 curr=67190 min=67048 max=67366 avg=67187 std=64 p5=67094 median=67184 p95=67295 INFO: Inference timings in us: Init: 39515, First inference: 16831746, Warmup (avg): 1.68317e+07, Inference (avg): 67187 INFO: Note: as the benchmark tool itself affects memory footprint, the following is only APPROXIMATE to the actual memory footprint of the model at runtime. Take the information at your discretion. INFO: Memory footprint delta from the start of the tool (MB): init=9.47266 overall=224.398 root@imx8mpevk:~# iMX93 CPU root@imx93evk:~# /usr/bin/tensorflow-lite-2.19.0/examples/benchmark_model --graph=yolov8n_full_integer_quant.tflite --num_threads=2 INFO: STARTING! INFO: Log parameter values verbosely: [0] INFO: Num threads: [2] INFO: Graph: [yolov8n_full_integer_quant.tflite] INFO: Signature to run: [] INFO: #threads used for CPU inference: [2] INFO: #threads used for CPU inference: [2] INFO: Loaded model yolov8n_full_integer_quant.tflite INFO: Created TensorFlow Lite XNNPACK delegate for CPU. INFO: The input model file size (MB): 3.42652 INFO: Initialized session in 57.963ms. INFO: Running benchmark for at least 1 iterations and at least 0.5 seconds but terminate if exceeding 150 seconds. INFO: count=3 first=247896 curr=198973 min=198973 max=247896 avg=215381 std=22991 p5=198973 median=199275 p95=247896 INFO: Running benchmark for at least 50 iterations and at least 1 seconds but terminate if exceeding 150 seconds. INFO: count=50 first=199533 curr=198880 min=197719 max=205262 avg=199032 std=1005 p5=198344 median=198886 p95=199961 INFO: Inference timings in us: Init: 57963, First inference: 247896, Warmup (avg): 215381, Inference (avg): 199032 INFO: Note: as the benchmark tool itself affects memory footprint, the following is only APPROXIMATE to the actual memory footprint of the model at runtime. Take the information at your discretion. INFO: Memory footprint delta from the start of the tool (MB): init=11.2539 overall=40.9961 root@imx93evk:~# NPU root@imx93evk:~# /usr/bin/tensorflow-lite-2.19.0/examples/benchmark_model --graph=yolov8n_full_integer_quant_vela.tflite --num_threads=2 --external_delegate_path=/usr/lib/libethosu_delegate.so INFO: STARTING! INFO: Log parameter values verbosely: [0] INFO: Num threads: [2] INFO: Graph: [yolov8n_full_integer_quant_vela.tflite] INFO: Signature to run: [] INFO: #threads used for CPU inference: [2] INFO: #threads used for CPU inference: [2] INFO: External delegate path: [/usr/lib/libethosu_delegate.so] INFO: Loaded model yolov8n_full_integer_quant_vela.tflite INFO: Ethosu delegate: device_name set to /dev/ethosu0. INFO: Ethosu delegate: cache_file_path set to . INFO: Ethosu delegate: timeout set to 60000000000. INFO: Ethosu delegate: enable_cycle_counter set to 0. INFO: Ethosu delegate: enable_profiling set to 0. INFO: Ethosu delegate: profiling_buffer_size set to 2048. INFO: Ethosu delegate: pmu_event0 set to 0. INFO: Ethosu delegate: pmu_event1 set to 0. INFO: Ethosu delegate: pmu_event2 set to 0. INFO: Ethosu delegate: pmu_event3 set to 0. INFO: EXTERNAL delegate created. INFO: EthosuDelegate: 8 nodes delegated out of 15 nodes with 8 partitions. INFO: Explicitly applied EXTERNAL delegate, and the model graph will be partially executed by the delegate w/ 8 delegate kernels. INFO: Created TensorFlow Lite XNNPACK delegate for CPU. INFO: The input model file size (MB): 2.9511 INFO: Initialized session in 638.148ms. INFO: Running benchmark for at least 1 iterations and at least 0.5 seconds but terminate if exceeding 150 seconds. INFO: count=7 first=87215 curr=81264 min=81079 max=87215 avg=82056.4 std=2107 p5=81079 median=81187 p95=87215 INFO: Running benchmark for at least 50 iterations and at least 1 seconds but terminate if exceeding 150 seconds. INFO: count=50 first=81497 curr=81232 min=80887 max=81783 avg=81153.1 std=178 p5=80921 median=81148 p95=81497 INFO: Inference timings in us: Init: 638148, First inference: 87215, Warmup (avg): 82056.4, Inference (avg): 81153.1 INFO: Note: as the benchmark tool itself affects memory footprint, the following is only APPROXIMATE to the actual memory footprint of the model at runtime. Take the information at your discretion. INFO: Memory footprint delta from the start of the tool (MB): init=7.36328 overall=8.73828 root@imx93evk:~# iMX95 CPU root@imx95evk:~# /usr/bin/tensorflow-lite-2.19.0/examples/benchmark_model --graph=yolov8n_full_integer_quant.tflite --num_threads=6 INFO: STARTING! INFO: Log parameter values verbosely: [0] INFO: Num threads: [6] INFO: Graph: [yolov8n_full_integer_quant.tflite] INFO: Signature to run: [] INFO: #threads used for CPU inference: [6] INFO: #threads used for CPU inference: [6] INFO: Loaded model yolov8n_full_integer_quant.tflite INFO: Created TensorFlow Lite XNNPACK delegate for CPU. INFO: The input model file size (MB): 3.42652 INFO: Initialized session in 35.268ms. INFO: Running benchmark for at least 1 iterations and at least 0.5 seconds but terminate if exceeding 150 seconds. INFO: count=7 first=115073 curr=74468 min=74170 max=115073 avg=80310.4 std=14192 p5=74170 median=74581 p95=115073 INFO: Running benchmark for at least 50 iterations and at least 1 seconds but terminate if exceeding 150 seconds. INFO: count=50 first=74143 curr=74135 min=73657 max=76392 avg=74346.9 std=447 p5=73829 median=74307 p95=75020 INFO: Inference timings in us: Init: 35268, First inference: 115073, Warmup (avg): 80310.4, Inference (avg): 74346.9 INFO: Note: as the benchmark tool itself affects memory footprint, the following is only APPROXIMATE to the actual memory footprint of the model at runtime. Take the information at your discretion. INFO: Memory footprint delta from the start of the tool (MB): init=11.5195 overall=40.8867 root@imx95evk:~# NPU: root@imx95evk:~# /usr/bin/tensorflow-lite-2.19.0/examples/benchmark_model --graph=yolov8n_full_integer_quant_neutron.tflite --num_threads=6 --external_delegate_path=/usr/lib/libneutron_delegate.so INFO: STARTING! INFO: Log parameter values verbosely: [0] INFO: Num threads: [6] INFO: Graph: [yolov8n_full_integer_quant_neutron.tflite] INFO: Signature to run: [] INFO: #threads used for CPU inference: [6] INFO: #threads used for CPU inference: [6] INFO: External delegate path: [/usr/lib/libneutron_delegate.so] INFO: Loaded model yolov8n_full_integer_quant_neutron.tflite INFO: EXTERNAL delegate created. INFO: NeutronDelegate delegate: 1 nodes delegated out of 33 nodes with 1 partitions. INFO: Neutron delegate version: v1.0.0-7399a58e, zerocp enabled. INFO: Explicitly applied EXTERNAL delegate, and the model graph will be partially executed by the delegate w/ 1 delegate kernels. INFO: Created TensorFlow Lite XNNPACK delegate for CPU. INFO: The input model file size (MB): 3.20989 INFO: Initialized session in 12.756ms. INFO: Running benchmark for at least 1 iterations and at least 0.5 seconds but terminate if exceeding 150 seconds. INFO: count=17 first=31509 curr=27588 min=27555 max=31509 avg=29101.2 std=1166 p5=27555 median=29071 p95=31509 INFO: Running benchmark for at least 50 iterations and at least 1 seconds but terminate if exceeding 150 seconds. INFO: count=50 first=28068 curr=29081 min=26573 max=31340 avg=29104.1 std=1204 p5=27306 median=29141 p95=31171 INFO: Inference timings in us: Init: 12756, First inference: 31509, Warmup (avg): 29101.2, Inference (avg): 29104.1 INFO: Note: as the benchmark tool itself affects memory footprint, the following is only APPROXIMATE to the actual memory footprint of the model at runtime. Take the information at your discretion. INFO: Memory footprint delta from the start of the tool (MB): init=6.98438 overall=12.2344 root@imx95evk:~ Disclaimer: Ultralytics YOLO models have not been officially validated/supported by NXP. Therefore, compatibility with i.MX processors and their corresponding NPUs cannot be guaranteed. Some models or configurations may not work as expected depending on operator support and hardware limitations.
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S32K3 上的 LDREX/STREX/CLREX——似乎在 SRAM 中也能正常工作? 我之前问过一个问题——https://community.nxp.com/t5/S32K/Understanding-Atomics-i-e-STREX-LDREX-on-S32K3/m-p/2356118 ——而回答似乎暗示,即使我仅在单核上使用 LDREX/STREX/CLREX,也无法依赖其行为来防止中断服务程序(ISRs)或中断请求(IRQs)与主线程发生冲突,尤其是当被检查的内存位于 SRAM 中时。 不过经过一些测试,结果似乎与我的预期一致——能否请设计团队确认,LDREX/STREX/CLREX 并不负责解决来自单个内核的访问冲突?我知道这无法阻止DMA与Cortex-M7内核之间的独占访问,但内核自身之间的访问又如何呢? Re: LDREX/STREX/CLREX on S32K3 - seems to work in SRAM? 你好 @kscz, 我也进行了测试,根据测试结果,我重新开启了这项讨论。 一旦有最新消息,我会尽快回复您。 此致, 丹尼尔 Re: LDREX/STREX/CLREX on S32K3 - seems to work in SRAM? 你好@kscz , 我已经确认,SRAM 中的行为与 TCM 中的行为相同。我已经据此更新了之前的回答。谢谢你指出这一点。 BR,丹尼尔
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Using Arduino interface of MIMX RT1170 EVK for sensor connection Hello. I am interfacing ultrasonic sensor to MIMX RT1170 EVK board. For interfacing the sensor I need to use Arduino interface for GPIOs connection. I am not able to find the proper connections for ultrasonic sensor connection, because not getting power at the pins. I gave supply to board using adapter (J43).  I need reference for pins connection and are there any settings required for powering ON the arduino interface region? Thank you.  Re: Using Arduino interface of MIMX RT1170 EVK for sensor connection Hi @SK02 , Thank you so much for your interest in our products and for using our community. regarding your issue, could you please verify the following power configuration? 1: The adapter is connected to J43 2:  The SW5 power switch is turned ON 3: J38 is set to pins 1–2 to select the external 5 V input Once these settings are confirmed, the board power rails—including those supplying the Arduino interface—should be available. Please try it. Best Regards May
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如何使用 S32K 的编译脚本? 各位恩智浦专家:   目前,我使用 IDE("S32 Design Studio for S32 Platform 3.4" )手动编译项目。 我能否通过脚本在项目中执行清理、刷新、构建和切换链接文件等操作? 这样一来,我就能实现部分自动编译,而无需打开 IDE 进行操作。 Re: How to use the compilation script for S32K? 谢谢你,petervlna!  我试试看,非常感谢! Re: How to use the compilation script for S32K? 你好 是的,你可以在不打开 IDE GUI 的情况下自动版本 S32 Design Studio。S32 设计工作室基于 Eclipse,你可以利用 Eclipse 无头编译机制进行命令行编译。 您可以在以下链接中找到教程: https://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/S32DS-list-of-HOWTOs/ta-p/1113475 对于命令行界面: https://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/HOWTO-S32-Design-Studio-Command-Line-Interface/ta-p/1112410 顺祝商祺! Peter
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T1042 DIFF_SYSCLK/DIFF_SYSCLK_B Termination Resistor Does DIFF_SYSCLK/DIFF_SYSCLK_B on the T1042 require an external termination resistor when used as an LVDS pair? The datasheet does not explicitly state it and only gives "Figure 11. LVDS receiver". AN4825 seems to show that it is internal, but this does not look to be consistent with the datasheet. Clocking Re: T1042 DIFF_SYSCLK/DIFF_SYSCLK_B Termination Resistor For T1042, you should treat the 100 Ω differential termination on DIFF_SYSCLK/DIFF_SYSCLK_B as internal , so you do not add another external 100 Ω resistor across the pair when the internal termination is enabled.
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Flutter 在 IMX93 上的运行 你好 我有一个 IMX93 主板,我想在上面运行一个 Flutter 程序。我在 CPU 使用率方面遇到了很大问题(显示一个每秒刷新一次的时钟的静态画面时,CPU 使用率约为 20%% ;而滚动包含图片的整页内容时,CPU 使用率则超过 90%% )。这主要取决于栅格(在静态屏幕上,每秒约180毫秒)。我正在尝试启用 PxP,但要么是我无法启用,要么是 Flutter 无法使用它进行栅格化。 我看到 Flutter 使用的 API 包括 OpenGL ES、Vulkan 和 Metal,因此我不确定是否可以使用 PXP 来辅助 CPU。  谢谢!
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Does the S32K364 support partial AB_SWAP mode? Hello! I have a customer’s S32K364 board here, which already has HSE configured in AB_SWAP mode. When I read the value of the DCMSTAT (0x402AC000) register, it is 0x00040FF1. According to the manual, this indicates that the DCMOTAA_EX bit is set.and the chip is in partial AB_SWAP mode. However, the manual also states, “This AB_SWAP mode is supported only for S32K328, S32K338, S32K348, S32K358, S32K356, S32K336, and S32K388." Is this a documentation error or is there another reason for this? Re: Does the S32K364 support the partial AB_SWAP mode? Hi@BianHaopeng1 看错文档了你,RN00176-for S32K396 HSE Firmware 0.2.50.0。 Senlent_0-1781161383580.png Re: Does the S32K364 support the partial AB_SWAP mode? For the S32K394, S32K374, and S32K364 devices, 0040_0000h is not available for IVT during AB-SWAP for boot loader but the ABSWAP function should be common feature
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Zephyr 3.5.0環境下で、i.MX RT1020のMCUbootイメージのスワップが再起動時にサイレントエラーで失敗する。(FlexSPI/RAMFUNCの問題) 私は、 Zephyr RTOSバージョン3.5.0 が動作する MIMXRT1020-EVK ボード上で、 MCUboot と MCUmgr/SMP UDPトランスポートスタック を使用して、マルチイメージOTAファームウェアアップデートパイプラインを実装しています。Sysbuild経由。 ネットワーク接続、アップロード、状態書き込みの各セグメントは問題なく動作しているにもかかわらず、 MCUbootは再起動時にイメージスワップ操作を完全にスキップ/拒否し、目に見えるエラーログを表示することなく、古いスロット0のイメージにそのまま戻ってしまう。 私はIntercreateのsmpmgrスクリプトを使用して、UDP経由で署名付きアプリケーションアップデートを送信しています。OSリセットをトリガーする直前のフラッシュテーブルのスナップショットクエリは、セカンダリスロットが適切に有効化され、フラグが付けられていることを示しています。 ImageState( slot=0, version='1.0.0', hash=HashBytes('00ECFDFD...'), bootable=True, pending=False, confirmed=True, active=True, permanent=False ) ImageState( slot=1, version='1.0.0', hash=HashBytes('2FD1F2FC...'), bootable=True, pending=True, confirmed=False, active=False, permanent=True ) リモートリセットコマンドを実行すると、ボードは正常にシステム再起動をトリガーしますが、MCUbootはセクターシャッフリングや遅延処理を実行しません。スロット 0 のまったく同じ HashBytes 00ECFDFD... に即座に起動します。 Flashレイアウト設定(.overlay) &flexspi { ステータス = "正常"; reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; is25wp064: is25wp064@0 { compatible = "nxp,imx-flexspi-nor"; サイズ = <67108864>; reg = <0>; spi-max-frequency = <133000000>; ステータス = "正常"; jedec-id = [9d 70 17]; 消去ブロックサイズ = <4096>; 書き込みブロックサイズ = <1>; パーティション { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; /* ステップ 1: ベースボード dts から競合するすべてのストックパーティションを削除します */ /delete-node/ partition@0; /delete-node/ partition@10000; /delete-node/ partition@310000; /delete-node/ partition@610000; /delete-node/ partition@630000; ブートパーティション: パーティション@0 { ラベル = "mcuboot"; reg = <0x00000000 DT_SIZE_K(64)>; }; /* slot0 のサイズを 3.5MB から 3.4MB (0x366000) に縮小しました */ slot0_partition: partition@10000 { ラベル = "image-0"; reg = <0x00010000 0x366000>; /* 3.5MB */ }; slot1_partition: partition@390000 { ラベル = "画像-1"; reg = <0x00376000 0x366000>; /* 3.5MB */ }; スクラッチパーティション: パーティション@710000 { ラベル = "image-scratch"; reg = <0x00710000 DT_SIZE_K(128)>; }; ストレージパーティション: パーティション@730000 { ラベル = "ストレージ"; reg = <0x00730000 DT_SIZE_K(832)>; }; }; }; }; app/prj.conf CONFIG_BOOTLOADER_MCUBOOT=y CONFIG_XIP=y CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_WITHOUT_SCRATCH=y CONFIG_USE_DT_CODE_PARTITION=y app/sysbuild/mcuboot.conf CONFIG_XIP=y CONFIG_BOOT_SWAP_USING_MOVE=y CONFIG_BOOT_SIGNATURE_TYPE_RSA=y CONFIG_BOOT_SIGNATURE_KEY_FILE="bootloader/mcuboot/root-rsa-2048.pem" CONFIG_BOOT_VALIDATE_SLOT0=y # Zephyr 3.5.0 用の RAM 機能分離フラグの試行 CONFIG_FLEXSPI_CONFIG_IN_RAM=y NXP FlexSPIドライバがフラッシュチャネルからコマンドを実行する際に、フラッシュブロックへの書き込みや消去を安全に行えないという実行インプレース(XIP)制約に引っかかっている可能性があり、その結果、MCUbootがシステムを保護するために起動時にトランザクションを安全に破棄していると考えられます。 しかし、最新のNXP RAM機能フラグ(CONFIG_CODE_FLEXSPI_RAMFUNCやCONFIG_MCUX_CODE_QUICK_ACCESS_RAMFUNCなど)のいくつかは、「未定義シンボル」コンパイラ例外または依存関係警告をスローします。 Zephyr 3.5.0では、MCUboot子イメージコンテキストにおいて、すべてのフラッシュドライバ操作フックを内部SRAM(ITCM/SRAM)に安全に強制的に移行させるために必要なKconfig変数は具体的に何ですか? RT1020固有の隠れたハードウェアアライメント制限、FlexSPIルックアップテーブル(LUT)構成、または書き込みブロックサイズによって、MCUbootがパーマネント=Trueとマークされたセカンダリイメージスロットをサイレントにスキップしてしまうことはありますか? Re: i.MX RT1020 MCUboot image swap failing silently on reboot under Zephyr 3.5.0 (FlexSPI/RAMFUNC is こんにちは、 @Deepa-khatri2588 さん。 NXP MIMXRTシリーズにご関心をお寄せいただきありがとうございます! KConfigファイルとDTSファイルを確認しましたが、いくつか問題があるようです。例えば、`CONFIG_FLEXSPI_CONFIG_IN_RAM` と `CONFIG_CODE_FLEXSPI_RAMFUNC` は Zephyr 3.5.0 には存在しません。 KConfigの設定については、こちらの公式ドキュメントをご確認ください。 https://docs.zephyrproject.org/3.5.0/kconfig.html 以下のKConfig設定に注意することをお勧めします。 CONFIG_CODE_FLEXSPI=y CONFIG_XIP=y CONFIG_FLASH_MCUX_FLEXSPI_XIP=y CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM=y CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER=y CONFIG_FLASH_LOG_LEVEL_OFF=y CONFIG_MEMC_LOG_LEVEL_OFF=y CONFIG_MEMC=y DTSでは、ノードIDとオフセットアドレスが一致しないという問題があり、これも確認する必要があるかもしれません。 slot1_partition: partition@390000 {  ラベル = "画像-1"; reg = < 0x00376000 0x366000>;  }; よろしくお願いします、 ギャビン Re: i.MX RT1020 MCUboot image swap failing silently on reboot under Zephyr 3.5.0 (FlexSPI/RAMFUNC is ご返信ありがとうございます mimxrt1020_evk.overlayファイル内のノードアドレス/オフセットラベルの不一致を修正し、3.4MBパーティション全体で構造的な整合性が完全に保たれるようにしました。 boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(64)>; }; /* Reduced slot0 to 3.4MB (0x366000) instead of 3.4MB */ slot0_partition: partition@10000 { label = "image-0"; reg = <0x00010000 0x366000>; /* 3.5MB */ }; slot1_partition: partition@376000 { label = "image-1"; reg = <0x00376000 0x366000>; /* 3.5MB */ }; scratch_partition: partition@6dc000 { label = "image-scratch"; reg = <0x006DC000 DT_SIZE_K(128)>; }; storage_partition: partition@6fc000 { label = "storage"; reg = <0x006FC000 DT_SIZE_K(1040)>; }; おすすめいただいたマクロも追加しました。 # MCUboot子イメージのスワップスクラッチモードを有効にする #CONFIG_BOOT_SWAP_USING_SCRATCH=y #CONFIG_BOOT_SWAP_USING_MOVE=y CONFIG_BOOT_SWAP_USING_SCRATCH =y # メインのMCUbootバイナリをフラッシュメモリから実行し続ける CONFIG_XIP =y # MCUbootにプロジェクトのRSA署名キーを使用してビルドするように明示的に強制する CONFIG_BOOT_SIGNATURE_TYPE_RSA =y CONFIG_BOOT_SIGNATURE_KEY_FILE = "bootloader/mcuboot/root-rsa-2048.pem" # MCUbootに対し、起動時に物理的に検証チェックを実行するように指示する CONFIG_BOOT_VALIDATE_SLOT0 =y # 起動時にイメージ検証チェックを有効にする CONFIG_IMG_ENABLE_IMAGE_CHECK =y # デバッグ中に予期しないセーフティ再起動を防ぐ CONFIG_WATCHDOG =n # NXP i.MX RTにとって重要: マスタークロック制御ツリードライバを強制する CONFIG_CLOCK_CONTROL =y CONFIG_CLOCK_CONTROL_MCUX_CCM =y # MCUbootイメージ用のIntel HEXファイル生成を強制する CONFIG_BUILD_OUTPUT_HEX =y # コアフラッシュハードウェアのイネーブルメント CONFIG_FLASH =y # 低オーバーヘッドのUARTコンソール設定 CONFIG_LOG =y CONFIG_SERIAL =y CONFIG_UART_CONSOLE =y # 標準の対話型シェルを無効にして、容量を節約し、ブートローダーのデッドロックを防ぎます CONFIG_SHELL =n # ==================================================================== # NXP ネイティブ ZEPHYR 3.5.0RAM実行構成 # ==================================================================== CONFIG_MEMC =y CONFIG_CODE_FLEXSPI =y CONFIG_FLASH_MCUX_FLEXSPI_XIP =y CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM =y CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER =y # 詳細なフラッシュログをオフにして、ログエンジンが XIP RAM コードをブロックしないようにします CONFIG_FLASH_LOG_LEVEL_OFF =y CONFIG_MEMC_LOG_LEVEL_OFF =y CONFIG_MCUBOOT_UTIL_LOG_LEVEL_INF =y 私はSMPマネージャツールを使用して、署名済みのバイナリをUDP経由で送信します。アップロード後、イメージ状態書き込みコマンドを明示的に実行します。スロット1において、保留フラグと永続フラグの両方が正常にTrueに変更されていることを確認しました。リセットコマンドを送信する直前にフラッシュの状態をスナップショットとして読み取ることで、メタデータが有効になっていることが証明されます。 ImageState( slot=0, version='1.0.0', hash=HashBytes('6835E08D...'), bootable=True, pending=False, confirmed=True, active=True, permanent=False ) ImageState( slot=1, version='1.0.0', hash=HashBytes('139D3CC6...'), bootable=True, pending=True, confirmed=True, active=False, permanent=True ) スロット1は永続的なアップグレード(pending=True、permanent=True)に対応しているにもかかわらず、OSリセットを実行すると、ボードには古いコードがロードされたままになっている。 MCUboot子イメージコンテキストのシリアルロギングを有効にし、デバッグインターフェースのUARTチャネル(lpuart1 / UART7)にルーティングしようと試みました。しかし、ハードウェアがリセットされると、 MCUbootからのコンソールテキストやエラーの痕跡は一切表示されません。端末に最初に表示されるログは、スロット0アプリケーションから発信された初期化文字列です。 RT1020 EVK上のMCUbootがアプリケーションイメージに実行制御を渡す前に、初期のシリアルコンソールログをキャプチャするための推奨される方法は何ですか? このスワップ処理がなぜサイレントに失敗しているのかについて、何かアドバイスがあれば大変ありがたいです。 Re: i.MX RT1020 MCUboot image swap failing silently on reboot under Zephyr 3.5.0 (FlexSPI/RAMFUNC is こんにちは、 @Deepa-khatri2588 さん。 LOGレベルの設定については、こちらのファイルを確認することをお勧めします: https://github.com/zephyrproject-rtos/zephyr/blob/94f5b2c2e828ed51a8e20c55d3f172dbf4a2dea8/tests/boot/test_mcuboot/sysbuild/mcuboot.conf また、スロットセクターのサイズが大きすぎる可能性があることに気づきました。以下の2つのKConfig設定を確認してください。 CONFIG_BOOT_MAX_IMG_SECTORS_AUTO CONFIG_BOOT_MAX_IMG_SECTORs よろしくお願いします、 ギャビン
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Does the S32K364 support the partial AB_SWAP mode? 你好!我手上有一块客户的S32K364板子,已经安装了AB_SWAP模式的HSE。读取DCMSTAT(0x402AC000)寄存器值为0x00040FF1,按手册代表DCMOTAA_EX这个位有效,芯片处于partial AB_SWAP模式,但是手册中又提到“This AB_SWAP mode is supported only for S32K328, S32K338, S32K348, S32K358, S32K356, S32K336, and S32K388”,请问这是一个doc bug还是什么原因? Re: Does the S32K364 support the partial AB_SWAP mode? Hi@BianHaopeng1 你看错文档了,是 RN00176-for S32K396 HSE 固件 0.2.50.0。 Senlent_0-1781161383580.png Re: Does the S32K364 support the partial AB_SWAP mode? 对于 S32K394、S32K374 和 S32K364 设备,在 AB-SWAP 启动加载程序期间,0040_0000h 不可用于 IVT,但是 ABSWAP 功能应该是常见功能
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Comparator pin description Hi, In 172-pin QFP part MCXN247VPBT, pins 135 & 139 only show CMP1_IN1 and do not have any suffix to indicate if these are CMP1_IN1P or CMP1_IN1N. Similarly, pins 156, 157, 162, 163 also have the same issue in datasheet as well as Config tool.   Can someone from NXP update this information in datasheet as well as config tool?  Thanks, Satish Acharya MCXN Re: Comparator pin description Thank you, Celeste. This answers my question. Re: Comparator pin description Hello @acharya_satishb , Thanks for your post.  I think there is no issue with either the datasheet or the Config Tool. The reason is that the pins you mentioned can be configured as either CMPx_INxP or CMPx_INxN. For example, pin 135 (also referred to as P0_3). As shown in “Table 375. CMP input connections” in reference manual, both CMP1_IN1P and CMP1_IN1N are mapped to P0_3. Celeste_Liu_0-1781148101856.png Celeste_Liu_1-1781148118393.png The same applies to other pins such as 139, 156, 157, 162, and 163. According to the table, only the inputs with index 4 and 5 are special cases. Therefore, these are explicitly differentiated in the pinmux. For instance, P4_15 is defined as CMP0_IN4P in the pinmux. About selecting the input used for the positive or negative mux, you can sconfigure the MSEL and PSEL bits in the CCR2 register.  And noted that PSEL should not be same as MSEL. Celeste_Liu_2-1781148389923.png Hope it helps. If you needs further help please do not hesitate to reach out. Any new issues, welcome to create a new post. BR Celeste -------------------------------------------------------------------------------------------------------------------- Note: If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! --------------------------------------------------------------------------------------------------------------------
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Inquiry about PINCFG Field Configuration in S32K146 LPI2C MCFGR1 Register Hello everyone, I'm working with the LPI2C module on the S32K146 and have some questions about the PINCFG field in the MCFGR1 (Master Configuration Register 1) register. According to the reference manual, the PINCFG field is used to configure the I2C pin operating mode. However, I need to understand the following specific information: What are the application scenarios for each of the 8 different PINCFG configuration values (000 to 111)? What is the pin output type for each configuration value? Is it Open-Drain or Push-Pull output? Any application notes, reference code, or practical experience you can share would be greatly appreciated. Thank you! Re: Inquiry about PINCFG Field Configuration in S32K146 LPI2C MCFGR1 Register Hi @GXY  The PINCFG field defines how the LPI2C pins are electrically driven and used, depending on whether a standard 2‑pin I2C bus or a separated 4‑pin configuration is required. 000 – Standard mode: bidirectional open-drain 001 – Both signals configured as output-only open-drain 010 – Bidirectional push-pull 011 – SCL/SDA used as inputs; SCLS/SDAS used as push-pull outputs 100 – SCL/SDA: bidirectional open-drain for master; SCLS/SDAS: bidirectional open-drain for slave 101 – SCL/SDA: output-only open-drain for master; SCLS/SDAS: output-only open-drain for slave 110 – SCL/SDA: bidirectional push-pull for master; SCLS/SDAS: bidirectional push-pull for slave 111 – SCL/SDA: input-only open-drain; SCLS/SDAS: inverted output-only push-pull For additional information, please refer to the UM10204: I2C-bus Specification and User Manual. Additionally, example codes demonstrating standard I2C pin configurations are available within the S32K1 software packages. BR, VaneB Re: Inquiry about PINCFG Field Configuration in S32K146 LPI2C MCFGR1 Register Hi @GXY  As mentioned earlier, the PINCFG field in the LPI2C peripheral defines the number of pins used and their electrical behavior. It does not directly determine the I2C speed mode. Regarding the operating modes, the LPI2C module can logically support different modes. However, the actual baud rate you can achieve also depends on several factors, such as the pad implementation, external loading, and the pull-up used on the bus. For S32K1 devices, the SCL and SDA signals use standard GPIO pads rather than high-drive pads, so the maximum achievable baud rate is somewhat limited. Also, Table 52-9  only provides example register settings. These configurations are intended as references and do not guarantee that the corresponding baud rates can be achieved in a real application. Re: Inquiry about PINCFG Field Configuration in S32K146 LPI2C MCFGR1 Register I know the meaning of this field, but my question is about the application scenarios of these fields. For example, 000 is used for standard two-wire I2C transmission; 001 is used for two-wire transmission in ultra mode; 010 is used for communication in HS mode; 011 and 111 are used for four wire communication; I am confused about how to flexibly use the other three configurations. If I am wrong, please correct me. In addition, the manual states that S32K146 does not support HS mode and ULTRA mode, but by changing the PINCFG register, I can achieve mutual communication between HS mode 3.4M (low-speed first, then high-speed) and ULTRA measured 4M (both master and slave are S32K146). I would like to know if there is any errata or if my test is incorrect. Re: Inquiry about PINCFG Field Configuration in S32K146 LPI2C MCFGR1 Register I feel increasingly puzzled. My biggest concern now is that by changing the PINCFG, S32K146 can directly communicate with each other at the speed of FASTPLUS, HS, and ULTRAFAST modes. However, in reality, S32K146 cannot communicate with other standard I2C devices in these three modes (as stated in the manual). Let me first explain how I made two 146 (one master and one slave) communicate in these three modes: 1. FASTPLUS (1M) adjusts the PINCFG of the master and slave to 010. 2. HSMODE (equipped with 2M measured 2M) adjusts the PINCFG of the master and slave devices to 010. 3. ULTRAFAST (equipped with 5M and tested 4M) adjusts the master PINCFG001 and slave PINCFG000. I would like to know if the standard equipment for FASTPLUS (1M), HS (3.4M), and ULTRAFAST (5M) modes has push-pull output or open drain output.
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在 Zephyr 3.5.0 环境下,i.MX RT1020 的 MCUboot 镜像在重启时会无提示地交换失败(FlexSPI/RAMFUNC 问题) 我正在运行 Zephyr RTOS 版本 3.5.0 的 MIMXRT1020-EVK 主板上使用 mcuBoot 和 mc umGR/SMP UDP 传输堆栈 实现多映像 OTA 固件更新管道来源:Sysbuild。 虽然网络连接、上传和状态写入环节均运行正常,但在重启时,MCUboot 会完全跳过/拒绝执行镜像切换操作,直接回退到旧的插槽 0 镜像,且未显示任何可见的错误日志: 。我正在通过 Intercreate smpmgr 脚本经由 UDP 发送经过签名的应用程序更新。在触发操作系统 RESET 之前对闪存表进行快照查询表明辅助插槽已正确布防并已标记 ImageState( slot=0, version='1.0.0', hash=HashBytes('00ECFDFD...'), bootable=True, pending=False, confirmed=True, active=True, permanent=False ) ImageState( slot=1, version='1.0.0', hash=HashBytes('2FD1F2FC...'), bootable=True, pending=True, confirmed=False, active=False, permanent=True ) 运行远程重置命令后,板成功触发系统重启,但是 MCUboot 没有执行任何扇区洗牌或延迟。它会立即重新启动,并直接回到插槽 0 中的完全相同的 HashBytes 00ECFDFD...。 闪存布局配置 (.overlay) &flexspi { status ="okay"; reg =<0x402a8000 0x4000>,<0x60000000 DT_SIZE_M(8)>; is25wp064:is25wp064 @0 { 兼容 = " nxp,imx-flexspi-nor "; 尺寸<67108864> = ; reg =<0> ;spi-max-frequency =<133000000> ;状态 = " 好吧 ";jedec-id = [9d 70 17]; erase-block-size =;<4096> write-block-size =;<1> 分区 { compatible ="fixed-partitions"; #address-cells =<1>; #size-cells =<1>; /* 第 1 步:从基板 dts 中删除所有冲突的库存分区 */ /删除节点/ 分区 @0; /删除节点/ 分区 @10000; /删除节点/ 分区 @310000; /删除节点/ 分区; /删除节点/ 分区 @610000; /删除节点/ 分区 @630000; boot_partition: partition@0 { label ="mcuboot"; reg =<0x00000000 DT_SIZE_K(64)>; }; /* 将 slot0 缩减为 3.4MB (0x366000) 而不是 3.5MB */ slot0_partition: partition@10000 { label ="image-0"; reg =<0x00010000 0x366000>; /* 3.5MB */ }; slot1_partition: partition@390000 { label ="image-1"; reg =<0x00376000 0x366000>; /* 3.5MB */ }; scratch_partition: partition@710000 { label ="image-scratch"; reg =<0x00710000 DT_SIZE_K(128)>; }; storage_partition: partition@730000 { label ="storage"; reg =<0x00730000 DT_SIZE_K(832)>; }; }; }; }; app/prj.conf CONFIG_BOOTLOADER_MCUBOOT=y CONFIG_XIP=y CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_WITHOUT_SCRATCH=y CONFIG_USE_DT_CODE_PARTITION=y app/sysbuild/mcuboot.conf CONFIG_XIP=y CONFIG_BOOT_SWAP_USING_MOVE=y CONFIG_BOOT_SIGNATURE_TYPE_RSA=y CONFIG_BOOT_SIGNATURE_KEY_FILE="bootloader/mcuboot/root-rsa-2048.pem" CONFIG_BOOT_VALIDATE_SLOT0=y # 尝试为 Zephyr 3.5.0 实现 RAM 功能隔离标志 CONFIG_FLEXSPI_CONFIG_IN_RAM=y 怀疑我们遇到了就地执行 (XIP) 限制,即恩智浦FlexSPI驱动程序在执行来自闪存通道的命令时无法安全地写入或擦除闪存块,从而导致McuBoot在启动时安全地删除事务以保护系统。 然而,一些现代的 NXP RAM 功能标志(例如 CONFIG_CODE_FLEXSPI_RAMFUNC 或 CONFIG_MCUX_CODE_QUICK_ACCESS_RAMFUNC)会引发“"”未定义符号的"编译器异常或依赖警告 在 Zephyr 3.5.0 中,在 MCUboot 子映像环境中,要安全地将所有闪存驱动程序操作钩子完全移至内部 SRAM(ITCM/SRAM)中,具体需要哪些 Kconfig 变量? 是否存在某些仅限于 RT1020 的隐藏硬件对齐限制、FlexSPI 查找表 (LUT) 配置或写入块大小,导致 MCUboot 会无提示地跳过标记为 permanent=True 的辅助映像槽? Re: i.MX RT1020 MCUboot image swap failing silently on reboot under Zephyr 3.5.0 (FlexSPI/RAMFUNC is 你好@Deepa-khatri2588、 感谢您对 NXP MIMXRT 系列的关注! 我已经检查了您的 KConfig 和 DTS 文件,似乎存在一些问题。例如,`CONFIG_FLEXSPI_CONFIG_IN_RAM` 和 `CONFIG_CODE_FLEXSPI_RAMFUNC` 在 Zephyr 3.5.0 中并不存在。 请查阅此官方文档中的 KConfig 设置:  https://docs.zephyrproject.org/3.5.0/kconfig.html 建议您注意以下 KConfig 设置: CONFIG_CODE_FLEXSPI=y CONFIG_XIP=y CONFIG_FLASH_MCUX_FLEXSPI_XIP=y CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM=y CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER=y CONFIG_FLASH_LOG_LEVEL_OFF=y CONFIG_MEMC_LOG_LEVEL_OFF=y CONFIG_MEMC=y 在 DTS 中,存在节点 ID 与偏移地址不匹配的问题,这一点可能也需要进行验证: slot1_partition:partition@390000{  标签 ="image-1"; reg =<0x003760000x366000>;  }; 致以最诚挚的问候, Gavin Re: i.MX RT1020 MCUboot image swap failing silently on reboot under Zephyr 3.5.0 (FlexSPI/RAMFUNC is 感谢您的回复 。我已修正 mimxrt1020_evk.overlay 文件中节点地址与偏移量标签不匹配的问题,以确保 3.4MB 分区之间的结构完全对齐: boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(64)>; }; /* Reduced slot0 to 3.4MB (0x366000) instead of 3.4MB */ slot0_partition: partition@10000 { label = "image-0"; reg = <0x00010000 0x366000>; /* 3.5MB */ }; slot1_partition: partition@376000 { label = "image-1"; reg = <0x00376000 0x366000>; /* 3.5MB */ }; scratch_partition: partition@6dc000 { label = "image-scratch"; reg = <0x006DC000 DT_SIZE_K(128)>; }; storage_partition: partition@6fc000 { label = "storage"; reg = <0x006FC000 DT_SIZE_K(1040)>; };  我也添加了你推荐的宏 # 为 MCUboot 子镜像启用交换暂存模式 #CONFIG_BOOT_SWAP_USING_SCRATCH=y #CONFIG_BOOT_SWAP_USING_MOVE=y CONFIG_BOOT_SWAP_USING_SCRATCH=y # 保持从 Flash 执行主 mcuBoot 二进制文件 CONFIG_XIP=y # 明确强制 McuBoot 使用项目 RSA 签名密钥进行构建 CONFIG_BOOT_SIGNATURE_TYPE_RSA=y CONFIG_BOOT_SIGNATURE_KEY_FILE="bootloader/mcuboot/root-rsa-2048.pem" # 指示 McuBoot 在启动时实际运行验证检查 CONFIG_BOOT_VALIDATE_SLOT0=y # 启动时启用图像验证检查 CONFIG_IMG_ENABLE_IMAGE_CHECK=y # 防止在调试期间意外功能安全重启 CONFIG_WATCHDOG=n # NXP i.MX RT 的关键组件:强制执行主时钟控制树驱动程序 CONFIG_CLOCK_CONTROL=y CONFIG_CLOCK_CONTROL_MCUX_CCM=y # 强制生成 MCUboot 镜像的 Intel HEX 文件 CONFIG_BUILD_OUTPUT_HEX=y # 核心闪存硬件启用 CONFIG_FLASH=y # 低开销 UART 控制台配置 CONFIG_LOG=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y # 禁用标准交互式 shell 以节省空间并防止引导加载程序死锁 CONFIG_SHELL=n # ==================================================================== # NXP NATIVE ZEPHYR 3.5.0内存执行配置 # ==================================================================== CONFIG_MEMC=y CONFIG_CODE_FLEXSPI=y CONFIG_FLASH_MCUX_FLEXSPI_XIP=y CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM=y CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER=y # 关闭详细闪存日志,以确保日志引擎不会阻塞 XIP RAM 代码 CONFIG_FLASH_LOG_LEVEL_OFF=y CONFIG_MEMC_LOG_LEVEL_OFF=y CONFIG_MCUBOOT_UTIL_LOG_LEVEL_INF=y 我使用 SMP 管理器工具将签名的二进制文件推送到 UDP 上。上传后,我明确执行图像状态写入命令。我确认插槽 1 中的“待处理”和“永久”标志均已成功设置为 True。在发送重置命令之前立即读取闪存状态的快照证明元数据已准备就绪: ImageState( slot=0, version='1.0.0', hash=HashBytes('6835E08D...'), bootable=True, pending=False, confirmed=True, active=True, permanent=False ) ImageState( slot=1, version='1.0.0', hash=HashBytes('139D3CC6...'), bootable=True, pending=True, confirmed=True, active=False, permanent=True ) 尽管 Slot 1 已经准备好进行永久升级(pending=True,permanent=True),但是当我执行操作系统 RESET 时,主板上仍然装有旧的代码 我尝试为 McuBoot 子映像上下文启用串行日志记录,将其路由到我们的调试接口 UART 频道(lpuart1/UART7)。但是,当硬件重置时,我看到的来自 McuBoot 的控制台文本或错误痕迹绝对为零。终端上最早出现的日志是来自插槽 0 应用程序的初始化字符串。 在将执行控制权移交给应用程序映像之前,在 RT1020 EVK 上从 McuBoot 捕获早期串行控制台日志的推荐方法是什么 如果您能就该交换例程为何会无声无息地失败提供任何建议,我将不胜感激。 Re: i.MX RT1020 MCUboot image swap failing silently on reboot under Zephyr 3.5.0 (FlexSPI/RAMFUNC is 你好@Deepa-khatri2588、 关于日志级别设置,建议您查看此文件:https://github.com/zephyrproject-rtos/zephyr/blob/94f5b2c2e828ed51a8e20c55d3f172dbf4a2dea8/tests/boot/test_mcuboot/sysbuild/mcuboot.conf 另外,我注意到你的槽区可能设置得过大。请检查以下两个 KConfig 设置: CONFIG_BOOT_MAX_IMG_SECTORS_AUTO CONFIG_BOOT_MAX_IMG_SECTORS 致以最诚挚的问候, Gavin
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LDREX/STREX/CLREX on S32K3 - seems to work in SRAM? I asked a question a little bit back - https://community.nxp.com/t5/S32K/Understanding-Atomics-i-e-STREX-LDREX-on-S32K3/m-p/2356118 - and the answer seemed to imply that I could not rely on the behavior of LDREX/STREX/CLREX even when I was only using it on a single core to prevent conflicts between things like ISRs/IRQs conflicting with the main thread if the memory being checked was in SRAM. Having done some testing though, it appears to work as I expect - could I get confirmation from the design team that LDREX/STREX/CLREX is not expected to deconflict accesses from a single core? I know that it won't prevent things like exclusive accesses between the DMA and the cortex-m7 core, but what about the core with itself? Re: LDREX/STREX/CLREX on S32K3 - seems to work in SRAM? Hi @kscz, I have tested it as well, and based on the results, I reopened the discussion. I will get back to you as soon as I have an update. Regards, Daniel Re: LDREX/STREX/CLREX on S32K3 - seems to work in SRAM? Hello @kscz, I have received confirmation that the behavior in SRAM is the same as in TCM. I have updated my previous answer accordingly. Thank you for pointing this out. BR, Daniel
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How to use the compilation script for S32K? Hi, NXP experts:   Now i use the IDE ("S32 Design Studio for S32 Platform 3.4" ) for project compile by manual. Can I achieve operations such as cleaning, refreshing, building, and switching link files in the project through scripts? This way, I can achieve some automated compilation without having to open the IDE for operation. Re: How to use the compilation script for S32K? Thank you petervlna  !  I will have a try, thank you very much! Re: How to use the compilation script for S32K? Hello, Yes — you can automate S32 Design Studio builds without opening the IDE GUI. S32 Design Studio is Eclipse-based, you can utilize the Eclipse headless build mechanism for command-line compilation. You can find tutorial on this link: https://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/S32DS-list-of-HOWTOs/ta-p/1113475 For command line interface: https://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/HOWTO-S32-Design-Studio-Command-Line-Interface/ta-p/1112410 Best regards, Peter
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i.MX RT1020 MCUboot image swap failing silently on reboot under Zephyr 3.5.0 (FlexSPI/RAMFUNC issue I am implementing a multi-image OTA firmware update pipeline using MCUboot and the MCUmgr / SMP UDP transport stack on a MIMXRT1020-EVK board, running Zephyr RTOS version 3.5.0 via Sysbuild. While the networking, upload, and state-writing segments are working flawlessly, MCUboot completely skips/refuses the image swap operation upon reboot, dropping right back into the older slot 0 image without throwing visible error traces I am sending signed application updates via an Intercreate smpmgr script over UDP. The snapshot query of the flash tables right before triggering an os reset indicates the secondary slot is properly armed and flagged ImageState( slot=0, version='1.0.0', hash=HashBytes('00ECFDFD...'), bootable=True, pending=False, confirmed=True, active=True, permanent=False ) ImageState( slot=1, version='1.0.0', hash=HashBytes('2FD1F2FC...'), bootable=True, pending=True, confirmed=False, active=False, permanent=True ) Upon running the remote reset command, the board successfully triggers a system reboot, but MCUboot does not execute any sector shuffling or delays. It boots instantly straight back into the exact same HashBytes 00ECFDFD... in Slot 0. Flash Layout Configurations (.overlay) &flexspi { status = "okay"; reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; is25wp064: is25wp064@0 { compatible = "nxp,imx-flexspi-nor"; size = <67108864>; reg = <0>; spi-max-frequency = <133000000>; status = "okay"; jedec-id = [9d 70 17]; erase-block-size = <4096>; write-block-size = <1>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; /* STEP 1: Delete all conflicting stock partitions from the base board dts */ /delete-node/ partition@0; /delete-node/ partition@10000; /delete-node/ partition@310000; /delete-node/ partition@610000; /delete-node/ partition@630000; boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(64)>; }; /* Reduced slot0 to 3.4MB (0x366000) instead of 3.5MB */ slot0_partition: partition@10000 { label = "image-0"; reg = <0x00010000 0x366000>; /* 3.5MB */ }; slot1_partition: partition@390000 { label = "image-1"; reg = <0x00376000 0x366000>; /* 3.5MB */ }; scratch_partition: partition@710000 { label = "image-scratch"; reg = <0x00710000 DT_SIZE_K(128)>; }; storage_partition: partition@730000 { label = "storage"; reg = <0x00730000 DT_SIZE_K(832)>; }; }; }; }; app/prj.conf CONFIG_BOOTLOADER_MCUBOOT=y CONFIG_XIP=y CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_WITHOUT_SCRATCH=y CONFIG_USE_DT_CODE_PARTITION=y app/sysbuild/mcuboot.conf CONFIG_XIP=y CONFIG_BOOT_SWAP_USING_MOVE=y CONFIG_BOOT_SIGNATURE_TYPE_RSA=y CONFIG_BOOT_SIGNATURE_KEY_FILE="bootloader/mcuboot/root-rsa-2048.pem" CONFIG_BOOT_VALIDATE_SLOT0=y # Attempted RAM function isolation flags for Zephyr 3.5.0 CONFIG_FLEXSPI_CONFIG_IN_RAM=y suspect we are hitting an execute-in-place (XIP) constraint where the NXP FlexSPI driver cannot write or erase flash blocks safely while executing commands out of the flash channel, causing MCUboot to safely drop the transaction on boot to protect the system. However, several modern NXP RAM function flags (such as CONFIG_CODE_FLEXSPI_RAMFUNC or CONFIG_MCUX_CODE_QUICK_ACCESS_RAMFUNC) throw "undefined symbol" compiler exceptions or dependency warnings In Zephyr 3.5.0, what are the precise Kconfig variables required to safely force all flash driver manipulation hooks entirely into internal SRAM (ITCM/SRAM) for the MCUboot child image context? Are there any hidden hardware alignment limits, FlexSPI look-up-table (LUT) configurations, or write-block sizes unique to the RT1020 that cause MCUboot to silently skip a marked permanent=True secondary image slot? Re: i.MX RT1020 MCUboot image swap failing silently on reboot under Zephyr 3.5.0 (FlexSPI/RAMFUNC is Hi @Deepa-khatri2588 , Thanks for your interest in NXP MIMXRT series! I’ve reviewed your KConfig and DTS files, and it appears there are some issues. For example, `CONFIG_FLEXSPI_CONFIG_IN_RAM` and `CONFIG_CODE_FLEXSPI_RAMFUNC` do not exist in Zephyr 3.5.0. Please check your KConfig settings in this official documentation:  https://docs.zephyrproject.org/3.5.0/kconfig.html I recommend paying attention to the following KConfig settings: CONFIG_CODE_FLEXSPI=y CONFIG_XIP=y CONFIG_FLASH_MCUX_FLEXSPI_XIP=y CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM=y CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER=y CONFIG_FLASH_LOG_LEVEL_OFF=y CONFIG_MEMC_LOG_LEVEL_OFF=y CONFIG_MEMC=y In DTS, there is an issue where node IDs and offset addresses do not match, which may also need to be verified: slot1_partition: partition@390000 {  label = "image-1"; reg = <0x00376000 0x366000>;  }; Best regards, Gavin Re: i.MX RT1020 MCUboot image swap failing silently on reboot under Zephyr 3.5.0 (FlexSPI/RAMFUNC is Thanks for your reply  I corrected the node address/offset label mismatch in my mimxrt1020_evk.overlay to ensure perfect structural alignment across the 3.4MB partitions: boot_partition: partition@0 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(64)>; }; /* Reduced slot0 to 3.4MB (0x366000) instead of 3.4MB */ slot0_partition: partition@10000 { label = "image-0"; reg = <0x00010000 0x366000>; /* 3.5MB */ }; slot1_partition: partition@376000 { label = "image-1"; reg = <0x00376000 0x366000>; /* 3.5MB */ }; scratch_partition: partition@6dc000 { label = "image-scratch"; reg = <0x006DC000 DT_SIZE_K(128)>; }; storage_partition: partition@6fc000 { label = "storage"; reg = <0x006FC000 DT_SIZE_K(1040)>; };  i added the macros you recommended as well # Enable swap scratch mode for the MCUboot child image #CONFIG_BOOT_SWAP_USING_SCRATCH=y #CONFIG_BOOT_SWAP_USING_MOVE=y CONFIG_BOOT_SWAP_USING_SCRATCH=y # Keep the main MCUboot binary executing from Flash CONFIG_XIP=y # Explicitly force MCUboot to build with the project RSA signing key CONFIG_BOOT_SIGNATURE_TYPE_RSA=y CONFIG_BOOT_SIGNATURE_KEY_FILE="bootloader/mcuboot/root-rsa-2048.pem" # Directs MCUboot to physically run verification checks on boot CONFIG_BOOT_VALIDATE_SLOT0=y # Enable image validation checks on boot CONFIG_IMG_ENABLE_IMAGE_CHECK=y # Prevent unexpected safety restarts during debugging CONFIG_WATCHDOG=n # Vital for NXP i.MX RT: Enforce master clock control tree drivers CONFIG_CLOCK_CONTROL=y CONFIG_CLOCK_CONTROL_MCUX_CCM=y # Force Intel HEX file generation for the MCUboot image CONFIG_BUILD_OUTPUT_HEX=y # Core flash hardware enablement CONFIG_FLASH=y # Low-overhead UART Console configuration CONFIG_LOG=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y # Disable standard interactive shell to save space and prevent bootloader deadlocks CONFIG_SHELL=n # ==================================================================== # NXP NATIVE ZEPHYR 3.5.0 RAM-EXECUTION CONFIGURATION # ==================================================================== CONFIG_MEMC=y CONFIG_CODE_FLEXSPI=y CONFIG_FLASH_MCUX_FLEXSPI_XIP=y CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM=y CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER=y # Turn off verbose flash logs to ensure logging engines don't block XIP RAM code CONFIG_FLASH_LOG_LEVEL_OFF=y CONFIG_MEMC_LOG_LEVEL_OFF=y CONFIG_MCUBOOT_UTIL_LOG_LEVEL_INF=y  I push the signed binary over UDP using an SMP manager tool. After upload, I explicitly execute an image state write command. I am confirming that both the pending and permanent flags are successfully changing to True in Slot 1. A snapshot read of the flash states immediately before sending the reset command proves the metadata is armed: ImageState( slot=0, version='1.0.0', hash=HashBytes('6835E08D...'), bootable=True, pending=False, confirmed=True, active=True, permanent=False ) ImageState( slot=1, version='1.0.0', hash=HashBytes('139D3CC6...'), bootable=True, pending=True, confirmed=True, active=False, permanent=True ) Even though Slot 1 is perfectly armed for a permanent upgrade (pending=True, permanent=True), when I execute an os reset the board is still loaded with the old code  I attempted to enable serial logging for the MCUboot child image context, routing it to our debug interface UART channel (lpuart1 / UART7). However, when the hardware resets, I see absolutely zero console text or error traces from MCUboot. The very first logs to appear on the terminal are the initialization strings originating from the Slot 0 application. What is the recommended method to capture early serial console logs from MCUboot on the RT1020 EVK before it hands execution control over to the application image Any advice on why this swap routine is silently failing would be highly appreciated. Re: i.MX RT1020 MCUboot image swap failing silently on reboot under Zephyr 3.5.0 (FlexSPI/RAMFUNC is Hi @Deepa-khatri2588 , Regarding the LOG level settings, I think you should check this file: https://github.com/zephyrproject-rtos/zephyr/blob/94f5b2c2e828ed51a8e20c55d3f172dbf4a2dea8/tests/boot/test_mcuboot/sysbuild/mcuboot.conf Also, I noticed that your slot sectors may be too large. Please check these two KConfig settings: CONFIG_BOOT_MAX_IMG_SECTORS_AUTO CONFIG_BOOT_MAX_IMG_SECTORS Best regards, Gavin
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