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Inquiry about PINCFG Field Configuration in S32K146 LPI2C MCFGR1 Register

Hello everyone,

I'm working with the LPI2C module on the S32K146 and have some questions about the PINCFG field in the MCFGR1 (Master Configuration Register 1) register.

According to the reference manual, the PINCFG field is used to configure the I2C pin operating mode. However, I need to understand the following specific information:

What are the application scenarios for each of the 8 different PINCFG configuration values (000 to 111)?
What is the pin output type for each configuration value? Is it Open-Drain or Push-Pull output?

Any application notes, reference code, or practical experience you can share would be greatly appreciated.

Thank you!

Re: Inquiry about PINCFG Field Configuration in S32K146 LPI2C MCFGR1 Register

Hi @GXY

The PINCFG field defines how the LPI2C pins are electrically driven and used, depending on whether a standard 2‑pin I2C bus or a separated 4‑pin configuration is required.

000 – Standard mode: bidirectional open-drain
001 – Both signals configured as output-only open-drain
010 – Bidirectional push-pull
011 – SCL/SDA used as inputs; SCLS/SDAS used as push-pull outputs
100 – SCL/SDA: bidirectional open-drain for master; SCLS/SDAS: bidirectional open-drain for slave
101 – SCL/SDA: output-only open-drain for master; SCLS/SDAS: output-only open-drain for slave
110 – SCL/SDA: bidirectional push-pull for master; SCLS/SDAS: bidirectional push-pull for slave
111 – SCL/SDA: input-only open-drain; SCLS/SDAS: inverted output-only push-pull

For additional information, please refer to the UM10204: I2C-bus Specification and User Manual.

Additionally, example codes demonstrating standard I2C pin configurations are available within the S32K1 software packages.

BR, VaneB

Re: Inquiry about PINCFG Field Configuration in S32K146 LPI2C MCFGR1 Register

Hi @GXY

As mentioned earlier, the PINCFG field in the LPI2C peripheral defines the number of pins used and their electrical behavior. It does not directly determine the I2C speed mode.

Regarding the operating modes, the LPI2C module can logically support different modes. However, the actual baud rate you can achieve also depends on several factors, such as the pad implementation, external loading, and the pull-up used on the bus.

For S32K1 devices, the SCL and SDA signals use standard GPIO pads rather than high-drive pads, so the maximum achievable baud rate is somewhat limited.

Also, Table 52-9 only provides example register settings. These configurations are intended as references and do not guarantee that the corresponding baud rates can be achieved in a real application.

Re: Inquiry about PINCFG Field Configuration in S32K146 LPI2C MCFGR1 Register

I know the meaning of this field, but my question is about the application scenarios of these fields. For example, 000 is used for standard two-wire I2C transmission; 001 is used for two-wire transmission in ultra mode; 010 is used for communication in HS mode; 011 and 111 are used for four wire communication; I am confused about how to flexibly use the other three configurations. If I am wrong, please correct me. In addition, the manual states that S32K146 does not support HS mode and ULTRA mode, but by changing the PINCFG register, I can achieve mutual communication between HS mode 3.4M (low-speed first, then high-speed) and ULTRA measured 4M (both master and slave are S32K146). I would like to know if there is any errata or if my test is incorrect.

Re: Inquiry about PINCFG Field Configuration in S32K146 LPI2C MCFGR1 Register

I feel increasingly puzzled. My biggest concern now is that by changing the PINCFG, S32K146 can directly communicate with each other at the speed of FASTPLUS, HS, and ULTRAFAST modes. However, in reality, S32K146 cannot communicate with other standard I2C devices in these three modes (as stated in the manual). Let me first explain how I made two 146 (one master and one slave) communicate in these three modes: 1. FASTPLUS (1M) adjusts the PINCFG of the master and slave to 010. 2. HSMODE (equipped with 2M measured 2M) adjusts the PINCFG of the master and slave devices to 010. 3. ULTRAFAST (equipped with 5M and tested 4M) adjusts the master PINCFG001 and slave PINCFG000.
I would like to know if the standard equipment for FASTPLUS (1M), HS (3.4M), and ULTRAFAST (5M) modes has push-pull output or open drain output.