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I asked a question a little bit back - https://community.nxp.com/t5/S32K/Understanding-Atomics-i-e-STREX-LDREX-on-S32K3/m-p/2356118 - and the answer seemed to imply that I could not rely on the behavior of LDREX/STREX/CLREX even when I was only using it on a single core to prevent conflicts between things like ISRs/IRQs conflicting with the main thread if the memory being checked was in SRAM.
Having done some testing though, it appears to work as I expect - could I get confirmation from the design team that LDREX/STREX/CLREX is not expected to deconflict accesses from a single core? I know that it won't prevent things like exclusive accesses between the DMA and the cortex-m7 core, but what about the core with itself?
Hi @kscz,
I have tested it as well, and based on the results, I reopened the discussion.
I will get back to you as soon as I have an update.
Regards,
Daniel
Hello @kscz,
I have received confirmation that the behavior in SRAM is the same as in TCM. I have updated my previous answer accordingly. Thank you for pointing this out.
BR, Daniel