1つのi3cバス上にP3T1084UKをいくつ接続できますか？ P3T1084UKの場合、i3cバスあたりに接続できるデバイスの最大数はいくつですか？ P3T1084UKはi3cの動的アドレス割り当てをサポートしていますが、表5のI3C暫定ID構成と表6によると、PIDビットはアドレスピン構成に関連付けられた固定値であるようです。つまり、単一のi3cバス上には、最大4個のP3T1084UKしか接続できないということでしょうか？P3T1084UKが8個必要な場合、それらは2つのi3cインターフェース上に配置する必要がありますか？ Re: how many P3T1084UK are allowed on a single i3c bus? それはA0の設定に依存します。 guoweisun_0-1781573924748.png

1500V BMS 参考应用程序中的编译错误 — SAF 库错误 尊敬的恩智浦支持团队： 我们在S32 Design Studio中的1500V 电池管理系统参考应用程序项目（S32K3-BESS-Firmware-Version-0.8.0-Demo）中遇到了致命的编译错误。 多个 sCheck_*.h 文件scheck_cfg.c 中引用的标头在 SDK 的任何地方都找不到（参见随附的屏幕截图）。 已安装的 SAF 软件包：s32k3x_saf_1_0_4 这导致中间件、操作系统、Startup_Code 和 SAF 模块连续 20 次版本失败。 你能否告诉我 s32k3x_saf_1_0_4 是否包含 sCheck 库，如果没有，我们应该安装哪个软件包版本？ 随函附上完整的构建日志、已安装的软件包列表以及缺失标头的屏幕截图供您参考。 Re: Build Error in 1500V BMS Reference Application – SAF Library Errors 你好@GauravXB， 这是因为您正在使用 SAF 库的 EVAL 版本，该版本可免费使用。 danielmartynek_0-1781528505723.png 头文件仅包含在库的完整版本中，这是一个付费（高级）代码包，软件包。 https://www.nxp.com/design/design-center/software/functional-safety-software/s32-safety-software-framework-saf-and-safety-peripheral-drivers-spd:SAF 此致， 丹尼尔

Yocto Wrynose 对 i.MX8M Plus 的支持 您好， Yocto Wrynose 的 meta-imx 支持有发布日期吗？ 谢谢！ Re: Yocto Wrynose support for i.MX8M Plus 你好@jcaballeros  希望你一切都好。 Yocto Wrynose 预计将于本月底或下月中旬发布。 顺祝商祺！ 萨拉斯 Re: Yocto Wrynose support for i.MX8M Plus 你好@csbg 实际上，你可以尝试编译那个特定版本。应该能正常工作。 https://github.com/nxp-imx/meta-imx/tree/wrynose-6.18.20-2.0.0 顺祝商祺！ 萨拉斯 Re: Yocto Wrynose support for i.MX8M Plus 嗨@Manuel_Salas 所以当前可用的分支“wrynose-6.18.20-2.0.0”还不能使用，对吗？ 整合工作何时完成会有公告吗？ BR，克里斯蒂安

CMSIS 软件包中不包含 S32K388 的闪存算法 我正试图在多个设计中使用 S32K388，但发现 CMSIS 软件包中没有针对它的闪存算法——https://www.keil.arm.com/packs/s32k3xx_dfp-keil/devices/ 有计划添加这个功能吗？我最快什么时候能拿到这个文件的更新版本？ Re: No Flash Algorithms for S32K388 in CMSIS Pack 你好@kscz 这超出了我们的支持范围。您应向 KEIL 技术支持寻求帮助。 根据目前的信息，KEIL 的 DFP 软件包尚未更新，并且不支持所有 S32K3 型号。 您需要自行实现 S32K388 的编程算法。 （我已在KEIL论坛上创建了一个提问帖，咨询关于S32K3 DFP未来更新计划。） Re: No Flash Algorithms for S32K388 in CMSIS Pack 真可惜——我还以为不用自己编写刷机算法呢…… 我可以根据内存文件之类的东西翻译其余字段，但目前我对闪存算法还不太了解。 你有 Keil 讨论帖的链接吗？您是否了解当前 DFP 被弃用的原因？ Re: No Flash Algorithms for S32K388 in CMSIS Pack 您好@kscz 请复制以下内容以供参考： ” 软件包 S32K3xx.DFP 已明确标记为“已弃用”。请参阅： https://www.keil.arm.com/packs/s32k3xx_dfp-keil/devices/ 这意味着我公司将不再发布任何更新。我们很久以前就停止维护 NXP 的 DFP（设计功能包），而 NXP 为其他器件创建了大量的 DFP，但显然没有为该系列器件创建。因此，NXP 需要为 S32K3 系列器件创建新的 DFP。 ” 与此同时，我正在向开发团队确认 NXP 是否会继续支持 DFP 软件包。但是，我还没有收到任何信息。 Re: No Flash Algorithms for S32K388 in CMSIS Pack 有任何进展吗？NXP是否会支持更新Keil工具链中的这些工具？ Re: No Flash Algorithms for S32K388 in CMSIS Pack 您好@kscz 抱歉，我忘记把收到的信息转发给你了。 内部反应非常明确。 “到目前为止，恩智浦还没有计划更新KEIL的S32K3xx的DFP。”

Build Error in 1500V BMS Reference Application – SAF Library Errors Dear NXP Support Team, We are facing a fatal build error in our 1500V BMS Reference Application project (S32K3-BESS-Firmware-Version-0.8.0-Demo) in S32 Design Studio. Multiple sCheck_*.h headers referenced in sCheck_Cfg.c are not found anywhere in the SDK (see attached screenshot). Installed SAF Package: s32k3x_saf_1_0_4 This is causing a cascade of 20 build failures across Middleware, OS, Startup_Code, and SAF modules. Could you please advise whether s32k3x_saf_1_0_4 includes the sCheck library, and if not, which package version we should install? Attached is the full build log, installed packages list, and a screenshot of the missing headers for your reference. Re: Build Error in 1500V BMS Reference Application – SAF Library Errors Hello @GauravXB, This is because you are using the EVAL version of the SAF library, which is available for free. danielmartynek_0-1781528505723.png The header files are only included in the FULL version of the library, which is a paid (premium) software package. https://www.nxp.com/design/design-center/software/functional-safety-software/s32-safety-software-framework-saf-and-safety-peripheral-drivers-spd:SAF Regards, Daniel

MBDTの参考例：RD-BESS1500BUN（1500V）および400V BMS設計 NXPコミュニティの皆様、こんにちは。 当社は、最新の互換性のあるMBDTバージョンとMATLAB R2023aを使用して、1500V（RD-BESS1500BUN）および400Vのバッテリーパック両方に対応するBMSソリューションを開発しており、S32K358 BMUおよびMC33774A CMUを対象としています。3つの分野に関していくつか質問がありますので、ご助言、参考となるモデル、または関連ドキュメントなどをご提供いただければ幸いです。 1. MBDTリファレンス例 – RD-BESS1500BUN（1500V設計） NXPは、RD-BESS1500BUNハードウェアを対象としたMBDT/Simulinkのリファレンスモデルまたはサンプルプロジェクトを提供していますか？私たちは特に、以下の点を示す出発点を探しています。 CMU初期化 セル電圧と温度の測定 S32K358 BMUとMC33774A CMU間の通信 基本的なデータ取得および監視フレームワーク 2. 400V設計サポート 弊社が設計する400V（S32K358ベース）パックに関して、MBDTに既に提供されているサンプルプロジェクトを基に、以下の点についてご指導をいただきたいと考えています。 a. MBDTにおけるSBCの統合 Simulink内でのSBC構成 覚醒マネジメントおよび監視サービス SPI通信の実装 b. コンタクタドライバ制御 MBDTフレームワーク内でのコンタクタ制御 プリチャージおよびコンタクタシーケンスロジック ドライバーの状態とフィードバックの監視 推奨されるアーキテクチャとベストプラクティス 3. アプリケーション層リファレンス BMSアプリケーション層が以下の項目を網羅していることを示す参考例はありますか？ BMSステートマシン（初期化 → 準備完了 → 実行 → 障害） 障害検出および処理フレームワーク SoC推定統合 電流および電力制限の計算 セーフティ監視の概念 高レベルのリファレンスモデル、アプリケーションノート、またはサンプルプロジェクトだけでも非常に役立ちます。

No Flash Algorithms for S32K388 in CMSIS Pack I am attempting to use the S32K388 in a number of designs but I see there are no flash algorithms for it in the CMSIS pack - https://www.keil.arm.com/packs/s32k3xx_dfp-keil/devices/ Is there plans to add this? How quickly could I get an updated file for this? Re: No Flash Algorithms for S32K388 in CMSIS Pack Hi@kscz This is beyond our support scope. you should seek for help from KEIL support. Based on current information, KEIL's DFP package hasn't been updated and doesn't support all S32K3 models. You will need to implement your own S32K388 programming algorithm. (I have created a KEIL question thread to inquire about future update plans for the S32K3 DFP.) Re: No Flash Algorithms for S32K388 in CMSIS Pack Bummer - I was hoping I wouldn't need to figure out how to write my own flashing algorithm... I can translate the rest of the fields based on things like the memories files, but the flashing algorithm is currently a bit beyond my knowledge. Do you have a link to the Keil thread? Do you happen to have any insight into why the current DFP is deprecated? Re: No Flash Algorithms for S32K388 in CMSIS Pack Hi@kscz copy the content for your reference: " The pack S32K3xx.DFP is clearly marked as 'Deprecated'. Please see: https://www.keil.arm.com/packs/s32k3xx_dfp-keil/devices/ This means that there will be no further updates from our company. We stopped maintaining DFPs for NXP quite some time ago, and NXP created lots of DFPs for other devices, but obviously not for this series. So it's up to NXP to create a new DFP for the S32K3 series.  " Meanwhile, I'm trying to confirm with the development team whether NXP will continue to support the DFP package. However, I haven't received any information yet. Re: No Flash Algorithms for S32K388 in CMSIS Pack Any updates? Will NXP support updating these tools in the Keil toolchain? Re: No Flash Algorithms for S32K388 in CMSIS Pack Hi@kscz Sorry, I forgot to forward the message I received to you. The internal response was very clear. "So far, NXP have not plan to update the S32K3xx' DFP of KEIL ."

SEC_CONFIG fuse on iMX8 Mini Hi, I'm trying to enable secure boot on a custom hardware platform based on iMX8 Mini. By following the available documentation, I was able to create a boot image with correct signatures, I'm sure about that because the hab_status command did not show any hab event and also the image verifier tool did not show any error. To close the device, I programmed the SRK_HASH fuses and the SEC_CONFIG fuses, but after this step my board does not start anymore and does not show anything on serial console. I'm quite sure that the SRK_HASH has been programmed properly, but I have doubts on SEC_CONFIG: to enable secure boot I should have used the below command: fuse prog 1 3 0x02000000 that sets bit 25. However, before doing the modification, I read the content of SEC_CONFIG and I saw the below value: fuse read 1 3 0x8000000 So, since I saw bit 27 set to 1, I had the great idea to use the below command: fuse prog 1 3 0x0A000000 To preserve bit 27 and set bit 25. Question: Is it possible that the above command put SEC_CONFIG to an invalid value so that the ROM bootloader does not even start the SPL? If yes, is there any way to restore the board? Best Regards Re: SEC_CONFIG fuse on iMX8 Mini Hi, many thanks for your answer, this is coherent with the current behaviour. Only a last question: Since I did not program any lock bit, do you think that using an hardware debugger would it be possible to restore the board? Best Regards Re: SEC_CONFIG fuse on iMX8 Mini If the chip became bricked after the reserved bits were written, then it is impossible to restore the chip, because the fuse operation is a one-time and irreversible process. Re: SEC_CONFIG fuse on iMX8 Mini Bit 27 is a reserved bit and cannot be programmed by the customer. Rather than whether this command(fuse prog 1 3 0x0A000000) will invalidate sec_config, it is more likely that the behavior of the entire chip will become unpredictable. Re: SEC_CONFIG fuse on iMX8 Mini Hello, Unfortunately, no, not by clearing fuses, eFuses are one-time programmable. Once sec_config is blown, you cannot “unblow” it

FS32K144UAVLL晶振问题！ 经理： 我们使用FS32K144UAVLL，晶振使用20MHZ，匹配电容10PF，负载电阻1MR，晶振单端对地正弦波20MHZ，0.5Vp-p, MCU使用外部晶振不能跑程序，但使用内部晶振可以。 使用开发板程序，开发板FS32K144HFVL，使用8MHZ晶振，匹配电容22PF，负载电阻1MR，晶振单端对地正弦波8MHZ，1Vp-p。 请问： 1. FS32K144UAVLL和FS32K144HFVL有什么区别？程序可以共用吗？外部晶振需要一样吗？ 2. FS32K144UAVLL外部晶振振幅多大合格？ 3. 怎样调整外部晶振振幅大小？ 谢谢！ 回复： FS32K144UAVLL晶振问题！ 你好@YF666666  在 S32K1xx 数据手册的第 4 节中指出，M 温度范围（–40°C 至 125°C）不支持 112 MHz 的核心频率。 建议您参考数据表中附带的 S32K1xx_Orderable_Part_Number_List.xlsx 文件，以核实可用的部件编号，并确定符合您要求的选项。 Re: FS32K144UAVLL晶振问题！ 你好@YF666666  1。设备差异 FS32K144UAVLL U：核心频率最高可达 112 MHz 答：包括 CAN FD、FlexIO 和网络安全功能 FS32K144HFVLL H：核心频率最高可达 80 MHz F：包括 CAN FD 和 FlexIO（无网络安全功能） 2。S32K1xx 系列支持 4 MHz 至 40 MHz 范围内的外部晶体或谐振器。 3.您可能会发现以下文档对晶振（晶体振荡器）设计和振幅注意事项很有帮助： AN14518：晶振（晶体振荡器）设计指南 AN5426：S32K1xx 硬件设计指南 这些参考资料提供了有关振荡器配置、负载电容器和设计最佳实践的详细指导。 BR、VaneB 回复： FS32K144UAVLL晶振问题！ 经理： FS32K144UAT0VLLT主频112MHZ，工作温度范围是-40°~ +105°吗？ 我们在汽车上使用，需要车规级温度范围-40°~+125°， 芯片型号修改为FS32K144UAT0MLLT，主频112MHZ，LQFP100，型号对吗？ 如果型号不对请发来正确型号，谢谢！ Re: FS32K144UAVLL晶振问题！ 您可以尝试使用FS32K144UAVLL，搭配 8 MHz 晶振（晶体振荡器）、22 pF 耦合电容和 1 MΩ 负载电阻。

LS2088ARDB: How to recover when QSPI Flash is corrupted Hi I was able to boot LS2088ARDB in QSPI-Boot mode. The QSPI-FLash has some preflashed boot images (bl2_qspi.pbl, RCW, fip.bin). Accidentally I erased the boot images in QSPI-FLash. Now the board does not boot in QSPI-Boot mode. I used Lauterbach JTAG - Trace32 and used the script `present at the path  C:\T32\demo\arm\hardware\ls208x\ls2088a\ls2088a-rdb\ls2088a_sieve_sram_failsave.cmm The script does the below 1)override RCW_src=Hardcoded, 2)JTAG Uses the basic RCW present int he script and boots 3)Loads basic app into internal RAM Question:  1) Can you provide us with a script which will configure clocks and DDR so that we can load U-boot onto RAM. 2) Also please provide steps OR correct me if my recovery steps are not proper. 3) Also in the path C:\T32\demo\arm\flash we dont see flash script for ls2088ardb. Can you please provide if you have it. Thanks and Regards Re: LS2088ARDB: How to recover when QSPI Flash is corrupted NXP only provides CodeWarrior to the customer. You could refer to section "9.4 Board recovery in case of missing/corrupt RCW in IFC memory" in the attached CodeWarrior document. Please refer to the attached CodeWarrior initialization file for LS2088ARDB.

imx95 M7 ブート こんにちは、 Cortex M7をU-Bootから起動する方法を教えていただけますか？ cortex a55/ubootはM7のTCMにアクセスできないようで、そのためイメージをロードすることができません。一方、M7が0x9000 0000でリリースされると、M33はクラッシュした。 uboot バージョン 04.2025 では、uboot コマンド (bootaux、prepaux、stopaux) は全く効果がないようです。 M33上のSMを使用してM7を起動しようとしましたが、停止やブートベクターの変更はできますが、DDRメモリ上で解放するとエラーが発生します。 M7をubootまたはSMで正しく起動する方法、あるいはM7のDDRアクセスを許可する方法について、何かヒントをいただけますか？ お手数ですが、よろしくお願いいたします。 Re: imx95 M7 boot こんにちは、 次のアプリケーションノートをご覧になることをお勧めします。 https://docs.nxp.com/bundle/AN14748/page/topics/introduction.html よろしくお願いいたします。 Re: imx95 M7 boot こんにちは、 ご返信よろしくお願いします。 残念ながら、あなたが言及したアプリケーションノートには、UbootからもM33のSMからもM7コアの起動方法が説明されていません。 また、M7にDDRアクセスを提供するプラットフォームの設定方法についても触れられていません。 これらのトピックについて手伝ってもらえますか?何かご提案はありますか？booaux、prepaux、stopauxコマンドはいつU-Bootに完全に実装され、使用可能になりますか？ よろしくお願いいたします！ Re: imx95 M7 boot こんにちは、 セクション4.7.4.1.5をご覧ください。i.MX Linuxユーザーガイド i.MX 95ページ。 よろしくお願いいたします。 Re: imx95 M7 boot 以下の手順に従うことで、なんとか動作させることができました。 fatload mmc 0:1 ${loadaddr} mcore-demos/imx95-15x15-evk_m7_TCM_hello_world.bin cp.b ${loadaddr} 0x203c0000 ${filesize} rproc stop 0 rproc 開始 0 ただし、そのためにはimx-system-マネージャの設定(imx95evk-configs/mx95evk.cfg)を編集する必要があります。アクセスを許可する必要があります A55非セキュアLMM用のTCMメモリ。 私の変更点（LMM_1をNOTIFYからALLに設定し、TCMとM7MIX領域をA55非セキュアに追加）： -LMM_1 通知 +LMM_1 すべて -OCRAM EXEC、開始=0x0204C0000、サイズ=96K +M7MIX EXEC、開始=0x020380000、終了=0x02047FFFF +OCRAM EXEC、開始=0x020480000、サイズ=352K +M7MIX EXEC、開始=0x04A060000、終了=0x04A09FFF Rebuild: imx-system-managerフォルダ内の - make config=mx95evk cfg - perlの再構築ファイル用にchagesを処理します。その後、Yoctoでパケットを再構築します: bitbake -f -ccompile imx-system-マネージャ bitbake imx-system-マネージャ bitbake -f -ccompile imx-boot bitbake imx-boot その後、U-bootからTCMメモリにアクセスできます。 しかし、私には別の問題があります。U-Boot内のファイルシステムからM7コードをリアルタイムで更新する必要があるのです。しかし、そのコードはTCM地域には適合しません。だから私はDDRを使っているんです。コードは正常に起動でき、DDRで完全に実行・ロードされますが、u-bootを使ってリアルタイムで更新する方法がわかりません。なぜならu-bootは0x90000000からDDRにアクセスできるからです......。 M7コード使用地域は0x80000000...このメモリ領域は、imx-system-マネージャ(.cfg)だけでなく、u-bootソースを通じてもu-bootから利用できません。これは、2つの異なるLMM間でメモリを異なるメモリ領域に分離するために意図的に行われたものだと思います。 M33コード(imx-system-マネージャ)を使ってM7のコードを更新したいと思い、このLMM(m33)に両方のリージョンを追加しましたが、M7リージョンだけが完全に見えてしまいます(0x80000000...)。U-boot領域(0x90000000)は見えるが、m33側からはゼロが読み取れる... Re: imx95 M7 boot こんにちは、 私のシステムにはrprocはありませんが、bootauxがあります。このコマンドはU-Bootでは何も実行しません。 私はこうしてM7を始動させることができました。 イメージを0x88000000に読み込むと、Cortex AとM7で共有されている32MBのスペースがありますが、U-Bootから読み書きするにはdcacheを無効にする必要があります System Managerのrst.wコマンドでコアを停止し、cpu.wコマンドでブートベクターを0x8800 0000に設定し、再びrst.wでM7コアを起動します。 これは私には効果がありました。 幸運を

S32K324 部署FreeRTOS SMP 你好，恩智浦的工程师：     我需要在S32K324芯片(多核)上运行FreeRTOS SMP, 我在参考S32K358_SMP的示例程序时发现并未对SMP进行任何相关配置(如图)  Wanyj_0-1781488803614.png 我使用的版本为RTD 5.0.0及FreeRTOS 5.0.0,我的问题点为： 1、S32K324(多核)这款芯片是否支持部署FreeRTOS SMP 2、请问贵司是否有其他关于它的参考示例？或者在更新的版本中加入了它的相关参考？ 期待您的回答 Re: S32K324 部署FreeRTOS SMP Hi@Wanyj 我们对FreeRTOS提供的技术支持有限，关于FreeRTOS的SMP功能，这应该是支持的。 你可以参考一下这个例程，这是我能找到的关于SMP使用的一个完整例程。 https://community.nxp.com/t5/S32K-Knowledge-Base/S32K3xx-FreeRTOS-SMP/ta-p/2292229

異種核 この仕様のMCUを発売する予定はありますか？ Cortex-A55 20倍 + Cortex-M7 10倍 Re: 异构核 こんにちは、 @r59461900さん。 現在のロードマップには、同等の仕様を持つチップは含まれていません。 よろしくお願いします、 志明

How to configure H.264 encoder bitrate when using H.264 encoder as part of the ISP graph We would like to know if the bitrate used for H.264 compression is configurable in the VSDK or if it is hardcoded when using the H.264 encoder as part of the ISP graph? S32 SDK for S32V Re: How to configure H.264 encoder bitrate when using H.264 encoder as part of the ISP graph Hello @mrosar11, I was not able to get an exact answer for your question with the available documentation. I will raise this topic with the internal team and I will get back to you once I have their feedback. Regards  Re: How to configure H.264 encoder bitrate when using H.264 encoder as part of the ISP graph Hello @mrosar11, I have have received feedback from the internal team. You can configure the bitrate according to your needs using the mBitsPerMbrw member of the H264ENC_Config_t struct, for instance, you could add the following line in the isp_sonyimx224_h264enc sample project: alejandro_e_0-1781632857787.png Let me know if you have more questions.

在 NVM 目录中导入经过身份验证的密钥时遇到 HSE_SRV_RSP_INVALID_ADDR 问题 您好，NXP团队： 我目前正在与HSE合作处理S32K3xx项目，并尝试将授权密钥导入NVM密钥目录槽中。 为此，我创建了一个容器，并执行了CMAC操作以获取TAG。然而，当我使用“导入”服务导入该密钥时，收到了来自 HSE 的响应HSE_SRV_RSP_INVALID_ADDR。 请您查看提供的代码片段，并指导我如何正确完成此操作？ uint8_t keyContainer[496]__attribute__((section(".mcal_bss_no_cacheable"))); static hseKeyInfo_t AuthkeyInfo__attribute__((section(".mcal_data_no_cacheable"))); uint8_t containerTag[16]__attribute__((section(".mcal_bss_no_cacheable"))); uint32_t containerTagLen__attribute__((section(".mcal_data_no_cacheable"))) = sizeof(containerTag);   //void fillContainer(uint8_t* pContainer, hseKeyInfo_t* pkeyInfo, uint8_t keyInfoLen, uint8_t* pkey, uint8_t keyLen) void fillContainer(void) {   AuthkeyInfo.keyBitLen = 128; AuthkeyInfo.keyType = HSE_KEY_TYPE_AES; AuthkeyInfo.keyFlags = HSE_KF_USAGE_ENCRYPT | HSE_KF_USAGE_DECRYPT; //| HSE_KF_USAGE_KEY_PROVISION; AuthkeyInfo.keyCounter = 0; // 在首次导入 NVM 密钥时，该值应大于或等于 0。 AuthkeyInfo.smrFlags = 0; AuthkeyInfo.specific.aesBlockModeMask= HSE_KU_AES_BLOCK_MODE_ANY;   unsigned int i = 0; i = i + 10; memcpy(&keyContainer[i],&AuthkeyInfo, sizeof(hseKeyInfo_t)); i = i + sizeof(hseKeyInfo_t); i = i + 5; memcpy(&keyContainer[i], App_au8EncAesNvmKey, sizeof(App_au8EncAesNvmKey)); }   hseSrvResponse_t AppGenCmac(void) { uint8_t u8MuInstance = 0U; hseSrvDescriptor_t* pCmacGenSrvDescriptor; hseSrvResponse_t RetVal = HSE_SRV_RSP_GENERAL_ERROR; uint8_t muChannel = Hse_Ip_GetFreeChannel(u8MuInstance);   pCmacGenSrvDescriptor =&Hse_aSrvDescriptor[muChannel]; hseMacSrv_t* pMacSrv =&pCmacGenSrvDescriptor->hseSrv.macReq;   pCmacGenSrvDescriptor->srvId = HSE_SRV_ID_MAC; pMacSrv->accessMode = HSE_ACCESS_MODE_ONE_PASS; pMacSrv->sgtOption = HSE_SGT_OPTION_NONE; pMacSrv->streamId = 0; pMacSrv->authDir = HSE_AUTH_DIR_GENERATE; pMacSrv->macScheme.macAlgo = HSE_MAC_ALGO_CMAC; pMacSrv->macScheme.sch.cmac.cipherAlgo=HSE_CIPHER_ALGO_AES; pMacSrv->keyHandle = GET_KEY_HANDLE(1,1,0); //标准AES密钥 pMacSrv->inputLength = sizeof(keyContainer); pMacSrv->pInput = (HOST_ADDR)keyContainer; pMacSrv->pTagLength = (HOST_ADDR)&containerTagLen; pMacSrv->pTag = (HOST_ADDR) containerTag;   HseIp_aRequest[muChannel].eReqType = HSE_IP_REQTYPE_SYNC; HseIp_aRequest[muChannel].u32Timeout = TIMEOUT_TICKS_U32;   /* 向 Hse Ip 层发送请求 */ RetVal = Hse_Ip_ServiceRequest(u8MuInstance, muChannel,&HseIp_aRequest[muChannel], pCmacGenSrvDescriptor); return RetVal; }   /*   如果我拥有超级用户权限，是否可以在不进行身份验证的情况下，将加密密钥导入 RAM/NVM 目录？ -不是。HSE 服务 API 参考手册明确规定： “加密密钥必须经过身份验证后才能导入。” 这适用于普通用户权限和超级用户权限。 */   static hseSrvResponse_t App_AesLoadAuthNvmKey(void) { hseSrvResponse_t RetVal = HSE_SRV_RSP_GENERAL_ERROR; hseSrvDescriptor_t *pHseSrvDescriptor; uint8 u8MuChannel = Hse_Ip_GetFreeChannel(MU0_INSTANCE_U8);     if(HSE_IP_INVALID_MU_CHANNEL_U8 != u8MuChannel) { pHseSrvDescriptor =&Hse_aSrvDescriptor[u8MuChannel]; memset(pHseSrvDescriptor, 0, sizeof(hseSrvDescriptor_t));   pHseSrvDescriptor->srvId = HSE_SRV_ID_IMPORT_KEY; pHseSrvDescriptor->hseSrv.importKeyReq.keyLen[2]= 16; pHseSrvDescriptor->hseSrv.importKeyReq.pKey[2]= HSE_PTR_TO_HOST_ADDR(App_au8EncAesNvmKey); pHseSrvDescriptor->hseSrv.importKeyReq.pKeyInfo=HSE_PTR_TO_HOST_ADDR(&AuthkeyInfo); pHseSrvDescriptor->hseSrv.importKeyReq.targetKeyHandle= GET_KEY_HANDLE(1,1,2);   // 以下两个字段必须进行配置。 pHseSrvDescriptor->hseSrv.importKeyReq.cipher.cipherKeyHandle= HSE_INVALID_KEY_HANDLE; // pHseSrvDescriptor->hseSrv.importKeyReq.cipher.cipherScheme.symCipher.cipherAlgo = HSE_CIPHER_ALGO_AES ; // pHseSrvDescriptor ->hseSrv.importKeyReq.cipher.cipherScheme.symCipher.cipherBlockMode= HSE_CIPHER_BLOCK_MODE_ECB ; // pHseSrvDescriptor->hseSrv.importKeyReq.cipher.cipherScheme.symCipher.ivLength = ; // pHseSrvDescriptor->hseSrv.importKeyReq.cipher.cipherScheme.symCipher.pIV = ;   pHseSrvDescriptor->hseSrv.importKeyReq.keyContainer.authKeyHandle= GET_KEY_HANDLE(1,1,0); pHseSrvDescriptor->hseSrv.importKeyReq.keyContainer.authLen[0]= containerTagLen; pHseSrvDescriptor->hseSrv.importKeyReq.keyContainer.authScheme.macScheme.macAlgo = HSE_MAC_ALGO_CMAC ; pHseSrvDescriptor->hseSrv.importKeyReq.keyContainer.authScheme.macScheme.sch.cmac.cipherAlgo=HSE_CIPHER_ALGO_AES; pHseSrvDescriptor->hseSrv.importKeyReq.keyContainer.keyContainerLen= sizeof(keyContainer); pHseSrvDescriptor->hseSrv.importKeyReq.keyContainer.pAuth[0]= (HOST_ADDR)containerTag; pHseSrvDescriptor->hseSrv.importKeyReq.keyContainer.pKeyContainer= (HOST_ADDR)keyContainer;     /* 生成要发送到 Hse Ip 层的请求 */         HseIp_aRequest[u8MuChannel].eReqType = HSE_IP_REQTYPE_SYNC;         HseIp_aRequest[u8MuChannel].u32Timeout = TIMEOUT_TICKS_U32;   /* 向 Hse Ip 层发送请求 */         RetVal = Hse_Ip_ServiceRequest(MU0_INSTANCE_U8, u8MuChannel,&HseIp_aRequest[u8MuChannel], pHseSrvDescriptor); } return RetVal; }   感谢您的支持。 此致，拉希凯什 Re: Facing the HSE_SRV_RSP_INVALID_ADDR issue while importing authenticated key in NVM catalog 谢谢@lukaszadrapa。 有效。 Re: Facing the HSE_SRV_RSP_INVALID_ADDR issue while importing authenticated key in NVM catalog 你好@KaleRushikesh  看起来您正在传递原始键和 KeyInfo 的地址： pHseSrvDescriptor->hseSrv.importKeyReq.pKey[2]= HSE_PTR_TO_HOST_ADDR(App_au8EncAesNvmKey); pHseSrvDescriptor->hseSrv.importKeyReq.pKeyInfo=HSE_PTR_TO_HOST_ADDR(&AuthkeyInfo); 但你需要在容器内部使用密钥和 KeyInfo 的地址。如果 HSE 发现您试图从不在容器范围内的地址提供密钥和 KeyInfo，它将返回地址无效的错误。 此致， Lukas

Wi-Fi 命令响应超时 我正在使用基于恩智浦 IW612 芯片组的 i.MXRT1062 跨界微控制器和村田 2EL M.2 无线卡开发一个项目。该项目使用了 MCUXpresso SDK 和 FreeRTOS。当前 SDK 版本为 25.12。 在固件运行过程中，调试控制台有时会显示以下输出： `[wifi] 警告：命令响应超时。命令 0x0，长度 1514，序列号 0x16` 或 `[wifi] 警告：命令响应超时。命令 0x0，长度 66，序列号 0x16` 或 `[wifi] 警告：命令响应超时。命令 0x0，长度 190，序列号 0x16` 或 `[wifi] 警告：命令响应超时。命令 0x0，长度 60，序列号 0x16` 我不知道这些行是什么意思，可能是无线模块出了问题。打印任务列表之后，会触发紧急情况并使固件停止运行。我认为这个问题通常发生在通过无线网络连接进行流量大小不一的传输约30分钟后。 SDK 文件中的相应位置位于 `wifi_wait_for_cmdresp` 函数中的 `中间件/wifi_nxp/wifidriver/wifi.c` 中。这一点还进一步得到证实：在之前的调试控制台输出与这一行之间，大约有20秒的间隔。 我该如何排查这个问题？我可以与您合作，提供进一步的调试信息或测试 SDK 的修复方案。 Re: Wi-Fi command response timeout 您好， 我知道您正在使用一个自定义应用程序，但您是以哪个 SDK 示例作为起点开发的？如果您能使用未经修改的 SDK 示例重现相同的问题，这将极大有助于定位问题。 看来驱动程序一直在等待命令响应，但在超时结束前并未收到响应。 请在 wifi_config.h 中启用以下调试宏： CONFIG_WIFI_CMD_RESP_DEBUG CONFIG_WIFI_EVENTS_DEBUG CONFIG_WIFI_IO_INFO_DUMP CONFIG_WIFI_EXTRA_DEBUG 启用宏后，请重新编译示例并再次进行测试。请分享输出结果。 最好用最新的 SDK 进行测试，看看问题是否依然存在。 Re: Wi-Fi command response timeout 这是固件卡住时的调试输出。如果您需要之前的日志行，请告诉我。 2026年6月23日 12:27:48.808 [RX] - [wifi] 警告：命令响应超时。命令 0x0，长度 890，序列号 0x16 SDIO多端口组寄存器值： **** 转储 @ 20218FC0 长度：196 **** 00 00 00 00 ff 00 00 00 c3 00 00 00 00 00 00 00 00 00 00 00 00 00 f0 7f 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 03 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 00 00 00 00 00 87 0c 00 00 00 00 00 00 00 00 00 00 1c c2 06 c0 f4 德 09 c0 00 1e ff ff 00 0a 36 01 00 00 96 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 10 cc f0 ff ff ff ff ff 00 00 ff ff ff ff ff ff f4 74 04 c0 80 98 04 c0 00 00 00 00 ******** 结束转储 ******* 名称 状态 优先级 堆栈号 ================================================== 主任务 X 3 581 6 print_dhcp R 0 683 17 空闲 R 0 92 2 tcp/ip B 3 400 1 Tmr Svc B 4 196 3 supplicant_main_tas B 2 1456 14 nfc_cfg B 0 715 7 dhcpd_task B 3 406 15 HTTP 服务器 B 1 888 18 wifi_scan_task B 1 255 11 wlcmgr_task B 3 244 13 wifi_drv_task B 3 228 10 lwip_rx B 3 431 8 wifi_core_task B 3 276 12 [wifi] 开始处理挂起 [wifi] 正在发起 wifi 身份验证 [固件下载] S 2026年6月23日 12:27:48.824 [RX] - 开始从 0x602319fc 下载固件：1618224 2026年6月23日 12:27:54.807 [RX] - [wifi_io] 错误：SDIO - 固件就绪寄存器未设置 [wifi] 错误：sd_wifi_reinit 失败。状态码-1 断言：wlan_process_hang：550 断言失败：恐慌！ 断言错误“0”：文件“C:/tmp/mcuxsdk/mcuxsdk/中间件/wifi_nxp/wifidriver/incl/mlan_api.h”第65行函数名“panic” Re: Wi-Fi command response timeout @DanielRuvalcaba你好，请问这个问题有任何进展吗？SDK 26.03 版本也存在这个问题，您还需要我提供更多调试信息吗？ Re: Wi-Fi command response timeout 你使用的是哪个SDK示例？ 请问能否提供重现此问题的步骤？ 您使用的是定制电路板还是恩智浦参考电路板？ 是否存在任何特定的操作或条件会持续触发该问题？ 问候， 丹尼尔。 Re: Wi-Fi command response timeout 我最初使用的是 wifi_setup SDK 示例，但现在已经做了很大的修改。我使用的是定制板。 我们注意到，当无线网卡接收（可能发送）流量较大（每秒 60 兆字节或更多）时，就会出现此问题，同时固件会向无线网卡发送命令以查询平均 RSSI 和 SNR。我们的代码每秒执行一次该操作，问题通常会在一分钟内（通常更短）被触发。 如果我禁用命令传输，就不会触发该问题。 我希望这些信息能帮助您重现该问题（关键时刻是接收流量和命令传输同时进行）。

RT118x 是如何实现对多张图像选择和加载的支持的？ 目前，我的开发环境是 MCUXpresso IDE。在 SDK 中，多核示例由一个主项目和一个从项目组成。此外，在主项目中，只能指定一个从属映像文件的位置。我想实现一个功能：将一个 CM33 镜像和多个 CM7 镜像烧录到 Flash 中。CM33 核心启动后，将根据交换机状态或其他配置项，将不同的 CM7 镜像加载到内存中以供运行。 如何实现这一点？有什么例子吗？ Re: How does RT118x achieve the support for multiple images selection loading? 你好@ethan_dang1、 感谢您对 NXP MIMXRT 系列的关注！ RT118x 支持此用例，但无法通过现成的 ROM/MCUXpresso IDE 功能来实现——该功能无法从多个候选项中自动选择一个 CM7 镜像。   RT118x 启动容器可以描述多个镜像，但这是一种固定的启动映像/容器机制，而不是基于 GPIO/Switch 的运行时选择策略。对于请求的行为，应将 CM33 实现为自定义启动管理器。CM33 启动后，它读取开关/配置，选择一个存储在 Flash 中的 CM7 镜像，将其加载到预期的目标内存中，配置 M7 向量/启动条件和访问权限，然后释放/启动 CM7。 目前尚无已确认的 SDK 示例直接实现“一个 CM33 镜像 + 多个可选 CM7 镜像”的功能。最接近的参考资料是多核示例、multicore_trigger、RT1180 M7 启动程序和动态代码加载/叠加概念。 对此给您带来的不便，我们深表歉意！   致以最诚挚的问候， Gavin

MR-CANHUBK344 MR_CANHUBK3_IEEE1722 Project for newer S32DS Hello! I'm following the "Start Building With MR-CANHUBK344s" post as a getting started project to test the capabilities of the MR-CANHUBK344 board since it is exactly what I need for an automotive on-going project. Te project as-is does not compile and could not be loaded into the board. The dependencies needed for the out-of-box project are as follows: S32DS 3.4 FreeRTOS for S32K3 2.0.0 (Not found on downloads website) S32K3 RTD AUTOSAR® 4.4 Version 2.0.0  S32K3xx development package Version 3.4.3 I have unsuscessfully tested a couple of setups already with current and previuos software versions like: S32DS 3.5.x S32DS 3.6.x Both with different versions of RTD drivers, and S32Kxx development package versions and also different FreeRTOS version. From the get-go the main issue is that the dependencies needed are no longer suported on new software versions and also the dependencies specified on the getting started document are no longer available to download from NXP's website. Could NXP provide the required dependancies for a local test of the IEEE1722 bridge getting started example or is the manual porting the only option to follow if I need to test that specific app? Re: MR-CANHUBK344 MR_CANHUBK3_IEEE1722 Project for newer S32DS Hi @Mianromo  Could you please help me check if, on the page where you download the FreeRTOS update site for S32DS, there is a “Previous” tab available? If yes, could you also take a look and let me know if you can see the SW32K3_FreeRTOS_10.4.6_2.0.0_D2204 package listed there? BR, VaneB Re: MR-CANHUBK344 MR_CANHUBK3_IEEE1722 Project for newer S32DS Hello @VaneB, Does the "Escalate" button works the same as requesting a Support Ticket? Best Regards, Re: MR-CANHUBK344 MR_CANHUBK3_IEEE1722 Project for newer S32DS Hi @Mianromo  Could you please help check if you are able to access the desired software version through this link? Note: Before accessing the link, please make sure to log in to flexnetoperations. You can do this via My NXP Account → Software Licensing and Support → Software Accounts. If no, please submit a support ticket so we can provide you with further assistance. Re: MR-CANHUBK344 MR_CANHUBK3_IEEE1722 Project for newer S32DS Hello @VaneB, This is where I am looking for that specific file that is being mentioned in similar post regarding the same issue: https://nxp.flexnetoperations.com/control/frse/product?child_plneID=833477# On that webpage several versions for the FreeRTOS package are available for download but that one you mention is not listed. The "Previous" tab is shown but it is grayed out and unclickable. Attached image is for reference. The other packages that are needed for the "Start Building With MR-CANHUBK344s" guide were downloaded from their respective previous tab but I'm missing the FreeRTOS one for it to compile as-is. Best regards, Re: MR-CANHUBK344 MR_CANHUBK3_IEEE1722 Project for newer S32DS Hello @VaneB, The link you provided sent me to this url: https://www.nxp.com/mynxp/profile Mianromo_0-1781632141137.png I made sure to be logged in before clicking on it. I guess the only option would be the support ticket. Best regards, Re: MR-CANHUBK344 MR_CANHUBK3_IEEE1722 Project for newer S32DS Hi @Mianromo  Thank you for your help in submitting the ticket. I have already replied to you through that channel.

LPC54xxx: Physical type of internal boot-ROM. What physical type of internal boot ROM is used in the LPC54005JBD100 or LPC54S005JBD100 (and other LPC54xxx)? Is it mask ROM? Or flash memory with write/erase functions disabled? Is it possible to load firmware into this microcontrollers from external SPI-MRAM memory (ex. MR25H40)? (memory located on the SPIFI or on the SPI bus). Or similar memories (FRAM, FeRAM (ex. MB85RS4MT). Insteed of FLASH. PS: This information is needed to select the appropriate MCU for a new device. LPC54xxx Re: LPC54xxx: Physical type of internal boot-ROM. Thank for you answer! My question wasn't about the ability to writing or erasing ROM LPC540xx (everything is clear here). My question was about the physical implementation of ROM-cells in LPC540xx. Boot-ROM in microcontrollers can be implemented either as a mask-ROM, or as flash-memory with disabled write/erase (or in some other way). I also know that microcontroller's manufacturers often implement boot-ROM based on flash-memory (physically = flash-cells), but with write-protected firmware. This flash-memory is programmed with firmware into the microcontroller during manufacturing. What is mask-ROM I mean: Mask ROM is a type of non-volatile read-only memory where data is physically hardcoded into the microchip during the semiconductor manufacturing process. Instead of being written electronically, the data (1s and 0s) is defined by the presence or absence of microscopic transistors or connections on the chip's photomasks. Which of these boot-ROM types (ROM-cells) is used in microcontrollers LPC540xx? Is there any documentation (or application note) about the boot-ROM-memory type in LPC540xx? The "MCX series MCUs" you recommended aren't suitable for our project according to the requirements specifications, as they contain flash memory. Besides these MCUs, we're also considering the i.MX RT1020 or LPC4370. What type of memory do they have? The LPC4370 and i.MX RT1020 are somewhat overkill for our needs. LPC540xx are preferable for us. What do you mean "legacy"? They're not marked as "NRND" on the NXP website. Re: LPC54xxx: Physical type of internal boot-ROM. Hello @jcxz  I’m not completely certain about the physical implementation of the boot ROM. However, I can confirm that it is not writable or erasable. There is no internal flash in LPC54005 and LPC54S005 devices, so the system can only boot from external memories such as SPI/SPIFI or parallel NOR flash.  Alice_Yang_0-1781495891637.png By the way, if you are preparing for a new project, I highly recommend considering the MCX series MCUs.  MCX Arm Cortex-M Industrial and IoT MCUs | NXP Semiconductors The LPC54xxx family is now considered legacy, while the MCX series represents NXP’s newer generation of products.  Thank you. BR Alice Re: LPC54xxx: Physical type of internal boot-ROM. Can somebody tell me about the technology of boot-ROM in LPC540xx? Or recommend some documentation about this? Application: civilian only.

imx95 M7 boot Hello, Can you please tell me how to boot the cortex M7 from uboot? It seems that cortex a55/uboot have no access to the TCM of M7, so it is not possible to load the image. On the other hand, the M33 crashed when the M7 is released on 0x9000 0000. It seems the the uboot commands (bootaux, prepaux, stopaux) have no effect at all, on uboot version 04.2025. I tried to boot the M7 with the SM on M33, I can stop it, change the boot vector, but releasing it on DDR memory causes an error. Can you give me some hints how to properly start the M7 with uboot or SM, or how to allow ddr access for the M7? Thank you in advance! Re: imx95 M7 boot Hello, I suggest you take a look in the next application note: https://docs.nxp.com/bundle/AN14748/page/topics/introduction.html Best regards. Re: imx95 M7 boot Hello, thank you for your reply. Unfortunately, the Application Note you mentioned, does not describe how to start the M7 core neither from Uboot, nor with SM on M33. It also doesn't mention how to configure the platform to provide DDR access to the M7. Can you help me with these topics? Do you have any suggestions? When will the booaux,prepaux and stopaux commands be fully implemented and usable in uboot? Thanks in advance! Re: imx95 M7 boot Hello, Please take a look in section 4.7.4.1.5 i.MX 95 of i.MX Linux User's Guide. Best regards. Re: imx95 M7 boot I managed to get it to work using the following instructions: fatload mmc 0:1 ${loadaddr} mcore-demos/imx95-15x15-evk_m7_TCM_hello_world.bin cp.b ${loadaddr} 0x203c0000 ${filesize} rproc stop 0 rproc start 0 But for this you need to edit the config imx-system-manager(for imx95evk-configs/mx95evk.cfg). You need to allow access to TCM memory for A55 non-secure LMM. My diff(Set LMM_1 from NOTIFY to ALL, add TCM and M7MIX region to A55 non-secure): -LMM_1                     NOTIFY +LMM_1                     ALL -OCRAM               EXEC, begin=0x0204C0000, size=96K +M7MIX                EXEC, begin=0x020380000, end=0x02047FFFF +OCRAM                EXEC, begin=0x020480000, size=352K +M7MIX                EXEC, begin=0x04A060000, end=0x04A09FFF Rebuild: in imx-system-manager folder - make config=mx95evk cfg - for perl rebuild files after chages. Then rebuild packets in yocto: bitbake -f -ccompile imx-system-manager bitbake imx-system-manager bitbake -f -ccompile imx-boot bitbake imx-boot After this there will be access to TCM memory from u-boot. But I have another problem: I need to update the M7 code from the file system in Uboot on the fly. But the code doesn't fit in the TCM region. That's why I'm using DDR. I've successfully launched the code, which runs and loads completely using DDR, but I don't know how to update it on the fly using u-boot, becaus u-boot have access to DDR from 0x90000000 .... M7 code use region from 0x80000000...This memory region not available from u-boot not only through imx-system-manager(.cfg), but also through the u-boot sources. I think this was done intentionally to separate memory across different memory regions between two different LMM. I wanted to update code M7 via the M33 code(imx-system-manager), added both regions for this LMM(m33), but only the M7 region is visible perfectly(0x80000000...). The U-boot region is visible(0x90000000), but the zeros are readable from m33 side... Re: imx95 M7 boot Hello, on my system I don't have rproc, but bootaux. The command does nothing in U-Boot. I managed to start the M7 like this. Load image to 0x88000000, there is a 32MB space which is shared my Cortex A and M7, but you have to disable dcache to be able to read/write to it from U-Boot Use System manager rst.w command to stop the core, cpu.w command to set boot vector to 0x8800 0000 and again rst.w to start the  M7 core. This worked for me. Good Luck