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system manager driver code for PCAL6524 could you please provide the system manager driver code for PCAL6524HEAZ fsl_pcal6524.c fsl_pcal6524.h Re: system manager driver code for PCAL6524 Dear Binson, I am not aware of an official MCUXpresso SDK/System Manager driver named fsl_pcal6524.cfsl_pcal6524.h for the PCAL6524HEAZ. NXP Linux BSPs support the device through the standard Linux GPIO-expander driver using the PCA6524 device-tree compatible string. The i.MX95 19x19 EVK is a public example that uses the PCAL6524 as an I²C GPIO expander: https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts   With Best Regards, Jozef
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Request for Software License Extension Due to Expiration   Dear Support Team, As shown in the attached image, I received an email notifying me that my S32DS license is about to expire. I need to continue using S32DS for my ongoing work. Could you please extend my license so that I can keep using the software? Thank you in advance for your assistance. Best regards,
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MFS2323BMBA5EP OTP Configuration Conflict: SPI vs I2C Mode Identification Dear NXP engineers and community experts, I am currently developing with the MFS2323BMBA5EP Safety SBC and have encountered a significant conflict between my configuration files and datasheet reports regarding the OTP factory configuration. I would greatly appreciate your expertise in clarifying this. The Configuration Conflict: 1. Evidence from the .cfg file: In my FS2320_BA5_CONFIG_Rev_A.cfg file, there is a direct register value: 0x30 : 0x00 According to the FS23 datasheet (Table 229, OTP_MAIN_SYS_I2C_CFG😞 Bit 4 (SPI_EN_OTP): 0 means I2C is enabled, SPI is disabled; 1 means SPI is enabled. Bit 3~0 (I2CDEVADDR_OTP): 0000 means the I2C slave address is 0x20. This clearly suggests the chip is factory-configured for I2C mode. 2. Evidence from the Configuration Report PDF: However, in my R_MFS2323BMBA5_Rev_A_test.pdf document, under Table 2. Device OTP configuration, the report explicitly states: SPI Enable: SPI pins are enabled. This suggests the hardware pins are locked to SPI mode. My Actual Hardware Test Results: When I configured my MCU (S32K344) as an SPI Master to communicate with this PMIC: The MISO pin stays at a constant 0.3V (indicating high-impedance with internal weak pull-down, meaning the slave is not driving the line). The SCK pin on the PMIC side was actually outputting clock signals on its own. I suspect the chip might be locked in OTP Emulation mode or configured as an I2C slave, which is causing the SPI communication to completely fail. My Specific Questions: Could you please confirm the actual factory OTP configuration for the MFS2323BMBA5EP? Is it SPI or I2C? When there is a conflict between the .cfg register file (0x30 : 0x00) and the PDF configuration report, which one should be considered the absolute hardware truth? Is there a possibility that the PDF report contains a documentation error? (I have attached the FS2320_BA5_CONFIG_Rev_A.cfg and the R_MFS2323BMBA5_Rev_A_test.pdf to this post for reference). Thank you in advance for your help! Re: MFS2323BMBA5EP OTP Configuration Conflict: SPI vs I2C Mode Identification Okay, thank you. Re: MFS2323BMBA5EP OTP Configuration Conflict: SPI vs I2C Mode Identification Which company are you from? Currently, you're using your own email address, which is considered a low-priority (C-level) customer. This requires checking your schematic and a series of things related to the CRC driver. I suggest you submit a ticket using your company email address. Home Re: MFS2323BMBA5EP OTP Configuration Conflict: SPI vs I2C Mode Identification Currently, it's not possible. I'm communicating in DEBUG mode. I've tested the SCK and MOSI waveforms on the 344 pin separately, and they can transmit the data I write. However, because the FS23's SCK pin is also sending a signal, when these two are connected together, the SCK signal sent by the MCU is pulled low by the FS23. The responses I send to the FS23 are all 0s. I've also configured CRC. The purple line represents the SCK signal after the top. Yellow indicates data signals. The scale is 5V. The data sent is {0x02, 0x00, 0x00, CRC} If you forcefully interpret the SCK waveform as a normal waveform, you can see that the data is correct; the first bit is 2, followed by 00 and CRC. Re: MFS2323BMBA5EP OTP Configuration Conflict: SPI vs I2C Mode Identification Can you successfully communicate using SPI? Re: MFS2323BMBA5EP OTP Configuration Conflict: SPI vs I2C Mode Identification Is it possible that the SCK signal of the FS23 is also being sent when communicating with the S32K344 via SPI? Because if I don't configure SPI communication with the FS23, there's no waveform when I try to capture the SCK pin of the FS23. Only when communicating with the S32K344 are both the SCK pins of the FS23 and the S32K344 sending signals, and the waveforms of the SCK and CS pins are exactly the same. Re: MFS2323BMBA5EP OTP Configuration Conflict: SPI vs I2C Mode Identification I uploaded the .cfg file to Mirror via the GUI. The register indicates SPI mode.
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PCAL6524 的系统管理器驱动程序代码 请问能否提供PCAL6524HEAZ的系统管理器驱动程序代码? fsl_pcal6524.c fsl_pcal6524.h Re: system manager driver code for PCAL6524 亲爱的宾森: 我不知道有名为fsl_pcal6524.cfsl_pcal6524.hf或 PCAL6524HEAZ 的官方 MCUXpresso SDK/系统管理器驱动程序。NXP Linux BSP 通过标准的 Linux GPIO 扩展器驱动程序,使用 PCA6524 设备树兼容字符串来支持该设备。i.MX95 19x19 EVK 是一个公开示例,它使用 PCAL6524 作为 I²C GPIO 扩展器: https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts   最诚挚的问候, 约瑟夫
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Reducing Power Consumption by Disabling CPU/GPU/VPU on i.MX95 Hi NXP, We are looking for ways to reduce the overall power consumption of our i.MX95-based system. Could you please help clarify the following questions? Is it possible to completely power down individual CPU cores when they are not required? Is it possible to completely power down the GPU and VPU if our application does not use them? If the CPU/ GPU / VPU is not required, is it possible to keep them disabled by default after boot to further reduce power consumption ? (by device-tree ?) Are there any recommended software configurations or reference documents for achieving the lowest possible power consumption? Our BSP is based on Yocto 5.2 / Linux 6.12.x. Thanks. Best Regards, Sean Linux
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MFS2323BMBA5EP OTP 配置冲突:SPI 与 I2C 模式识别 尊敬的恩智浦工程师和社区专家们: 我目前正在使用以下技术进行开发 MFS2323BMBA5EP 功能安全单板计算机 (SBC) 的配置文件与数据手册中关于一次性密码 (OTP) 出厂配置的报告存在重大冲突。非常感谢您能凭借专业知识对此进行澄清。 配置冲突: 1. 来自以下方面的证据 .cfg 文件: 在我的 FS2320_BA5_CONFIG_Rev_A.cfg 文件中,有一个直接的寄存器值: 0x30 : 0x00 根据 FS23 数据表(表 229), OTP_MAIN_SYS_I2C_CFG😞 位 4 ( SPI_EN_OTP ) : 0 方法 I2C 已启用,SPI 已禁用; 1 表示SPI已启用。 位 3~0 ( I2CDEVADDR_OTP ) : 0000 意思是 I2C 从机地址是 0x20 。 这清楚地表明该芯片是出厂时就已配置好的。 I2C模式。 2. 来自配置报告 PDF 的证据: 然而,在我的 R_MFS2323BMBA5_Rev_A_test.pdf 文件,在 表 2. 设备 OTP 配置,报告中明确指出: SPI 使能:SPI 引脚已启用。 这表明硬件引脚被锁定。 SPI模式。 我的实际硬件测试结果: 当我将我的MCU(S32K344)配置为SPI主设备以与该PMIC通信时: MISO引脚保持恒定 0.3伏 (表示高阻抗,内部下拉电阻较弱,意味着从设备无法驱动线路)。 PMIC 侧的 SCK 引脚实际上会自行输出时钟信号。 我怀疑该芯片可能被锁定在 OTP 仿真模式或配置为 I2C 从设备,这导致 SPI 通信完全失败。 我的具体问题: 请您确认一下。 MFS2323BMBA5EP的实际出厂OTP配置是什么?是SPI还是I2C? 当两者之间发生冲突时 .cfg 寄存器文件( 0x30:0x00 )和PDF配置报告,哪个才是硬件配置的绝对权威?PDF报告是否存在文档错误的可能性? (我已附上) FS2320_BA5_CONFIG_Rev_A.cfg 以及 R_MFS2323BMBA5_Rev_A_test.pdf (参见此帖)。 提前感谢您的帮助! Re: MFS2323BMBA5EP OTP Configuration Conflict: SPI vs I2C Mode Identification 好的谢谢您 Re: MFS2323BMBA5EP OTP Configuration Conflict: SPI vs I2C Mode Identification 请问你们是哪个公司?目前您是用的自己的邮箱属于C客户优先级很低的 这个是需要检查您的原理图,驱动CRC一系列的东西。 我建议您用公司的邮箱提交一个ticket Home  Re: MFS2323BMBA5EP OTP Configuration Conflict: SPI vs I2C Mode Identification 目前不能,我现在是在DEBUG模式下去通讯,我单独测试344端的SCK和MOSI的波形是能发出我写的数据的,但是由于,FS23的SCK引脚也在发信号,这两个接在一块后,MCU发出来的SCK信号被FS23对顶后拉低了,我发送给FS23回复的都是0,我也配置了CRC了 紫色的线是对顶后的SCK信号 黄色是数据信号 刻度都是5V 发送的数据是 {0x02, 0x00, 0x00,CRC} 如果强行把SCK看成正常波形是能看出来数据是对的,第一位是2然后00和CRC Re: MFS2323BMBA5EP OTP Configuration Conflict: SPI vs I2C Mode Identification 你配置成SPI 能通信成功吗? Re: MFS2323BMBA5EP OTP Configuration Conflict: SPI vs I2C Mode Identification 会出现与S32K344SPI通讯时FS23的SCK信号也在发送吗,因为如果我不配置SPI与FS23通讯,我去抓FS23的SCK脚是没有波形的,只有344和他通讯的时候这两个的SCK引脚都在发信号,而且SCK和CS引脚的波形是一模一样的 Re: MFS2323BMBA5EP OTP Configuration Conflict: SPI vs I2C Mode Identification 我在GUI upload .cfg文件到mirror register显示就是SPI 模式
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From Simulation to Vehicle Control: Real-Time Decision Making on the S32N55 1 Table of Contents • Introduction • Overview • Context • References • Conclusion 2 Introduction Modern vehicle development increasingly relies on digital validation before physical prototypes are available. Simulation enables rapid testing and iteration, but engineering teams also need to demonstrate how virtual behavior maps to real hardware. In the Hello World demonstrator, this connection is handled by the Main Node application running on the NXP S32N55. The Main Node acts as the central execution point of the demonstrator, transforming vehicle information generated inside MATLAB ® and Simulink ® into decisions and actions that can be observed on physical hardware. By combining Model-Based Design, CAN communication, and centralized decision making, the system creates a bidirectional link between the virtual vehicle and the physical demonstrator. This article explains how the Main Node converts simulation inputs into coordinated vehicle behavior while maintaining synchronization between the digital and physical domains. 3 Overview As introduced in the previous article, the S32N55 functions as the communication hub of the demonstrator, aggregating information from distributed modules and distributing commands throughout the system. Beyond communication, however, the Main Node also serves as the decision-making layer responsible for interpreting vehicle state and translating it into actionable control signals. Developed using the NXP Model-Based Design Toolbox (MBDT), the application is entirely modeled in Simulink and deployed directly onto the target hardware. This workflow enables engineers to focus on vehicle functionality and system behavior while leveraging automated code generation and integrated CAN communication support. The Main Node receives data from simulated and physical sources, maintains a coherent vehicle-state view, runs vehicle-level control logic, and sends commands to the actuator nodes that make up the demonstrator. This centralized architecture reflects the direction of modern software-defined vehicle platforms, where coordination moves from isolated ECUs toward higher-level compute nodes. Figure 1. Main Node overview showing how the S32N55 coordinates simulation inputs, vehicle-state processing, and commands to distributed hardware modules. 4 Context The Main Node is positioned between the virtual vehicle environment and the physical hardware modules that form the demonstrator. Driver inputs generated through the Driver-in-the-Loop simulation environment are transmitted over CAN and received by the S32N55, where they are processed alongside feedback arriving from multiple distributed nodes. Commands such as vehicle speed, steering angle, gear selection, braking requests, and lighting controls enter the Main Node from the simulation environment. These inputs are then evaluated by the application and translated into CAN messages that drive the corresponding hardware modules. This architecture enables the physical demonstrator to mirror the behavior of the virtual vehicle. When the simulated vehicle accelerates, the speed command is interpreted by the Main Node and forwarded to the motor control subsystem. Steering-wheel movements are translated into steering-angle commands for the steering module, while lighting commands activate headlights, fog lights, hazard lights, and turn indicators on the physical hardware. Figure 2. System context illustrating the Main Node as the bridge between the virtual vehicle environment and the physical demonstrator hardware. The Main Node can be driven either by the Driver-in-the-Loop simulation or by the External Control model. In both cases, the command source publishes the same DBC-defined CAN frames, so the S32N55 receives speed, steering, brake, gear, and lighting commands through the same interface. This allows the same deployed application to be exercised from two sources without changing the Main Node software. This approach is especially useful during integration, demonstrations, and incremental validation. Engineers can exercise the Main Node and the downstream actuator modules even when the complete virtual environment is not active, while still preserving the exact communication contract used by the full system. As a result, the application can be validated against two different input sources without changing the deployed software on the board. Rather than acting as a simple gateway, the Main Node continuously evaluates received information and executes vehicle-level decisions. One example is the processing of motor feedback data, where information from multiple motors is combined to derive a representative vehicle speed used throughout the system. Centralizing this functionality simplifies system coordination while ensuring consistency across all connected modules. Gear selection is handled as part of this centralized decision layer. The incoming gear command is interpreted as a driving mode that affects how the requested speed is applied: Park and Neutral block motion commands, Reverse changes the sign of the velocity reference, and Drive or Sport propagate the requested speed as a forward-driving command. This keeps speed-control behavior aligned with the selected driving mode while preserving the same driver-input signal set. The target-speed command is computed from the requested speed reference, the selected gear mode, the reported vehicle speed, and the effective brake command. Motor feedback is fused into a representative reported speed, which provides the actual-speed reference used during braking decisions. Under normal driving conditions, the requested target speed passes through the gearbox-aware logic and is converted into the motor-speed command sent over CAN. When braking is active, the Main Node bases the outgoing command on the detected speed and brake value, reducing the command until the vehicle is considered stopped. The Main Node also hosts the demonstrator's automated emergency braking functionality. Parking sensor nodes continuously report obstacle distances over CAN. The application evaluates these measurements and determines whether an object has entered a predefined safety zone. When this condition is met, the braking command issued by the driver can be overridden and replaced with an emergency braking request generated by the system. Figure 3. Parking sensors in action detecting nearby obstacles and providing distance feedback used by the Main Node to support emergency braking decisions. An important aspect of this implementation is that the braking behavior is reflected across both domains. The physical hardware responds to the braking request, while the simulation environment can receive corresponding vehicle-state updates through the same CAN-based loop. This closed-loop behavior demonstrates bidirectional interaction between simulation and embedded execution, allowing safety-related functionality to be validated in a realistic environment before a full vehicle prototype is available. Figure 4. Closed-loop emergency braking flow showing how parking sensor feedback can trigger an automated braking request across both the physical and simulated domains. CAN communication is the key enabler of this architecture. Every subsystem communicates through DBC-defined interfaces, allowing functionality to be distributed across multiple independent nodes while preserving a consistent and scalable communication framework. The shared DBC approach ensures that signal definitions remain synchronized across all parts of the demonstrator. To support this workflow, MathWorks Vehicle Network Toolbox ™ provides direct integration between MATLAB ® , Simulink ® , and CAN communication interfaces. DBC files can be used directly throughout the development process, simplifying signal management and ensuring consistency across the virtual vehicle, the Main Node, and all peripheral modules. As the demonstrator grows to include additional functionality, the same network definition can be reused across all participating systems, reducing integration effort and helping accelerate development. Note: The combination of NXP Model-Based Design Toolbox and MathWorks Vehicle Network Toolbox creates a workflow in which vehicle behavior, communication interfaces, and deployed software remain aligned from modeling through system integration. Figure 5. CAN and DBC workflow showing how shared signal definitions keep the virtual vehicle, Main Node, and distributed hardware modules synchronized. 5 References NXP Model-Based Design Toolbox (MBDT) NXP S32N Vehicle Super-Integration Processors Vehicle Network Toolbox ™ NXP Model-Based Design Toolbox Community 6 Conclusion The Main Node demonstrates how a centralized compute platform can act as more than a communication gateway. Running on the NXP S32N55, it combines signal aggregation, decision making, and command distribution into a single application that coordinates the entire demonstrator. By transforming simulation-generated inputs into physical vehicle behavior and feeding real-world information back into the virtual environment, the Main Node creates a practical closed-loop development platform. Together, NXP Model-Based Design Toolbox, MathWorks Vehicle Network Toolbox, and CAN-based communication enable rapid iteration, simplified integration, and efficient validation of vehicle functionality across simulated and physical domains.
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i.MX8M Plus — Secondary image boot (IMG_CNTN_SET1_OFFSET) on ECSPI/SPI NOR: does ROM fall back in OP i.MX8M Plus -- Secondary image boot (IMG_CNTN_SET1_OFFSET) on ECSPI/SPI NOR: does ROM fall back in OPEN config? ==== Setup ==== - SoC: i.MX8M Plus (custom SMARC module) - Boot device: serial NOR on ECSPI2 / CS1 (Winbond W25Q128, 16 MiB). This is the legacy eCSPI controller, NOT FlexSPI. - Security: OPEN configuration (device is not HAB-closed). - Fuse IMG_CNTN_SET1_OFFSET (fuse read 2 1) = 0x00000000. - Flash map: primary bootloader at 0x000000, secondary copy at 0x400000 (4 MiB). Per the documented SPI mapping: "For SPI: secondary boot disabled if fuse > 10; n == 0 -> Offset = 4 MB; n == 2 -> 1 MB; others & n <= 10 -> 1 MB * 2^n." With fuse n = 0 (factory default, no burn needed) the secondary offset should be exactly 0x400000. ==== The problem ==== We placed a byte-identical, cmp.b-verified copy of the primary image at 0x400000, then invalidated the primary boot header (sf erase 0 0x1000) and reset. The ROM does NOT fall back to the secondary image -- the board is bricked (recoverable only via USB SDP). We also tried erasing a hole inside the primary body (sf erase 0x100000 0x40000) with the same result. ==== Questions ==== 1. On SPI/ECSPI NOR, what exactly triggers the ROM to switch to the secondary image at the IMG_CNTN_SET1_OFFSET? Is it any invalid primary boot header / failed image parse, or specifically a HAB authentication failure? 2. Does secondary-image boot work in OPEN (non-secured) configuration, or only when the device is HAB-closed? 3. Does it fall back on the same reset, or does it require a power cycle / second reset (persistent-boot style)? 4. Must the secondary image at 0x400000 be a separately-built bootable image (its own IVT/boot data for that offset), or is a byte-identical copy of the primary sufficient? ==== Logic-analyzer evidence (SPI bus captured during reset) ==== We probed the ECSPI2 bus (CLK, MOSI, MISO, CS) with a Saleae Logic Pro 16 at 500 MS/s and decoded every SPI transaction during reset. For comparison we did the same on an i.MX8QM module which boots from FlexSPI NOR and does fall back to secondary successfully. ---- i.MX8M Plus (ECSPI NOR), primary corrupted ---- The ROM issues only 0x03 READ commands, reading strictly sequentially from offset 0: 0x03 00 00 FC -> READ 0x0000FC 0x03 00 04 EC -> READ 0x0004EC 0x03 00 08 DC -> READ 0x0008DC ... (~50 reads per 64 KiB block, strictly increasing) ... 0x03 00 13 xx -> read count drops here (erased hole 0x100000-0x140000, MISO=0xFF) 0x03 00 18 xx -> continues LINEARLY past the hole ... up to ~0x1A69E8 ... The ROM reads linearly through the entire primary region, straight through the erased/invalid area (getting 0xFF back), and NEVER issues a read to 0x400000 or 0x800000 (the secondary region). There is no "0x03 40 xx xx" anywhere in the full capture (25 million samples, 654 decoded transactions). On a fully-erased-header case the ROM loads 0xFF, executes it, and crashes with a Synchronous Abort -- no fallback of any kind. ---- i.MX8QM (FlexSPI NOR), for contrast -- secondary fallback DOES work ---- When only the primary container header is invalidated (FCB left intact at 0x000400), the QM ROM does: 0x0B 00 04 00 -> Fast-Read FCB @0x000400, MISO: 46 43 46 42 ("FCFB" magic, FlexSPI config valid) ... reads FCB configuration data ... 0x0B 00 10 00 -> Fast-Read primary container @0x001000, MISO: FF FF FF FF (invalid!) 0x0B 40 10 00 -> Fast-Read SECONDARY container @0x401000, MISO: valid <-- ROM switched, SAME reset 0x0B 40 30 00, 0x0B 40 40 00, ... -> loads whole secondary image (~90 reads at 0x40xxxx) The QM ROM reads FCB, configures FlexSPI, checks the primary container at 0x001000, sees 0xFF, and immediately (same reset) switches to the secondary container at 0x401000. This works. If we instead erase the whole first 4 MB (including the FCB), the QM ROM makes only 2 reads at 0x000400, gets 0xFF, and does NOT fall back -- so a valid FCB is required for the fallback to engage. ---- Comparison ---- i.MX8M Plus (this board): Controller : eCSPI (legacy SPI) Read opcode: 0x03 READ FCB present: No (eCSPI has no FCB concept) Reads secondary on corrupt primary: NO -- bus never shows "0x03 40 xx xx" Result: bricks (loads 0xFF -> crash) i.MX8QM (reference): Controller : FlexSPI Read opcode: 0x0B Fast Read FCB present: Yes (0x400, magic "FCFB") Reads secondary on corrupt primary: YES -- "0x0B 40 10 00", same reset Result: boots secondary successfully ==== Summary ==== From the bus captures, the IMG_CNTN_SET1_OFFSET secondary-image boot on i.MX8M Plus appears to be either FlexSPI-only, or gated by HAB-closed config, and does not engage for eCSPI NOR in OPEN config. Could NXP please confirm: - Whether eCSPI (as opposed to FlexSPI) NOR is supported for secondary-image boot at all on i.MX8M Plus; - Whether the trigger is HAB-auth-failure (closed config only) vs. any invalid header (open config too); - Whether fallback is same-reset or requires a power cycle; - Whether the secondary must be separately built for that offset, or a byte-identical copy is OK. Thank you.
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IMX95EVK-19-REV-A1 flash problem Dear NXP, I'm trying to flash a linux image(6.18.20_2.0.0/ 6.18.2_1.0.0/6.12.49_2.2.0) to eMMC/SD Card on IMX95LP5-19 EVK REV A1 and none of them is successful. The command prompt shows [HID(W): LIBUSB_ERROR_PIPE (-9) ] SDPS: boot -f imx-boot-imx95-19x19-lpddr5-evk-sd.bin-flash_all. IMX95LPD5EVK-19CM: UUU eMMC flash of L6.18.2 fails (LIBUSB errors on Linux and Windows) The reference above mentioned that A1 silicon does not support current images on official site(6.12.34 does not have IMX95EVK patch). so I wonder if there is an unpublished official link that includes suitable images?  Looking forward to your reply, Thanks. BR/david Here is a reference IMX95LPD5EVK-19CM: UUU eMMC flash of L6.18.2 fails (LIBUSB errors on Linux and Windows) Re: IMX95EVK-19-REV-A1 flash problem A1 silicon: The recommended BSP is LF 6.6.52_2.2.x Please download demo image L6.6.52_2.2.2_MX95 And use image imx-boot-imx95-a1-19x19-lpddr5-evk-sd.bin-flash_all I just verified the following command, it worked. uuu.exe -b emmc imx-boot-imx95-a1-19x19-lpddr5-evk-sd.bin-flash_all
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ls1021a eTSEC tx timeout I have a LS1021A IOT and a prototype board based on this cpu. On both we use our boot loader. It works perfectly in the IOT board but on my board I get TX timeout on the Ethernet port. I get a few pings going and then tx timeout and more pings.  This makes tftp rarely possible. There are hardware difference of course. Our MAC is connected to a BCM54616S then to a LAN9514. The autonegotiation is limited to 100FD. TX timeout also happens in loopback mode. In order to transmit data, I had to set bit SGMII_AN bit in the TBI PHY on my boards while I did not have to on the IOT (IOT can negotiate at 1000FD). Not sure why the TX is so intermittent. Could it be related to this speed limitation? Re: ls1021a eTSEC tx timeout Hello, For 100FD SGMII , verify these items in your boot loader on the prototype board: Set LS1021A eTSEC for SGMII 100 Mbps ECNTRL[TBIM] = 1 ECNTRL[SGMIIM] = 1 ECNTRL[R100M] = 1 MACCFG2[I/F Mode] = 01 for 10/100 mode The LS1021A RM specifically notes setting R100M = 1 for SGMII 100 Mbps. Reset and program the internal TBI PHY The RM states that SGMII uses the TBI register set and that it is important to reset the TBI for all interface modes, including SGMII. Keep SGMII_AN set The TBI SGMII_AN bit is documented as “must be set to 1.” So the fact that your board only transmits after setting this bit is not surprising; it suggests your boot-loader initialization was incomplete for this PHY/MAC mode. Do not rely on 1G-style SGMII AN behavior at 100 Mbps There are known LS1021A reports where 100 Mbps SGMII operation shows “SGMII link is not ok” or intermittent no-packet behavior after link cycling, while 1G operation is clean. That does not prove your exact TX timeout root cause, but it makes 100FD SGMII configuration a strong suspect. The loopback result matters. If your “loopback mode” is external PHY loopback or SGMII-side loopback, the 100FD SGMII/TBI setup can still be involved. If it is internal MAC/eTSEC loopback , then the external BCM54616S/LAN9514 path is mostly out of the picture, and I would focus on eTSEC initialization, descriptor-ring handling, cache coherency, and TX halt/error status. For debugging, check the eTSEC TX halt status when the timeout occurs. The RM says the transmit halt bits are set when eTSEC is no longer processing transmit frames from a TxBD ring; repeatable causes include bus errors, invalid BD/data addresses, uncorrectable BD/data read errors, and TxBD programming errors such as Ready = 1 with length 0 . Also check whether you are seeing IEVENT_BSY ; NXP material describes BSY as dropped RX frames due to lack of buffers/software not servicing the BD ring fast enough, which is a software/BD-ring symptom rather than a pure SGMII electrical symptom. Recommended isolation sequence: 1. Force external PHY to 100FD, no autoneg toward copper if needed. 2. Force LS1021A MAC/eTSEC to SGMII 100 Mbps: TBIM=1, SGMIIM=1, R100M=1, MACCFG2 I/F mode=10/100. 3. Reset/reinitialize TBI after setting SGMII mode. 4. Set TBI SGMII_AN=1. 5. Confirm TBI link/AN status, eTSEC ECNTRL/MACCFG2, and PHY SGMII-side status. 6. On timeout, dump IEVENT, TX halt registers, DMA status, and TXBD ring contents. regards  Re: ls1021a eTSEC tx timeout Forgot to say my port is set for SGMII mode.
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MTC40F2046S1RC64BD2 Are you able to confirm if this mpn: MTC40F2046S1RC64BD2 is X-ray sensitive?  Re: MTC40F2046S1RC64BD2 That's not true. X-ray exposure is a common testing procedure and will not cause damage. We suggest you find a seller with a Certificate of Conformity (COC) for safety assurance.
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Support Request: HD-SDI Interface Using i.MX8M Plus LVDS Output Dear Sir, We are designing a system based on the NXP i.MX8M Plus processor and would like your guidance regarding the implementation of an HD-SDI interface. Our requirement is to support three HD-SDI outputs. We are planning to use the LVDS interface of the i.MX8M Plus and convert it to HD-SDI using the following devices: LMH0340SQE/NOPB – LVDS to HD-SDI Serializer 2 × LMH0324RTWT – 1-to-3 HD-SDI Distribution Amplifiers Could you please confirm whether the LVDS interface of the i.MX8M Plus is compatible with this architecture for generating three HD-SDI outputs? If this approach is not recommended or supported, could you please suggest an alternative solution for implementing three HD-SDI interfaces while continuing to use the i.MX8M Plus processor? We would prefer to retain the i.MX8M Plus in our design, as it satisfies all of our other system requirements. We would appreciate your recommendations and any reference designs or application notes that may help us implement this interface successfully. Thank you for your support. We look forward to your guidance. Best regards, Samudralankaiah Jampani Analog(ADC|CMP|DAC|OpAmps) Board Design MCXA MCXC
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ICODE SLI 无法切换到 ICODE SLIX 我的客户一直在使用我提供的 ICODE SLI 芯片,但该芯片已经停产了。我们正在尝试切换到 ICODE SLIX,但客户的 RFID 阅读器无法识别它。 Re: ICODE SLI can't be switch to ICODE SLIX 你好, ICODE SLIX 旨在向后兼容 ISO15693 级别的 ICODE SLI,因此读卡器至少应该在盘点期间检测到 SLIX UID。如果读卡器无法识别,请先检查故障是出在射频存货层面还是出在应用程序的标签识别逻辑层面。常见原因包括 AFI/UID 过滤、硬编码的 SLI 产品识别、旧的读卡器固件,或者在迁移过程中使用 SLIX 特有的网络安全/功能。对于第一个测试,禁用 AFI 过滤和标签白名单,执行标准的 ISO15693 清单,读取 UID/DSFID/AFI,然后将应用程序的接受逻辑与旧的 SLI 标签进行比较。 此致
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i.MX8M Plus - SPDIFプロトコル実装例 こんにちは、チームのみなさん。 どなたか、i.MX8M plusでSPDIFプロトコルを実装し検証する方法を教えていただけませんか? Re: i.MX8M Plus - SPDIF Protocol Implementation Example 最もシンプルな i.MX 8M Plus S/PDIF実装については、i.MX Audio Board / MCIMX8M-AUDを最も近いNXPの参照ハードウェアとして使用し、ベース i.MX 8M Plus EVK単独ではありません。オーディオボードは8M Plus i.MX をサポートし、RCAおよびTOSLINKコネクタを備えたS/PDIF I/Oを提供し、最大192 kHzまでのTOSLINK対応であることが文書化されています。 推奨されるシンプルなアプローチ: 可能であれば、まず光S/PDIFを使用してください。 最も簡単なハードウェアパス:i.MX8MP SPDIF_OUT →光式TOSLINKトランスミッタ。 受信用:光TOSLINK受信モジュール→ i.MX8MP SPDIF_IN。 これにより、同軸75Ωライン駆動、トランス/カップリング、および接地に関する問題を回避できます。 i.MX 8M PlusのS/PDIFピンをIOMUX経由で使用する i.MX 8M PlusオーディオサブシステムはSPDIFの入出力を備えています。 リファレンスマニュアルには、選択可能なパッドのAUDIOMIX_SPDIF1_OUTとAUDIOMIX_SPDIF1_INのIOMUXオプションが示されています。 Linuxでは対応するIOMUX定義にはMX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF_OUTとMX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF_INが含まれます。 同軸RCAが必要な場合は SoCピンを直接RCAのラインドライバーのように扱わないでください。 選択したトランスミッタ/インターフェース回路ごとに適切な75 Ω S/PDIF同軸ケーブル出力ネットワーク/結合を追加してください。 光ファイバー方式は、通常、よりシンプルで安全な最初の実装方法です。 参考資料 MCIMX8M-AUD / i.MX オーディオボード:i.MX 8MファミリのS/PDIF I/OおよびRCAおよびTOSLINKに最適なNXPリファレンス。 i.MX 8M Plusリファレンスマニュアル:AUDIOMIX_SPDIF1_INおよびAUDIOMIX_SPDIF1_OUT用のpinmux / IOMUXセットアップ。 i.MX 8M Plusのデータシート:クロックのハイ/ロータイミングを含む、S/PDIFのタイミングパラメータが記載されています。 最も単純な設計では、AUDIOMIX_SPDIF1_OUT/INを光TOSLINKモジュールにルーティングし、MCIMX8M-AUDをNXPのS/PDIF I/O挙動の基準点として使用します。 Re: i.MX8M Plus - SPDIF Protocol Implementation Example こんにちは、Yipingwangさん、 SPDIFを最もシンプルに実装するための参考回路図を教えていただけませんか? Re: i.MX8M Plus - SPDIF Protocol Implementation Example i.MX8M Plusで既存のLinux ALSA Audio XCVR / S/PDIFドライバーを使用;通常、S/PDIFプロトコルを最初から実装することはありません。i.MX8M Plus Audio XCVRはeARC、ARC、S/PDIFモードをサポートし、LinuxのS/PDIF対応では、ALSAを通じてTx用の再生デバイスとRx用のキャプチャデバイスを1台公開します。 推奨される実装方法: カーネルドライバーを有効にしてください有効化: CONFIG_SND_IMX_SPDIF メニューパス: コピー デバイスドライバー -> サウンドカードサポート -> 高度なLinuxサウンドアーキテクチャ -SoCオーディオサポート> ALSA - フリースケール i.MX CPU向けの> SoC オーディオ - > S/PDIF対応 i.MX ボード向けのSoCオーディオサポート ドキュメント化されたDTバインディングは、ドキュメント/devicetree/bindings/sound/fsl spdif.txtおよびドキュメント/devicetree/bindings/sound/imx-audio-spdfif.txtにあります。 デバイスツリーの設定i.MX8M Plusでは、xcvrオーディオブロックを使い、サウンドカード/DAIリンクを有効にしてください。代表的な構成例は以下のとおりです。 サウンドトランスフォーマー { 互換 = 「FSL,IMX-オーディオカード」; model = "imx-audio-xcvr"; pri-dai-link { リンク名 = "XCVR PCM"; CPU { sound-dai = <&xcvr>;         }; }; }; &xcvr { #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_xcvr>; ステータス = "正常"; }; Tx ピンの多重化については、文書化された例の 1 つで MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF1_OUT が使用されています。 ボードのルーティングやジャンパーを確認してくださいNXPオーディオボードを使用する場合、意図するS/PDIFパスの物理ルーティングを設定します。i.MX8M Plusの場合、J1500=1-2は同軸コネクタをi.MX8M Plusにルーティングし、J1500=4-5は光コネクタをi.MX8M Plusにルーティングします。CPLD/HDMIカードを経由してルーティングする場合、J2511=1-3は「i.MX 8M PlusからCPLD、そしてHDMIカードへ」として文書化されています。 ALSA / IEC958を正しく使いましょうS/PDIF Txドライバーは32、44.1、48 kHzのサンプリングレートをサポートし、S16_LEおよびS24_LEフォーマットに対応しています。24ビット出力の場合、ファイルは1チャネルフレームあたり32ビットを使用し、有効な24個のLSBのみを使用します。パスが生のPCMではなくIEC958サブフレームを想定する場合は、ユーザー空間でPCMからIEC958への変換を行い、例えばALSA PCMプラグインを使って行います。 検証手順: aplay -l arecord -l これらを使用して、S/PDIF再生/キャプチャカードおよびデバイスIDを特定します。ドキュメントには、S/PDIFデバイスがIMXSPDIF[imx-spdif]のようなALSAカードとして表示され、デバイス0: S/PDIF PCMとして表示されています。 トランザクション検証: aplay -D hw: , audio48k24S.wav リファレンス検証方法 は、M-Audio Transit USBサウンドカードとWaveLabを組み合わせた外部の光S/PDIF レシーバ を使用し、ストリームを外部に録音して再生して正確性を確認します。 処方箋の検証: arecord -D hw: , -c 2 -d 20 -r 48000 -f S24_LE record.wav レコードに渡されるサンプルレートは、入力されるS/PDIFストリームのサンプルレートと一致している必要があります。Rxの場合、アプリケーションフローはS/PDIF Rx PCMデバイスを開き、内部DPLLが入力ビットストリームにロックされるのを待ち、入力サンプリングレートを取得し、チャネル/フォーマット/レートパラメータを設定し、準備してキャプチャをトリガーすることです。 プロトコルレベルのチェックには、以下を使用してください。 iecset -c iecsetはIEC958ステータスビットの設定またはダンプに記載された標準ユーティリティであり、ドライバはALSA制御インターフェースを通じてチャネル状態処理も公開します。 i.MX8M Plus EVKスタイルの検証については、NXPはimxaudioxcvrカードを用いたループバックスタイルのLinuxテストも記録しており、例えばimxaudioxcvrからの録音とwm8960audioへの再生などがあります。 arecord -Dsysdefault:CARD=imxaudioxcvr -c2 -r48000 -fS32_LE -twav | \ aplay -Dsysdefault:CARD=wm8960audio 簡単に言うと、i.MX S/PDIF / XCVR ALSAドライバーを有効にし、xcvrデバイスツリーとボードルーティングを設定し、aplay 、arecord、iecset 、および外部の光/同軸S/PDIFソースまたはシンクでTx/Rxを検証します。
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Facemesh Landmark 模型 ptq 转换中的性能下降 本仓库中使用的是 NXP 在 ptq 之后发布的 Google FaceMesh 模型: nxp-demo-experience-demos-list/downloads.json 位于 lf-6.12.3_1.0.0 · nxp-imx-support/nxp-demo-experience-demos-list 但该模型基于谷歌旧的 FaceMesh 模型,该模型有 468 个地标点。 现在我们想升级到谷歌新的 FaceMesh 模型,它有 478 个地标点。我们希望在 iMX 95 FRDM 板 NPU 上运行此程序。所以,我们想把它量化。我们使用的是NXP的eIQ-neutron-sdk-linux-3.1.3量化该模型。 经过量化之后,我们发现模型性能显著下降,几乎无法实际使用。 最初我们使用 MIN-MAX 选项对其进行量化。那个模型根本没法用。然后我们尝试使用百分位数选项,发现将百分位数设置为 95 时性能更好(即使这是回归器的输出)。 但这仍然无法带来理想的性能。 1)NXP为旧版FaceMesh(468)模型创建ptq文件时,使用了MIN-MAX选项吗?或者百分位数? 2)量化后性能急剧下降时,我们还需要检查其他方面吗? 3) 我们使用 CelebA 数据集进行性能分析,在 scripts 目录中使用 serialize_image.py 脚本并设置了模型特定选项。我们应该运行完整的媒体管道并创建校准数据集,还是应该修改 serialize 脚本? 提供的选项 serialize_image.py : -i //218 x 178 正面 RGB 图像 -o -f bin -t float32 -m 0到1 -s 256,256 -布局 NHWC -co RGB tflite-profiler: --input --dataset --输出 tflite-quantizer: --input --profile --quantize-inputs=false --quantize-outputs=false --quantization-calibration-method= //最小值、最大值或百分位数
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S32K148 FlexCAN 仅输出 SOF 脉冲,然后进入总线关闭状态 我用S32DS开发了这个程序。当尝试发送 CAN 帧时,TX 引脚上只会输出一个短的低电平脉冲,后续的 ID 和数据位会被截断,因此无法发送完整的帧。USB-CAN 分析仪未收到任何数据,FlexCAN 控制器直接进入总线关闭状态。 我已经检查了时钟配置和寄存器值,并测试了不同的 CAN 通道,但问题仍然没有解决。我想找出哪个配置参数设置错误。感谢您的帮助。 Re: S32K148 FlexCAN Only Output SOF Pulse then Enter BusOff 嗨,朱利安, 感谢你的回复。我想更正并补充我之前匆忙写成的消息中的一些重要细节。 主板:这是第三方主板(不是 NXP EVB),型号为 S32K148_REV2_Q144。值得注意的是:我发现卖家提供的原理图存在错误(标注的收发器位置与实际 PCB 丝印不符),因此该电路板的参考设计文档可能并不完全可靠。 官方 CAN 示例:我尝试构建 Can_example_S32K148,但遇到了与 CAN 本身无关的环境问题(缺少工具链/包含路径,最终 Port_Ci_Port_Ip.h 和 Port_Ci_Port_Ip_Cfg.h 之间出现版本不匹配错误——“不同的供应商 ID”/“AutoSar 版本号不同”)。这看起来像是 RTD 包版本与我的项目不匹配,而不是 IDE 版本问题。我会尝试解决这个问题,但我认为这与硬件问题的核心无关。 新证据(来自您已审阅过的我自己的项目):自从我上次留言以来,我使用逻辑分析仪进行了更深入的验证: MB8 内容 100% 正确— 直接从 CDD_CanTransmit() 之后的寄存器读取:CS=0x0C080000 (CODE=0xC 待定,DLC=8),ID=0x00400304 (>>18 = 0x10,与配置匹配),DATA=0x01020304/0x05060708 (与我的 8 字节有效载荷完全匹配)。 引脚上的 TX 信号也正确——同时探测 PTE5 和收发器的 TXD 输入(200MHz 逻辑分析仪),两个波形相同,证实 PCB 走线良好。 但传输在大约 8-9 位转换后中止(大致为 SOF + 几个仲裁位),控制器随后进入总线关闭状态(ESR1 确认 FLTCONF=11,TXERRCNT 每次尝试递增)。 即使正确连接了 USB-CAN 分析仪并启用了 120Ω 终端(总线未浮空), CANH/CANL 也显示为零活动。作为对照测试,我在另一块已知可正常工作的 STM32 板上运行了相同的设置(浮空与终端),终端后 CANH 显示出了正确的转换。在我的 S32K148 板上,在相同的端接条件下,CANH/CANL 保持完全平坦。 在 CAN1 上也出现了同样的结果(不同的引脚/收发器)。 由于 MCU 端的 TXD 信号在收发器输入端之前均已确认正常,但即使正确端接,CANH/CANL 信号也始终没有响应,因此我怀疑是收发器输出级(或两个通道共用的某个部分,例如……)出现了问题。电源瞬态行为——我只能用逻辑分析仪检查,无法用示波器检查。 问题: “TXD 在收发器输入端正确,但 CANH/CANL 在正确端接下完全平坦”是否更强烈地表明收发器硬件故障,还是存在其他常见的板级问题(使能/待机电路、电源去耦)也可能导致这种症状? 当总线上没有实际活动时,FlexCAN 是否应该在发送完前几个仲裁位后中止(而不是完成整个帧并在 ACK 时失败)?我想确认一下我对位监控机制的理解是否正确。 对于示例项目中的 RTD 版本不匹配问题——是否有办法检查哪个 RTD 版本与给定的 S32 配置工具版本匹配,以便我可以获取匹配的示例包? 再次感谢您的帮助。 此致敬礼,艾普丽尔 Re: S32K148 FlexCAN Only Output SOF Pulse then Enter BusOff 嗨,朱利安, 我非常惊讶,也很感谢您回复我的问题。   我使用的是自己设计的硬件板;只有电源电路与官方 EVB 原理图不同,而其余电路与参考设计一致。 我测试了官方的 CAN 示例项目。我只配置了 CAN0 引脚,而没有启用和配置 MCAL 层中的 PORT 模块,但项目一直编译失败。   具体的编译错误是: “f ../board/Port_Ci_Port_Ip_Cfg.h:47:10: 致命错误: Port_Ci_Port_Ip_Types.h: 没有该文件或目录”。   我的自定义项目文件中已有此头文件,但是导入此官方示例项目后,代码生成过程中并未自动生成此头文件。 缺少头文件错误是否可能是由于 IDE 软件版本不匹配造成的?目前我正在使用S32DS 为 S32 平台进行开发,现在我正在下载S32DS for ARM 2.2.2来切换开发环境。 期待您的指导。   顺祝商祺!   四月 Re: S32K148 FlexCAN Only Output SOF Pulse then Enter BusOff 你好@April , 从你的项目来看,配置和流程似乎都是正确的。请问您使用的是恩智浦半导体的S32K148EVB芯片,还是您自己设计的芯片? 您是否尝试过测试 RTD 中包含的 Can_example_S32K148 项目?您可以简单地添加 CAN0 引脚并禁用环回模式以启用 Tx/Rx 并测试该程序。 最后,您是否确认两个节点(S32K148 和 CAN 分析仪)都设置为相同的位时序和协议配置(CAN 与 CAN FD)?您可以使用以下工具来计算值: MPC5xxx/S32Kxx/LPCxxxx:CAN / CAN FD 位定时计算。 如果您使用的是自定义设计,您可以参考S32K148 EVB 的原理图和S32K1xx 硬件设计指南,了解 CAN 接口设计和建议。 此致, 朱利安
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IPCFのバージョンに関する問題 私は以下のRTDバージョンを使用しています:SW32K3_S32M27x_RTD_R21-11_6.0.0_QLP01&04、IPCFバージョン:SW32K3_IPCF_4.2.1_D2504、EBバージョン:29.0。Excampleにインポートする際...プロジェクト「IPCF_AutosarOS_S32K358_M7_0」でエラーが発生しました。内容は以下のとおりです。 エラー (11061) モジュール OS TS T40D34M413R184 をインストールしていません - プロジェクト IPCF AutosarOS S32K358 M7 0 のモジュール構成を作成できません 0 (11061) モジュール「pc TS T40D34M4210R0」がインストールされていないため、プロジェクト「IPCF AutosarOS $32K358 M7 0」のモジュール構成を作成できません。 0 (11061) モジュールリソースTS T40D34M5010Roをインストールせずにプラグインします - プロジェクトIPCF AutosarOS $32K358 M7 0°のモジュール構成を作成できません @ (11061) モジュール「BaseNXP TS T40D34M50I0RO」がインストールされていません - プロジェクト IPCF AutosarOS $32K358 M7 0 のモジュール構成を作成できません @ (11061) モジュール「Mcu TS T40D34M5010R0」を含むプラグインがインストールされていません - プロジェクト「IPCF AutosarOS $32K358 M7 0」のモジュール構成を作成できません 適切なIPCFまたはEBバージョンを使用して、この問題を解決するにはどうすればよいでしょうか? Re: IPCF版本问题 こんにちは@liyongfeng 現在EB Tresos環境にインストールされているプラグインのバージョンを教えていただけますか? また、RTDパッケージを再インストールして、その後も問題が続くか確認してみてはどうでしょうか? BR、VaneB
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マーキングの詳細 マーキングの意味を教えてください。 MPN: PCA9553DP/01,118 用 04 01 616
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NFCカードについて助けが必要です 最近、AmazonでMIFARE Classic 1Kに対応しているACR122U-A9と13.56MHzのRFID近接IDカードキータグを買いました。書き込み可能な再書き込み可能なCUIDフォブタグです。MWT V.1.6.8424.424.63をインストールして、4tagくらいは動作しましたが、今はカードを読み取れないか、64で63くらいで止まってしまいます。どなたか助けていただけますか?私は本当にテクノロジーにはあまり詳しくありません NFCリーダー・ライブラリ Re: I need help with my NFC card お世話になります。 弊社製品をご利用いただきありがとうございます。 ACR122U-A9の使用についてですが、公式ページでは新しいデザインにはこのリーダーは推奨されていないと記載されているのに気づきました。私の推奨は、推奨されサポートされているものに移行することです。 インストールされたミドルウェアについてですが、公式ページで見つけることができなかったので、どこで入手されたのか教えていただけますか? MIFARE Classicに対応しているタグが4タグのように動作するというのはどういう意味か理解したいです。MIFARE ClassicカードはISO14443〜3コマンドしかサポートできません。正確なコマンドの説明については データシート をご覧ください。 もしプロジェクトについてもっと詳しく教えていただければ、 MIFARE Classic カードもセキュリティ上の理由で推奨されていないので、より良いおすすめができるかもしれません。
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MTC40F2046S1RC64BD2 请问您能否确认一下这个产品型号: MTC40F2046S1RC64BD2是否对X射线敏感? Re: MTC40F2046S1RC64BD2 那不是真的。X射线照射是一种常见的检测程序,不会造成损害。为了功能安全起见,我们建议您寻找拥有合格证书(COC)的卖家。
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