FS6500的故障标志清除行为 大家好， 我有一个关于 FS6500 故障标志清除行为的问题。   根据数据手册，MODE 寄存器（地址 0x15）内的 LPOOF（位 0）和 DFS（位 1）标志只能通过上电复位或寄存器读取操作清除。 然而，根据我的硬件测试：   向 MODE 寄存器写入数据还会意外地清除 LPOOF 和 DFS 故障位。   数据手册中没有说明写入操作可以清除这些状态标志。 您能否帮忙解释一下造成这种现象的根本原因？   这是硅芯片的预期行为还是未记录的副作用？   谢谢 & 此致敬礼   DEVKIT-MPC5744P FS6500 Re: Fault flag clearing behavior of FS6500 你好， 请检查您的书写说明是否正确。 在大多数软件驱动程序中，寄存器写入操作都是以读-修改-写 (RMW) 序列实现的。 如果数据手册规定读取 MODE 会清除 LPOOF/DFS，那么这些标志可能在读取阶段就已经被清除了。随后的写入操作只会造成写入操作导致清除的假象。 顺祝商祺！ Peter

Update on S32K388 BIST issue: Soft reset causing peripheral init failure in App Hi NXP Support Team, Following up on the previous BIST hard reset issue: we applied your proposed change, and the BIST now successfully performs a soft reset instead. To adapt to this soft reset and avoid double MCU clock initialization, we initially kept the MCU clock initialization in the Application. However, after the BIST soft reset and jumping to the App, the clock re-initialization was taking an unusually long time. We suspect this delay and lock-up occurred because the clocks were already initialized by the Boot Manager, causing conflicts during the second attempt. To resolve that extreme delay, we removed the MCU clock initialization from the Application entirely, leaving it exclusively in the Boot Manager. Unfortunately, this has introduced a new issue: after jumping to the Application, the system now hangs during peripheral initialization (specifically FlexCAN), which points back to a clock availability issue. Could you advise on the correct clock configuration strategy here? Specifically, does the BIST soft reset disrupt the clocks initialized by the BM in a way that requires re-initialization in the App, and how can we properly hand off the clocks between the BM and App without causing lockups or extreme delays? Re: Update on S32K388 BIST issue: Soft reset causing peripheral init failure in App Hi @HazemIhab, I haven't found your previous BIST hard reset issue in any support ticket or community thread. I understand you see ST_DONE functional reset. After the reset the clock configuration is reset, so it needs to be initialized. If you use the RTD drivers, the Clock_Ip_InitClock() function resets all the clocks to a safe state first — which is probably the delay you see if you initialize the clocks in both the Boot Manager and the application. It can be configured in the Boot Manager only, but you need to make sure the driver enables all the clocks the application needs — in this case the FlexCAN clock. Also, all the system clocks must match one of the clock options listed in the RM, e.g. Table 156. Option A - High Performance mode (CM7_CORE_CLK @ 160 MHz) (For S32K388/S32K389). BR, Daniel Re: Update on S32K388 BIST issue: Soft reset causing peripheral init failure in App Hello @danielmartynek  Thanks for the explanation. To clarify our setup: our Boot Manager (BM) and Application (App) already use the exact same clock configuration, including the FlexCAN clock settings. To avoid the delay from the safe-state reset, we let the BM initialize all clocks and removed Clock_Ip_InitClock() from the App. However, when the App tries to initialize FlexCAN after the jump, the system still hangs with a clock-related error. Re: Update on S32K388 BIST issue: Soft reset causing peripheral init failure in App Hi @HazemIhab, I understand there is a fault exception, can you confirm? If so, you need to find more information about the exception to confirm it is really clock related. https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-HARDFAULT-Handling-Interrupt-DS3-5-RTD300/ta-p/1806259 https://community.nxp.com/t5/S32K-Knowledge-Base/How-To-Debug-A-Fault-Exception-On-ARM-Cortex-M-V7M-MCU-S32K3XX/ta-p/1595570 https://community.nxp.com/t5/S32K-Knowledge-Base/Fault-handling-on-S32K14x/ta-p/1114447 If there is no exception, but the execution is stuck in a loop, where exactly? Also, as I mentioned, all the system clocks must match one of the clock options listed in the RM, e.g. Table 156. Option A - High Performance mode (CM7_CORE_CLK @ 160 MHz) (For S32K388/S32K389) can you confirm? Thank you, BR, Daniel

使用 DMA 描述符接收大于 1024 字节的数据 (LPC55S69) 大家好， 考虑到 DMA 的最大传输大小为 1024 字节，我一直难以找到一种方法，通过 DMA 将大量数据（超过 2000 字节）接收到我的 LPC55S69 板。 我查看了示例“usart_dma_double_buffer_transfer”，但是其中一些函数已经过时，例如： DMA_PrepareTransfer() 变为 DMA_PrepareChannelTransfer()，DMA_SubmitTransfer() 变为 DMA_SubmitChannelTransfer()，DMA_CreateDescriptor() 变为 DMA_SetupDescriptor()。因此，我在填写这些新函数的新输入参数时有点迷茫，这些参数在示例中没有出现，主要是参数“xfercfg”，即新 DMA_SetupDescriptor() 中 DMA 描述符的传输配置。 我还查看了示例“dma_channel_chain”，它帮助我从另一个角度了解了一些新功能，但它并不完全符合我的需求。 此外，我还查看了NXP 社区的文章“DMA Ping-Pong 应用” ，但它与我正在使用的 LPC 板并不完全兼容。 在综合了我能从网上获取的信息，并绞尽脑汁敲击键盘之后，我终于达到了我想要的目标，即通过 DMA 接收大量数据。（将数据保存到 3 个不同的缓冲区中，每个缓冲区大小为 1024 字节） 因此，我借此机会分享这段代码，希望能对那些曾经和我一样迷茫的人有所帮助或提供一些指导。我也想尽我所能，将我从这个美好的社区学到的一切回馈给大家。 （希望在这里发帖没问题，因为这与其说是一个问题，不如说是一个可以讨论的话题。） 祝你好运！ #include "fsl_usart_dma.h" #include "fsl_dma.h" #define NUMBER_DESCRIPTORS 3 #define DESCRIPTOR_TRANSFER_SIZE 1024 #define RX_BUFFER_SIZE 1024 uint8_t g_data_buffer[RX_BUFFER_SIZE]; uint8_t g_data_1[RX_BUFFER_SIZE]; uint8_t g_data_2[RX_BUFFER_SIZE]; uint8_t g_data_3[RX_BUFFER_SIZE]; /* Custom Descriptors (Must be 16-byte aligned) */ SDK_ALIGN(dma_descriptor_t g_Desc[NUMBER_DESCRIPTORS], 16); /* equal to writing: __attribute__((aligned(FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE))) dma_descriptor_t g_Desc[NUMBER_DESCRIPTORS] = {0}; or DMA_ALLOCATE_LINK_DESCRIPTORS_AT_NONCACHEABLE(g_Desc, NUMBER_DESCRIPTORS); */ /* Function definitions ****************************************************************************/ //Initialising Rx DMA to receive data bigger than 1024 bytes. void init_USART_DMA(void){ //Channel configuration for DMA descriptor dma_channel_config_t channelConfig; /* 1. System/Peripheral Level Init */ // Done in peripheral.c, initialized the functions USART_Init(), DMA_EnableChannel(), DMA_CreateHandle(), USART_TransferCreateHandleDMA(). /*I have not used the function DMA_SubmitChannelDescriptor(), by giving as input the g_ChannelTable, as it would not allow to receive data. the g_ChannelTable variable should be initalized as follow: //Allocates the mandatory, 512-byte aligned master table in RAM used by the hardware to manage all DMA channels SDK_ALIGN(dma_descriptor_t g_ChannelTable[FSL_FEATURE_DMA_MAX_CHANNELS], 512); then call the function here in the code DMA_SubmitChannelDescriptor(FLEXCOMM5_USB_PC_RX_Handle,g_ChannelTable); */ /* 2. Enable USART RX DMA requests */ USART_EnableRxDMA(FLEXCOMM5_USB_PC_PERIPHERAL, true); /* 3. Prepare the Descriptor Configuration Variable Flags */ //Intermediate Descriptors, where it jumps from one to another /* Common XFER configuration options for intermediate descriptors (1, 2,...) */ /* reload = true (keeps the chain moving to the next descriptor) */ /* intA = false (we only want the final interrupt when everything is done) */ uint32_t intermediatexfercfg = DMA_CHANNEL_XFER( true, /* reload: true to move to the next descriptor */ false, /* clrTrig: false */ false, /* intA: false */ false, /* intB: false */ sizeof(uint8_t), /* width: 1 byte for USART char processing */ kDMA_AddressInterleave0xWidth, /* srcInc: 0x (read from fixed USART FIFO address) */ kDMA_AddressInterleave1xWidth, /* dstInc: 1x (increment buffer pointer by 1 byte) */ DESCRIPTOR_TRANSFER_SIZE /* totalBytes: DESCRIPTOR_TRANSFER_SIZE */ ); //Final Descriptor, where it stops jumping to another descriptor /* Final XFER configuration options for the last descriptor */ /* reload = false (this is the end of the chain) */ /* clrTrig = true (stop the DMA hardware channel) */ /* intA = true (fire the completion interrupt) */ uint32_t finalxfercfg = DMA_CHANNEL_XFER( false, /* reload: false because this is the terminal descriptor */ true, /* clrTrig: true to clear peripheral hardware requests */ true, /* intA: true to fire our completion interrupt */ false, /* intB: false */ sizeof(uint8_t), /* width: 1 byte for USART char processing */ kDMA_AddressInterleave0xWidth, /* srcInc: 0x (read from fixed USART FIFO address) */ kDMA_AddressInterleave1xWidth, /* dstInc: 1x (increment buffer pointer by 1 byte) */ DESCRIPTOR_TRANSFER_SIZE /* totalBytes: DESCRIPTOR_TRANSFER_SIZE */ ); /* 4. Configure the Custom Descriptors structure */ //Descriptor #0 DMA_SetupDescriptor( &g_Desc[0], intermediatexfercfg, (void *)&FLEXCOMM5_USB_PC_PERIPHERAL->FIFORD, /* Source address: USART FIFO Read Register */ &g_data_1[0], /* Destination address: RAM buffer */ &g_Desc[1] /* Point to next descriptor */ ); //Descriptor #1 DMA_SetupDescriptor( &g_Desc[1], intermediatexfercfg, (void *)&FLEXCOMM5_USB_PC_PERIPHERAL->FIFORD, /* Source address: USART FIFO Read Register */ &g_data_2[0], /* Destination address: RAM buffer */ &g_Desc[2] /* Point to next descriptor */ ); //Descriptor #2 (final) DMA_SetupDescriptor( &g_Desc[2], finalxfercfg, (void *)&FLEXCOMM5_USB_PC_PERIPHERAL->FIFORD, /* Source address: USART FIFO Read Register */ &g_data_3[0], /* Destination address: RAM buffer */ NULL /* Final descriptor, does not move to another*/ ); /* 5. Set up Head Transfer to execute first descriptor first */ /* Point the initial hardware channel block straight to the first buffer to save data */ DMA_PrepareChannelTransfer( &channelConfig, /* 1. Pointer to configuration structure */ (void *)&FLEXCOMM5_USB_PC_PERIPHERAL->FIFORD, /* 2. Source start address */ (void *)&g_data_1[0], /* 3. Destination start address */ DMA_CHANNEL_XFER( /* 4. Initial transfer settings bitmask */ true, /* reload: true to step into linked descriptor */ false, false, false, sizeof(uint8_t), kDMA_AddressInterleave0xWidth, kDMA_AddressInterleave1xWidth, DESCRIPTOR_TRANSFER_SIZE ), kDMA_PeripheralToMemory, /* 5. Transfer type enum path */ NULL, /* 6. Hardware Trigger parameters (NULL uses default peripheral request) */ &g_Desc[1] /* 7. Address of next descriptor. (including already 2nd descriptor, as this will already transfer all the data to begining of rxBuffer like first descriptor would have done*/ ); DMA_SubmitChannelTransfer(&FLEXCOMM5_USB_PC_RX_Handle,&channelConfig); DMA_StartTransfer(&FLEXCOMM5_USB_PC_RX_Handle); } LPC55xx 外设 Re: Using DMA Descriptors to receive Data bigger than 1024 bytes (LPC55S69) 你好， 感谢您分享您的研究结果和代码。社区是分享发现、提出问题、提供指导和支持的好地方，所以我们感谢您在这里发帖。 如果您需要任何进一步的帮助，请与我们联系。 此致敬礼，路易斯

S32K312 ADCトリガーRTD3.0.0 S32DS3.5を使ったMCUのウェイクアップ こんにちは、 私はS32k312コントローラーmini EVBKITを使っており、MCUのスリープとウェイクアップの機能チェックに使っています。ADCで低いしきい値と高いしきい値電圧値を付けることで、ADC割り込みを通じてMCUのウェイクアップを実現しようとしています。この機能を使ってMCUを起動させてください。 LavanyaPilli_1-1784889112438.png Re: S32K312 MCU wakeup using ADC trigger RTD3.0.0 S32DS3.5 こんにちは、 ご説明いただきありがとうございます。 ご指摘いただいたとおり、スタンバイウェイクアップにLPCMPを使用することを検討してみます。しかし、アプリケーション要件に関しては、ADC割り込みウェイクアップ機能の実装が必要です。 ADCを外部割り込みウェイクアップとして特定設定できるかどうか、MEXファイルの検証を手伝ってもらえますか? Re: S32K312 MCU wakeup using ADC trigger RTD3.0.0 S32DS3.5 こんにちは、 @LavanyaPilli さん。 もちろん。PTA1(ADC0_S9)を外部割り込みウェイクアップとして使用している場合は、割り当てられたWKPUチャネルを見つけるためにS32K312_IOMUX.xlsxファイルを参照できます: Julin_AragnM_0-1785173159422.png PTA1はWKPU[5]ですが、4つの内部ウェイクアップソースがあるため、オフセットとして+4も追加する必要があります。これにより、PTA1はWKPU_CH_9になります。 Julin_AragnM_1-1785173923562.png WKPUユニットを初期化し、それぞれのチャネルを設定する必要があります: /* WKPU configuration */ Wkpu_Ip_Init(WKPU_INST, &Wkpu_Ip_Config_PB); Wkpu_Ip_EnableInterrupt(WKPU_INST, Wkpu_Ip_ChannelConfig_PB[0].hwChannel); 以下の低消費電力の例を参考にしてください: S32K3の低消費電力管理ANとデモ 例：CAN-0-RXおよびGPIOスイッチDS3.5 RTD300を使用してS32K312スタンバイ・モードからウェイクアップする [RTD600 IP] S32K312EVB-Q172 スタンバイRAM GPIOウェイクアップ よろしくお願いします、 ジュリアン Re: S32K312 MCU wakeup using ADC trigger RTD3.0.0 S32DS3.5 こんにちは、 @Julián_AragónM さん、 参考資料をありがとうございます。大変参考になりました。現在、CANベースのウェイクアップ構成を使用しています。ADCベースのウェイクアップ設定については、後日評価する予定です。

xaf_record 示例在 SDK_26_06_00_MIMXRT700-EVK 中因 comp_setup 失败而失败 板： MIMXRT700-EVK SDK 版本： SDK_26_06_00_MIMXRT700-EVK 示例：SDK_26_06_00_MIMXRT700-EVK/mcuxsdk/中间件/cadence/multicore-xaf/examples/xaf_record/cm/ 版本配置：默认示例，未做任何修改 使用 shell 命令 record_dmic en 启动 DMIC 录音后 DSP 报告元器件设置失败，导致录制管道无法正常工作。 控制台输出 ****************************** DSP音频框架演示开始 ****************************** [CM33 主控] 配置编解码器 [DSP_Main] Cadence Xtensa 音频框架 [DSP_Main] 库名称：音频框架（无主机） [DSP_Main] 库版本：3.6 [DSP_Main] API 版本：3.4 [DSP_Main] 开始 [DSP_Main] 已建立 RPMsg 连接 [CM33 主控] DSP 图像已复制到 DSP TCM [CM33 主程序][APP_DSP_IPC_Task] 开始 [CM33 主程序][APP_Shell_Task] 开始 版权所有 2024 NXP >> record_dmic en [CM33 CMD] 设置 VIT 语言为英语 [DSP_Main] 通道数：1，采样率：16000，PCM 带宽：32 [CM33 CMD] [APP_DSP_IPC_Task] 来自 DSP 的响应，命令：13，错误：0 [DSP 录音] 音频设备已准备就绪 [CM33 CMD] DSP DMIC 录音已开始 [DSP 记录] comp_setup 失败：4294967294 [CM33 CMD] 要查看 VIT 功能，请说出唤醒词和命令 [CM33 CMD] [APP_DSP_IPC_Task] 来自 DSP 的响应，命令：13，错误：4294967295 [CM33 CMD] DSP DMIC 录音已开始 [CM33 CMD] 要查看 VIT 功能，请说出唤醒词和命令 预期行为 执行后： record_dmic en DMIC 录制管道应成功初始化，从而实现音频捕获和 VIT 唤醒词检测，而不会出现任何元器件设置错误。 实际行为 DSP报告： [DSP 记录] comp_setup 失败：4294967294 随后是IPC的回应： 错误：4294967295 因此，录制管道无法按预期运行。 要求 请问您能否帮忙辨认以下物品？ 默认 xaf_record 示例中导致 comp_setup 失败（错误代码 4294967294）的原因是什么？ 这是否表明缺少 DSP 元器件、编解码器配置问题或其他初始化问题？ SDK 26.06.00 中的 xaf_record 示例是否存在已知问题或补丁？ 使用 record_dmic 命令之前是否需要任何额外的配置步骤？ 非常感谢您能提供任何关于调试此问题的指导。 评估板 Re: xaf_record Example Fails with comp_setup failure in SDK_26_06_00_MIMXRT700-EVK 嗨@suhas1503 ， 请问您能否提供一下您正在使用的集成开发环境（IDE）的相关信息？是MCUXpresso IDE还是VS Code？ 我尝试在 MCUXpresso IDE 中重现该问题，但运行正常。 Gavin_Jia_0-1785739563410.png 在您的日志信息中，我没有找到任何与“[DSP VIT]”相关的内容。我怀疑这可能是由于本地项目中缺少内容造成的，而不是软件错误。 此致， 加文 Re: xaf_record Example Fails with comp_setup failure in SDK_26_06_00_MIMXRT700-EVK 我们已从以下链接下载了 SDK；同时附上截图；我们下载的 SDK 版本为 26.06.00。 Screenshot from 2026-08-03 12-23-01.png https://mcuxpresso.nxp.com/download/c7b3a37a7e9e773a92291031541e9b58 我们正在通过命令行进行编译和烧录。 版本命令： west build -b mimxrt700evk 中间件/cadence/multicore-xaf/examples/xaf_record/cm -d build/ -- -Dcore_id=cm33_core0 -Dtarget=flash_debug 闪存命令： LinkServer flash MIMXRT798S:MIMXRT700-EVK load dsp_xaf_record_cm33_core0.elf Re: xaf_record Example Fails with comp_setup failure in SDK_26_06_00_MIMXRT700-EVK 请查收以上回复。 Re: xaf_record Example Fails with comp_setup failure in SDK_26_06_00_MIMXRT700-EVK 我使用相同的软件包重现了该问题。 我将展开内部调查，看看是否存在任何出入。这可能需要一些时间。与此同时，我建议您继续基于 MCUXpresso IDE 项目进行开发，以节省时间。 一旦基于 Arm GCC 工具链的 SDK 代码包，软件包的问题得到解决，你就可以移植你的项目了。

etpuc mpc5775 eTPUCのcw関数セレクタから関数の1つを実行させたいです。私はetpucの開始/終了RAMアドレスを認識しています（mpc5777c_vars_c.hと同じです）。それに応じて、etpuc 用にmy_system_etpu_init を修正しました。私は（crankのような）関数ファイルをコピーして、etpuc用の新しいファイルを生成するだけです。 すべてを実行してプログラムを中断すると、デバッガーが停止します。PC: "0x800400" のソースが利用できません 何が問題なのでしょうか？ Re: etpuc mpc5775 以下にいくつかのアプリケーションノートがありますが、ETPUイニシエーションコードについて何が変更されましたか? AN5374:アプリケーションにおけるeTPUライブラリの使用 – アプリケーションノート AN4907:エンジン制御eTPUライブラリ – アプリケーションノート [[ ## completed ##]] AN2864:eTPUの一般的なC機能 – アプリケーションノート AN4908:エンジン制御eTPUデモアプリケーション – アプリケーションノート [[ ## completed ##]] Re: etpuc mpc5775 eTPUコードはどのように生成されたのですか？関数セレクタを使って完全な関数セットを生成しましたか?それともCRANK関数ファイルをコピーしただけですか? あなたの修正されたmy_system_etpu_init()実装を教えてもらえますか? 初期化中に生成されたeTPUコードイメージはSCMに正常にロードされましたか？ 生成されたeTPUプロジェクトファイル(例:)etpu_set.c、etpu_set.h)? PCは常に0x800400で停止するのですか、それとも毎回異なるのですか？

无法为 SE051C2 生成代码 各位同事，大家好！我正在尝试将 SE051 与 FRDM-MCXN947 开发板集成。我参考了 AN13030 指南，并按照所有步骤操作，直到运行 Python 脚本生成代码，但遇到了以下错误： 找不到“cmake.exe”。假设'cmake.exe'已在路径中并且正在运行。 信息： __main__ ：正在预处理 C:\Users\yash.bawankar\Downloads\se05x_mw_v04.08.01\simw-top/ext/open62541/tools/schema/Opc.Ua.NodeSet2.Minimal.xml 信息： __main__ ：正在为后端生成代码：open62541 信息： __main__ ：节点集生成代码已成功打印 请告诉我我遗漏了什么。 FRDM 培训 MCX N 安全（Edgelock | 安全启动 | OTP） Re: Unable to generate code for SE051C2 你好@yashbawankar ， 你是打算在窗户下面建造微波设备吗？如果答案是肯定的，请确保满足以下先决条件： • 已安装 Visual Studio • 已安装 Python 3.8 32 位版本 有关先决条件安装步骤的更多详细信息，请参阅https://www.nxp.com/docs/en/application-note/AN12398.pdf 。您可以在https://www.nxp.com/docs/en/application-note/AN12398.pdf的第 8 章中找到 cmake 安装步骤。 希望对您有所帮助。 祝你有美好的一天， 坎 ------------------------------------------------------------------------------- 笔记： - 如果此回复解答了您的问题，请点击“标记为正确答案”按钮。谢谢你！ - 我们会持续关注帖子，从最后一条回复发出后持续7周，之后的回复将被忽略。 如果您之后有相关问题，请另开新帖并引用已关闭的帖子。 -------------------------------------------------------------------------------

SDK_26_06_00_MIMXRT700-EVK で、xaf_record の例が comp_setup の失敗により失敗する ボード: MIMXRT700-EVK SDK Version: SDK_26_06_00_MIMXRT700-EVK 例: SDK_26_06_00_MIMXRT700-EVK/mcuxsdk/middleware/cadence/multicore-xaf/examples/xaf_record/cm/ ビルド構成：変更なしのデフォルト例 シェルコマンド record_dmic en を使用して DMIC 録音を開始した後 DSPはコンポーネントセットアップの失敗を報告し、記録パイプラインが正しく機能しなくなります。 コンソール出力 ****************************** DSPオーディオフレームワークのデモ開始 ****************************** [CM33 メイン] コーデックの設定 [DSP_Main]Cadence Xtensa オーディオフレームワーク [DSP_Main]ライブラリ名:Audio Framework(ホストレス) [DSP_Main]ライブラリバージョン:3.6 [DSP_Main]APIバージョン:3.4 [DSP_Main] スタート [DSP_Main] RPMsgリンクを確立しました [CM33メイン]DSPイメージをDSP TCMにコピー [CM33メイン][APP_DSP_IPC_Task] スタート [CM33メイン][APP_Shell_Task] スタート 著作権 2024 NXP >> record_dmic en [CM33 CMD]VIT 言語を en に設定する [DSP_Main]チャネル数1、サンプリングレート16000、PCM幅32 [CM33 CMD][APP_DSP_IPC_タスク]DSPからの応答、cmd: 13、エラー: 0 [DSPレコード]オーディオデバイス準備完了 [CM33 CMD]DSP DMIC録音開始 [DSP記録] comp_setup故障:4294967294 [CM33 CMD]VIT機能を見るにはwakewordとcommandを選んでください [CM33 CMD][APP_DSP_IPC_タスク]DSPからの応答、cmd: 13、error: 4294967295 [CM33 CMD]DSP DMIC録音開始 [CM33 CMD]VIT機能を見るにはwakewordとcommandを選んでください 期待される動作 実行後： record_dmic en DMIC録音パイプラインは正常に初期化され、コンポーネント設定エラーなしに音声キャプチャやVITウェイクワード検出が可能になります。 実際の行動 DSPの報告は以下の通りです: [DSP記録] comp_setup故障:4294967294 続いて、IPCからの応答が以下のように表示されます。 エラー: 4294967295 その結果、レコーディングパイプラインが期待どおりに機能しない。 要望 以下の点を特定するのを手伝ってもらえますか? デフォルトのxaf_recordサンプルで、comp_setupエラー4294967294が発生する原因は何ですか？ これはDSPコンポーネントの欠落、コーデック設定の問題、あるいは他の初期化の問題を示しているのでしょうか? SDK 26.06.00のxaf_record例に対して既知の問題やパッチはありますか? record_dmicコマンドを使用する前に、追加の設定手順が必要ですか？ この問題のデバッグに関するアドバイスをいただければ幸いです。 評価ボード Re: xaf_record Example Fails with comp_setup failure in SDK_26_06_00_MIMXRT700-EVK 上記の回答をご確認ください。 Re: xaf_record Example Fails with comp_setup failure in SDK_26_06_00_MIMXRT700-EVK 同じパッケージで問題を再現できました。 内部調査を実施し、矛盾点がないか確認します。これには時間がかかるかもしれません。その間、時間を節約するためにMCUXpresso IDEプロジェクトをベースに開発を続けることをお勧めします。 ARM GCCツールチェーンに基づくSDKパッケージの問題が解決したら、プロジェクトを移植できます。 Re: xaf_record Example Fails with comp_setup failure in SDK_26_06_00_MIMXRT700-EVK こんにちは@suhas1503さん 使っているIDEについて何か情報を教えていただけますか?MCUXpresso IDEですか、それともVS Codeですか? MCUXpresso IDEで問題を再現しようとしましたが、問題なく動作しました。 Gavin_Jia_0-1785739563410.png ログ情報には「[DSP VIT]」に関するものは見つかりませんでした。これはソフトウェアのバグというよりは、ローカルプロジェクトにコンテンツが不足していることが原因かもしれません。 よろしくお願いします、 ギャビン Re: xaf_record Example Fails with comp_setup failure in SDK_26_06_00_MIMXRT700-EVK 以下のリンクからSDKsをダウンロードしました。また、スナップの取り付けも行います。SDKsバージョン26.06.00をダウンロードしました Screenshot from 2026-08-03 12-23-01.png https://mcuxpresso.nxp.com/download/c7b3a37a7e9e773a92291031541e9b58 [[ ## completed ##]]コマンドライン経由でコンパイルとフラッシュを行っています ビルドコマンド: west build -b mimxrt700evk middleware/cadence/multicore-xaf/examples/xaf_record/cm -d build/ -- -Dcore_id=cm33_core0 -Dtarget=flash_debug フラッシュコマンド: LinkServer フラッシュ MIMXRT798S:MIMXRT700-EVK ロード dsp_xaf_record_cm33_core0.elf

SE051C2のコードを生成できません こんにちは、チームの皆さん。SE051をFRDM-MCXN947ボードに統合しようとしています。ガイドを読AN13030んで、Pythonスクリプトを実行するまですべての手順を踏んでコードを生成しましたが、このエラーが出ています: 「cmake.exe」は見つかりませんでした。「cmake.exe」がパスに含まれており、実行中であることを前提とします。 情報:__main__:P再解析 C:\Users\yash.bawankar\Downloads\se05x_mw_v04.08.01\simw-top/ext/open62541/tools/schema/Opc.Ua.NodeSet2.Minimal.xml INFO: __main__ :バックエンドのコードを生成中: open62541 INFO: __main__ :NodeSet生成コードが正常に出力されました 何か見落としている点があれば教えてください。 FRDMトレーニング MCX N セキュリティ（EdgeLock | セキュアブート | OTP） Re: Unable to generate code for SE051C2 こんにちは、 @yashbawankar さん。 MWをビルディングしていますか?はいの場合、以下の前提条件を満たしていることを確認してください。 • Visual Studioがインストールされています • Python 3.8 32ビット版がインストールされている 前提条件となるインストール手順の詳細については、 https://www.nxp.com/docs/en/application-note/AN12398.pdfを参照してください。cmake のインストール手順については、 https://www.nxp.com/docs/en/application-note/AN12398.pdfの第 8 章を参照してください。 お役に立てば幸いです。 すてきな一日を、 カン ------------------------------------------------------------------------------- 注記： この投稿があなたの質問への回答になっている場合は、「正解としてマーク」ボタンをクリックしてください。ありがとうございます! - 前回の投稿から7週間Threadをフォローしており、その後の返信は無視しています もし後で関連する質問があれば、新しいThreadを開き、閉じたThreadを参照してください。 -------------------------------------------------------------------------------

RTC電力計算 こんにちは、NXPさん。 RT1176のSNVS電源ドメインに必要なアクティブ電流とスリープ電流を用いて、RTCのバッテリー寿命を計算しています。 ただし、データシートIMXRT1170BIEC - 表13、35ページを参照してください。スリープ電流のみが記載されています。 SNVS電力領域における有効電流に影響を与える要因と、有効電流に関連する各種計算についてお知らせください。 Re: RTC Power Calculation こんにちは、 @specneeraj さん。 NXP MIMXRTシリーズにご関心をお寄せいただきありがとうございます！ VDD_SNVS_INはSNVS/RTCドメインに電力を供給します。このドメインは常時オンの低消費電力ドメインで、主に32 kHzのRTC、SNVSロジック、関連するウェイクアップおよびセーフティ機能を維持します。現在の消費量はCM7/CM4の活動状態/睡眠状態とは弱い相関しかありません。したがって、表13に示されたSNVSモードのVDD_SNVS_IN値は「スリープのみ」のデータではなく、RTCバックアップシナリオで使用できるベースライン値です。 コイン型電池が主電源の故障時のみ電力を供給する場合 → SNVSモードの電流推定値を直接使用する。 システムがアクティブな間、コイン型電池が VDD_SNVS_IN にも電力を供給する場合、アクティブ/SNVSデューティサイクルに基づいて平均電流を計算します。 SNVS電流に影響を与える主な要因としては、温度、 VDD_SNVS_IN 電圧、プロセスばらつき、32kHz RTC水晶発振器/基板からのリーク電流、SNVS関連ピンからの外部リーク電流、およびデバイスが実際にSNVSモードに入っているかどうかなどが挙げられます。詳細については、 AN13104を参照してください。 よろしくお願いします、 ギャビン

Unable to generate code for SE051C2 Hello Team, I am trying to Integrate SE051 with FRDM-MCXN947 board, by reading AN13030 guide, I followed all the steps till running python script to generate code but I am getting this error:  Could not find 'cmake.exe'. Assuming 'cmake.exe' is in path and running. INFO:__main__:Preprocessing C:\Users\yash.bawankar\Downloads\se05x_mw_v04.08.01\simw-top/ext/open62541/tools/schema/Opc.Ua.NodeSet2.Minimal.xml INFO:__main__:Generating Code for Backend: open62541 INFO:__main__:NodeSet generation code successfully printed Please let me know what am I missing. FRDM-Training MCXN Security(Edgelock | secure boot | OTP) Re: Unable to generate code for SE051C2 Hi @yashbawankar , Are you building the MW under windows? If yes, please make sure the following Prerequisite are met: • Visual studio installed • Python 3.8 32 bit installed and please refer https://www.nxp.com/docs/en/application-note/AN12398.pdf  for more details on prerequisite installation steps. and you may find cmake install steps in chapter 8 within https://www.nxp.com/docs/en/application-note/AN12398.pdf . Hope that helps, Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

FS6500の障害フラグ消去動作 チームの皆さん、こんにちは。 FS6500の障害フラグ消去動作について質問があります。   データシートによると、MODEレジスタ（アドレス0x15）内のLPOOF（ビット0）およびDFS（ビット1）フラグは、電源投入リセットまたはレジスタ読み出し操作によってのみクリアされます。 しかし、私のハードウェアテストの結果はこうです。   MODEレジスタへの書き込みは、予期せずLPOOFおよびDFS障害ビットをクリアしてしまう。   データシートには書き込みアクセスでこれらのステータスフラグが消えるという説明はありません。 この現象の根本原因について説明してもらえますか?   これはシリコンの意図された挙動なのか、それとも記録されていない副作用なのか？   ありがとうございます。よろしくお願いいたします。   DEVKIT-MPC5744P FS6500 Re: Fault flag clearing behavior of FS6500 こんにちは、 指示書が正しく書かれているか確認してください。 ほとんどのソフトウェアドライバでは、レジスタ書き込みは読み取り・修正・書き込み(RMW)シーケンスとして実装されています。 データシートに読み取りモードによってLPOOF/DFSがクリアされると記載されている場合、読み取りフェーズ中に既にフラグがクリアされている可能性があります。その後の書き込みは、書き込み操作によってクリアリングが行われたという印象を与えるに過ぎない。 よろしくお願いいたします。 ピーター

Using DMA Descriptors to receive Data bigger than 1024 bytes (LPC55S69) Hello Community,  I was having difficulties to find a way to receive big amounts of data (over 2000 bytes) via DMA to my LPC55S69 board, considering that DMA has a maximum transfer size of 1024 bytes. I had a look at example "usart_dma_double_buffer_transfer" however some functions were outdated, considering for example: DMA_PrepareTransfer() became DMA_PrepareChannelTransfer(), DMA_SubmitTransfer() became DMA_SubmitChannelTransfer() and DMA_CreateDescriptor() became DMA_SetupDescriptor(). So i was a bit lost filling the new input parameters of these new functions that did not appear in the example, mostly the parameter "xfercfg" Transfer configuration for DMA descriptor present in new DMA_SetupDescriptor(). I also had a look at example "dma_channel_chain" which also helped me to get another view on some of the new functions, however it was not exactly what i was looking for.  In addition i took a look at the article DMA Ping-Pong application - NXP Community however it was not exactly compatible to the LPC board i was using. After putting altogether the information from what i could acquire online and smashing my head a bit against the keyboard i finally made it to arrive to the point i wanted, receiving big amounts of data via DMA. (Saving data in 3 different buffers, each with 1024 bytes of size) So i'm using this opportunity to share the code in the hope of being helpful or giving some guidance to maybe someone that finds itself in the same road i was before. Also trying to give back a bit from all the things i have learned from this beautiful community. (Hope that is fine that this is posted here, considering is not exactly a question, but is also a topic open for discussions). Best of luck! #include "fsl_usart_dma.h" #include "fsl_dma.h" #define NUMBER_DESCRIPTORS 3 #define DESCRIPTOR_TRANSFER_SIZE 1024 #define RX_BUFFER_SIZE 1024 uint8_t g_data_buffer[RX_BUFFER_SIZE]; uint8_t g_data_1[RX_BUFFER_SIZE]; uint8_t g_data_2[RX_BUFFER_SIZE]; uint8_t g_data_3[RX_BUFFER_SIZE]; /* Custom Descriptors (Must be 16-byte aligned) */ SDK_ALIGN(dma_descriptor_t g_Desc[NUMBER_DESCRIPTORS], 16); /* equal to writing: __attribute__((aligned(FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE))) dma_descriptor_t g_Desc[NUMBER_DESCRIPTORS] = {0}; or DMA_ALLOCATE_LINK_DESCRIPTORS_AT_NONCACHEABLE(g_Desc, NUMBER_DESCRIPTORS); */ /* Function definitions ****************************************************************************/ //Initialising Rx DMA to receive data bigger than 1024 bytes. void init_USART_DMA(void){ //Channel configuration for DMA descriptor dma_channel_config_t channelConfig; /* 1. System/Peripheral Level Init */ // Done in peripheral.c, initialized the functions USART_Init(), DMA_EnableChannel(), DMA_CreateHandle(), USART_TransferCreateHandleDMA(). /*I have not used the function DMA_SubmitChannelDescriptor(), by giving as input the g_ChannelTable, as it would not allow to receive data. the g_ChannelTable variable should be initalized as follow: //Allocates the mandatory, 512-byte aligned master table in RAM used by the hardware to manage all DMA channels SDK_ALIGN(dma_descriptor_t g_ChannelTable[FSL_FEATURE_DMA_MAX_CHANNELS], 512); then call the function here in the code DMA_SubmitChannelDescriptor(FLEXCOMM5_USB_PC_RX_Handle,g_ChannelTable); */ /* 2. Enable USART RX DMA requests */ USART_EnableRxDMA(FLEXCOMM5_USB_PC_PERIPHERAL, true); /* 3. Prepare the Descriptor Configuration Variable Flags */ //Intermediate Descriptors, where it jumps from one to another /* Common XFER configuration options for intermediate descriptors (1, 2,...) */ /* reload = true (keeps the chain moving to the next descriptor) */ /* intA = false (we only want the final interrupt when everything is done) */ uint32_t intermediatexfercfg = DMA_CHANNEL_XFER( true, /* reload: true to move to the next descriptor */ false, /* clrTrig: false */ false, /* intA: false */ false, /* intB: false */ sizeof(uint8_t), /* width: 1 byte for USART char processing */ kDMA_AddressInterleave0xWidth, /* srcInc: 0x (read from fixed USART FIFO address) */ kDMA_AddressInterleave1xWidth, /* dstInc: 1x (increment buffer pointer by 1 byte) */ DESCRIPTOR_TRANSFER_SIZE /* totalBytes: DESCRIPTOR_TRANSFER_SIZE */ ); //Final Descriptor, where it stops jumping to another descriptor /* Final XFER configuration options for the last descriptor */ /* reload = false (this is the end of the chain) */ /* clrTrig = true (stop the DMA hardware channel) */ /* intA = true (fire the completion interrupt) */ uint32_t finalxfercfg = DMA_CHANNEL_XFER( false, /* reload: false because this is the terminal descriptor */ true, /* clrTrig: true to clear peripheral hardware requests */ true, /* intA: true to fire our completion interrupt */ false, /* intB: false */ sizeof(uint8_t), /* width: 1 byte for USART char processing */ kDMA_AddressInterleave0xWidth, /* srcInc: 0x (read from fixed USART FIFO address) */ kDMA_AddressInterleave1xWidth, /* dstInc: 1x (increment buffer pointer by 1 byte) */ DESCRIPTOR_TRANSFER_SIZE /* totalBytes: DESCRIPTOR_TRANSFER_SIZE */ ); /* 4. Configure the Custom Descriptors structure */ //Descriptor #0 DMA_SetupDescriptor( &g_Desc[0], intermediatexfercfg, (void *)&FLEXCOMM5_USB_PC_PERIPHERAL->FIFORD, /* Source address: USART FIFO Read Register */ &g_data_1[0], /* Destination address: RAM buffer */ &g_Desc[1] /* Point to next descriptor */ ); //Descriptor #1 DMA_SetupDescriptor( &g_Desc[1], intermediatexfercfg, (void *)&FLEXCOMM5_USB_PC_PERIPHERAL->FIFORD, /* Source address: USART FIFO Read Register */ &g_data_2[0], /* Destination address: RAM buffer */ &g_Desc[2] /* Point to next descriptor */ ); //Descriptor #2 (final) DMA_SetupDescriptor( &g_Desc[2], finalxfercfg, (void *)&FLEXCOMM5_USB_PC_PERIPHERAL->FIFORD, /* Source address: USART FIFO Read Register */ &g_data_3[0], /* Destination address: RAM buffer */ NULL /* Final descriptor, does not move to another*/ ); /* 5. Set up Head Transfer to execute first descriptor first */ /* Point the initial hardware channel block straight to the first buffer to save data */ DMA_PrepareChannelTransfer( &channelConfig, /* 1. Pointer to configuration structure */ (void *)&FLEXCOMM5_USB_PC_PERIPHERAL->FIFORD, /* 2. Source start address */ (void *)&g_data_1[0], /* 3. Destination start address */ DMA_CHANNEL_XFER( /* 4. Initial transfer settings bitmask */ true, /* reload: true to step into linked descriptor */ false, false, false, sizeof(uint8_t), kDMA_AddressInterleave0xWidth, kDMA_AddressInterleave1xWidth, DESCRIPTOR_TRANSFER_SIZE ), kDMA_PeripheralToMemory, /* 5. Transfer type enum path */ NULL, /* 6. Hardware Trigger parameters (NULL uses default peripheral request) */ &g_Desc[1] /* 7. Address of next descriptor. (including already 2nd descriptor, as this will already transfer all the data to begining of rxBuffer like first descriptor would have done*/ ); DMA_SubmitChannelTransfer(&FLEXCOMM5_USB_PC_RX_Handle,&channelConfig); DMA_StartTransfer(&FLEXCOMM5_USB_PC_RX_Handle); } LPC55xx Peripherals Re: Using DMA Descriptors to receive Data bigger than 1024 bytes (LPC55S69) Hello, Thank you for sharing your findings and code. The community is a great place to share discoveries, ask questions, and provide guidance and support, so we appreciate you posting it here.  If you need any further assistance, please let us know. Best Regards, Luis

imx93 AHAB SGK support Are SGKs for secure boot signatures now supported in imx93 or still only SRKs? Application note 12312 "Secure Boot on AHAB Supported Devices" says in Chapter 3: Note: For i.MX8ULP and i.MX93, only SRK is supported in the current released firmware. Is this still true or are SGKs supported now? If so, from which firmware release? Re: imx93 AHAB SGK support This is still true. SGK is not supported in i.MX93.  Regards Harvey Re: imx93 AHAB SGK support Hi, how about the imx91, does it support SGK? (The Reference Manual suggests it does)

LS1046A DDR4 32GB DDR4 Size Support Hi,  I would like to know if LS1046A support 32GB of DDR4 Memory. Also can it work with DDR3L. Re: LS1046A DDR4 32GB DDR4 Size Support Thank you yipingwang for the prompt reply, what might be the maximum supported size of DDR for LS1034A. Re: LS1046A DDR4 32GB DDR4 Size Support 1. Does LS1046A support 32 GB DDR4? Yes. 2. Can LS1046A work with DDR3L? No. LS1043A supports a 32-bit DDR3L/DDR4 controller , while LS1046A/LS1088A support a 64-bit DDR4 controller . Re: LS1046A DDR4 32GB DDR4 Size Support LS1043A supports up to 32 GB DDR/main memory per the LS1043A Reference Manual/Product Brief

关于 S32K388 BIST 问题的更新：软复位导致应用程序外设初始化失败 您好，NXP支持团队， 针对之前 BIST 硬复位的问题：我们应用了您提出的更改，现在 BIST 可以成功执行软复位。 为了适应这种软复位并避免两次 MCU 时钟初始化，我们最初将 MCU 时钟初始化保留在应用程序中。然而，在 BIST 软复位并跳转到应用程序后，时钟重新初始化花费的时间异常长。我们怀疑出现这种延迟和死机的原因是启动管理器已经初始化了时钟，导致第二次尝试时发生冲突。 为了解决这个严重的延迟问题，我们完全从应用程序中移除了 MCU 时钟初始化，只将其保留在启动管理器中。不幸的是，这又引入了一个新问题：跳转到应用程序后，系统现在会在外围设备初始化期间（特别是 FlexCAN）挂起，这表明存在时钟可用性问题。 您能否就正确的时钟配置策略提供一些建议？具体来说，BIST 软复位是否会扰乱 BM 初始化的时钟，从而需要在应用程序中重新初始化？我们如何在 BM 和应用程序之间正确地交接时钟，而不会导致死机或极端延迟？ Re: Update on S32K388 BIST issue: Soft reset causing peripheral init failure in App 嗨@HazemIhab ， 我没有在任何支持工单或社区帖子中找到您之前提到的 BIST 硬RESET问题。 我理解您看到的是 ST_DONE 功能复位。 RESET后，时钟配置会被重置，因此需要重新初始化。 如果您使用 RTD 驱动程序，Clock_Ip_InitClock() 函数会首先将所有时钟重置为安全状态——如果您在启动管理器和应用程序中都初始化时钟，这可能就是您看到的延迟。 它只能在启动管理器中进行配置，但您需要确保驱动程序启用应用程序所需的所有时钟——在本例中为 FlexCAN 时钟。 此外，所有系统时钟必须与 RM 中列出的时钟选项之一相匹配，例如表156。选项 A - 高性能模式 (CM7_CORE_CLK @ 160 MHz) (适用于 S32K388/S32K389)。 BR，丹尼尔 Re: Update on S32K388 BIST issue: Soft reset causing peripheral init failure in App 你好@danielmartynek 谢谢你的解释。 为了澄清我们的设置：我们的启动管理器 (BM) 和应用程序 (App) 已经使用完全相同的时钟配置，包括 FlexCAN 时钟设置。 为了避免安全状态 RESET 带来的延迟，我们让 BM 初始化所有时钟，并从 App 中移除了 Clock_Ip_InitClock()。但是，当应用程序尝试在跳转后初始化 FlexCAN 时，系统仍然会因时钟相关错误而挂起。 Re: Update on S32K388 BIST issue: Soft reset causing peripheral init failure in App 嗨@HazemIhab ， 我了解到存在故障例外情况，您能确认一下吗？ 如果是这样，你需要找到更多关于该异常的信息，以确认它是否真的与时钟有关。 https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-HARDFAULT-Handling-Interrupt-DS3-5-RTD300/ta-p/1806259 https://community.nxp.com/t5/S32K-Knowledge-Base/How-To-Debug-A-Fault-Exception-On-ARM-Cortex-M-V7M-MCU-S32K3XX/ta-p/1595570 https://community.nxp.com/t5/S32K-Knowledge-Base/Fault-handling-on-S32K14x/ta-p/1114447 如果没有异常，但程序执行陷入了循环，那么究竟是哪个环节出了问题？ 另外，正如我提到的，所有系统时钟必须与 RM 中列出的时钟选项之一相匹配，例如：表156。选项 A - 高性能模式 (CM7_CORE_CLK @ 160 MHz) (适用于 S32K388/S32K389)，请确认？ 谢谢！ BR，丹尼尔

UM11490 and Bluetooth Classic Dear NXP support, one of our customer is running the following commands from pag 149 of UM11490, but cannot see any waveform. Please kindly check and verify if any additional command / condition is missing. Thanks Best Regards Pier ------------------------------------ # RESET root@myboard:/home/BTtest# hcitool -i hci0 cmd 0x03 0x0003 < HCI Command: ogf 0x03, ocf 0x0003, plen 0 > HCI Event: 0x0e plen 4 01 03 0C 00 # ENABLE SCAN root@myboard:/home/BTtest# hcitool -i hci0 cmd 0x03 0x001a 0x3 < HCI Command: ogf 0x03, ocf 0x001a, plen 1 03 > HCI Event: 0x0e plen 4 01 1A 0C 00 # ENABLE EVENT FILTER root@myboard:/home/BTtest# hcitool -i hci0 cmd 0x03 0x0005 0x02 0x00 0x02 < HCI Command: ogf 0x03, ocf 0x0005, plen 3 02 00 02 > HCI Event: 0x0e plen 4 01 05 0C 00 # ENTER IN TEST MODE root@myboard:/home/BTtest# hcitool -i hci0 cmd 0x06 0x0003 < HCI Command: ogf 0x06, ocf 0x0003, plen 0 > HCI Event: 0x0e plen 4 01 03 18 00 # START THE TX TRANSMISSION root@myboard:/home/BTtest# hcitool -i hci0 cmd 0x3F 0x0019 0x80 0x80 0x80 0x80 0x01 0x00 0x01 0x01 0x0D 0x03 0x0F 0x00 0x00 0x00 0x00 0x00 0x00 0x04 < HCI Command: ogf 0x3f, ocf 0x0019, plen 18 80 80 80 80 01 00 01 01 0D 03 0F 00 00 00 00 00 00 04 > HCI Event: 0x0e plen 4 01 19 FC 00 # STOP THE TX TRANSMISSION root@myboard:/home/BTtest# hcitool -i hci0 cmd 0x3F 0x0019 0x80 0x80 0x80 0x80 0xF F 0x00 0x01 0x01 0x0D 0x03 0x0F 0x00 0x00 0x00 0x00 0x00 0x00 0x04 < HCI Command: ogf 0x3f, ocf 0x0019, plen 18 80 80 80 80 FF 00 01 01 0D 03 0F 00 00 00 00 00 00 04 > HCI Event: 0xff plen 6 19 01 39 00 00 00 -------------------- STOPPING THE SCAN FOR BLE AND CLASSIC BEFORE THE TX TRANSMISSION ---------------- # RESET root@myboard:/home/BTtest# hcitool -i hci0 cmd 0x03 0x0003 < HCI Command: ogf 0x03, ocf 0x0003, plen 0 > HCI Event: 0x0e plen 4 01 03 0C 00 # ENABLE SCAN root@myboard:/home/BTtest# hcitool -i hci0 cmd 0x03 0x001a 0x3 < HCI Command: ogf 0x03, ocf 0x001a, plen 1 03 > HCI Event: 0x0e plen 4 01 1A 0C 00 # ENABLE EVENT FILTER root@myboard:/home/BTtest# hcitool -i hci0 cmd 0x03 0x0005 0x02 0x00 0x02 < HCI Command: ogf 0x03, ocf 0x0005, plen 3 02 00 02 > HCI Event: 0x0e plen 4 01 05 0C 00 # ENTER IN TEST MODE root@myboard:/home/BTtest# hcitool -i hci0 cmd 0x06 0x0003 < HCI Command: ogf 0x06, ocf 0x0003, plen 0 > HCI Event: 0x0e plen 4 01 03 18 00 # DISABLE THE BLE SCAN root@myboard:/home/BTtest# hcitool -i hci0 cmd 0x03 0x001a 0x0 < HCI Command: ogf 0x03, ocf 0x001a, plen 1 00 > HCI Event: 0x0e plen 4 01 1A 0C 00 # DISABLE THE CLASSIC SCAN root@myboard:/home/BTtest# hcitool -i hci0 cmd 0x08 0x000C 0x00 0x00 < HCI Command: ogf 0x08, ocf 0x000c, plen 2 00 00 > HCI Event: 0x0e plen 4 01 0C 20 00 # START THE TX TRANSMISSION root@myboard:/home/BTtest# hcitool -i hci0 cmd 0x3F 0x0019 0x80 0x80 0x80 0x80 0x01 0x00 0x01 0x01 0x0D 0x03 0x0F 0x00 0x00 0x00 0x00 0x00 0x00 0x04 < HCI Command: ogf 0x3f, ocf 0x0019, plen 18 80 80 80 80 01 00 01 01 0D 03 0F 00 00 00 00 00 00 04 > HCI Event: 0x0e plen 4 01 19 FC 00 # STOP THE TX TRANSMISSION root@myboard:/home/BTtest# hcitool -i hci0 cmd 0x3F 0x0019 0x80 0x80 0x80 0x80 0xFF 0x00 0x01 0x01 0x0D 0x03 0x0F 0x00 0x00 0x00 0x00 0x00 0x00 0x04 < HCI Command: ogf 0x3f, ocf 0x0019, plen 18 80 80 80 80 FF 00 01 01 0D 03 0F 00 00 00 00 00 00 04 > HCI Event: 0xff plen 6 19 01 63 07 00 00 ** When disabling the scan before entering in the test mode, the stop for TX transmission give us: root@myboard:/home/BTtest# hcitool -i hci0 cmd 0x3F 0x0019 0x80 0x80 0x80 0x80 0xFF 0x00 0x01 0x01 0x0D 0x03 0x0F 0x00 0x00 0x00 0x00 0x00 0x00 0x04 < HCI Command: ogf 0x3f, ocf 0x0019, plen 18 80 80 80 80 FF 00 01 01 0D 03 0F 00 00 00 00 00 00 04 > HCI Event: 0xff plen 6 19 01 ED 04 00 00 For Wifi 5 GHz -------------------------------------------------------------------------------- Paramters: Continuous transmit, BW = 40 MHz, 802.11ac, No DFS, CH = 40, MCS0 (13.5), Power = 14 dBm root@myboard:/home/BTtest# cat /proc/mwlan/adapter0/config hardware_status=0 netlink_num=31 drv_mode=7 hssetpara=7,0xff,200,400 sdcmd52rw=0 0x0 0x00 rf_test_mode=1 tx_antenna=1 rx_antenna=1 band=1 bw=1 channel=44 radio_mode[0]=3 radio_mode[1]= total rx pkt count=0 rx multicast/broadcast pkt count=0 rx fcs error pkt count=0 tx_power=14 2 0 tx_continuous=0 tx_frame=1 4352 0xaaa 1024 1 20 4294967295 0 0 4294967295 0 0 0 -1 -1 -1 -1 -1 -1 -1 05:43:3f:c4:51:ff he_tb_tx=0 trigger_frame=0 otp_mac_add_rd_wr= 00:00:00:00:00:00 Re: UM11490 and Bluetooth Classic Hi @Christine_Li, sorry for missing the context: kernel version: lf-6.6.52-2.2.2 merged with 6.6.y community kernel FW version: IW612-18.99.3.p25.7, sepaated BT/WiFi FW, no combo product: IW612 UM11490 version: Rev. 1.8 — 2 June 2025 The following details will come ASAP dmesg logs or console logs when you load FW screenshot of the spectrum analyzer settings In the meanwhile, please let us know if you may need anything else. Thanks Best Regards Pier Re: UM11490 and Bluetooth Classic Hi, @pierluigi_p  Which Wi-Fi/Bluetooth product are you using? And what is your Linux kernel version? WiFi/Bluetooth driver and FW version? From the command logs, all HCI commands are completed successfully and the TX start command is accepted by the controller. In addition, the vendor-specific event returned by the TX stop command contains non-zero packet counters, which indicates that the controller believes packets have been transmitted during the test period. Therefore, the issue does not appear to be caused by a missing HCI command in the test sequence. I would recommend checking: The spectrum analyzer center frequency and span settings. The Bluetooth channel configured by the TX test command. The RF antenna configuration on the board. Whether the Bluetooth firmware are loaded correctly. Could you also share: The chip being used (IW416/IW612/etc.)? The exact UM11490 version? The dmesg logs or console logs when you load FW? Are you loading a combo FW or BT only FW? A screenshot of the spectrum analyzer settings? Best regards, Christine. Re: UM11490 and Bluetooth Classic Just adding, it was attempted with different settings for HackRF (gain and graphic adjustments), and we can see the 2.4 GHz (wifi) waveforms. Furthermore, we tested using different firmwares, for different versions in the imx-firmware repository, which includes one firmware for RF-test (sduart_nw61x_rftm_v1.bin.se in https://github.com/nxp-imx/imx-firmware/blob/lf-6.1.1_1.0.0/nxp/FwImage_IW612_SD/IW612_SD_RFTest/sduart_nw61x_rftm_v1.bin.se) without success. Re: UM11490 and Bluetooth Classic Hello Pier and Christine I'm Helbert, the developer who started the thread in the Veriscite forum. Here are some attachments about the testing: Dmesg log (without the power configuration):  Dmesg log (with the power configuration):  Screenshot with the spectrum analyzer and the config file for 5 GHz (own implementation and NXP implementation) 5GHz-running-test.png after 5GHz-after-test.png Note: it was found that using -1 for power, we use the default value, however different values was experimented too. NXP script: NXP-5GHz-running-test.png Screenshot with the classic Bluetooth test: Bluetooth-2.4-Classic-RUNNING.png As you can see, there is no waveform generated Screenshot with the BLE test running: BLE-RUNNING-2.4-CH2.png Screenshot after the BLE testing (waveform interrupted):   BLE-FINISHED.png We can see in the graphic below that the waveform was interrupted when finishing the test Modinfo log: Tested HCI cmds:  Re: UM11490 and Bluetooth Classic Hi, @HelbertPaulino  Thanks for providing me the details. Let me check your info and screenshot, then reply to you. Please allow me some time. Best regards, Christine. Re: UM11490 and Bluetooth Classic Hi， @HelbertPaulino  Thanks for providing us the details. Your screenshot only shows some Background noise, there is no any useful RF waveform information. May I ask: 1.You are using our IW612-EVK? or any module? If module, would you mind let me know your module part number? 2.How is your HW connections with the test equipment? 3.Your question is for BT or Wi-Fi? If for BT, I see your test commands, in our RF test guide, the stop command is: hcitool -i hci0 cmd 0x3F 0x0019 0x80 0x80 0x80 0x80 0xFF but you are sending: root@oaslv:/home/hexagon# hcitool -i hci0 cmd 0x3F 0x0019 0x80 0x80 0x80 0x80 0xFF 0x00 0x01 0x01 0x0D 0x03 0x0F 0x00 0x00 0x00 0x00 0x00 0x00 0x04 Please follow exactly our guide command to execute. Best regards, Christine. Re: UM11490 and Bluetooth Classic Hello Christine, thanks for your checkings 1.You are using our IW612-EVK? or any module? If module, would you mind let me know your module part number? We have the module integrated into the SoM Variscite DART-IMX8M https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-plus/dart-mx8m-plus/ It has the part number: LBES5PL2EL.4 2.How is your HW connections with the test equipment We have wireless access to the equipment's radio through the HackRF One equipment, which can capture the signals using its antenna (but it can capture other signals too; that's the reason for why you are seeing some noise) 3 - Your question is for BT or Wi-Fi? It's for both. For classical Bluetooth, we weren't able to see the generated waveforms (only for Bluetooth Low Energy), and for Wifi, we couldn't capture signals in 5 GHz About the hci command, I saw both, and we have both recommended in the NXP/Murata documents In AN14114, we have the short command on page 47 In UM11490 we have the long command on page 150 For the classic Bluetooth, I think I found the solution. When checking the UM11490, the explanation for the command is: hcitool -i hci0 cmd The examples in the document set tx_test_interval as 0x0D, in this scenario, the interval seems to be a little longer and, hence, it's a little hard to see the generated waveform. It appears like noise. When setting this parameter to 0x01, I could see a consistent waveform. Furthermore, I decreased the frequency range because it's a low-BW waveform. So, I think this solves the Bluetooth issue. However, I'm still not able to see the 5 GHz waveform. Do you have any tips for it? Thanks very much for your assistance Re: UM11490 and Bluetooth Classic Hey Christhine, It was raised the possibility of having another Murata Module in my used SoM. I disassembled the mine and I detected that its part number is: LBEE5PL2DL Hence, I have to review if the commands for 2EL are applicable to this model too Re: UM11490 and Bluetooth Classic Hello Christine, Thanks very much for your support. Debugging here a little more, I found a potential trouble here. When changing the region using the files provided here: https://github.com/murata-wireless/nxp-linux-calibration/tree/imx-6-6-23/murata/files/2DL, I noticed a trouble with iw reg set Basically, following the idea posted here: https://murata.my.site.com/muratacommunity/s/question/0D5RC00001HGuiQ0AT/rf-test-mode-firmware-and-tools-for-murata-type-2dl-module-not-working  I used the files directed for 2EL (and 2DL, they are the same), but when switching the regions, I could note that the iw reg get wasn't changing its location, by presenting the following message: HelbertPaulino_0-1784905230306.png Hence, when changing the regions to be used by the driver with the file *txpower*.bin, we weren't changing the system region. I saw that this has the potential to prevent the waveforms from being triggered, depending on the chosen region and settings applied to the radio. I removed the regulatory.db* files from Murata and used the original, and it seems to have better behavior. I was able to trigger some 5 GHz waveforms, and others I think are being masked by the noises May you confirm if the iw reg set / reg and the used regulatory files can affect the waveform generation? If yes, then I think we found the root cause of the problem. It's not Firmware / Script / Calibration files, but a region limitation. Do you think it makes sense or do you have another suspect for this? Thanks very much again Re: UM11490 and Bluetooth Classic Hi, @HelbertPaulino  Thanks for your info and glad to hear that Bluetooth is now working. So now let's focus on the Wi-Fi 5G RF test mode issue. LBEE5PL2DL module's Chipset is our NXP's WiFi/Bluetooth chipset: IW611. The difference between IW611 and IW612 is: IW612 supports 802.15.4, but IW611 does not support. But for WiFi and Bluetooth, IW611 and IW612 are same. So it means,  the commands for 2EL are applicable to this model(LBEE5PL2DL) too. Then now please help to follow AN14114's section: 2 Wi-Fi RF test mode to set your board and start the WiFi 5G RF test. Currently from your shared cat /proc/mwlan/adapter0/config results, I do not find any suspect points. The only thing is: please check your test equipment connections and also HW connections. At the same time, let me check internally to see whether it is supported to test RF on these 2 modules. What I confirmed is: we can test on our IW611 or IW612 EVK board, but for these 2 modules, I need to check whether need to do any HW reworks to allow to test RF performance. Once have any updates, will let you know. Best regards, Christine. Re: UM11490 and Bluetooth Classic Hi Christine, I didn't see this message and replied to the other. Yes, I tried different BW settings, but I'm trending to think the problem can be attributed to the region limitation and noise in some regions. Re: UM11490 and Bluetooth Classic Hi, @HelbertPaulino  Can you please have a try with changing 40MHz to 20 MHz bandwidth for initial capture? echo "tx_frame=0" >> /proc/mwlan/adapter0/config echo "bw=0" >> /proc/mwlan/adapter0/config Your readback shows  bw=1  , which AN14114 defines as 40 MHz ;  bw=0  is 20 MHz . For HackRF observation, 20 MHz is the better first test because 40 MHz Wi-Fi is harder to capture/recognize cleanly on a narrow or marginal SDR setup. Please let me know whether it works fine for 20MHZ. Then we step by step to move to 40MHZ.   Best regards, Christine. Re: UM11490 and Bluetooth Classic Hi, @HelbertPaulino  Can you please have a try with below command: echo "tx_continuous=1 0 0xAAA 0 3 0x1100" >> /proc/mwlan/adapter0/config instead of tx_frame command？ I found in your previous output of "cat /proc/mwlan/adapter0/config" tx_frame=1 4352 0xaaa 1024 1 20 4294967295 0 0 4294967295 0 0 0 -1 -1 -1 -1 -1 -1 -1 05:43:3f:c4:51:ff I worry it might not be recognized correctly. Best regards, Christine. Re: UM11490 and Bluetooth Classic Hey Christine I was verifying the command, and you are right, but I don't know why that parameters (SHORT_PREAMBLE and ADVANCED_CODING) was appearing as -1 (represented as 4294967295) Maybe in the first implementation for the code, they was wrongly set as -1. However, replying your request, now we can generate the waveform for 5 GHz (tx_frame). For tx_continuous I could see the waveforme, but in a lower amplitude (almost not possible to see) You can look the frame generation in the picture below: 5GHz-CH100-BW40-FRAME-0x1100-14.png When trying to trigger the continuous, I could see the waveform, but very smoothly 5GHz-CH100-BW40-CONTINUOUS-0x1100-14.png I used the configuration above. I think the problem of not being able to see the waveforms for channels is due to the noise we have in the equipment are bigger than the waveform generated. I requested the Hardware team to verify using a more powerful spectrum analyzer. I'm waiting for its response to close the question for the non-generated waveforms. But about the regions, do you think it can explain why some waveforms are not being generated?   Re: UM11490 and Bluetooth Classic Hi, @HelbertPaulino  Yes, an incorrect Region/Regulatory Domain configuration can also explain why some 5 GHz Wi-Fi waveforms are not being generated, or why the device does not transmit at all on certain channels.    Does your Hardware team to verify using a more powerful spectrum analyzer? Anything else I can do for you on this case?   Best regards, Christine. Re: UM11490 and Bluetooth Classic Hello Christine, I think this confirmation and the tests that the guys did in another noiseless environment confirm that everything is now working properly. Thanks very much for your support. Nice to meet you Re: UM11490 and Bluetooth Classic Hi, @HelbertPaulino  Thanks for your reply and glad to hear that everything is now working properly. Then would you please help to mark my answer as a solution for this thread so that we can close this case? And also, please feel free to create new case to us if you have any other topic questions in the future. We are always glad to support you! Best regards, Christine. Re: UM11490 and Bluetooth Classic Thanks very much again, Christine. I'll do that 🙂

S32K312 MCU wakeup using ADC trigger RTD3.0.0 S32DS3.5 Hi, I am using S32k312 controller mini EVBKIT, for checking the functionality of MCU sleep and wakeup. I am trying to make MCU-Wake up through ADC interrupt by giving low threshold and high threshold voltage value in ADC. Do this functionality work to make MCU wakeup. LavanyaPilli_1-1784889112438.png Re: S32K312 MCU wakeup using ADC trigger RTD3.0.0 S32DS3.5 Hello @LavanyaPilli Since ADC module is not available in Standby, you cannot use it to wakeup (unless the ADC pin is used as interrupt wakeup). However, LPCMP is available in Standby, and can be used instead: Julin_AragnM_2-1784927254532.png LPCMP reads the analog input pin voltage against a programmable DAC reference and generates a wakeup once the threshold is crossed. You can refer to the following examples: S32K312 : MCU wakeup using LPCMP trigger RTD3.0.0 S32DS3.5 [RTD600 IP] S32K3X4EVB-T172 LPCMP Wake-up S32K3 Low Power Management AN and demos Best regards, Julián Re: S32K312 MCU wakeup using ADC trigger RTD3.0.0 S32DS3.5 Hi, Thank you for the clarification. I will evaluate using the LPCMP for the Standby wakeup as you suggested. However, for our application requirements, we still need to implement the ADC interrupt wakeup functionality. Could you please assist me in verifying MEX file, if the ADC can be configured specifically as an external interrupt wakeup. Re: S32K312 MCU wakeup using ADC trigger RTD3.0.0 S32DS3.5 Hello @LavanyaPilli, Sure. If you are using PTA1 (ADC0_S9) as external interrupt wakeup, you can refer to the S32K312_IOMUX.xlsx file to find the assigned WKPU channel: Julin_AragnM_0-1785173159422.png PTA1 is WKPU[5], however, you must also add +4 as offset because of the 4 internal wake up sources. This makes PTA1 WKPU_CH_9. Julin_AragnM_1-1785173923562.png You must initialize the WKPU unit, and configure the respective channel: /* WKPU configuration */ Wkpu_Ip_Init(WKPU_INST, &Wkpu_Ip_Config_PB); Wkpu_Ip_EnableInterrupt(WKPU_INST, Wkpu_Ip_ChannelConfig_PB[0].hwChannel); You can use the following low power examples as reference: S32K3 Low Power Management AN and demos Example S32K312 STANDBY wake up using CAN-0-RX and GPIO Switch DS3.5 RTD300 [RTD600 IP] S32K312EVB-Q172 Standby RAM GPIO Wake-up Best regards, Julián Re: S32K312 MCU wakeup using ADC trigger RTD3.0.0 S32DS3.5 Hello @Julián_AragónM , Thank you for the reference; it is very helpful. We are currently utilizing the CAN-based wakeup configuration. We will evaluate the ADC-based wakeup setup at a later stage.

etpuc mpc5775 I would like to run one of function from cw function selector in eTPUC. I am aware of the starting/ending ram addresses of the etpuc (it is same as mpc5777c_vars_c.h). I modified my_system_etpu_init for the etpuc accordingly. I just copy the function files (like crank) and generate new files for etpuc.  While running all and suspend the program, the debugger's stuck PC: No source available for "0x800400"  What should be wrong? Re: etpuc mpc5775 There are several application notes as below, what have been changed about etpu initiailzation code? AN5374: eTPU library usage in an application – Application Note AN4907: Engine Control eTPU Library – Application Note AN2864: General C Functions for the eTPU – Application Note AN4908: Engine Control eTPU Demo Application – Application Note Re: etpuc mpc5775 How was the eTPU code generated? Did you use the Function Selector to generate a complete function set, or did you only copy the CRANK function files? Can you share your modified my_system_etpu_init() implementation? Is the generated eTPU code image successfully loaded into SCM during initialization? Can you provide the generated eTPU project files (e.g. etpu_set.c, etpu_set.h)? Is the PC always stopping at 0x800400, or does it vary?

RTC功率计算 您好，NXP， 我们正在计算RTC的电池寿命，RT1176中SNVS功率域需要活动电流和睡眠电流。 但是请参阅数据表 IMXRT1170BIEC - 表 13，第 35 页，其中只给出了睡眠电流。 请与我们联系影响 SNVS 功率域有功电流的因素以及与有功电流相关的各种计算方法。 Re: RTC Power Calculation 嗨@specneeraj ， 感谢您对 NXP MIMXRT 系列产品的关注！ VDD_SNVS_IN 为 SNVS/RTC 功能域供电。该域是一个始终开启的低功耗域，主要维护 32 kHz RTC、SNVS 逻辑以及相关的唤醒和功能安全。其当前功耗与 CM7/CM4 的活动/睡眠状态的相关性很弱；因此，表 13 中列出的 SNVS 模式的 VDD_SNVS_IN 值不是省略的“仅睡眠”数据，而是可以在 RTC 备份场景中使用的基准值。 如果纽扣电池仅在主电源故障时供电 → 直接使用 SNVS 模式电流估算； 如果纽扣电池在系统活动期间也向 VDD_SNVS_IN 供电，则根据活动/SNVS 占空比计算平均电流。 影响 SNVS 电流的主要因素包括温度、 VDD_SNVS_IN 电压、工艺偏差、32 kHz RTC 晶体/板的漏电流、SNVS 相关引脚的外部漏电流，以及设备是否实际进入 SNVS 模式。更多详情请参考AN13104 。 此致， 加文