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Hard Fault in C40_Ip_MainInterfaceHVJobStatus api when flash is erase in s32k312 Hi NXP team. The HardFault(1.jpg) issue happens while checking sector(0x00400000) erase functionality of S32K312. The below API functions have to be placed into SRAM (".ramcode" section), as the attached files(2.jpg). C40_Ip_MainInterfaceSectorErase C40_Ip_MainInterfaceSectorEraseStatus C40_Ip_MainInterfaceWrite C40_Ip_MainInterfaceWriteStatus                                                                                                         Could you please let me know to resolve this issue? Re: Hard Fault in C40_Ip_MainInterfaceHVJobStatus api when flash is erase in s32k312 Hi Daniel. This issue is resolved. Thank you for your support. BRs. Eddie Park Re: Hard Fault in C40_Ip_MainInterfaceHVJobStatus api when flash is erase in s32k312 Hello @EddiePark, Please specify the RTD revision. Does the fault occur during or after the flash operation? If you are erasing the sector starting at 0x00400000, where is the application code located? As discussed here: https://community.nxp.com/t5/S32K/S32K344-C40-IP-Hardware-Fault-Problem/td-p/1697432 Place this function to SRAM too: C40_Ip_MainInterfaceHVJobStatus() Check the .map file to confirm the functions are in SRAM. Regards, Daniel
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SAI_TxSetBitClockRate parameter questions I'm trying to set up SAI (send only, as master). But I'm confused by the SAI_TxSetBitClockRate parameters, documented as: /*! * brief Transmitter bit clock rate configurations. * * param base SAI base pointer. * param sourceClockHz, bit clock source frequency. * param sampleRate audio data sample rate. * param bitWidth, audio data bitWidth. * param channelNumbers, audio channel numbers. */ void SAI_TxSetBitClockRate( I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers) 1) What is uint32_t channelNumbers? In the code this seems to be used as numberOfChannels (ie 2 for stereo): uint32_t bitClockFreq = sampleRate * bitWidth * channelNumbers; 2) What is uint32_t sourceClockHz? Is this just the module's clock input, as generated by the clock tool, ie #define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL Thanks in advance, Best Regards, Dave 回复: SAI_TxSetBitClockRate parameter questions Hi @davenadler , Thanks for your interest in NXP MIMXRT series! 1) What is uint32_t channelNumbers? In the code this seems to be used as numberOfChannels (ie 2 for stereo): >> Yes, you are right. 2) What is uint32_t sourceClockHz? Is this just the module's clock input, as generated by the clock tool, ie >> Yes. It is the clock frequency of the SAI peripheral. It is used to configure the appropriate BCLK.
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在 s32k312 中擦除闪存时,C40_Ip_MainInterfaceHVJobStatus API 中发生硬故障 嗨,恩智浦团队。 硬故障(1.jpg)检查 S32K312 的扇区(0x00400000)擦除功能时出现问题。 以下 API 函数必须放入 SRAM(“.ramcode”部分),如附件(2.jpg)。 C40_Ip_MainInterfaceSectorErase C40_Ip_MainInterfaceSectorEraseStatus C40_Ip_MainInterfaceWrite C40_Ip_MainInterfaceWriteStatus 您能告诉我如何解决这个问题吗?
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Questions about 'volatile' and 'static' keywords for global variables. Hello, In the demos of the MIMXRT1010 all global variables seem to be preceded by the 'volatile' keyword. And sometimes also the 'static' keyword. Why is that? These are global variables, not hard ware registers. And MIMXRT1010 has only one core (demos are written for one core anyway), so no problem if the value stays in cache. So why are these keywords needed? I ask this because I like to understand the code. But also when I put these keywords before some of my own global variables (that are structures) and I use a pointer to them, I get warnings like: ../source/sai_interrupt.c:245:27: warning: passing argument 1 of 'xs_biquad_init_LP' discards 'volatile' qualifier from pointer target type [-Wdiscarded-qualifiers] I could try to solve this, but if 'volatile' is not really needed I also could just skip it. Re: Questions about 'volatile' and 'static' keywords for global variables. Hi @simmania , If  "static" is used for global variables, it doesn't mean make the variables "static" or immutable. , the use of "static" is mainly  to restrict their scope, making global variables visible only within the file in which they are defined. BR  mayliu Re: Questions about 'volatile' and 'static' keywords for global variables. And what about the static keyword for global variables? Re: Questions about 'volatile' and 'static' keywords for global variables. Hi @mayliu1 , yes, this is a correct usage of volatile: #define ADC_RESULT_REGISTER ((volatile uint16_t*)0x4XXXXXXX)  Because you are referring here to a hardware register with possible side effects. But this volatile is wrong and needs to be deleted: volatile uint16_t usadc_result; Volatile is not justified here. Moreover, a global variable is not needed in your example, as you have implemented a getter for the ADC result. I hope that makes it clear. Re: Questions about 'volatile' and 'static' keywords for global variables. Hi @ErichStyger , Thanks for your update information. I want clarify my point 2 about Keyword "volatile". I mean the next situation.  For example :// Assuming this is the memory-mapped address of the ADC result register #define ADC_RESULT_REGISTER ((volatile uint16_t*)0x4XXXXXXX)  //Address is based on your MCU type // global variable "usadc_result" used to store the ADC result volatile uint16_t usadc_result; // This function is used to read the ADC result uint16_t read_adc_result() {     // Directly read the value from the ADC result register to a global variable     usadc_result = *ADC_RESULT_REGISTER;     return usadc_result; } Wish it helps you. If you still have question about it, please kindly let me know. Best Regards mayliu Re: Questions about 'volatile' and 'static' keywords for global variables. Hi @simmania, 'static' for data and functions means that it has 'internal linkage'. So it tells the linker that the static symbol is only part of that compilation unit and cannot be accessed (or linked) from the outside world. Think about 'static' used to limit the scope for the linking phase. I recommend that you might have a look at the following article on that subject: https://mcuoneclipse.com/2022/01/01/spilling-the-beans-storage-class-and-linkage-in-c-including-static-locals/ I hope this helps, Erich Re: Questions about 'volatile' and 'static' keywords for global variables. Hi BR, 'atomic' is a key aspect assessing if something can be reentrant or not. My point is that 'volatile' is a different concept and does not help you in any way with reentrancy or synchronization. Or in other words: using volatile for anything else than hardware registers is wrong and a programmer error (with few exceptions outlined in the article). I hope this clarifies it. Erich Re: Questions about 'volatile' and 'static' keywords for global variables. Hi @ErichStyger , Thank you so much for your interest in our products and for using our community. I have read your suggest link, I find this article is based on "atomic".  As I said before, there is no guarantee that its access will be atomic or free from race conditions. It is because the compiler and processor maybe optimized your code, resulted in variable reads and writes not occurring directly in memory but instead using register caching or other optimization techniques. Wish you a nice day! BR mayliu Re: Questions about 'volatile' and 'static' keywords for global variables. Hi @simmania , Thanks for your update. 1: Regarding the "static" keyword, my previous explanation maybe some misleading. If  "static" is used for global variables, it doesn't mean make the variables "static" or immutable. , the use of "static" is mainly  to restrict their scope, making global variables visible only within the file in which they are defined. If  "static" is  declared within a function, which retain their value between function calls instead of being reinitialized each time the function is called. 2: Regarding the "volatile" keyword, my reply is that in an RTOS  system, even if a variable is accessed on the same core and using the same cache, there is no guarantee that its access will be atomic or free from race conditions. It is because the compiler and processor maybe optimized your code, resulted in variable reads and writes are not occurring directly in memory but instead using register caching or other optimization techniques. If a other task, ISR  changed  the variable between when the code reads its value and when it accesses it again, the code may obtain an outdated value. Using the keyword "volatile"  tells  the compiler do not to optimize such variables ,and always read their values directly from memory, make sure that the code can correctly obtain the latest state of the variables. Wish it helps you. If you still have question about it, please kindly let me know. Best Regards mayliu Re: Questions about 'volatile' and 'static' keywords for global variables. Thanks for the answer. You say 'static' is used to maintain their value. But the static keyword is used on global variables that are read and written. They are not static at all. That is why it confuses me so much. So what do you main by maintain their value? You also say that 'volatile' is needed because variables may be changed in interrupt routines or other processes in a RTOS. I do not understand this. What is wrong with changing a variable in some other piece of code. If it is on the same core, using the same cache, what is wrong with that? Re: Questions about 'volatile' and 'static' keywords for global variables. Hi @mayliu1  Respectfully, I have to disagree 100% with your answer to point 2. I recommend to have a read at https://mcuoneclipse.com/2021/10/12/spilling-the-beans-volatile-qualifier/ or check the C/C++ language definition for volatile. 'volatile' is appropriate for hardware registers with side effects, as a workaround for compiler bugs, or as a qualifier for assembly code (but not needed there if the compiler is handling it correctly). It 'might' be used in a 'documentation like manner', but never to make code 'work'. If 'volatile' for non-hardware registers is used, this is a sign for bad or wrong code. If you are using 'volatile' for synchronization (e.g. the FreeRTOS case mentioned) or anything other than hardware registers with side effects, this is clearly wrong. You have to use proper synchronization primitives or correctly using critical sections. I hope this helps and clarifies this, Erich Re: Questions about 'volatile' and 'static' keywords for global variables. Hi @simmania , Thank you so much for your interest in our products and for using our community. Question: In the demos of the MIMXRT1010 all global variables seem to be preceded by the 'volatile' keyword. And sometimes also the 'static' keyword. Why is that? These are global variables, not hard ware registers. And MIMXRT1010 has only one core (demos are written for one core anyway), so no problem if the value stays in cache. So why are these keywords needed? Answer: Please see the explain these two 'volatile'  and  'static'  keyword  1: "static" keyword: It is used for limiting the scope and maintaining the variable value. 2:  "volatile" keyword: Even though the MIMXRT1010 has only one Arm Cortex®-M7 Core, It is still need use "volatile" keyword.       a: The global variables may be changed in interrupt ISR. In this case,   "volatile" keyword is needed.     b: As you said these are not hardware registers, but it still need "volatile" keyword, because  global variables may be used as an indirect means of interacting with hardware, for example, through memory-mapped I/O ,and so on.       c: If you use FREERTOS or other RTOS , global variables shared with multi tasks, In this case,   "volatile" keyword is needed. Question: I ask this because I like to understand the code. But also when I put these keywords before some of my own global variables (that are structures) and I use a pointer to them, I get warnings. Answer:  It might be because pointer operations do not compatible with the semantic definition of  keyword volatile. Wish it helps you. If you still have question about it, please kindly let me know. Best Regards mayliu
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I can't probe my mcu-link debug probe I can't probe my mcu-link debug probe.  What I did:  I follow the instruction to update the muc-link. Installing drivers and updating firmware for MCU-Link Which seems to work according to the output of program_CMSIS.cmd from the MCU-LINK_installer.  Tried with Version  MCU-LINK_installer 2.263, 3.146 and 3.148. After that the red led is blinking smoothly. I tied to probes the MCU-Link with the LinkServer  1.6.133 and 24.9.75  booth exit with the same error. C:\NXP\LinkServer_1.6.133>LinkServer.exe probes ERROR: Failed to boot probes ERRMSG: ValueError: invalid literal for int() with base 16: 'E109_QC5GNRCOEXMGR' CRITICAL: Critical error ERRMSG: ValueError: invalid literal for int() with base 16: 'E109_QC5GNRCOEXMGR' Running on Windows 11 @brendonslade #MCU-LINK #LINKERSERVER  Re: I can't probe my mcu-link debug probe Thank you. That workaround works for me. Re: I can't probe my mcu-link debug probe Hi kaspt, We've analyzed the reports and found that there is an issue with handling on of the PIDs in your system. We will work on a fix in our next release,  but in the meantime please try this workaround: For version LinkServer_24.9.75, modify the “c:\\nxp\\LinkServer_24.9.75\\binaries\\Scripts\\listusb.vbs” script: change line: sPID = ReplaceX(sDvcID, ".*PID_([^\\\&\+]*).*", "$1") with:             sPID = ReplaceX(sDvcID, ".*PID_([^_\\\&\+]*).*", "$1") Let us know if this works for you. Re: I can't probe my mcu-link debug probe Program firmware  C:\NXP\MCU-LINK_installer_3.148\scripts\program_CMSIS CMSIS-DAP firmware for MCU-Link programming script V3.148 September 2024. Place the board in ISP USB mode using the appropriate jumper on your MCU-Link. Refer to the board documentation for more information. Connect board via USB then press Space. WARNING: This firmware version requires MCUXpresso IDE version 11.7.1 or later. Press any key to continue . . . Programming "MCU-LINK_CMSIS-DAP_V3_148.s19" Programmed successfully - To use: remove ISP jumper and reboot. Connect Next Board then press Space (or CTRL-C to Quit) Press any key to continue . . . probes log C:\NXP>LinkServer_24.9.75\LinkServer.exe -l5 probes --no-boot [229]DEBUG:asyncio: Using proactor: IocpProactor [229]DEBUG:launcher.core.redlinkserv: Starting redlinkserv: C:\NXP\LinkServer_24.9.75\binaries\redlinkserv.exe ['--port', '11111', '--telnetport', '12222', '--no-telnet-defaults'] [229]DEBUG:launcher.core.redlinkserv: Connecting to redlinkserv (localhost:12222) [249]DEBUG:launcher.core.redlinkserv: Connected to redlinkserv [249]DEBUG:launcher.core.redlinkserv: [read] [249]DEBUG:launcher.core.redlinkserv: [write] probelist [440]DEBUG:launcher.core.redlinkserv: [read] Index = 1 Manufacturer = NXP Semiconductors Description = MCU-LINK (r0FF) CMSIS-DAP V3.148 Serial Number = 4BBXRM21A3B4T VID:PID = 1FC9:0143 Path = 0002:0019:00 [440]DEBUG:launcher.core.probeboot: Listing usb devices [440]DEBUG:launcher.core.utils: Subprocess exec: cscript ['/nologo', 'C:\\NXP\\LinkServer_24.9.75\\binaries\\Scripts\\listusb.vbs'] [1594]DEBUG:launcher.core.redlinkserv: [write] exit [1609]DEBUG:launcher.core.redlinkserv: Waiting for redlinkserv to close [1840]DEBUG:launcher.core.redlinkserv: Redlinkserv has closed [1840]CRITICAL:__main__: Critical error Traceback (most recent call last): File "launcher\__main__.py", line 39, in File "click\core.py", line 1130, in __call__ File "click\core.py", line 1055, in main File "click\core.py", line 1657, in invoke File "click\core.py", line 1404, in invoke File "click\core.py", line 760, in invoke File "launcher\cli\utils\funcs.py", line 145, in wrapper File "asyncio\runners.py", line 190, in run File "asyncio\runners.py", line 118, in run File "asyncio\base_events.py", line 654, in run_until_complete File "launcher\cli\cmd\probes.py", line 84, in cmd_probes File "launcher\core\redlinkserv.py", line 333, in cmd_probelist File "launcher\core\probeboot.py", line 126, in list_usb File "launcher\core\probeboot.py", line 128, in ValueError: invalid literal for int() with base 16: 'E109_QC5GNRCOEXMGR' List usb devices  C:\NXP>usbipd list Connected: BUSID VID:PID DEVICE STATE 2-3 1fc9:0143 MCU-LINK (r0FF) CMSIS-DAP V3.148, USB Input Device, MCU-L... Not shared 2-6 1bcf:2bb3 Camera AI Effect Opt-in, APP Mode Not shared 2-10 8087:0033 Intel(R) Wireless Bluetooth(R) Not shared C:\NXP>cscript /nologo c:\\nxp\\LinkServer_24.9.75\\binaries\\Scripts\\listusb.vbs VID: 1FC9 PID: 0143 Serial: 7&1B09FF6B&0&0000 VID: 8086 PID: 7EC3 Serial: 4&1F0EBEEC&0&0 VID: 0489 PID: E109_QC5GNRCOEXMGR Serial: 6&246D92E1&0&04 VID: 8087 PID: 0AC2 Serial: 7&3F876ED&0&0000 VID: 8087 PID: 0AC2 Serial: 6&2BC0E6A5&0&00 VID: 0489 PID: E109_QCGNSS Serial: 6&246D92E1&0&01 VID: 1BCF PID: 2BB3 Serial: 6&2C833700&0&0002 VID: 1FC9 PID: 0143 Serial: 4BBXRM21A3B4T VID: 0489 PID: E109_QCPSAUTOREG Serial: 6&246D92E1&0&03 VID: 1FC9 PID: 0143 Serial: 6&2CEB9B2&0&0002 VID: 1FC9 PID: 0143 Serial: 6&2CEB9B2&0&0001 VID: 1BCF PID: 2BB3 Serial: 01.00.00 VID: 8087 PID: 0033 Serial: 5&290E2439&0&10 VID: 1FC9 PID: 0143 Serial: 6&2CEB9B2&0&0000 VID: 0489 PID: E109_QCMBBNETADAPTER Serial: 6&246D92E1&0&02 VID: 1BCF PID: 2BB3 Serial: 6&2C833700&0&0000 Re: I can't probe my mcu-link debug probe Hi kaspt, Your error is a strange one - we havent see anything quite like it before. can you try running LinkServer like this: “c:\nxp\LinkServer_24.9.75\LinkServer.exe -l5 probes --no-boot” ...and check the output reported by: “cscript /nologo c:\\nxp\\LinkServer_24.9.75\\binaries\\Scripts\\listusb.vbs” command. If possible, please also try another computer. Please do the steps above with the latest firmware version programmed into the MCU-Link, and ensure the ISP jumper is removed and the board has been power cycled after programming. thanks Brendon Re: I can't probe my mcu-link debug probe Yes, I removed the jumper J3 MCU-link (not pro version) and disconnect and reconnect the USB.  Re: I can't probe my mcu-link debug probe Hello, my name is Pavel, and I will be supporting your case, did you remove the jumper of ISP and reset your device? Best regards, Pavel
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Issue with imx8mp and embedding several DTBs in FIT image for SPL stuck in ddr training Hi,    We are trying to have multiple device trees in SPL using evaluation kit board imx8mp-evk and uboot 2023.04. To achieve this we enabled few u-boot configuration options: CONFIG_SPL_OF_CONTROL, CONFIG_SPL_MULTI_DTB_FIT and CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION. And for start we are providing just one device tree in SPL list: CONFIG_SPL_OF_LIST="imx8mp-evk" Reading specific value from EEPROM in board_fit_config_name_match() we set proper device tree. Problem that we see now when we try to boot platform with multiple dtb fit image is that dram phy is hanging in SPL in DRAM phy training. U-Boot SPL 2023.04-5.4.70-2.3.3 (Nov 26 2024 - 12:56:43 +0000) DDRINFO: start DRAM init DDRINFO: DRAM rate 4000MTS Adding some printouts to SPL functions we found out that code is stuck in infinite loop in call: ddr_cfg_phy()->wait_ddrphy_training_complete()->get_mail()->poll_pmu_message_ready() Read registry function in poll_pmu_message_ready() is returning all the time 0x10 value. Can you tell us if this feature is supported imx8mp, and if it is we missing some configuration options? We are building ixm-boot image in custom yocto environment there recipe for imx firmware is "firmware-imx-8m-mp_8.10.1.bb". We tried booting platform from sdcard and using uuu-tool and behavior is same.   Thank you, Sinisa i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: Issue with imx8mp and embedding several DTBs in FIT image for SPL stuck in ddr training Thanks for your reply. I am currently working with Pro Support on this issue. Rick Stievenart Johnson Outdoors, Inc. Marine Electronics-Humminbird Re: Issue with imx8mp and embedding several DTBs in FIT image for SPL stuck in ddr training Hi Rick, Unfortunately, I found more issues. The trouble with loading the DDR training firmware is that the firmware offset isn’t calculated properly when multiple DTBs are embedded into the SPL image. To move forward, I used a hardcoded offset calculated from a memory dump. However, the next issue appeared when the SPL had to start U-Boot and pass the device tree. The device tree is always taken from the imx-boot image that the imx-boot tool in the soc.mak scripts packs, not the one selected by the SPL in board_fit_config_name_match(). Best regards, Sinisa Vik Re: Issue with imx8mp and embedding several DTBs in FIT image for SPL stuck in ddr training Greetings! I have the same issue! Did you ever find a REAL solution? Thank you for you reply! Rick Stievenart rick.stievenart@johnsonoutdoors Johnson Outdoors - Marine Electronics - Humminbird Re: Issue with imx8mp and embedding several DTBs in FIT image for SPL stuck in ddr training Hello, Unfortunately I believe we may not have this feature enabled or ready by default, as I was checking on the documentation, I see that SPL uses board_fit_config_name_match() to find the correct DTB within the FIT, as in our case this function is empty, as you can see here: https://github.com/nxp-imx/uboot-imx/blob/lf_v2022.04/board/freescale/imx8mp_evk/spl.c#L140 This may be causing issues on the SPL, please note that this feature has not been tested on our side. Best regards/Saludos, Aldo. Re: Issue with imx8mp and embedding several DTBs in FIT image for SPL stuck in ddr training Hi Aldo, Basically without these additional configuration options platform is booting correctly (it is default unchanged imx8mp_evk_defconfig). We have custom board based on imx8mp processor and we want to support booting multiple variants of that platform with single bootloader image. Our idea is that SPL provides correct device tree to u-boot based on specific identifier from eeprom. We observe same behavior if we modify our bootloader configuration as for evk platform, SPL hang in ddr_cfg_phy(). As starting point we are tying to resolve this problem on NXP evaluation kit platform with clean u-boot source since it's not affected by our changes. First we observe this hang when we packed multiple device tree into bootloader fit image: CONFIG_SPL_OF_LIST="imx8mp-evk imx8mp-evk-2". imx8mp-evk-2.dts was copy of imx8mp-evk.dts with modified model property node. Alternative on the end was to enable this feature and specify just one device tree in CONFIG_SPL_OF_LIST. If you need more detailed steps pleas let me know. Re: Issue with imx8mp and embedding several DTBs in FIT image for SPL stuck in ddr training Hello, If you do not enable this feature does the board boot correctly? Also, what do you mean by multiple device tree? Could you share more information of what are you trying to achieve? Best regards/Saludos, Aldo.
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IMXRT1010 SAI transfer I'm developing a project that convolve an IR with the data acquired by the codec; I use the IMXRT1010 board. I take the SDK example and I modify it to get what I need to do the convolution. The example use this function to receive the data: * @brief Performs an interrupt non-blocking receive transfer on SAI. * @note This API returns immediately after the transfer initiates. * Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer * is finished. * * @param base SAI base pointer * @param handle Pointer to the sai_handle_t structure which stores the transfer state. * @param xfer Pointer to the sai_transfer_t structure. * @retval kStatus_Success Successfully started the data receive. * @retval kStatus_SAI_RxBusy Previous receive still not finished. * @retval kStatus_InvalidArgument The input parameter is invalid. */ status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer); and the function: SAI_TransferSendNonBlocking(....) to send the data. Both need to check the status: ---> Call the SAI_RxGetTransferStatusIRQ  ---> Call the SAI_TxGetTransferStatusIRQ The problem is that I don't find the status check routines; may you help me ? Thanks. Luigi Re: IMXRT1010 SAI transfer Thank you Sam, great !! Re: IMXRT1010 SAI transfer Hi @LuigiV  Certainly! Thanks for your questions, plz see my comments below, please correct me if my understanding is wrong. To perform non-blocking data transfer using the SAI (Serial Audio Interface) module on the IMXRT1010 board, you need to use the provided functions and check the transfer status properly. The functions you mentioned (`SAI_TransferReceiveNonBlocking` and `SAI_TransferSendNonBlocking`) initiate the transfer, and you need to check the status using the appropriate status functions.  The functions like `SAI_RxGetTransferStatusIRQ` and `SAI_TxGetTransferStatusIRQ` are used to check the status of the receive and transmit transfers, respectively. These functions might not be directly named as such, but they are part of the SAI driver in the SDK. Here's how you typically use them: ### Receiving Data To receive data non-blocking, you need to initialize the SAI module, create a transfer handle, and initiate the receive transfer. Then, you periodically check the status to see if the transfer is complete. #include "fsl_sai.h" #include "fsl_debug_console.h" #include "board.h" #define EXAMPLE_SAI SAI1 #define EXAMPLE_SAI_CHANNEL (0) #define BUFFER_SIZE (1024U) sai_handle_t rxHandle; uint8_t rxBuffer[BUFFER_SIZE]; volatile bool isRxFinished = false; // Callback function for receive void SAI_UserRxIRQHandler(I2S_Type *base, sai_handle_t *handle, status_t status, void *userData) { if (status == kStatus_SAI_RxIdle) { isRxFinished = true; } } void InitSAI(void) { sai_config_t config; SAI_TxGetDefaultConfig(&config); SAI_Init(EXAMPLE_SAI); SAI_TransferRxCreateHandle(EXAMPLE_SAI, &rxHandle, SAI_UserRxIRQHandler, NULL); SAI_TransferRxSetConfig(EXAMPLE_SAI, &rxHandle, &config); } void StartReceive(void) { sai_transfer_t xfer; xfer.data = rxBuffer; xfer.dataSize = BUFFER_SIZE; if (SAI_TransferReceiveNonBlocking(EXAMPLE_SAI, &rxHandle, &xfer) != kStatus_Success) { PRINTF("Failed to start receive transfer.\r\n"); } } int main(void) { BOARD_InitBootPins(); BOARD_InitBootClocks(); BOARD_InitDebugConsole(); InitSAI(); StartReceive(); while (!isRxFinished) { // Poll the transfer status status_t status = SAI_TransferGetReceiveCount(EXAMPLE_SAI, &rxHandle); if (status == kStatus_SAI_RxError) { PRINTF("Receive error occurred.\r\n"); break; } } PRINTF("Receive finished.\r\n"); while (1) { } } ``` ### Transmitting Data Similarly, for transmitting data, you initialize the SAI module, create a transfer handle, and initiate the transmit transfer. Then, you periodically check the status to see if the transfer is complete. ```c #include "fsl_sai.h" #include "fsl_debug_console.h" #include "board.h" #define EXAMPLE_SAI SAI1 #define EXAMPLE_SAI_CHANNEL (0) #define BUFFER_SIZE (1024U) sai_handle_t txHandle; uint8_t txBuffer[BUFFER_SIZE]; volatile bool isTxFinished = false; // Callback function for transmit void SAI_UserTxIRQHandler(I2S_Type *base, sai_handle_t *handle, status_t status, void *userData) { if (status == kStatus_SAI_TxIdle) { isTxFinished = true; } } void InitSAI(void) { sai_config_t config; SAI_TxGetDefaultConfig(&config); SAI_Init(EXAMPLE_SAI); SAI_TransferTxCreateHandle(EXAMPLE_SAI, &txHandle, SAI_UserTxIRQHandler, NULL); SAI_TransferTxSetConfig(EXAMPLE_SAI, &txHandle, &config); } void StartTransmit(void) { sai_transfer_t xfer; xfer.data = txBuffer; xfer.dataSize = BUFFER_SIZE; if (SAI_TransferSendNonBlocking(EXAMPLE_SAI, &txHandle, &xfer) != kStatus_Success) { PRINTF("Failed to start transmit transfer.\r\n"); } } int main(void) { BOARD_InitBootPins(); BOARD_InitBootClocks(); BOARD_InitDebugConsole(); InitSAI(); StartTransmit(); while (!isTxFinished) { // Poll the transfer status status_t status = SAI_TransferGetSendCount(EXAMPLE_SAI, &txHandle); if (status == kStatus_SAI_TxError) { PRINTF("Transmit error occurred.\r\n"); break; } } PRINTF("Transmit finished.\r\n"); while (1) { } } ``` ### Notes 1. Interrupt Handler: The callback functions `SAI_UserRxIRQHandler` and `SAI_UserTxIRQHandler` handle the interrupt service routines. They set a flag when the transfer is finished. 2. Polling Status: In the main loop, the status is periodically checked using `SAI_TransferGetReceiveCount` and `SAI_TransferGetSendCount` functions to determine if the transfer is complete. 3. SDK Documentation: Ensure to refer to the specific SDK documentation for your board and SAI driver functions as there might be slight variations in function names or parameters. By following the above examples, you should be able to perform non-blocking transfers with status checks on the IMXRT1010 board. Have a nice day! Sam
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使用 CAN LLCE 时在长消息缓冲区中接收标准短 CAN 帧 尊敬的恩智浦社区成员: 我目前正在使用 LLCE 固件 v1.0.7 在 S32G274A 评估板。 当我通过 CAN 日志工具向 LLCE 发送一个 CAN 标准帧(8 字节)时,它会将其视为一个长帧(大于 8 字节)。因此,当我获取 Rx 描述符表索引时,我发现它低于与长帧相对应的 LLCE_CAN_CONFIG_MAXRXMB(1732)。 我应该获得大于LLCE_CAN_CONFIG_MAXRXMB 的索引,因为我只向 LLCE 发送短帧。 你知道是什么原因导致了这种行为吗? 感谢您的支持。 此致,
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IMX8MP spread spectrum Hello, I wanna add spread spectrum for my IMX8MP LVDS screen signal. I find that the feature is available for 8QuadMax and i.MX 8QuadXPlus Display but not for i.MX 8MP. Do you know when this will be available or there is already a patch to add it ? Thanks. Re: IMX8MP spread spectrum It works, thank you. Re: IMX8MP spread spectrum Hi @clemntnxp,  Thank you for contacting NXP Support. On our i.MX8MP EVK the enablement of Spread Spectrum Clocking is via software. We don't have any code example to apply the required changes. Here is a description of Spread Spectrum enablement for LVDS interface. The LVDS interface doesn't have an integrated PLL such as MIPI or USB interface, therefore, LDB (LVDS Display Bridge) module uses VIDEO_PLL1 as root clock and VIDEO_PLL1 support SSCG (Spread Spectrum Clock Generator). Here is a block diagram of LVDS interface on iMX8M Plus. To enable the Spread Spectrum Clocking for LVDS interface you will need to write on VIDEO_PLL1 control register. You will need to set SSCG_EN and the other parameters (MFR, MRR, SEL_PF, SEL_PF) with U-Boot. For a proper setting up, please have a look to the section 5.1.5.4.4 SSCG and Fractional PLLs on the i.MX8MP Reference Manual. Have a great day!
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CAN LLCE 使用時の長いメッセージバッファでの標準ショート CAN フレームの受信 親愛なるNXPコミュニティ、 現在、LLC Eファームウェアv1.0.7 on S32G274A evalボードを使用しています。 CAN 標準フレーム (8 バイト) を CAN log ツール経由で LLCE に送信すると、長いフレーム (8 バイト以上) であるかのように処理されます。したがって、Rx記述子テーブルインデックスを取得すると、長いフレームに対応するLLCE_CAN_CONFIG_MAXRXMB(1732)よりも低いことがわかりました。 私は短いフレームだけをLLCEに送信するので、LLCE_CAN_CONFIG_MAXRXMB より大きいインデックスを取得するべきでした。 この行動の原因について何か考えはありますか? 再開まで今しばらくお待ちください。 よろしくお願いいたします
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Reception of standard short CAN frames in long message buffers when using CAN LLCE Dear NXP community, I'm currently using LLCE firmware v1.0.7 on S32G274A eval board. When I send a CAN standard frame (8bytes), via my CAN log tool, to the LLCE, it handles it as if it is a long frame (greater than 8Bytes).So When I get the Rx descriptor table index, I found it lower than LLCE_CAN_CONFIG_MAXRXMB (1732) which corresponds to the long frames. I should have gotten an index greater than LLCE_CAN_CONFIG_MAXRXMB because I send to LLCE only short frames. Do you have any idea about what can cause this behavior ? Thank you for your support.  Best regards, Re: Reception of standard short CAN frames in long message buffers when using CAN LLCE Hi @Daniel-Aguirre , Indeed you are right. I solved the problem. The issue was due to the fact that I've not set Llce_CanRx_MbLengthType to the correct value. Thank you for your support. Best regards, Re: Reception of standard short CAN frames in long message buffers when using CAN LLCE Hi, Are you using any of the NXP available examples? Can you share with us the configuration for the CanHardwareObject you are using and shows the behavior? How did you configure the CanObject Payload Lenght? For the information, there is only 2 types of messages and it is defined by the following structure: Seems to be a misconfiguration of the filter at this moment. Please, let us know.
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MPC5746C Machine Check Exception (IVOR1) w/ SPI Example Code Greetings! I am using the MPC5746C on a custom PCB with PEmicro Debugger. I am attempting to run an example SPI program provided by NXP, located at C:\NXP\S32DS_Power_v2.1\S32DS\software\S32_SDK_S32PA_RTM_3.0.0\examples\MPC5746C\driver_examples\communication\spi_pal inside my local file system.  The pin assignments/connections on my custom board are inspired from the MPC5748G-LCEVB evaluation kit, but not exact. Hence, I changed the pin_mux and spi1/2 component configurations to be aligned with what our board supports and generated the Processor Expert code. The program builds. I also followed the instructions at the following webpage and modified the physical connections to align with our board: S32 SDK: SPI PAL MPC5746C When I run the program, inside main() the code calls SPI_MasterInit(): Inside SPI_MasterInit() the code calls DSPI_MasterInit(): Inside DSPI_MasterInit() the code calls DSPI_Set_MCR_Halt(): Finally, inside DSPI_Set_MCR_Halt(), when the program attempts to execute the first line inside the function, a Machine Check Interrupt (IVOR1) is raised. At this point the execution is paused in an infinite loop.  The cause of this issue is puzzling and my efforts to track it down have been unsuccessful. Is there any guidance that you can offer me to assist me solving this issue? When I run the equivalent example on the MPC5748G-LCEVB, it works fine. If it's helpful, here is what my MCSR register looks like: Thanks for your time. Kind Regards, Paul Re: MPC5746C Machine Check Exception (IVOR1) w/ SPI Example Code Thanks David. The issue was incorrectly configured clocks, which was not allowing the mode entry sequence to complete. Once I got that right I ended up just using the clock_manager inside Processor Expert to configure everything and initialized by calling the two functions below, which I learned about through some of the examples in the S32 SDK (the functions are in clock_MPC57xx.c). Just using the CLOCK_DRV_Init() processor expert function was not enough. Re: MPC5746C Machine Check Exception (IVOR1) w/ SPI Example Code Yes, the component configures ME setup, so it is it properly configured, it could be enough. Re: MPC5746C Machine Check Exception (IVOR1) w/ SPI Example Code Follow-up question: Instead of manually coding the Mode Entry module, can I just use the clock_manager component in Processor Expert? Isn't that the point of it, to do the Mode Entry leg-work? Or no? Thanks. Paul Re: MPC5746C Machine Check Exception (IVOR1) w/ SPI Example Code Hi David, I followed your advice and read up on the Mode Entry module in the reference manual. I have added some code in the Initialize_Components(void) function within main.c to enable the clocks and peripherals, aiming to transition the chip to RUN0 mode. The primary issue I'm encountering now is that when I write to the MC_ME_MCTL register to transition to RUN0 mode (with the KEY and then again with the inverted KEY), the program hangs after the second write to MC_ME_MCTL. I have attached my latest project for your reference and testing. I would appreciate any insights or suggestions you might have regarding this issue. Thank you very much for your help.  Below is a summary of changes I made to my project (and other observations) in light of the current state of the situation: I transitioned my configuration from the MPC5746_256 package to the MPC5746C_100 package, as the 100-pin package is what I'm using on my custom board The ADC1 MCR/MSR registers continue to show a value of 0x0 (I am not aiming to use ADC0, just FYI) I added a Power Manager configuration to my project, initializing it for DRUN mode, which appears to be the controller's default mode after RESET. My objective is to operate in RUN0 mode if possible, although the manual suggests the ADC should be operational in either DRUN or RUN0 mode I've also adjusted the clock settings, slowing down the FIRC to 8MHz and further dividing it to 1MHz for the FS80_CLK, which the ADC1 module uses. My concern was that a high clock speed might be contributing to the issue, so I reduced the clock speed to potentially increase the likelihood of proper functionality without adverse effects As an aside: I was able to successfully run the ADC and SPI examples on the MPC5748G-LCEVB without needing to manually configure the Mode Entry module. Any idea why this might be the case? - Paul Re: MPC5746C Machine Check Exception (IVOR1) w/ SPI Example Code If I run this code on my board it goes to IVOR1 as well because ADC registers are not available because Mode Entry transition didn't happen and device is not clocked according the setting. Pay attention to Mode Entry module. Re: MPC5746C Machine Check Exception (IVOR1) w/ SPI Example Code Hi David, I am not sure what is going on but I have tried running multiple NXP example projects using the built-in function from the processor expert, and among all of them what I am seeing in common is when a function tries to access a module register (like MCR) it triggers the IVOR1 exception handler and won't return to finish executing the rest of the code. Here's an example function:  When the controller tries to execute the REG_BIT_SET32(&(base->MCR), ADC_MCR_PWDN(1u));, this is where the IVOR1 is raised and it won't execute. I still haven't figured out the issue with the SPI module from before, so I tried moving on to other modules but I'm facing the same obstacle. I've also tried commenting out the IVOR1 segments inside the startup files but instead of IVOR1, it just sends it up the chain to a different IVORn handler and the result is ultimately the same. Would it be possible for you to view my project or attempt to execute it on your end and see if the issue  persists (I've atttached a .zip)? I would greatly appreciate any additional insights you can offer. Thank You. Re: MPC5746C Machine Check Exception (IVOR1) w/ SPI Example Code I see your point regarding a potential mismatch. However, inside the PE generated function "SPI_MasterInit()", it uses "DSPI_MasterInit()" so I am not sure how to disassociate the two... Additionally, I am encountering the same problem with the IVOR1 exception even when I change the module from SPI_2 to a DSPI module. I also tried using the DSPI peripheral driver component rather than the spi_pal component...same result. Re: MPC5746C Machine Check Exception (IVOR1) w/ SPI Example Code OK, it does make sense now. Bus error during reading from SPI_2. I guess there is some mismatch between SPI_2 and DSPI_2 as these are different modules. Re: MPC5746C Machine Check Exception (IVOR1) w/ SPI Example Code Hi David, I ran the program again and realized that in the original screenshot I didn't capture the MCSRR0 register at the moment the exception is raised. Here is an updated screenshot taken at the proper time and including the MCAR register you requested. Thank you. Re: MPC5746C Machine Check Exception (IVOR1) w/ SPI Example Code Could you screenshot also MCAR register? Interesting value is stored in MCSRR0 register as it should be address of instruction causing an IVOR1 exception (machine check) and you have 0xFFFF_C000 what's reserved region within PBRIDGE_A memory space.
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PCF8576D阻抗要求 您好,咨询一下,PCF8576D到金手指那边是否有阻抗要求,如果有是否有相关数据或者建议可以参考呢,谢谢 Re: PCF8576D阻抗要求 请看上面的图片 Re: PCF8576D阻抗要求 这个是通用的吗?符合我们所有的LCD Drive产品
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How do I get the wake source for K344 I looked at the S32K3 Low Power Management AN and demos, but those demos uses DS3.4, which I couldn't open and compile. Is there a demo of DS3.5 available? I have a problem with low power Management. After the MCU is awakened, the reset type obtained by using Power_Ip_GetResetReason() is MCU_WAKEUP_REASON, and this is correct. But when I used Wkpu Ip GetInputState() to get the wake source, I didn't get the correct result.  I don't know why. This is my test project. I hope someone could help me. Thanks! Re: How do I get the wake source for K344 Hi @ZDDL, You can refer to the following examples: S32K3 Low Power Management AN and demos RTD 4.0.0 & 5.0.0 - NXP Community. For the wakeup source, please try reading the registers directly: uint32_t WISR_Value; uint32_t WISR64_Value; void WKPU_Handler(void) { /*store the WISR value which indicate the wake up source.*/ WISR_Value = IP_WKPU->WISR; WISR64_Value = IP_WKPU->WISR_64; if(MCU_WAKEUP_REASON == Power_Ip_GetResetReason()) { printf("Reset reason = MCU_WAKEUP_REASON\r\n"); } printf("WISR = %"PRIu32",", WISR_Value); printf("WISR64 = %"PRIu32".\n", WISR64_Value); /*Clear the flag by writing 1.*/ IP_WKPU->WISR = 0xffffffff; IP_WKPU->WISR_64 = 0xffffffff; __asm("dsb"); __asm("isb"); } Best regards, Julián
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PCF8576Dのインピーダンス要件 こんにちは。PCF8576Dと金端子間のインピーダンス要件はありますか?もしある場合、参考になるデータや提案はありますか?よろしくお願いします。 PCF8576Dのインピーダンス要件について これは汎用ですか?当社のすべての LCD ドライバー製品と互換性があります。
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PCF8576D impedance requirements Hello, I would like to ask, is there any impedance requirement for PCF8576D to the gold finger? If so, is there any relevant data or suggestions for reference? Thank you Re: PCF8576D impedance requirements Is this universal? It is compatible with all our LCD Driver products. Re: PCF8576D阻抗要求 Hi Chenyuan shen 请看附件的app note page7:  2. Guidelines for power supply lines VSS, VDD and VLCD 里面有阻抗的需求每个信号.
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How to test the PWM duty cycle and frequency of input using S32K144 software FTM-IC 1.I need to test the PWM duty cycle and frequency, if configured to measure whether the input signal is reasonable 2.When I configure it as measure input signal, DUTY Cycle ON and Period between two risk edges can only choose one of the two options.Can I obtain both the duty cycle and frequency simultaneously, using only one channel of feedback 3.When I tried to set channel 1 of FTM0 as Measure input signal, I encountered an error, meaning that only even numbered channels can be set as Measure input signal? Is there any special reason? I couldn't find it in the data manual Re: How to test the PWM duty cycle and frequency of input using S32K144 software FTM-IC By the way, regarding the software configuration of S32DS, besides basic usage (which can be searched a lot online), do you have a comprehensive manual on usage and configuration. Thank you once again. Re: How to test the PWM duty cycle and frequency of input using S32K144 software FTM-IC Thank you for your help! I think I have solved all the questions. Best regards. Re: How to test the PWM duty cycle and frequency of input using S32K144 software FTM-IC If you want to measure the pulse width and the period you will need to use two channels, one for t the pulse width an the other for the period. Re: How to test the PWM duty cycle and frequency of input using S32K144 software FTM-IC From what I have found, only this function FTM-DRV_GetInputCaptureMeasurement() can be used to obtain the count value. Therefore, when I use Measure input signal, I can only select  pulse width or the period of the tested signal. If I need to measure both the pulse width and the period, I can only use both the rising and falling edges for detection. I'm worried about what functions I haven't considered in Measure input signal mode, which can easily measure both the pulse width and the period simultaneously. Re: How to test the PWM duty cycle and frequency of input using S32K144 software FTM-IC Hi, Thank you so much for your interest in our products and for using our community. Yes, you need to choose between to measure the pulse width or the period of the tested signal. And in Dual Edge Capture Mode is specified that is only available in channel (n) where n = 0, 2, 4 or 6. Hope it helps you. Have a nice day!
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S32K3xx RTD default MPU implementation causes problems/seems wrong Hi all, we're having problems with MemManage faults being generated on startup. This is either a IACCVIOL or a DACCVIOL error. This happens not in our own code, but already in RTD or NXP IPCF code. I'm currently suspecting the MPU setup that's at fault, as when I am not defining MPU_ENABLED it works. On further investigation, I am very puzzled about the MPU code provided by NXP in this file: "Platform_TS_T40D34M40I0R0\startup\src\system.c" I am looking at the linker file from the Dio_Example_S32K358 of RTD 4.0. Before we head into the file itself, I was also confused by this post: https://community.nxp.com/t5/S32K/S32K312-W-R-FULL-access-MPU-address-leads-to-MemManage-exception/m-p/1773906 It seems to me that for the S32K3xx the wrong document was shown, as Cortex M7 is afaik ARMv7E-M architecture, thus not the Arm v7-M manual but this document must be used: https://developer.arm.com/documentation/ddi0489/latest/ This is quite important, as the MPU RBAR are different between those two architectures! Here are the relevant snippets for Cortex M7: Coming back to the start.c file: The MPU is configured via the rbar and rasr arrays, for example region 6: /*Ram unified section*/ #if defined(S32K396) || defined(S32K394) || defined(S32K344) || defined(S32K324) || defined(S32K314) || defined(S32K374)|| defined(S32K376) rbar[6]=(uint32)__INT_SRAM_START; /* Size: import information from linker symbol, Type: Normal, Inner Cache Policy: Inner write-back, write and read allocate, Outer Cache Policy: Outer write-back, write and read allocate, Shareable: No, Privileged Access:RW, Unprivileged Access:RW */ /* Disable subregion 7 & 8*/ rasr[6]=((uint32)0x030B0001UL)|(((uint32)__RAM_CACHEABLE_SIZE - 1) << 1)|(1<<15)|(1<<14); #else rbar[6]=(uint32)__INT_SRAM_START; /* Size: import information from linker symbol, Type: Normal, Inner Cache Policy: Inner write-back, write and read allocate, Outer Cache Policy: Outer write-back, write and read allocate, Shareable: No, Privileged Access:RW, Unprivileged Access:RW */ rasr[6]=((uint32)0x030B0001UL)|(((uint32)__RAM_CACHEABLE_SIZE - 1) << 1); #endif Question 1 Why are the addresses of the linker are directly written into RBAR? The ADDR field is high withing the 32-bit word, and must be shifted. Furthermore, the shift is dependent on "N", which itself results of the "SIZE" field of RASR. Also impacts of course currently the VALID and REGION field. Question 2 (special case S32K344) RAM section is 256 KB, thus subregions are 32 KB big. Top 2 regions 7 and 6 are disabled via "SRD" field. However, shouldn't region 5 also be disabled to get 160 KB size? 256 KB / 8 * 6 = 192 KB 256 KB / 8 * 5 = 160 KB Further remark: This table is not correct, at least because the code uses "__INT_SRAM_START" rather than "__RAM_CACHEABLE_START" as stated in the table. However, this is fine and should be even better, as this also includes the sram BSS section which should be fine to enable cache on as well. Also the "ADDR" must somewhat be aligned based on the SIZE field. In the example __INT_SRAM_START is set to "ORIGIN(int_sram)" (so kind of aligned), but "__RAM_CACHEABLE_START" would be not aligned somewhere after sram BSS. /* Region Description Start End Size[KB] Type Inner Cache Policy Outer Cache Policy Shareable Executable Privileged Access Unprivileged Access -------- ------------- ---------- ---------- ---------- ---------------- -------------------- -------------------- ----------- ------------ ------------------- --------------------- 0 Whole memory map 0x00000000 0xFFFFFFFF 4194304 Strongly Ordered None None Yes No No Access No Access 1 ITCM 0x00000000 0x0000FFFF 64 Strongly Ordered None None Yes Yes Read/Write No Access 2 Program Flash 1 0x40000000 PFLASH SIZE PFLASH SIZE Normal Write-Back/Allocate Write-Back/Allocate No Yes Read-Only Read-Only 3 Data Flash 0x10000000 0x1003FFFF 256 Normal Write-Back/Allocate Write-Back/Allocate No No Read-Only Read-Only 4 UTEST 0x1B000000 0x1B001FFF 8192 Normal Write-Back/Allocate Write-Back/Allocate No No Read-Only Read-Only 5 DTCM 0x20000000 0x2001FFFF 128 Normal None None No Yes Read/Write Read/Write 6 SRAM CACHE __RAM_CACHEABLE_START __RAM_CACHEABLE_END __RAM_CACHEABLE_SIZE Normal Write-Back/Allocate Write-Back/Allocate No Yes Read/Write Read/Write 7 SRAM N-CACHE __RAM_NO_CACHEABLE_START __RAM_NO_CACHEABLE_END __RAM_NO_CACHEABLE_SIZE Normal None None Yes No Read/Write Read/Write 8 SRAM SHARED __RAM_SHAREABLE_START __RAM_SHAREABLE_END __RAM_SHAREABLE_SIZE Normal None None Yes No Read/Write Read/Write 9 AIPS_0/1/2 0x40000000 0x405FFFFF 6144 Strongly ordered None None Yes No Read/Write Read/Write 10 AIPS_3 0x40600000 0x407FFFFF 2048 Strongly ordered None None Yes No Read/Write Read/Write 11 QSPI Rx 0x67000000 0x670003FF 1 Strongly ordered None None Yes No Read/Write Read/Write 12 QSPI AHB 0x68000000 0x6FFFFFFF 131072 Normal Write-Back/Allocate Write-Back/Allocate No Yes Read/Write Read/Write 13 PPB 0xE0000000 0xE00FFFFF 1024 Strongly Ordered None None Yes No Read/Write Read/Write 14 Program Flash 2 0x00800000 PFLASH SIZE PFLASH SIZE Normal Write-Back/Allocate Write-Back/Allocate No Yes Read-Only Read-Only 15 ACE 0x44000000 0x440003FF 1 Strongly-ordered None None Yes No Read/Write Read/Write */ BR Andreas Edit: Exchanged link to documentation, was another document. Re: S32K3xx RTD default MPU implementation causes problems/seems wrong Hi Daniel, thanks for the reply. I'm getting it now, however, it is very implicitly done. Due to the regions being at minimum 32 bytes, if you align the addresses accordingly, the lower 5 bits 0:4 will always be zero, as 2^5 = 32. Going further, if you increase the region size, for each doubling, the needed bits shift by two, thus the N comes into place. So I guess you don't need to test it, the code now makes implicitly sense. Thank you Andreas Re: S32K3xx RTD default MPU implementation causes problems/seems wrong Hi Andreas, ARMv7E-M is Armv7-M implementation that includes the DSP extension. In Arm Cortex-M7 Processor Technical Reference, there is reference to Armv7-M Architecture Reference Manual that I was using in that thread. https://developer.arm.com/documentation/ddi0489/f/memory-protection-unit/mpu-functional-description?lang=en You use the description from the Cortex-M7 Devices Generic User Guide r1p2 https://developer.arm.com/documentation/dui0646/c/Cortex-M7-Peripherals/Optional-Memory-Protection-Unit/MPU-Region-Base-Address-Register?lang=en Which looks different. But if the region is 32B, log2(32) = 5 = N. For 4KB region, N = 12, and so on. The address is written as a 32bit word to the whole register without any bit shift, but it must be alligned, at least 5 zeros at RBAR[4-0]. The system.c does not use the REGION bits of the RBAR register, because VALID = 0, REGION is ignored. It uses the RNR register. The size of region 6 is 128KB so a subregion is 16KB. The MPU configuration is just an example. The configuration is up to the user. I haven't tested the RTD project yet on S32K358. I will test it tomorrow and come back to you, Regards, Daniel
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IMXRT1176 CAN peripheral behaves as if Loop back enabled I have two CANs used in my PCB. CAN1, CAN3. I am using message buffers for TX and RX.   #define RX_MESSAGE_BUFFER_NUM (9) #define TX_MESSAGE_BUFFER_NUM (8) #define USE_CANFD (0) ** I am trying to take any Classical Standard or Extended CAN message with interrupt and send it back with +1 increment for coming id and each received can data.  ** I am using interrupt for only receiving. For transmitting, I do not use interrupt. I sent it with "FLEXCAN_WriteTxMb" non blocking- method. ** Even though I am sending only one time, FLEXCAN sends continously data. I disabled "loopback" disabled at init procedure. However, it behaves as I stated. Here is my simple code important areas : /* #define EXAMPLE_CAN CAN1 #define EXAMPLE_FLEXCAN_IRQn CAN1_IRQn #define EXAMPLE_FLEXCAN_IRQHandler CAN1_IRQHandler */ #define EXAMPLE_CAN CAN3 #define EXAMPLE_FLEXCAN_IRQn CAN3_IRQn #define EXAMPLE_FLEXCAN_IRQHandler CAN3_IRQHandler void EXAMPLE_FLEXCAN_IRQHandler(void){ uint64_t flag = 1U; if (0U != FLEXCAN_GetMbStatusFlags(EXAMPLE_CAN, flag << RX_MESSAGE_BUFFER_NUM)) { FLEXCAN_ClearMbStatusFlags(EXAMPLE_CAN, flag << RX_MESSAGE_BUFFER_NUM); (void)FLEXCAN_ReadRxMb(EXAMPLE_CAN, RX_MESSAGE_BUFFER_NUM, &rxFrame); rxComplete = true; } SDK_ISR_EXIT_BARRIER; } flexcan_config_t flexcanConfig; flexcan_rx_mb_config_t mbConfig; clock_root_config_t rootCfg = {0}; rootCfg.mux = FLEXCAN_CLOCK_SOURCE_SELECT; rootCfg.div = FLEXCAN_CLOCK_SOURCE_DIVIDER; /* CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg);*/ CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg); FLEXCAN_GetDefaultConfig(&flexcanConfig); flexcanConfig.bitRate = 250000U; flexcanConfig.enableLoopBack = false; FLEXCAN_Init(EXAMPLE_CAN, &flexcanConfig, EXAMPLE_CAN_CLK_FREQ); mbConfig.format = kFLEXCAN_FrameFormatExtend; mbConfig.type = kFLEXCAN_FrameTypeData; mbConfig.id = FLEXCAN_ID_EXT(0x00000000); FLEXCAN_SetRxMbConfig(EXAMPLE_CAN, RX_MESSAGE_BUFFER_NUM, &mbConfig, true); FLEXCAN_SetTxMbConfig(EXAMPLE_CAN, TX_MESSAGE_BUFFER_NUM, true); FLEXCAN_EnableMbInterrupts(EXAMPLE_CAN, flag << RX_MESSAGE_BUFFER_NUM); (void)EnableIRQ(EXAMPLE_FLEXCAN_IRQn); while (true) { rxComplete = false; while (!rxComplete) { } rxFrame.id = FLEXCAN_ID_EXT(rxFrame.id) + 0x01; rxFrame.dataByte0 += 1; rxFrame.dataByte1 += 1; rxFrame.dataByte2 += 1; rxFrame.dataByte3 += 1; rxFrame.dataByte4 += 1; rxFrame.dataByte5 += 1; rxFrame.dataByte6 += 1; rxFrame.dataByte7 += 1; if (kStatus_Success == FLEXCAN_WriteTxMb(EXAMPLE_CAN, TX_MESSAGE_BUFFER_NUM, &rxFrame)) {;} ** I have one data logger with sending capability. I am also using debugger to find the problem. What I see is that; as soon as I send such as 0x18aabbcc id message, it produces continously interrupt and that is why I am taking 0x18aabbcd, 0x18aabbce, 0x18aabbcf...  ** I read with debugger in interrupt handler, there is always "1" in RX_MESSAGE_BUFFER_NUM place in  IFLAG register. So it continously produces interrupt. I do not understand where I am missing? i.MXRT 105x i.MXRT 106x Re: CAN peripheral behaves as if enable loop back is enabled Many thanks @PetrS for your very quick response.  You are right. MCR[SRXDIS]  was 0 means self reception enabled. After your guide, I noticed that disableSelfReception flag controls SRXDIS bit. After changing it, everything now works as accepted. Thanks a lot again. flexcanConfig.enableLoopBack = false; flexcanConfig.disableSelfReception =true; Re: CAN peripheral behaves as if enable loop back is enabled Hi, exact setting is hidden here, but it seems you can have self-reception enabled. Check MCR[SRXDIS] bit. BR, Petr Re: CAN peripheral behaves as if enable loop back is enabled Hi @PetrS, I see the you replied most questions on FLEXCAN for MPC and S32 series. I am using IMXRT1176 but thinks flexcan structure is similiar. Can you please help me my above issue regarding CAN? Thank you
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S32DS ARMデバッガ ファイル形式なし ARM IDE for ARMが、作業しているパスとは異なるパスから「ソースファイル名がありません」と文句を言っているという問題が発生していますが、これは正しくありません。 添付のDebug_Configurations.jpgファイルとDebugger_Console.jpgファイルをご覧いただき、解決させて頂きます。 デバッグ環境 - ウィンドウズ11 - S32 Design Studio for ARMバージョン2.2 ●対象マイコン:S32K144F512M15 - デバッガプローブ:Segger J-Link Base Version 12.0 Re:S32DS ARMデバッガは、ソウレファイルはありません S32DS ARM が "No source file named" というエラーを表示しても、デバッグに何も影響していないように見えるため、これは閉じられます。  Re:S32DS ARMデバッガは、ソウレファイルはありません 参考までに 私がこの問題を抱えるまで、それは働いていました。 また、NXP Communityの以下のリンクは私の場合には機能しません。 https://community.nxp.com/t5/Kinetis-Design-Studio/breakpoint-quot-No-source-file-named-quot/m-p/740013
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