MPC5744P互換HSM みなさん。 MPC5744Pを使用しています。また、MCUにHSMがないことを確認します。 MPC5744P対応HSMを教えてください。 RSAやECCなどのデジタル署名を適用しようとしています。 Re:MPC5744P互換HSM 迅速な対応をありがとう。 また、NXPにアドオンHSMがあることも知りたいです。 アドオンとは、MCUに継承されず、MCUの外部に継承されることを意味します。 MCUを変更するのが難しいため、変更されている場合はHSMチップを追加したいと思います。 感謝 Re:MPC5744P互換HSM こんにちは @LCGSEMS  MPC57xxファミリの唯一のオプションは、HSMモジュールを含むMPC5748Gです。他の一部のMPC57xxデバイスには、SHE要件を満たすCSEモジュールのみがあります。そのため、RSA や ECC はサポートされていません。 ただし、HSM ファームウェアを搭載したMPC5748Gは、サポートが限られているため、承認されたお客様 (大量の注文を想定) にのみ提供されます。標準の MPC5748G デバイスには HSM ファームウェアがインストールされていないことに注意してください。HSEファームウェアを搭載したデバイスには、特別な部品番号があります。ご興味のある方は、お近くのNXP営業所までお問い合わせください。 いずれにせよ、HSEモジュールを搭載したS32K3デバイスに移行するのが、はるかに良い選択肢です。HSEファームウェアは、すべてのお客様が使用できます。RSA と ECC はサポートしています。 https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32k-auto-general-purpose-mcus/s32k3-microcontrollers-for-automotive-general-purpose:S32K3 また、新しいデバイスであるため、保証される可用性はより長くなります。 https://www.nxp.com/products/nxp-product-information/nxp-product-programs/product-longevity:PRDCT_LONGEVITY_HM よろしく ルーカス

freeRTOS stack size configuration I am currently learning FreeRTOS on the LPC51U68 development board (OM40005). I have created 7 tasks for testing and am using the RTOS task list monitor provided by MCUXpresso IDE. I noticed that the stack sizes displayed in the task list don't match the configurations I set. Could this be related to memory alignment? Where can I check the rules for configuration differences? Below is the code I modified from the freertos_hello example. /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ /* FreeRTOS kernel includes. */ #include "FreeRTOS.h" #include "task.h" #include "queue.h" #include "timers.h" /* Freescale includes. */ #include "fsl_device_registers.h" #include "fsl_debug_console.h" #include "pin_mux.h" #include "board.h" #include /******************************************************************************* * Definitions ******************************************************************************/ /* Task priorities. */ #define hello_task_PRIORITY (configMAX_PRIORITIES - 1) /******************************************************************************* * Prototypes ******************************************************************************/ static void task1(void *pvParameters); static void task2(void *pvParameters); static void task3(void *pvParameters); static void task4(void *pvParameters); static void task5(void *pvParameters); static void task6(void *pvParameters); static void task7(void *pvParameters); /******************************************************************************* * Code ******************************************************************************/ /*! * @brief Application entry point. */ int main(void) { /* Init board hardware. */ /* attach 12 MHz clock to FLEXCOMM0 (debug console) */ CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH); BOARD_InitBootPins(); BOARD_InitBootClocks(); BOARD_InitDebugConsole(); if (xTaskCreate(task1, "task1", configMINIMAL_STACK_SIZE + 50, NULL, hello_task_PRIORITY, NULL) != pdPASS) { PRINTF("Task creation failed!.\r\n"); while (1) ; } if (xTaskCreate(task2, "task2", configMINIMAL_STACK_SIZE + 100, NULL, hello_task_PRIORITY, NULL) != pdPASS) { PRINTF("Task creation failed!.\r\n"); while (1) ; } if (xTaskCreate(task3, "task3", configMINIMAL_STACK_SIZE + 160, NULL, hello_task_PRIORITY, NULL) != pdPASS) { PRINTF("Task creation failed!.\r\n"); while (1) ; } if (xTaskCreate(task4, "task4", configMINIMAL_STACK_SIZE + 161, NULL, hello_task_PRIORITY, NULL) != pdPASS) { PRINTF("Task creation failed!.\r\n"); while (1) ; } if (xTaskCreate(task5, "task5", configMINIMAL_STACK_SIZE + 170, NULL, hello_task_PRIORITY, NULL) != pdPASS) { PRINTF("Task creation failed!.\r\n"); while (1) ; } if (xTaskCreate(task6, "task6", configMINIMAL_STACK_SIZE + 200, NULL, hello_task_PRIORITY, NULL) != pdPASS) { PRINTF("Task creation failed!.\r\n"); while (1) ; } if (xTaskCreate(task7, "task7", configMINIMAL_STACK_SIZE + 300, NULL, hello_task_PRIORITY, NULL) != pdPASS) { PRINTF("Task creation failed!.\r\n"); while (1) ; } vTaskStartScheduler(); for (;;) ; } /*! * @brief Task responsible for printing of "Hello world." message. */ static void task1(void *pvParameters) { for (;;) { PRINTF("Hello world.\r\n"); vTaskSuspend(NULL); } } static void task2(void *pvParameters) { for (;;) { PRINTF("H\r\n"); vTaskSuspend(NULL); } } static void task3(void *pvParameters) { for (;;) { PRINTF("H\r\n"); vTaskSuspend(NULL); } } static void task4(void *pvParameters) { for (;;) { PRINTF("H\r\n"); vTaskSuspend(NULL); } } static void task5(void *pvParameters) { for (;;) { PRINTF("H\r\n"); vTaskSuspend(NULL); } } static void task6(void *pvParameters) { for (;;) { PRINTF("H\r\n"); vTaskSuspend(NULL); } } static void task7(void *pvParameters) { for (;;) { PRINTF("H\r\n"); vTaskSuspend(NULL); } } Re: freeRTOS stack size configuration Hi @Relas  In FreeRTOS, the stack size specified in xTaskCreate() is measured in words (not bytes). For the LPC51U68, which uses a 32-bit word size, each word is 4 bytes. For instance, if you specify configMINIMAL_STACK_SIZE + 50, this translates to (configMINIMAL_STACK_SIZE + 50) * 4 bytes of stack space. The alignment adjustments by FreeRTOS or the compiler can cause discrepancies between the requested stack size and the actual allocated size. BR Hang

MPC5744P compatible HSM Hello everyone. We are using MPC5744P. And we check the MCU does not have HSM. Please let me know what is the MPC5744P compatible HSM. We are trying to apply digital signature such as RSA or ECC. Re: MPC5744P compatible HSM I can't see suitable device for this. Have you considered SW emulation? There are libraries like Mbed TLS or wolfSSL which could help to implement it. That's the most cost-effective solution. Otherwise I think that S32K3 would be the best option. Regards, Lukas Re: MPC5744P compatible HSM Thanks for quick response. I also want to know NXP has add-on HSM. Add-on means that it is not inherited in MCU, but external to MCU. Because it is hard to change the MCU, we want to add the HSM chip if it is. Thanks Re: MPC5744P compatible HSM Hi @LCGSEMS  The only option in MPC57xx family is MPC5748G which contains HSM module. Some other MPC57xx devices has CSE module only which meets SHE requirements. So, there's no support for RSA or ECC. However, MPC5748G with HSM firmware is provided only to approved customers (expecting large ordering quantity) due to limited support. Notice that standard MPC5748G devices does NOT have HSM firmware installed. Devices with HSE firmware has special part numbers. If you are interested, please contact local NXP sales office. Anyway, much better option is to migrate to S32K3 devices which has HSE module. HSE firmware can be used by all customers. It does support RSA and ECC. https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32k-auto-general-purpose-mcus/s32k3-microcontrollers-for-automotive-general-purpose:S32K3 It's also newer device, so guaranteed availability is longer: https://www.nxp.com/products/nxp-product-information/nxp-product-programs/product-longevity:PRDCT_LONGEVITY_HM Regards, Lukas

MPC5744P兼容HSM 大家好。 我们正在使用MPC5744P。我们检查 MCU 没有 HSM。 请告诉我什么是与 MPC5744P 兼容的 HSM。 我们正在尝试应用 RSA 或 ECC 等数字签名。 回复：MPC5744P兼容HSM 感谢您的快速回复。 我还想知道 NXP 是否有附加 HSM。 Add-on 指的是它不是继承于 MCU 内部，而是位于 MCU 外部。 因为 MCU 很难更换，所以如果可以的话我们想添加 HSM 芯片。 谢谢 回复：MPC5744P兼容HSM 你好@LCGSEMS MPC57xx 系列中唯一的选择是包含 HSM 模块的 MPC5748G。一些其他 MPC57xx 设备仅具有满足 SHE 要求的 CSE 模块。因此，不支持 RSA 或 ECC。 然而，由于支持有限，带有 HSM 固件的 MPC5748G 仅提供给获得批准的客户（预计订购数量较大）。请注意，标准 MPC5748G 设备没有安装 HSM 固件。带有 HSE 固件的设备有特殊的零件编号。如果您有兴趣，请联系当地的恩智浦销售办事处。 无论如何，更好的选择是迁移到具有 HSE 模块的 S32K3 设备。所有客户都可以使用 HSE 固件。它确实支持 RSA 和 ECC。 https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32k-auto-general-purpose-mcus/s32k3-microcontrollers-for-automotive-general-purpose:S32K3 这也是一种较新的设备，因此保证的可用性更长： https://www.nxp.com/products/nxp-product-information/nxp-product-programs/product-longevity:PRDCT_LONGEVITY_HM 问候， 卢卡斯

i.MX8MのROMイベント i.MX8MN上で動作するRTOSアプリケーションでROMイベントを取得したいです。 i.MX8MシリーズのROMイベントはどのように入手できますか? AN12853を読んだのですが、i.MX8Mに当てはまるものがどれなのかわからなかった。 i.MX8MのROMイベントについて 返信ありがとうございます。 ログを確認することができました。 パラメータの詳細が記載されたドキュメントはありますか? HAB を試行しているところ、ROM イベント ID 定義バージョン 2 に 0xA0:Image 認証結果のログが見つかりましたが、その Parameter0 値が何を意味するのか知りたいです。 現在私が知っているのは、それが0xF0ではなく、通過しないことだけです。

ROM Event on i.MX8M I want to get ROM Event on an RTOS application running on i.MX8MN. How can I get ROM Event of i.MX8M series? I read AN12853, but I couldn't figure out which one applies to i.MX8M. Re: ROM Event on i.MX8M Thanks for clarifying! Could successfully read from 0x0090E558 and the value there seem to make sense. Kind regards, Markus Re: ROM Event on i.MX8M Hi, Check the OCRAM starting from address 0x90E558. You should find the ROM event buffer there. The OCRAM address pointed to by 0x9E0 should correspond to the ROM event buffer. Regards, Re: ROM Event on i.MX8M Hi, I'm currently trying to get mainline u-boot v2025.01 running on an i.MX8MM on a custom board. However, we're stuck in the boot loader and don't get output via serial interface. So, I connected a J-Link base and read out the registers. Found out that SPL obviously returns to Boot ROM (as the PC is in the Boot ROM range when halting the Cortex-A53), so I wanted to read out the ROM event log buffer to get more info. Having found this post, I tried also with 0x9E0 as address, but the output doesn't seem to make sense: --- Cortex-A53 identified. J-Link>halt PC = 00000000000160C4 CPSR = 600003CD (AArch64, EL3h (SP_EL3) mode, IRQ masked, FIQ masked) SP = 0000000000901F40 ELR_EL1 = 2280006102140688 ELR_EL2 = A700010002088A08 ELR_EL3 = 0000000000016390 SP_EL0 = 01C0000202200002 SP_EL1 = 030C001080440040 SP_EL2 = 000000002002F0F3 SP_EL3 = 0000000000901F40 R0 = 000000000090CC90, R1 = 0000000000000006 R2 = 0000000000901DFB, R3 = 0000000000000000 R4 = 000000000000C1DC, R5 = 0000000000901DFC R6 = 0000000000000000, R7 = 0000000000000000 R8 = 0000000000000000, R9 = 0000000000000180 R10 = 0000000000000047, R11 = 0000000000000000 R12 = 000000000090B5E0, R13 = 000000000090B528 R14 = 0000000000004000, R15 = 000000000090B5E0 R16 = 0000000000000000, R17 = 0000000000000000 R18 = 0000000000000000, R19 = 0000000030350480 R20 = 000000000000000F, R21 = 000000000090E6D8 R22 = 000000000090C000, R23 = 0000000030350480 R24 = 0000000000000002, R25 = 0000000000910000 R26 = 0000000030390070, R27 = 0000000072000000 R28 = 0000000000000000, R29 = 0000000000901F40 R30 = 00000000000160C4, R31 = 0000000000000000 JMISC = 0000000000000008 J-Link>mem32 0x9E0 4 000009E0 = 0090E558 00000000 0090E6D8 00000000 J-Link> --- Is 0x9E0 the correct buffer address also for ixm8m Mini (not only for Nano)? AN12853 is not very clear in this regard... If this is correct, the read data doesn't make sense to me since the first 8 bits should be the ROM event ID (starting with 0x01), but were read as 0x00? Or did I make some mistake in interpreting here? Kind regards, Markus Re: ROM Event on i.MX8M Thanks for the reply. I was able to check the logs. Is there any documentation with details of the parameters? I am trying HAB and I found a log of 0xA0:Image authentication result in the ROM Event ID definition version 2, but I would like to know what that Parameter0 value means. Currently I only know that it is not 0xF0 and that it does not pass. Re: ROM Event on i.MX8M Hello @spthx  I hope you are doing very well. As you can see on the AN12853, the ROM event log buffer is located at a fixed address in the on-chip RAM: Please refer to the Mscale Series. Best regards, Salas.

i.MX8M 上的 ROM 事件 我想在 i.MX8MN 上运行的 RTOS 应用程序上获取 ROM 事件。 如何获取i.MX8M系列的ROM事件？ 我读过 AN12853，但我不知道哪一个适用于 i.MX8M。 回复：i.MX8M 上的 ROM 事件 谢谢您的回复。 我能够检查日志。 是否有包含参数详细信息的文档？ 我正在尝试 HAB，并且在 ROM 事件 ID 定义版本 2 中发现了 0xA0：图像认证结果的日志，但我想知道 Parameter0 值的含义。 目前只知道不是0xF0，不通过。

LLCE CAN transmission issue on S32G VNP RDB2 Rev.E Dear NXP community, I'm currently encountering an issue when I try to send a CAN frame via the BCAN0 of the S32G2 LLCE module. I'm using the demoboard S32G-VNP-RDB2 Rev.E. I've seen via the emulator that everything performs well when I pop the BLROUT FIFO to get the index of the Tx Transmit table, after that I fill the message in the shared memory and then I send back the index via the BLRIN FIFO. The issue is that nothing happens on the CAN bus. So after popping the index 15, the BLROUT returns 0xFFFFFFFF. Is there any configuration that we should set in order to enable the BCANs ? FYI, the firmware responds well to the commands I send and I've correctly configured the SIUL2 to configure the Tx and Rx pins of the LLCE_CAN_0. We have also observed that transceiver of the BCAN0 (U17) did not change the logic level of LLCECAN0H and LLCECAN0L when we drive the LLCE_CAN0_TXD signal. We have also checked that the signal LLCE_CAN01_EN is in the high logic level. Thank you for your support. Best regards, Re: LLCE CAN transmission issue on S32G VNP RDB2 Rev.E Hi @Daniel-Aguirre , As discussed in the support ticket, the problem is solved. It was due to the fact that the SIUL2 was not correctly configured for LLCE_CAN0_RX. Thanks for your support. Best regards, Re: @Re: LLCE CAN transmission issue on S32G VNP RDB2 Rev.E Hi @Daniel-Aguirre , Yes, I can confirm you that after building the example project (can_loopback.elf) with "Make" and program it to the board, I've been able to see Tx transfers. So It seems that the issue of the STARTED state is really software on my side and not hardware. Yes the CAN log tool that I use contains a PHY. BR, Re: @Re: LLCE CAN transmission issue on S32G VNP RDB2 Rev.E Hi, Thanks for your feedback. On regards of the CAN log tool, does it contain a CAN PHY? Or is it only a logic analyzer? Also, can you help us confirm that using NXP packages you are able to see the correct outcome? Since it is the intended implementation to install LLCE on top of RTD. You should be able to use the available LLCE examples which do not make usage of external tools and use the same S32G to create the CANbus. Please, let us know. Re: @Re: LLCE CAN transmission issue on S32G VNP RDB2 Rev.E Yes, I was mistaken, I have actually 2 nodes, the second one is the CAN log tool. Best regards, Re: @Re: LLCE CAN transmission issue on S32G VNP RDB2 Rev.E Hi, Thanks for your feedback. Given the previous comment: "Regarding the number of nodes on the CAN bus, we have only one which is the BCAN0." CANBus standard specifies that the minimum CAN nodes that need to be available under the bus should be 2. We understand that you only have 1, which is not correct. If there is still only 1 node available under your CANbus, then the minimum conditions are not met, hence it is not starting. Please, let us know. @Re: LLCE CAN transmission issue on S32G VNP RDB2 Rev.E Hi @Daniel-Aguirre , Thanks for your reply. I've found out that the issue of not being able to transmit was due to the fact that the controller stays in the START_PENDING state instead of being in the STARTED state. The conditions "Bus sync" and "BCAN exit freeze" seem not to be satisfied to pass to the STARTED state. Can this be related to the baudrate configuration that can be wrong ? Best regards, Re: LLCE CAN transmission issue on S32G VNP RDB2 Rev.E Hi, All examples available for RTD+LLCE should be available under S32DS once the packages are installed. As for the Makefile, under the sample application of LLCE a makefile is provided for each of the examples (or a single one for all of them) in which the different steps in order to build an application are provided: Again, this is with the NXP RTD package being used as a base. Still, if you are looking for NXP to provide it directly, we can recommend either contacting your local NXP FAE/DFAE/representative or opening a ticket under the NXP online services, since it is not a common practice to share files through the public community, we do apologize. Please, let us know. Re: LLCE CAN transmission issue on S32G VNP RDB2 Rev.E Hi @Daniel-Aguirre , Is it possible to provide us a sample application executable (elf) that we can test on our side ? Otherwise what arguments should be specified in the command Make in order to build the application ? The Readme file does not specify it. Thank you. Best regards, Re: LLCE CAN transmission issue on S32G VNP RDB2 Rev.E Hi, Thanks for your feedback. We understand that the LLCE v1.0.7 was tested on top of RTD v4.0.2, as told under the Release Notes fro LLCE v1.0.7: "This package was tested on top of the S32G RTD (Real Time Drivers) SW32_RTD_4.4_4.0.2_D2306 product for the generic stubs and platform dependencies (Base, Platform, Resource, Det, Dem, Ecum, EcuC, RTE, MCU, Os, CanIf, LinIf, FrIf)." Can you help us confirm that using NXP packages you are able to see the correct outcome? As for the following comments, below will be some information from our side: "Regarding the number of nodes on the CAN bus, we have only one which is the BCAN0." CANBus standard specifies that the minimum CAN nodes that need to be available under the bus should be 2. We understand that you only have 1, which is not correct. I noticed that when I send the command LLCE_CAN_CMD_INIT_HSE the firmware returns "command not supported". Is this command mandatory for using the BCANs ? We understand that HSE+LLCE is only available under the LLCE FDK (premium software). If you are working with the LLCE FDK, help us contacting your local NXP FAE/DFAE/representative, given it is a premium software. Please, let us now. Re: LLCE CAN transmission issue on S32G VNP RDB2 Rev.E Hi @Daniel-Aguirre , I'm using the LLCE FW version 1.0.7 but I do not use the NXP's RTD. We are developing our own drivers. So for testing the BCAN I followed the examples given by NXP. Regarding the number of nodes on the CAN bus, we have only one which is the BCAN0. I noticed that when I send the command LLCE_CAN_CMD_INIT_HSE the firmware returns "command not supported". Is this command mandatory for using the BCANs ? Maybe it is due to the fact that we have not provisioned the HSE FW into the demoboard. We are not making use of the HSE, so I think we can get rid of this command. Thanks. Best regards, Re: LLCE CAN transmission issue on S32G VNP RDB2 Rev.E Hi, Can you let us know which RTD/LLCE version are you using? Below will be some comments on regards of your questions: Q > Is there any configuration that we should set in order to enable the BCANs ? [DA]: As for enabling the BCAN, you should have previously configured the respective pins to be able to use it. As for LLCE, all should be done within the NXP API if configured correctly under Config Tools. How many nodes do you have connected to your CAN Bus? Are you using any NXP examples? Please, let us know.

S32G wdog and standby mode Hi NXP,       My device is S32G-VNP-RDB3. I have a question that I would like you to answer. If i do not disable the PMIC watchdog when my device in STANDBY mode, what will happen on my device, reset or nothing?.  Whether it is necessary to disable the watchdog before entering low power mode. Re: S32G wdog and standby mode Hi @LIU_HAO, It depends on the configuration of the PMIC (if applicable), in your case you can review the AN12952: S32Gx Power Saving Techniques Application Note there is mentioned at the chapter 4.3 Standby mode entry processes, that you need to configure the PMIC's Standby Window Counter prior to the Standby entry to make it start counting for this particular case of the S32G-VNP-RDB3 that use the VR5510. If this configuration is not done the device will reset. [page 25, AN12952: S32Gx Power Saving Techniques Application Note, Rev. 2, 07/2021] Also, you can review the demo: S32G: M kernel Standby demo and how to porting to Mcal  Let me know if you have any question. 

After lpddr4 initialization in Imx8m mini global variable doesn't have zero Hi, I am initialized spl lpddr4 after that further global variable doesn't have zero at initial time. Where it is causing issue for global variable, global structure and static variable. Re: After lpddr4 initialization in Imx8m mini global variable doesn't have zero The issue was resolved. Thank you for your response Re: After lpddr4 initialization in Imx8m mini global variable doesn't have zero Hello @Hariharan1  Could you please share more details to try to replicate by my side? (BSP, steps, etc.) Best regards. Salas.

S32G VNP RDB2 Rev.E 上的 LLCE CAN 传输问题 尊敬的恩智浦社区成员： 当我尝试通过 S32G2 LLCE 模块的 BCAN0 发送 CAN 帧时，我遇到了一个问题。我正在使用演示板 S32G-VNP-RDB2 Rev.E。 我已经通过模拟器看到，当我弹出 BLROUT FIFO 以获取 Tx 传输表的索引时，一切都运行良好，之后我将消息填充到共享内存中，然后通过 BLRIN FIFO 发回索引。 问题是 CAN 总线上没有任何反应。因此，弹出索引 15 后，BLROUT 返回 0xFFFFFFFF。 为了启用 BCAN，我们需要设置什么配置吗？ 仅供参考，固件对我发送的命令响应良好，并且我已正确配置 SIUL2 来配置 LLCE_CAN_0 的 Tx 和 Rx 引脚。 我们还观察到，当我们驱动 LLCE_CAN0_TXD 信号时，BCAN0（U17）的收发器并没有改变 LLCECAN0H 和 LLCECAN0L 的逻辑电平。我们还检查了信号LLCE_CAN01_EN处于高逻辑电平。 感谢您的支持。 顺祝商祺！ 回复：@Re: S32G VNP RDB2 Rev.E 上的 LLCE CAN 传输问题 是的，我错了，我实际上有2个节点，第二个是CAN日志工具。 此致，

chromium could not play video on network on imx93evk Hi experts:   I found that the chromium could not play video on network on platfrom imx93evk, yocto: LF 6.1.55.  No log print out,  just show "network could not connect" on wed.  Does any knows why ?    Thanks  Best Regards Linux Multimedia Yocto Project Re: chromium could not play video on network on imx93evk HI Bio_TICFS: Thanks . I't's not the problem of ethernet, but the problem of no hardware decoder in imx93. I have fixed the problem,  it need to add config to chromium to build h264 software decoder. Best Regards Re: chromium could not play video on network on imx93evk Hello, Please send us the log file, is this your custom board or is EVK? I have the MX93EVK and everything works well on ethernet. Regards Re: chromium could not play video on network on imx93evk Hi Bio_TICFSL: I have upgraded  to LF.6.6.36, but the issue still remain.  Any suggestion ?  Re: chromium could not play video on network on imx93evk Hello, Try the latest BSP, chromium has some bugs in the version you are playing. Regards

Debug problems with FlexSPI2 on i.MX RT1171 Hello, iMX RT1171 SDK v2.15.1 was used for the linker, startup, and driver files. External Flash is connected with FlexSPI2 - A pins. For this reason, the flash base address in the linker has been updated to 0x60000000. FLEXSPI_INSTANCE is set to 2 with the help of GPIO pins. FLEXSPI_PIN_GROUP_SEL = 1 and FLASH_CONNECTION_SEL = 0 efuses are set. At this stage, I have no problem writing to external flash. When I read it after writing, it was seen that there were spi configurations at 0x60000400. However, when I start debugging, it branches to different unknown points. What could be my problem here? Can you explain the steps I should check? Should I burn fuses like FLEXSPI_PIN_GROUP_SEL and FLASH_CONNECTION_SEL to help set up FlexSPI-2? Is there a place I need to update in the linker and startup in imx1171 SDK v2.15.1? Re: Debug problems with FlexSPI2 on i.MX RT1171 Hi @BrK_ , There are technical sharing on this topic, please kindly refer to the following links for details. https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/i-MX-RT-FLEXSPI-booting-guide/ta-p/1669262 https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/RT1170-flexSPI1-secondary-QSPI-flash-debug-flashdriver/ta-p/1761851  Hope that helps, Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: Debug problems with FlexSPI2 on i.MX RT1171 Hi @Kan_Li, The external flash I use is different from the eval-board external flash. For this reason, I need to change the settings in the flexspi_nor_config file. Can you give me flexspi_nor_config.c configurations or documentation that explains how to configure according to my external flash? Re: Debug problems with FlexSPI2 on i.MX RT1171 Hi @Kan_Li, If I were to give information about my latest situation: I can now work in debug mode. I made some edits to the Flexspi_nor_config.c file; I activated QEN and set serialclkfreq to 50mhz. I set the gpio to FLEXSPI INSTANCE 2. I set the FLEXSPI_PIN_GROUP_SEL bit of the 0x9a0 flexspi nor efuse and burnt it. I defined XIP_BOOT_HEADER_ENABLE=1. I updated the flash base addresses in the linker to start from 0x60000000. I am working in internal boot mode. In this case, I expect it to work in XIP mode and now I can debug it. But my current problem is that when I turn the power of my microcontroller off and on, my code does not run. I observed it with the debug LED I put in the code. I think the problem here may be that it goes into serial downloader mode due to an error during the rom bootloader. What should I check or is there a fuse I should use or a flexspi configuration I should change? Re: Debug problems with FlexSPI2 on i.MX RT1171 Hi @BrK_ , If I understand correctly , your application can run standalone without any issue but failed to debug with it, right? Was the application running in XIP mode or not? Was the boot mode configure by GPIO or eFuse? Please kindly clarify. Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

S32G VNP RDB2 Rev.E での LLCE CAN 伝送の問題 親愛なるNXPコミュニティ、 現在、S32G2 LLCE モジュールの BCAN0 経由で CAN フレームを送信しようとすると問題が発生しています。デモボードはS32G-VNP-RDB2 Rev.Eを使用しています。 エミュレータを介して、BLROUT FIFOをポップしてTx Transmitテーブルのインデックスを取得し、その後、共有メモリにメッセージを入力してから、BLRIN FIFOを介してインデックスを送り返すと、すべてがうまく機能することを確認しました。 問題は、CANバスでは何も起こらないことです。したがって、インデックス 15 をポップした後、BLROUT は 0xFFFFFFFF を返します。 BCANを有効にするために設定する必要がある構成はありますか? 参考までに、ファームウェアは私が送信したコマンドによく応答し、SIUL2を正しく構成してLLCE_CAN_0のTxピンとRxピンを構成しました。 また、BCAN0(U17)のトランシーバーでは、LLCE_CAN0_TXD信号を駆動するときにLLCECAN0HとLLCECAN0Lのロジックレベルが変更されないことも確認されています。また、シグナルLLCE_CAN01_ENがハイロジックレベルにあることも確認しました。 再開まで今しばらくお待ちください。 よろしくお願いいたします。 日時:@Re:S32G VNP RDB2 Rev.EでのLLCE CAN伝送の問題 はい、私は間違っていました、私は実際には2つのノードを持っています、2番目はCANログツールです。 よろしくお願いいたします

Wrong documentation for the slew rate (SRE) setting for pads I'm using iMXRT1176 and MCUXpresso IDE (v11.8.0 [Build 1165] [2023-07-26]). Many pads have a "Slew rate" option, to choose between "fast" and "slow" rise/fall times. The datasheet ("IMXRT1170IEC", Rev. 5, 01/2024) describes the correct behavior. For example, in table 40, "AC specifications for GPIO_AD/GPIO_LPSR/GPIO_DISP_B2 bank", we see that the rise/fall time in normal conditions is 3ns (row #1, DSE = 0, SRE = 0), and the rise/fall time is 6ns when the slew rate is limited (row #2, DSE = 0, SRE = 1). From physical testing, it is indeed the case that SRE=0 results in fast transition times, while SRE=1 results in slower times, so that SRE seems to mean "Slew-rate-limiter enable". However, the reference manual and all the source code uses the opposite (wrong) meaning: 0 is "slow", 1 is "fast". In the reference manual ("IMXRT1170RM", Rev. 2, 06/2023): * Table 11.2 indicates "SRE - Fast slew rate" (which implies that SRE=1 means "fast") * Section 12.4.4.18.4 indicates: ==== SRE - Slew Rate Field [default value: 0] Select one out of next values for pad: GPIO_LPSR_00 0b - Slow Slew Rate 1b - Fast Slew Rate ==== This section is for SW_PAD_CTL_PAD_GPIO_LPSR_00, but a similar one appears for all the other pads with SRE capability (§12.4.6.210.3, §12.4.6.276.3, etc.). The source code file "board/pin_mux.c" present in the SDK examples, contains the wrong definitions (used with the SETUP, SETUPG macros): ==== #define DISP_B2_SLEW_FAST (1<<0) /* fast slew rate */ #define DISP_B2_SLEW_SLOW (0<<0) /* slow slew rate */ #define AD_SLEW_FAST (1<<0) /* fast slew rate */ #define AD_SLEW_SLOW (0<<0) /* slow slew rate */ #define LPSR_SLEW_FAST (1<<0) /* fast slew rate */ #define LPSR_SLEW_SLOW (0<<0) /* slow slew rate */ #define SNVS_SLEW_FAST (1<<0) /* fast slew rate */ #define SNVS_SLEW_SLOW (0<<0) /* slow slew rate */ ==== The code generated by Config Tools is wrong too. For instance, choosing "Fast slew rate" in the GUI, leads to the following code being generated in "board/pin_mux.c": ==== - {pin_num: L17, peripheral: LPSPI1, signal: SCK, pin_signal: GPIO_AD_28, direction: OUTPUT, pull_up_down_config: no_init, pull_keeper_select: Keeper, slew_rate: Fast} IOMUXC_SetPinConfig( IOMUXC_GPIO_AD_28_LPSPI1_SCK, /* GPIO_AD_28 PAD functional properties : */ 0x03U); /* Slew Rate Field: Fast Slew Rate Drive Strength Field: high drive strength Pull / Keep Select Field: Pull Disable, Highz Pull Up / Down Config. Field: Weak pull down Open Drain Field: Disabled Domain write protection: Both cores are allowed Domain write protection lock: Neither of DWP bits is locked */ ==== SRE is bit #0, so the configuration 0x03U has this bit set to 1 (meaning "fast", which is wrong). The wrong description is also present in the debugging "Peripherals" view, in MCUXpresso. For instance, for IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_28.SRE, the values shown are "SRE_0_Slow_Slew_Rate" and "SRE_1_Fast_Slew_Rate". Also, for IOMUXC.SW_PAD_CTL_PAD_GPIO_AD_28.DSE, the values shown are "DSE_0_normal_driver" and "DSE_1_high_driver". i.MXRT Re: Wrong documentation for the slew rate (SRE) setting for pads Hello, sorry for the late response, I made the report, and the department told me the fixed document will scheduled in June. SRE = 1 means slow slew rate. So, when the tool follows RM, the result is also wrong. Best regards, Pavel Re: Wrong documentation for the slew rate (SRE) setting for pads Hello, my name is Pavel, and I will be supporting our case, let me get into your case, when I have more information, I will contact you. Best regards, Pavel

DCDデータは必須ですか? DCDデータは主にSDRAMを構成するためのものだと思いますが、開発者が読み込んで変更するのは本当に難しいです。 dcd をそのままにして、実際の C コードで sdram を設定できますか? i.MXRT 101倍 i.MXRT 105倍 i.MXRT 106倍 Re:dcdデータは必須ですか? こんにちは @5angxr  それは私には有効な方法のように聞こえます。 よろしくお願いします。 Re:dcdデータは必須ですか? 私がやりたいことは: それは私のブートローダープロジェクトであり、スタック/ヒープ/ ZW / ZIデータをocramに入れ、CコードでフラッシュとSDRAMを設定した後、アプリをフラッシュからSDRAMとITCMにコピーし、次にアプリに移動します。 アプリにアクセスしたら、データをSDRAMに入れます。 では、この場合、DCDを空のままにしておくことはできますか? 回复: DCDデータは必須ですか? 私がやりたいことは: それは私のブートローダープロジェクトであり、スタック/ヒープ/ ZW / ZIデータをocramに入れ、CコードでフラッシュとSDRAMを設定した後、アプリをフラッシュからSDRAMとITCMにコピーし、次にアプリに移動します。 アプリにアクセスしたら、データをSDRAMに入れます。 では、この場合、DCDを空のままにしておくことはできますか? Re:dcdデータは必須ですか? こんにちは @5angxr、 はい、DCD を空のままにするか、省略して C コードでメモリ インターフェイスを初期化できます。 ただし、これにより、スタック/ヒープ/bss/...外部メモリでは、これらの領域は main の前のスタートアップ コードに作成されます。 よろしくお願いします。

implement gpio-imx-rpmsg driver on imx8mn Hi everyone  I am writing an application that both M7 core and A53 use different gpio in one port ( ex: A53 use GPIO1_IO_10 , M7 core use GPIO1_IO_11 ), this will make kernel linux stuck forever . So my solution is Cortex-M will do physical writes/reads to GPIO and send RPMSG messages to core A53 when interrupt happens. All GPIO pins references from disabled &gpio could be easily remapped to virtual GPIO. libgpiod with Linux gpio-imx-rpmsg.c driver, base on this post IMX8M PLUS: GPIO Interrupt conflicts between M7 and A53 - Technical Support - Toradex Community I have download SDK for M7 core application for IMX8mn chip and has no example implement to service with gpio-imx-rpmsg diver from linux for M7 core. Anyone can help me solve this problem ? Regards congphuong Re: implement gpio-imx-rpmsg driver on imx8mn Hi @phuongnguyen1  gpio-imx-rpmsg driver in kernel is for i.MX7ULP and i.MX8ULP, you can download imx7ul/imx8ulp SDK for reference. For example, evkmimx8ulp_power_mode_switch\app_srtm.c and evkmimx8ulp_power_mode_switch\srtm\services\srtm_io_service.c

1028 DSPI communication clock has a significant delay hi Recently, I have been using DSPI as the host for slave communication, but I found that the communication speed is very slow. Through logic analysis, I found that when CS is lowered by 2ms, the clock sends every 1ms, and 1ms corresponds to SPI communication which is too slow. Do you have any optimization solutions? The currently used edge bsp5.10 Re: 1028 DSPI communication clock has a significant delay Thank you for your response. I have solved the issue by adjusting the timing parameters of the SPI. Re: 1028 DSPI communication clock has a significant delay Would you share which pins you are using and log when you access the interface.

KW38 CAN-FD 64bytes Hi,  I am using sample project "frdmkw38_flexcan_interrupt_transfer" to try CAN-FD. If I want to send 64 bytes data through, I set "DLC" as 15. In loopback mode, I send 64 bytes data, but I only receive 16 bytes. Is there any configuration I miss? Thanks. Product: KW 37|38|39 Re: KW38 CAN-FD 64bytes @Christine_Li  Thanks,  It's work. Best  Regards,  Adam Re: KW38 CAN-FD 64bytes Hi, @Adam_Ho  #define RX_MESSAGE_BUFFER_NUM (6) #define TX_MESSAGE_BUFFER_NUM (5) If use kFLEXCAN_64BperMB, the Maximum MBs is 7. So the "RX_MESSAGE_BUFFER_NUM" and "TX_MESSAGE_BUFFER_NUM"  should less than 7. Pleas set "RX_MESSAGE_BUFFER_NUM" to 6, and "TX_MESSAGE_BUFFER_NUM" to 5, then the system would work normally. I tested it on my side, it is ok. Please try it on your side and let me know your results. Best regards, Christine. Re: KW38 CAN-FD 64bytes Hi @Christine_Li m  Thank for you kindly support. When this issue have further step, please let me know. Best Regards,  Adam Re: KW38 CAN-FD 64bytes Hi, @Adam_Ho  Thanks for your quick reply. I can't agree with you more. I will create an internal case to track further. Once receive any response from our internal team, I will share with you. Thanks again for creating such an important issue to us, it give a great chance to make us better. Have a nice weekend! Best regards, Christine. Re: KW38 CAN-FD 64bytes Hi @Christine_Li , Yes, you reproduce  my issue. I think Rx buffer size is wrong, so system in 64Bytes parameter when rx data  coming system go to wrong address. Then system halt. Re: KW38 CAN-FD 64bytes Hi, @Adam_Ho  Thanks for your reply. Just to confirm with you, after you change all parameters related to 64Bytes, then the board doesn't have any response, am I right? I am trying to reproduce your issue, and above is what I saw on my two boards(one as TX, one as RX). But when I changed back to 32Bytes related parameters, it can work properly. Error phenomenon is like below: Is is same as your side? Best regards, Christine. Re: KW38 CAN-FD 64bytes Hi @Christine_Li , Yes, I am using 12V as power voltage. Thanks. Best Regards,  Adam Re: KW38 CAN-FD 64bytes Hi, @Adam_Ho  Did you connect 12V power supply on J32 of the two boards? I checked the Readme, it mentioned this point. And also I am trying on my local side to repro this issue. Best regards, Christine. Re: KW38 CAN-FD 64bytes Hi @Christine_Li , I check all the parameter in Table. and the result is in below. Yes, It's only have problem in 64Byte. I think the problem is on Rx buffer size, maybe this is the clue to find out the result. I attach the source code for loopback mode, and comment the place I configurate. You can find the place by //TODO: adam_test    loopback enable loopback disable kFLEXCAN_8BperMB Pass Pass kFLEXCAN_16BperMB Pass Pass kFLEXCAN_32BperMB Pass Pass kFLEXCAN_64BperMB Fail Fail Re: KW38 CAN-FD 64bytes Hi, @Adam_Ho  Thanks for your feedback. I checked your current settings, and also checked our Reference Manual. In reception, this DLC field is written by the FlexCAN module, copied from the DLC (Data Length Code) field of the received frame. In transmission, this DLC field is written by the CPU and corresponds to the DLC field value of the frame to be transmitted. I think it should be matched with below: * DWORD_IN_MB DLC BYTES_IN_MB Maximum MBs * 2 8 kFLEXCAN_8BperMB 32 * 4 10 kFLEXCAN_16BperMB 21 * 8 13 kFLEXCAN_32BperMB 12 * 16 15 kFLEXCAN_64BperMB 7 May I ask whether it can work well with below? It only has problem when you use in 64Byte, am I right? Or you didn't tried 8Bytes and 32Bytes? * DWORD_IN_MB DLC BYTES_IN_MB Maximum MBs * 2 8 kFLEXCAN_8BperMB 32 * 8 13 kFLEXCAN_32BperMB 12 How about disable loop back mode? Best regards， Christine. Re: KW38 CAN-FD 64bytes Hi @Christine_Li , I modify the parameters to fit "kFLEXCAN_64BperMB", but seems not work. If I use "kFLEXCAN_32BperMB", it is work. Please give me more hint.  Thanks. Re: KW38 CAN-FD 64bytes Hi, @Adam_Ho  Thanks for creating case to us and hope you are doing well. I checked our SDK code, and may I ask whether you only modified DLC from 10 to 15 or also changed DWORD_IN_MB and BYTES_IN_MB? For your information: Dword in each message buffer, Length of data in bytes, Payload size must align, and the Message Buffers are limited corresponding to each payload configuration.   So please also modified DWORD_IN_MB and BYTES_IN_MB to the one related to DLC to have a try.   Best regards, Christine.

dcd 数据是必须的吗？ 我认为 dcd 数据主要用于配置 sdram，但开发人员很难读取和修改它。 我可以不用 dcd，而是在真正的 C 代码中配置 sdram 吗？ i.MXRT 101x i.MXRT 105x i.MXRT 106x 回复：dcd 数据是必须的吗？ 你好@5angxr 对我来说这听起来像是一个有效的方法。 此致 回复：dcd 数据是必须的吗？ 我想要做的是： 这是我的引导加载程序项目，我将堆栈/堆/ZW/ZI 数据放入 ocram，在 C 代码中配置闪存和 sdram 后，我将 App 从闪存复制到 sdram 和 ITCM，然后转到 App。 当我进入应用程序时，我将数据放入 SDRAM 中。 那么，在这种情况下，我可以将 DCD 留空吗？ 回复： dcd数据是必须的吗？ 我想要做的是： 这是我的引导加载程序项目，我将堆栈/堆/ZW/ZI 数据放入 ocram，在 C 代码中配置闪存和 sdram 后，我将 App 从闪存复制到 sdram 和 ITCM，然后转到 App。 当我进入应用程序时，我将数据放入 SDRAM 中。 那么，在这种情况下，我可以将 DCD 留空吗？ 回复：dcd 数据是必须的吗？ 你好@5angxr ， 是的，您可以将 DCD 留空或省略它并在 C 代码中初始化内存接口。 然而，这使得将堆栈/堆/bss/...存储在外部存储器中变得更加困难，因为这些区域是在主程序之前的启动代码中创建的。 此致