/******************************************************************************** Detailed Description: Configures the FlexCAN 0 to transmit and receive a CAN message Baudrate to is set to 500kbps. In this config, RXFIFO is used to receive a messages. 8 filter elements are defined in the RXFIFO table. Both standard and extended IDs are used. DMA is enabled in component inspector to read RXFIFO. MB9 is moreover used to receive a message with given standard ID and MB8 is used to transmit a message upon buttons press. The callback function is installed as well and is it called each time message is received in MB9, RXFIFO or message is transmitted. * ------------------------------------------------------------------------------ * Test HW: DEVKIT-MPC5748G * MCU: PPC5748GSMKU6 0N78S * Target: Debug_FLASH * EVB connection: PCAN-View with PCAN-USB Pro connected to CAN port P5 * Compiler: S32DS.Power.2.1 * SDK release: S32_SDK_S32PA_RTM_3.0.3 * Debugger: OpenSDA, Lauterbach Trace32 ******************************************************************************** Revision History: Ver Date Author Description of Changes 1.0 02-May-2023 Petr Stancik Initial version, based on SDK demo example *******************************************************************************/

******************************************************************************** * Detailed Description: * * * This example shows synchronization between eTimer, CTU and ADC modules. * The eTimer0 module timer 2 is initialized to generate PWM signal, and rising edge * of this signal is used to generate trigger signal for CTU module. The CTU module * use one command list with 4 ADC_0 channels. Single conversion mode is used, * so ADC0 ch0, ch1, ch2 and ch3 are sampled. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * * EVB connection: * * P8.1  - A[0]  .. GPIO output, used to see CTU-ADC ISR period * P9.1     - B[7]  .. ADC0 AN[0] input * P9.2     - B[8]  .. ADC0 AN[1] input * P16.4 - I[3] .. CTU0 EXT TRG output * * see CTU0 EXT TRG output signal (toggle on each trigger) on P16.4 with respect of eTimer PWM signals. * ********************************************************************************

******************************************************************************** * Detailed Description: * Example configure DRUN mode with PLL running at 160MHz. * It also contain basic PIT and INTC driver for interrupt demonstration. * On PIT timer timeout the PIT is triggering an interrupt which is served in PIT interrupt * service routine. * ------------------------------------------------------------------------------ * Test HW:     X - PC5748G - MB (rev C) * MCU:          PPC5748GMMN6A * Maskset:    1N81M * Fsys:          160 MHz * Debugger:    Lauterbach Trace32 *               * Target:         Internal_FLASH * ********************************************************************************

******************************************************************************** * File main.c * Owner David Tosenovjan * Version 0.1 * Date May-31-2023 * Classification General Business Information ******************************************************************************** * Detailed Description: * The purpose of this example is show how to keep data in SRAM memory over SW * reset. * INIT_Derivative (file MPC5607B_HWInit.c) is modified to skip ECC RAM * initialization for SW reset source. Linker command file defines my_ram * section, a data being kept over reset are accesses as address pointer to this * location. After initialization SW resets are periodically triggered, * incrementing data on address test_address_3. * * ------------------------------------------------------------------------------ * Test HW: XPC5607B 176LQFP, XPC56XX EVB MOTHEBOARD Rev.C * MCU: PPC5607BMLUAM03Y * Terminal: 19200-8-no parity-1 stop bit-no flow control on LINFLEX_0 * Fsys: 64/48 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: RAM, internal_FLASH * EVB connection: none * ********************************************************************************

MPC5746R STCU2 configuration guide for: 1. Off-line BIST 2. On-line BIST rev 0.4

******************************************************************************** * Detailed Description: * Application performs basic initialization, initializes interrupts, blinking * one LED by core e200z4a, second by core e200z4b, third by core e200z2, * initializes and display notice via UART terminal and then terminal ECHO. * * ------------------------------------------------------------------------------ * Test HW:         MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU:             PPC5748GMMN6A 1N81M * Fsys:            160 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_2 * ********************************************************************************

******************************************************************************** * Detailed Description: * * ------------------------------------------------------------------------------ * Test HW:  TRK-MPC5634M rev.B, SPC5634M * Maskset:  1M35Y * Target :  RAM * Terminal: no * Fsys:     64 MHz PLL with 8 MHz crystal reference * * 1. you have to use an external power supply to the board (SBC power)   2. The SBC chip must be initialized (via SPI interface) to turn on the CAN transceiver.   3. For ease of use, install the VSUP shunt on (jumper J5). This it to put 9 V on the SBC's DBG pin - refer to the SBC Data Sheet for more details about the DBG pin of the SBC chip.   4. This code initializes the MCU, then sends commands to the SBC chip over the SPI bus to turn on the CAN transceiver, then the FlexCAN_A module transmits a message out of the board.   I/O configuration for the TRK-MPC5634M CAN example:   SBC_TXD  (MPC5634M CANATX PCR[83] ALT1 function) SBC_RXD  (MPC5634M CANARX PCR[84] input function)   SPI bus between the MCU and SBC:   SBC_!CS    (MPC5634M DSPI_B CS0  ALT1 function PCR[105]) SBC_CLK    (MPC5634M DSPI_B SCK  ALT1 function PCR[102]) SBC_MOSI   (MPC5634M DSPI_B SOUT ALT1 function PCR[104]) SBC_MISO   (MPC5634M DSPI_B SIN  input function PCR[103])  * ********************************************************************************

******************************************************************************** * Detailed Description: * ------------------------------------------------------------------------------ * Test HW: MPC57xx * Maskset: 1N81M * Target : SRAM * Fsys: 160 MHz PLL * ******************************************************************************** Revision History: 1.0 Oct-29-2014 b21190(Vlna Peter) Initial Version 1.1 Nov-20-2014 b21190(Vlna Peter) Modified for Cut2.0 1.2 Nov-20-2014 b21190(Vlna Peter) Added SWT_0 dissabling in startup 1.3 Mar-10-2016 b21190(Vlna Peter) Fixed clock configuraion for PLL 1.4 Feb-23-2017 b21190(Vlna Peter) FCCU EOUT and bi-stable protocol 1.5 Aug-26-2021 nxa13250(Vlna Peter) modified for MPC5746C *******************************************************************************/

******************************************************************************** * Detailed Description: * This example shows, how to use overlay feature - how to remap SRAM over Flash. * The remapping is visible only in mirrored flash address space. Normal address * space is not affected. * To see effect of the remapping, read the comments and watch following * addresses in debugger before and after executing Overlay() function: * * SRAM over Flash test case: * 0x4003_0000 * 0x090C_0000 * * Test HW: X-MPC5744PE257DC, MPC57xx motherboard * MCU: PPC5744PFMMM8 1N65H * Fsys: 200 MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH (debug mode, release mode) * EVB connection: none * ********************************************************************************

******************************************************************************** * Detailed Description: * * Application performs basic initialization, setup PLLs. * DSPI_A is configured as master using DMA to send/receive 8 words. * * Two DMA descriptors are initialized: * - TCD[32] master transmit * - TCD[33] master receive * * * EVB connection: * * Do external loopback to connect SOUT to SIN * * PM6 ... SCKA * PM7 ... SINA * PM8 ... SOUTA * PM13... PCSA0 ** * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 3N45H * Fsys: PLL1 = core_clk = 260MHz, PLL0 = 200MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * *********************************************************************************

The device can be secured by adding a Non-Volatile System Censorship Information (NVSCI) record to the DCF record list in the UTEST Flash block. A value of 55AAh in the censorship control word of the NVSCI record determines that the device is unsecured, any other value determines that the device is secured.   Censoring the device (example for lauterbach script) 1. Program NVSCI DCF record to first available space in UTEST memory.    data.set 0x00400308 %QUAD 0x55AA12340100000C ;NVSCI - Censorship Control enabled 2. Program Censorship password (0x1234567812345678)    data.set 0x00400310 %QUAD 0x1234567801000004 ;NVPWDL                                                            data.set 0x00400318 %QUAD 0x1234567801000008 ;NVPWDH    3. Perform reset   Now the device is censored and JTAG PASSWORD must be inserted in order to work with JTAG. Lauterbach ->   sys.option.keycode 0x1234567812345678 sys.attach sys.break The device is now accessible trough JTAG.   " After every reset the JTAG PASSWORD key must be reentered on censored device "   Uncensoring device: data.set 0x004003018 %QUAD 0x55AA55AA0100000C ;NVSCI - Censorship Control disabled   NOTE:   Peter Original Attachment has been moved to: MPC5744P_DCF_Censorship.cmm.zip

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, * * Initializes the MCU including the FlexCAN peripherals. * Configures the FlexCAN to transmit and receive a CAN message. * * Individual RX masking was added to the last version of this example. * Three messages with different ID's are sent via FlexCAN_0 MB0 MB1 and MB2. * These messages are received by FlexCAN_1 MB0, MB1 and MB2 according to masking * register settings. * * For MB0 data receive is used interrupt. * * * ------------------------------------------------------------------------------ * Test HW:         S32R274RRUEVB, MPC57xx Motherboard * MCU:             S32R274KAMMM 1N58R * Fsys:            PLL0 240MHz *                    Z4 Core 120MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, debug_ram and release mode) * EVB connection: * * It is necessary to remove both J35 jumpers. * * * Connect J35.2 to PA14 (CAN_1 TX) * Connect J35.4 to PA15 (CAN_1 RX) * * CAN0 is connected internally to J37 (this pin is placed on daughter card) * * Connect CAN P5.2 to J37.2 (CAN_1 and CAN_0 CANL) * Connect CAN P5.1 to J37.1 (CAN_1 and CAN_0 CANH) * * This connection has to be observed, otherwise correct communication between * CAN modules is not guaranteed. * * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * start both Z7 cores, interrupts initialization, blinking three LED by interrupts, * initializes and display notice via UART terminal and then terminal ECHO. * Each core serves one interrupt and one LED. * * The example configures the device for maximum performance by initialization of * instruction/data cache and enabling of branch prediction for each core * (startup.s files). * * ------------------------------------------------------------------------------ * Test HW:         MPC5777M-512DS, MPC57xx Motherboard * MCU:             PPC5777MQMVA8 0N78H * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_2 * Fsys:               600MHz * * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  USER LED1 connected to P8.0, LED2 connected to P8.1 *                  LED3 connected to P8.2 * ********************************************************************************

******************************************************************************** * Detailed Description: * * This example shows how to use CRC module. * - CRC32 is used * - byte stream is written into input register * - one test case uses direct access to CRC registers * - second test case uses DMA to write the data stream * - the results can be compared using this online calculator: *   http://www.zorc.breitbandkatze.de/crc.html * - screenshots from online calculator are attached * ------------------------------------------------------------------------------ * Test HW:         MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU:             PPC5748GMMN6A 1N81M * Fsys:            160 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH ********************************************************************************

The purpose of the example is to present advantage of streaming mode feature.   Example initializes eQADC module, converts specified command queue and displays results into terminal window. Used analog inputs ANB_0 and ANB_1 requires external connection to converted voltage (potentiometer) to see some valid numbers. Following channels are being converted: CH0 = signal ANB_0 (connect pot USER_DEV_RV2(J4-7) --> ANB_0 (J19-3)) CH1= signal ANB_1 (connect pot USER_DEV_RV3(J4-8) --> ANB_1 (J19-4)) CH2 = may be left open (example configures the pin to be pulled-up) CH3 = may be left open (example configures the pin to be pulled-down) Result are being filled to 2 result queues to see loop switching in the terminal window when advance trigger occurs (results are displayed in two columns, 1st column is related to Rqueue0, 2nd to Rqueue1). Advance trigger occurs when EVB's USER switch 1 is being pressed (considering USER_DEV_1D(J4-2) --> TPU_A0 (J22-1)). Repeat trigger is initiated automatically by PIT3 timer in 1 sec intervals. eQADC command filled by eDMA, results drained by interrupt service routines.   For detailed description SEE ATTACHED document.

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * For XPC564AKIT324S it initializes EBI for mounted external SRAM. * Its intention is to offer advanced startup code additional to CW stationery. * ------------------------------------------------------------------------------ * Test HW:        XPC564AKIT208S and XPC564AKIT324S * MCU:            SPC5644AMMG1,0M14X and SPC5644AMVZ1,0M14X * Fsys:           150/132/120/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************   NOTE: It cannot be used with MPC5642A device, only with MPC5644A and MPC5643A !   For MPC5642A device, use following project instead of attached one: Example XPC5642AKIT PinToggleStationery CW10.6

******************************************************************************** * Detailed Description: * * Application initializes SPI0 module as a master and SPI2 module as a slave. * Data are sent from master to slave and from slave to master. Simple * polling method is used to determine, when data were sent/received. * Received data are saved to global variables. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777M-512DS, MPC57xx Motherboard * MCU:             PPC5777MQMVA8 0N78H * Fsys:            PLL0 300MHz *                    PLL1 300MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, debug_ram mode, release mode) * EVB connection:  P18.12 to P14.13 (CS_0) *                    P11.4 to P8.13 (SCK) *                    P11.1 to P11.5 (SOUT - SIN) *                    P11.8 to P12.9 (SIN - SOUT) * * ********************************************************************************

******************************************************************************** * Detailed Description: * * The example shows how to initialize 3 submodules to generate 120° phase shift * between submodules. * CNTR register of each submodule is initialized with shifted value when PWM * generators are disabled using FORCE feature. * * ------------------------------------------------------------------------------ * Test HW:  MPC5744P (MPC5744P-257DS + MPC577xx motherboard) * Maskset:  1N15P * Target :  internal_FLASH, RAM * Fsys:     200 MHz PLL with 40 MHz crystal reference * * EVB connection: * * P8.12    - A[11] .. FlexPWM A[0] output * P8.11    - A[10] .. FlexPWM B[0] output * P8.13    - A[12] .. FlexPWM A[2] output * P8.14    - A[13] .. FlexPWM B[2] output * P10.8    - C[7] .. FlexPWM A[1] output * P10.7    - C[6] .. FlexPWM B[1] output * ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows how to configure Wake up unit and CAN sampler. * Once the device is woken up from STOP mode by falling edge on CAN0RX pin, * the CAN sampler starts to sample this pin in given period. * FlexCAN module is not initialized and used in this example because the CAN * sampler is independent of FlexCAN. * ------------------------------------------------------------------------------ * Test HW:  XPC56xxMB2 + XPC560B 176LQFP, PPC5607B * Target :  internal_FLASH, RAM * Fsys:     64 MHz PLL * ********************************************************************************

******************************************************************************** * Detailed Description: * Basic initialization of CMPU: * Region 0 (Instruction): Internal Flash @ 0x0040_0000-0x01FF_FFFF * Region 1 (Instruction): SRAM   @ 0x4000_0000-0x4005_FFFF * Region 6 (Data): SRAM @ 0x4000_0000-0x4005_FFFF * Region 7 (Data): Internal Flash @ 0x0040_0000-0x011F_FFFF * Region 8 (Data): PBRIDGE1/0 @ 0xF800_0000-0xFFFF_FFFF * * This excel configurator has been used: * https://community.nxp.com/docs/DOC-335467 * * ------------------------------------------------------------------------------ * Test HW:         X-MPC5744PE257DC, MPC57xx motherboard * MCU:             PPC5744PFMMM8 1N65H * Fsys:            200 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * ********************************************************************************