Error Correction Codes Implemented on MPC5777C PRELIMINARY INFORMATION, Subject to Change without Notice   Related code examples can be found here: Example MPC5777C-1b+2b_RAM_ECC_error_injection GHS614 Example MPC5777C-1b+2b_FLASH_ECC_error_injection GHS614  

******************************************************************************** * Detailed Description: * ------------------------------------------------------------------------------ * Test HW: MPC57xx * Maskset: 1N81M * Target : SRAM * Fsys: 160 MHz PLL * ******************************************************************************** Revision History: 1.0 Oct-29-2014 b21190(Vlna Peter) Initial Version 1.1 Nov-20-2014 b21190(Vlna Peter) Modified for Cut2.0 1.2 Nov-20-2014 b21190(Vlna Peter) Added SWT_0 dissabling in startup 1.3 Mar-10-2016 b21190(Vlna Peter) Fixed clock configuraion for PLL 1.4 Feb-23-2017 b21190(Vlna Peter) FCCU EOUT and bi-stable protocol 1.5 Aug-26-2021 nxa13250(Vlna Peter) modified for MPC5746C *******************************************************************************/

******************************************************************************** * Detailed Description: * * * This example shows synchronization between eTimer, CTU and ADC modules. * The eTimer0 module timer 2 is initialized to generate PWM signal, and rising edge * of this signal is used to generate trigger signal for CTU module. The CTU module * use one command list with 4 ADC_0 channels. Single conversion mode is used, * so ADC0 ch0, ch1, ch2 and ch3 are sampled. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * * EVB connection: * * P8.1  - A[0]  .. GPIO output, used to see CTU-ADC ISR period * P9.1     - B[7]  .. ADC0 AN[0] input * P9.2     - B[8]  .. ADC0 AN[1] input * P16.4 - I[3] .. CTU0 EXT TRG output * * see CTU0 EXT TRG output signal (toggle on each trigger) on P16.4 with respect of eTimer PWM signals. * ********************************************************************************

WARNING 1: Use censorship feature very carefully, because an inappropriate usage can lead in making the device useless!!! Thoroughly read all instructions before use!!!   WARNING 2: Version of ICDPPCNEXUS debugger that is included with CodeWarrior 2.10 is not capable to enable debug on certain devices including MPC5604B. Workaround is either using of Codewarrior 10.6 or using of PKGPPCNEXUS debugger - can be downloaded from P&E Microcomputer Systems   WARNING 3: In case TRACE32 debugger is being used (Lauterbach), it is needed to have updated TRACE32 software. TRACE32 releases 02/2015 and 09/2016..02/2018 may not be able to access to censored device. LAUTERBACH DEVELOPMENT TOOLS   The example consists of 2 parts and document describing how to access censored device via JTAG with using of PeMicro or Lauterbach debugger:   1) MPC5604B-Censor_device-CW210: ******************************************************************************** * Detailed Description: * The example code reprogram content of shadow flash to enable censorship. * After succesful operation LED1 is lighting. After power-on-reset the device * is censored with private 0xFEED_FACE_CAFE_BEEF. Subsequently the access can be * allowed by enabling debug of censored device as decipted in attached pdf * document. On this device password must be entered in reverse order i.e. * 0xCAFE_BEEF_FEED_FACE. Shadow flash re-programming code must be executed from * internal RAM. * ------------------------------------------------------------------------------   2) MPC5604B-Uncensor_device-CW210: ******************************************************************************** * Detailed Description: * Supposing the device is censored by example MPC5604B-Censor_device-CW210 * Firstly it is needed to enabled debug of censored device as decipted in * attached pdf document. On this device password must be entered in reverse * order i.e.0xCAFE_BEEF_FEED_FACE. MPC5604B_run_from_ram.cmm script does it by * command SYStem.option.keycode 0xCAFEBEEFFEEDFACE. * Then run this code to uncensor the device. After succesful operation LED1 is * lighting. After power-on-reset the device is uncensored and subsequent access * will be without password. Shadow flash re-programming code must be executed * from internal RAM. * ------------------------------------------------------------------------------

******************************************************************************** * Detailed Description: * This example initializes SMPU_0 and SMPU_1 to cover all memory resources for * all masters. * Simple test case is used in this example: after initialization, SMPU * configuration is changed to disable write access to last 4kB of RAM. * Once this area is written by CPU, exception will occur due to access * violation. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N81M * Target :  SRAM * Fsys:     160 MHz PLL * ********************************************************************************

This example follows application notes AN3283 and AN4365. It is intended for users who develop own JTAG programmer. It shows how to implement basic functions: - enter debug mode during reset - enable external debug mode - OnCE access to GPR, SPR and memory - Nexus access to memory The example is written in PRACTICE script language using Trace32 debugger from Lauterbach (www.lauterbach.com). Low level functions for JTAG are used, so users can see sequences of ‘0’s and ‘1’s which are sent to JTAG interface. Used commands are described in this document: www2.lauterbach.com/pdf/general_ref_j.pdf This example was tested on MPC5607B device and VLE instruction set was used for OnCE access.

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop (by second core), initializes and display notice via UART terminal and * then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * For XPC567XKIT516 it initializes EBI for mounted external SRAM device. * * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC567xADAT516 Rev.D, MPC567XEVBFXMB Rev.C * MCU:             PPC5676RDMVY1 3N23A * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:            180MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  ETPUC0(J24-0) -> USER_LED_8 (J5-8) *                  ETPUC1(J24-1) -> USER_LED_7 (J5-7)(to see blinking LEDs) * ********************************************************************************

******************************************************************************** * Detailed Description: * * Example gives possible implementation of input signal period/freq measurement. * eTimer channel capture 1 and 2 features are used. CAPT1/CAPT2 capture counter * value on rising/falling edge of input signal. The FIFO is set to 2 entries * and ICF2 is monitored. Free-running mode is used here. * * eTimer channel 0-1 are cascaded to achieve 1sec/1Hz measuring with 32bit counter. * * DMA is used to read CAPT1/2 registers and form 32bit values used in calculation. * * EVB connection: *   P8.2  - A[1]  .. eTimer0 channel1 input signal *   P8.1  - A[0]  .. GPIO output, used to show measurement period * *   Route LINFlexD_0 TXD/RXD (PB2/PB3) signals to the main board RS-232 transceiver *   Daughtercard: *   J17.11–12 ON  .. Connect LINFlexD_0 TXD (PB2) to main board. *   J17.8–9 ON .. Connect LINFlexD_0 RXD (PB3) to main board. * *   Motherboard *   J14 - SCI_RX ON *   J13 - SCI_TX ON *   J25 - SCI_PWR ON * * connect pulse signal to the P8.2. * See results on PC terminal (19200, 8N1, None). * Change freq/duty of input signal. * * ------------------------------------------------------------------------------ * Test HW:  MPC5744P * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * Terminal: 19200, 8N1, None ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows how to configure Wake up unit and CAN sampler. * Once the device is woken up from STOP mode by falling edge on CAN0RX pin, * the CAN sampler starts to sample this pin in given period. * FlexCAN module is not initialized and used in this example because the CAN * sampler is independent of FlexCAN. * ------------------------------------------------------------------------------ * Test HW:  XPC56xxMB2 + XPC560B 176LQFP, PPC5607B * Target :  internal_FLASH, RAM * Fsys:     64 MHz PLL * ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows, how to use overlay feature - how to remap SRAM over Flash. * The remapping is visible only in mirrored flash address space. Normal address * space is not affected. * To see effect of the remapping, read the comments and watch following * addresses in debugger before and after executing Overlay() function: * * SRAM over Flash test case: * 0x4003_0000 * 0x090C_0000 * * Test HW: X-MPC5744PE257DC, MPC57xx motherboard * MCU: PPC5744PFMMM8 1N65H * Fsys: 200 MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH (debug mode, release mode) * EVB connection: none * ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes eQADC module, performs calibration and converts channel 146 * (voltage level of VDD) to check core voltage level and displays it into * terminal window. No external connection required excluding terminal via eSCI. * * ------------------------------------------------------------------------------ * Test HW:        XPC564AKIT208S and XPC564AKIT324S * MCU:            SPC5644AMMG1,0M14X and SPC5644AMVZ1,0M14X * Fsys:           150/132/120/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

This document describes how to use Lauterbach FCCU (fault collection and control unit) periphery extension for MPC57xx devices. It is expected that user has deep knowledge on FCCU mechanisms in order to effectively use this extension. This scripting tool consist of 136 scripts for Lauterbach debugger. It helps user to quickly debug micro without need of reference manual. Here is and example of windows that user can use (detailed description can be found in user guide):

******************************************************************************** * Detailed Description: * * Application initializes SPI0 module as a master and SPI2 module as a slave. * Data are sent from master to slave and from slave to master. Simple * polling method is used to determine, when data were sent/received. * Received data are saved to global variables. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777M-512DS, MPC57xx Motherboard * MCU:             PPC5777MQMVA8 0N78H * Fsys:            PLL0 300MHz *                    PLL1 300MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, debug_ram mode, release mode) * EVB connection:  P18.12 to P14.13 (CS_0) *                    P11.4 to P8.13 (SCK) *                    P11.1 to P11.5 (SOUT - SIN) *                    P11.8 to P12.9 (SIN - SOUT) * * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts. STM_0 channel 0 is initialized to generate 100ms * periodic interrupt. Notice that STM is free running up counter, so it's * necessary to add calculated value to compare register each time in ISR handler. * * Test HW:         X-MPC5744PE257DC, MPC57xx motherboard * MCU:             SPC5744PGMMM9 1N15P * Fsys:            200 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  User LED 1 connected to A0 (P8.0), * ********************************************************************************

******************************************************************************** * Detailed Description: * * This example shows how to use CRC module. * - CRC32 is used * - byte stream is written into input register * - one test case uses direct access to CRC registers * - second test case uses DMA to write the data stream * - the results can be compared using this online calculator: *   http://www.zorc.breitbandkatze.de/crc.html * - screenshots from online calculator are attached * ------------------------------------------------------------------------------ * Test HW:         MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU:             PPC5748GMMN6A 1N81M * Fsys:            160 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH ********************************************************************************

Demo application MPC5606S-DEMO + LM75B + HIH-5030 + PCA8565 + GUI Simple weather station demo using 2 external sensors and  external real time clock/calendar   For detailed description SEE ATTACHED document. ------------------------------------------------------------------------------ Test HW:            MPC5606S-DEMO-V2 + LM75BD + HIH-5030 + PCA8565 sensors MCU:             PPC5606SEF OMLU 0M25V DD68391 XOTAC1003 Fsys:            64MHz Debugger:        Lauterbach Trace32 Target:          internal_FLASH Terminal:        none EVB connection:  1) Temperature sensor LM75B:                        J51.40 - F[6] -> LM75B SDA                        J51.43 - F[7] -> LM75B SCL                        J52.1  - 3.3V -> LM75B Vcc                        J50.1  - GND  -> LM75B Gnd                   2) Humidity sensor HIH-5030:                        J52.1  - 3.3V -> HIH-5030 Ve+                        J50.1  - GND  -> HIH-5030 Ve-                        J50.1  - ANS0 -> HIH-5030 Out                   3) External Real Time Clock:                        J51.40 - F[6] -> PCA8565 SDA                        J51.43 - F[7] -> PCA8565 SCL                        J52.1  - 3.3V -> PCA8565 Vcc                        J50.1  - GND  -> PCA8565 Gnd                                        *******************************************************************************

* Version: 1.1 * Date: Sep-22-2021 * Classification: General Business Information * Brief: This example content a basic PMPLL initialization and * configuration of Mode Entry module and Clock Generation * module. By default active is core 2 -> e200z4 ******************************************************************************** ******************************************************************************** * Detailed Description: * ------------------------------------------------------------------------------ * Test HW: MPC57xx + S32R274RRUEVB * Maskset: 1N58R * Target : internal_FLASH * Fsys: 240 MHz PLL with 40 MHz crystal reference for z7 and 120MHz for z4 * ******************************************************************************** Revision History: 1.0 Apr-02-2019 b21190(Vlna Peter) Initial Version 1.1 Sep-22-2021 b21190(Vlna Peter) FCCU fault reading

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to simulate Multi-bit or Single-bit ECC * error in FlexCAN RAM (user must choose it in the option at the end of * main function). * Example configures FlexCAN module, initializes ECC for all FlexCAN RAMs, then * it injects ECC error to the Message Buffer 9. * When corrupted data is accessed the IVOR1 exception handler is called in case * of multi-bit ECC error (IVOR1 exception occurs) and FCCU_Alarm_Interrupt * handler is called in case of single-bit ECC error (FCCU interrupt occurs). * Both function calls MEMU handler. * Reported FlexCAN ECC error address is corrected according RM, section 7.12.2.3 * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW: MPC57xx_Motherboard + MPC5744P-144DC * MCU: PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys: 200 MHz PLL with 40 MHz crystal reference * Debugger: Lauterbach Trace32 * Target: internal_FLASH, RAM * Terminal: 19200-8-no parity-1 stop bit-no flow control * EVB connection: default ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes eQADC module, performs calibration and converts channel 0 and * displays results into terminal window by interrupt service routine. Analog * input AN[0] requires external connection to converted voltage (potentiometer). * ------------------------------------------------------------------------------ * Test HW:        MPC5554EVB * MCU:            MPC5554MVR132 * Fsys:           132/112/80/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: USER_DEV pin RV2(i.e. pin8) -> pin B7 on I/O header ring *                 (potentiometer RV2 to analog input AN[0])   * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * The example configures the device for maximum performance (OPTIMIZATIONS_ON). * * ------------------------------------------------------------------------------ * Test HW:        MPC5554EVB * MCU:            MPC5554MVR132 * Fsys:           132/112/80/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: TPU_PORT_37 -> USER_LED_8 *                 TPU_PORT_38 -> USER_LED_7 (to see blinking LEDs)   * ********************************************************************************