Freescale and Boundary Devices are excited to announce the availability of the i.MX6x Sabre Lite Board, a low-cost development platform featuring the powerful i.MX 6Quad Application Processor.     $299   i.MX6 Development Board Highlights of the platform include: Quad-Core ARM® Cortex A9 processor at 1GHz 1GByte of 64-bit wide DDR3 @ 532MHz Three display ports (RGB, LVDS, and HDMI 1.4a) Two camera ports (1xParallel, 1x MIPI CSI-2) Multi-stream-capable HD video engine delivering H.264 1080p60 decode, 1080p30 encode and 3-D video playback in HD Triple Play Graphics system consisting of a Quad-shader 3D unit capable of 200MT/s, and a separate 2-D and separate OpenVG Vertex acceleration engine for superior 3D, 2D and user interface acceleration Serial ATA 2.5 (SATA) at 3Gbps Dual SD 3.0/SDXC card slots PCIe port (1 lane) Analog (headphone/mic) and Digital (HDMI) audio Compact size (3″x3″) 10/100/Gb IEEE1588 Ethernet 10-pin JTAG interface 3 High speed USB ports (2xHost, 1xOTG) 1xCAN2 port I2C GPIOs     See Compatible Products for: 7″ Display SATA Cable 5MP Camera Android Button Board LVDS Cable for Freescale 10.1″ PCIE DB   LEAD TIME IS CURRENTLY 2-3 WEEKS Cost will be $199 in Production (October 2012)   Click here for more information.  

Optimizing ARM Cortex-A9 support in Windows Embedded Compact     A Discussion of random hangs and other issues using Windows Embedded Compact on Freescale i.MX6 Application Processor and how they were solved By Adeneo Embedded Engineering Team Rev 1.0, November 2014 Summary Over the last year Adeneo Embedded has been confronted with reports of random processor deadlocks and operating system crashes from customers using our Freescale i.MX6 Windows Embedded Compact Board Support Package.   The random hangs and other issues surfaced while testing the devices comprehensively, i.e., regular CTK test passes did not bring out the failures to occur.   A dedicated team of senior engineers in Adeneo worked with a number of our key customers to analyze and solve the issues across the board. With the latest version of the Adeneo i.MX6 Windows Embedded Compact (7 and 2013) BSPs we are confident this has been achieved.   This white paper is about the investigation and shares some of our discoveries. All information in this document applies to Windows Embedded Compact 7 and 2013 as well as all variants of the i.MX6. Format of the investigation   Based on the problem reports from the field it was complex to identify a single component in a system as the culprit, so we decided to use a formal and broad process to investigate the situation.   A formal code review was done for the BSP code, Microsoft kernel code and customer application code; Lauterbach JTAG hardware debuggers were used to capture all available processor data at the time of crashes; Microsoft’s kernel team assisted with all questions around the Windows CE kernel; Customer’s engineering teams with their specific knowledge of their application developed test applications to replicate the problem more easily Freescale support engineers assisted with all questions around the silicon. Adeneo engineers redesigned the BSP from the ground and optimized it for i.MX6 and Cortex-A9 architecture    In summary, the collaboration of multiple companies, and more important, a diverse group of dedicated individuals with unique value add provided the comprehensive technical coverage to develop the solution to this complex problem History of the i.MX6 BSP   Starting point for the i.MX6 Windows Embedded Compact BSP were earlier BSPs for other application processors from Freescale like i.MX5x series and back to i.MX2x series. On the OS side the history goes back to Windows CE 5.   The good thing with Freescale application processors is that they share peripheral IP blocks across a range of processors, so developers can share and reuse a lot of code. This was very helpful in the beginning to get a BSP working on the new i.MX6 SoC and get projects started. However, the i.MX6 with its multi-core Cortex-A9 architecture which made is challenging to reuse the code designed for single core Cortex A8 or ARM9 CPUs.   In particular, cache management, multi-core support and memory configuration were the areas where existing Cortex-A8 and ARM9 code first was able to get enablement possible, but then failed in long-term stability tests. Cortex-A9 Architecture   The Freescale i.MX6 Application Processor is an implementation of the ARM Cortex-A9 and ARMv7 Instruction Set architecture. This powerful architecture provides a number of features to improve the processing performance, but requires special attention when developing system software.   The i.MX6 provides up to four cores in a symmetric multi-processing configuration under Windows Embedded Compact.   Some of the stability affecting features addressed during the investigation are:   Speculative load and execution Speculative table walks Branch prediction Out-of-order execution and instruction reordering Parallel internal busses Multiple internal buffers and caches Multi-core coherency L1/L2 cache operations Abort handling As part of our code review we identified shortcomings in existing code to correctly configure these features and take proper advantage of them. All code was verified with the ARM architecture documentation and updated to follow the latest recommendations by ARM. Freescale engineers helped to understand implementation details where ARM documentation is vague as it leaves some freedom to silicon vendors how to implement a feature.  All errata documents from Freescale, ARM and other IP vendors were reviewed, and we made sure all applicable fixes or workarounds got implemented in BSP or kernel code.   In discussion with customers we decided on a good working configuration for the i.MX6 processor that focuses on stability without compromising performance.   In multi-core configurations we updated the code to operate all available cores in the same configuration at all times. A critical area was power management code to reapply the same settings when coming back from low power states. Memory Configuration   Cortex-A9 provides a powerful memory management unit that allows it to implement a virtual memory system that operates the device in multiple modes, isolates application processes from each other and provides layers of protection and security.   Looking at the memory space, we have several types of memory with this architecture. We focused on:   Normal memory Device memory ARM architecture has a flat unified memory address space as compared to x86 architecture where we have a memory address space and an I/O address space. This means all our peripheral registers and other I/O addresses are mapped into the same address space together with RAM and ROM (memory-mapped I/O). By default, this is nothing new and not a bad design as it makes things easier for software and hardware developers. In previous versions of Windows CE and other OS all addresses where treated a normal memory and the only difference between RAM and I/O was to set the non-cache flag in the memory properties for I/O. For architectures up to Cortex-A8 this was enough to ensure a stable operation of a system.  In particular with Cortex-A9 speculative engines the legacy approach causes problems. While some speculative features of the cores can be disabled, speculative table walks (which implicitly do speculative loads) can’t be disabled – for Normal Memory. So with Cortex-A9 it is necessary to use the extended access permission features of the architecture and configure all I/O memory as device memory. Device memory amongst others has the no-execute flag set in its properties (XN flag), and the processor doesn’t touch it during speculative operations. Under heavy load and stress this becomes an issue as the processor does more speculative operations per time and the chance to touch I/Os grows. It was one of the main reasons for crashes and deadlocks.   For Windows CE, Microsoft introduced a new way for OEMs to report available memory to the kernel with Compact 7. However, since the issue described above is not an issue on x86 and older ARM architectures, the i.MX6 BSP inherited the old reporting style from its ancestors.   With the legacy memory reporting the OEM fills a memory mapping table with the information about available memory and provides that to the CE kernel during startup. The kernel then creates the initial MMU page table with a cached and a non-cached entry per memory block from the OEM. For the MMU everything is normal memory.   The new WEC7 model works with two tables, the old one for RAM and ROM, and a new one for I/Os (device table). All blocks in the device table are configured as device memory in the MMU and are protected then.   This sounds straight forward, but the devil is in the details. The new model changes the way BSP code can use address translation during the early boot phase. Functionality in the startup code and the KITL component had to be updated in order to work with the new model and allow parameter transfer from boot loader code to OAL code. It is also not well documented and required kernel code reviews and discussions with Microsoft kernel engineers to fine tune this part of the code and optimize it for i.MX6. Another issue was that internal SRAM of the i.MX6, which in the first place appears as part of the processor’s I/O space, and so ended up in the device table. However, the internal RAM is used in low power modes to run power-management code while external RAM is in self-refresh, so it has to be mapped as normal memory without the XN flag set. After all, it wasn’t a trivial piece of work. Synchronization Barriers   Due to the above listed enhancements in Cortex-A9 it is necessary to set synchronization points in the flow of operation at which the processor and all memory has a known state and is in sync. This is especially important when updating processor configuration or during context switches in the OS.   Through code reviews of OAL and kernel code and in discussions with Microsoft we updated the BSP to meet all ARM requirements and fine tune the interfaces between kernel and OAL to provide optimal performance. Errata   During the investigation we spent time on errata for the i.MX6 and its various IP blocks. BSP and kernel code where intensively reviewed for each erratum, if they are affected and a fix or workaround is necessary to be implemented.   As part of this we also looked at the all software implemented BSP for i.MX6 (by Freescale) and its change log to double-check that we didn’t miss anything.   Several critical errata were identified as missing in the code and implemented during the investigation. Three of the necessary code changes were in Microsoft kernel code and required a kernel update. Adeneo Embedded implemented these modifications in the kernel, tested the updated kernel in our test lab as well as with selected customers in the field, and then submitted the kernel change requests to Microsoft to formally release the update through the Windows Embedded Update mechanism. Cache Management   The i.MX6 implements the Cortex-A9 architecture with an internal L1 data and instruction cache and an external L2 unified cache. Internal L1 means the L1 RAM array is located inside the ARM MPCore IP block, and each Cortex-A9 core in the MP cluster has its own L1 cache. External L2 means the L2 RAM array is located outside the ARM MPCore IP block but inside the SoC and connected to the internal AXI bus. Both RAM arrays are not accessible through processor load/store instructions.   Cache memory allows the system to keep often used data in memory with faster access but this requires to synchronize cache memory and external SDRAM so that observers outside the processor-cache block can see data changes.   When configured as SMP cluster some of the necessary L1 maintenance is done by the hardware cache controller. Since we may have up to 4 cores each with its own L1 cache, and a multi-tasking operating system which may assign the same execution thread to different cores due to context switches, it is necessary that all cores have the same synchronized view of the memory. This is done in hardware through the coherency unit in the MPCore as long as single addresses are affected. If the L1 needs maintenance as a whole software has to handle it.   Software also has to handle all L2 cache maintenance operations.   Cache maintenance gets invoked by the kernel normally, but there are a few situations where device drivers or even application software has to request cache maintenance. In any case, the OAL gets these requests and executes them. All cache related code in the OAL was updated and redesigned to meet the ARM architecture requirements and collaborate with the kernel in an optimized way. Shortcomings Cortex-A9 support in the cache maintenance code and maintenance requests from drivers were another major source of instability in the initial BSP.   Some of the complications in this area are:     Optimize L1 code to take advantage of the available hardware support Maintenance requests that include L1 and L2 require a specific procedure to make sure all levels of memory are in sync Maintenance requests can come from multiple threads and CPUs in parallel – L2 code has to be reentrant and multi-core safe DMA controllers work with physical addresses and do not know about caches; when DMA operations are used drivers have to make sure to request the necessary cache maintenance. Some instability with USB, SD and video operations were related to bugs in this area.    Build and Testing   As we learned at the beginning of this investigation that the CTK BSP testing failed to identify these issues we also reviewed our testing approach and implemented improved procedures. A new component in our testing is the stability lab, where we provide a dedicated set of hardware together with IT infrastructure to automate tasks and log results. With approval from our key customers we transferred customer test applications and applications that helped reproducing the issues into more generic test applications and added them to our portfolio.   Another lesson learned is that knowledge of customer use cases is important. We restructured our testing to be closer to real world scenarios and integrate feedback from customers directly.   A number of times during the investigation concerns were raised that the build process or the tools may be the root cause for some issues. Test teams reported different results based on where and how an OS image was built. We analyzed the tool installation and update process and the process to install OS bug fixes from Microsoft, but conclusion was that these observations were red herrings. But we used the knowledge gained from this part of the investigation to improve the build lab in Adeneo Embedded. We enhanced our infrastructure and upgraded tools so that it is easier for us to switch between versions and QFE levels of Windows Embedded Compact and our BSPs. Commitment   This investigation was done over a period of about 8 months, and Adeneo Embedded put a committed effort into it to solve the problems. A core team of engineers worked fulltime on it while an extended group of engineers was available to support where needed (test, build, debugging, applications,..). The problems we had to solve here were not trivial; at times it was like a wild roller coaster ride.   But as a result we have a Freescale i.MX6 Windows Embedded Compact board support package by Adeneo Embedded with significantly improved quality and optimized for this system-on-chip. This brings out the benefits to all customers running Windows Embedded Compact i.MX6 and future CPU architectures on similar ARM cores on WEC7 and WEC2013. For more information email the Adeneo Embedded Support Team at sales@adeneo-embedded.com or visit our website at http://www.adeneo-embedded.com/

NXP i.MX7 processors, 1GHz Up to 2GB DDR3 and 32GB on-board eMMC LVDS, MIPI-DSI, Parallel RGB, up to 1920 x 1080 PCIe, 2x GbE, 5x USB2, 7x UART, 2x CAN, 124x GPIO Dual-band 802.11a/b/g/n WiFi and Bluetooth 4.1 BLE Yocto and Debian Linux, RTOS CL-SOM-iMX7 is a tiny System-on-Module (SoM) / Computer-on-Module (CoM) board designed to serve as a building block in embedded applications.   CL-SOM-iMX7 is built around the Freescale i.MX7 System-on-Chip featuring an advanced ARM Cortex-A7 CPU coupled with a dedicated real-time ARM Cortex-M4 MCU. The SoC is supplemented with up-to 2GB DDR3 and 32GB of on-board SLC NAND or eMMC storage.   Featuring a wide range of embedded interfaces, CL-SOM-iMX7 is a versatile platform for industrial automation and control systems. Dual Gbit Ethernet, 2x2 MIMO dual-band 802.11a/b/g/n WiFi and Bluetooth 4.1 make CL-SOM-iMX7 an excellent solution for networking, communications and IoT applications.   Low price makes CL-SOM-iMX7 an ideal selection for cost-sensitive systems, while its miniature size and low power consumption enable integration into portable and space-constrained designs.   CL-SOM-iMX7 is provided with a full Board Support Package and ready-to-run images for the Linux operating system. The CL-SOM-iMX7 BSP includes Linux kernel 3.14, Yocto Project file-system and U-Boot boot-loader. In addition, CompuLab will support CL-SOM-iMX7 with mainline Linux and upstream Yocto Project.   CL-SOM-iMX7 Detailed Spec CL-SOM-iMX7 Block Diagram CL-SOM-iMX7 Development Kit CL-SOM-iMX7 Online Pricing

New Taipei City, 27.Oktober 2015 – TechNexion announces PICO-i.MX6UL System-on-Module for Google Brillo OS Googles OS Brillo is a lightweight embedded OS, based on Android that is open, extensible, secure and applicable to a variety of devices. Brillo’ comes with ‘Weave’ Googles communication API, which easily allows ‘Brillo’ devices to communicate and exchange with each other or store data in the cloud. TechNexion provides with the PICO-IMX6UL System-on-Module (SoM) the fitting hardware for this new operating system. The PICO Module is equipped with a Freescale i.MX6 UltraLite Processor (Cortex-A7 Core) and is a very compact, ubiquitous computing, high performance SoM that are highly optimized for mobile Internet of Things applications. Connectivity is given by Gigabit Ethernet, WiFi (802.11ac) and Bluetooth 4.0. Memory ranges from 256MB over 512MB to 1GB DDR3 Available with on-board eMMC Memory (default 4GB, others available on request) or SD-Card Slot. Using a pin-compatible scale-able platform that not only utilizes the “Edison” connector connectivity for sensors and low-speed I/O, but also adds additional expansion possibilities for multimedia and connectivity. Additionally the “DWARF” platform eases proto-typing and accelerates time to market by offering a complete platform; introducing a large number of ready to use sensors like 3d-Accelerator, Gyroscope or Altitude-meter and available I/O’s to take advantage of todays’ technology and communication challenges, giving our customers’ cutting edge technology that can easily be expanded and implemented into Industry 4.0 applications. The schematics are freely available for the DWARF Carrier board. TechNexion’s Brillo Page is here: http://technexion.com/solutions/brillo The Freescale announcement is here: http://blogs.freescale.com/processors/2015/10/freescale-joins-google-in-enabling-brillo-access-to-the-developer-community/ And for more information you can find the Google announcement here: http://googledevelopers.blogspot.tw/2015/10/building-brillo-iant-devices-with-weave_27.html

Here is a video that shows the NFC feature integrated into our Android Lollipop 5.0.0 code base. It is running on our Nitrogen6x platform along with the NXP PN7120 development kit. The video shows that a NFC tag, programmed with Boundary's URL, is automatically read and starts the Browser accordingly. In order to read/write data from a NFC data, Android provides a fully documented API. If you seek an existing application to write tags, here are a couple of options: NXP TagWriter app StickyNotes sample code For more information, please visit http://boundarydevices.com/

Measuring 60mm by 49mm, the MYC-C8MMX CPU Module is a high-performance and cost-effective ARM SoM powered by i.MX 8M Mini which is NXP's first embedded multi-core heterogeneous applications processors built using advanced 14LPC FinFET process technology. The MYC-C8MMX CPU Module provides an outstanding embedded solution for Home and Building Control, IOV, Industrial and Medical Instruments, Human Machine Interface (HMI) and more other general purpose industrial and IoT applications which require optimized power consumption while maintaining high-performance. It is a minimum system integrated with CPU, 2GB DDR4, 8GB eMMC, 32MB QSPI Flash, GigE PHY and PMIC. All controller signals are brought out through two 0.8mm pitch 100-pin Expansion Connectors. It is capable of running Linux and Android OS and provided with plenty of software resources.                         MYC-C8MMX CPU Module Top-view                                         MYC-C8MMX CPU Module Bottom-view   MYIR offers MYD-C8MMX development board for evaluating the MYC-C8MMX CPU Module, the base board has taken great media capabilities of the i.MX 8M Mini processor to provide MIPI-DSI, MIPI-CSI, LVDS interfaces and Audio In/Out ports. It also has strong communication connectivity with 2 x USB 2.0 Host ports and 1 x Micro USB 2.0 Host/Device port, Gigabit Ethernet, MicroSD card slot, USB based Mini PCIe interface for 4G LTE Module, WiFi/Bluetooth and NVMe PCIe M.2 2280 SSD Interface. MYIR can offer design services to help customize the base board according to customers’ requirements.                                                    MYD-C8MMX Development Board Top-view                                                     MYD-C8MMX Development Board Bottom-view   MYIR offers commercial and industrial grades options for CPU Modules. More information can be found at: http://www.myirtech.com/list.asp?id=617

The MYC-C8MMX CPU Moduleis designed by MYIR, which is an ARM embedded System-on-Module (SoM) based on NXP’ i.MX 8M Mini Quad Application Processor. The MYD-C8MMX development board is built around the MYC-C8MMX CPU Module, it is a complete evaluation module for your prototype and reference design. It is capable of running Linux and Android OS and provided with plenty of software resources. Typical applications are for Industry Control, Smart City, Smart Home, HMI, Internet of Things (IoT), etc. Let’s see a video introduction of the MYD-C8MMX development board. https://youtu.be/FL_CZiSMYsM The MYC-C8MMX CPU Moduleis using the MIMX8MM6CVTKZAA (MIMX8MM6DVTLZAA) processor chip which is among the NXP i.MX 8M Mini family and combines advanced 14LPC FinFET process technology to provide more speed and improved power efficiency. It has a quad Cortex-A53 core which operates at speeds of up to 1.6 (1.8) GHz. It also has a general-purpose Cortex-M4 400 MHz core processor for low-power processing. Some parameters and target applications of the processor chip are listed below for reference. Parameter Value Core: Number of cores (SPEC) 4 Core Type Arm Cortex-A53 Operating Frequency [Max] (MHz) 1600 (MIMX8MM6CVTKZAA)/1800 (MIMX8MM6DVTLZAA) L2 Cache (Max) (KB) 512 Co-Processor Type Arm Cortex-M4F Co-Processor Frequency (MAX) (MHz) 400 External Memory Supported DDR3L SDRAM, DDR4 SDRAM, ECC, LPDDR4 DRAM, NAND FLASH, NOR FLASH, QSPI GPU 2D / GPU 3D 1x shader, Vivante GC320, Vivante GCNanoUltra MIMX8MM6CVTKZAA (MIMX8MM6DVTLZAA) processor The chip only has MIPI-DSI and MIPI-CSI interfaces and no HDMI or other display interfaces. It can support wide working temperature range from -40 to 105 Celsius degree. MYIR’s MYC-C8MMX CPU Module can support working temperature from -40 to 85 Celsius degree. Parameter Value HW Video Encoder / Decoder HD1080p60 H.264, HD1080p60 H.265 Video/Display features MIPI-CSI, MIPI-DSI PCIe PCIe 2.0 x 1 Audio Specific Modules 8-ch PDM input, SAI USB Controllers 2 Serial Communication 1 x PCIe 2.0,3 x SPI,4 x I²C,4 x UART Junction Temperature (℃) -40 to 105 (MIMX8MM6CVTKZAA), 0 to 95 (MIMX8MM6DVTLZAA) MIMX8MM6CVTKZAA (MIMX8MM6DVTLZAA) processor Target Applications of i.MX 8M Mini Processors Automotive Smart City Heating Ventilation, and Air Conditioning (HVAC) Automatic Vehicle Identification Motorcycle Engine Control Unit (ECU) and Small Engine Control Fleet Management 　 Inventory and Supply Chain Management Industrial Public Address Systems Air Conditioning (AC) Transport Ticketing Building Safety 　 Building Security Smart Home Digital Signage Audio/Video (AV) Receivers Energy Gateway Gaming Console Heat Metering Home Control Panel Hospital Admission Machine Home Security & Surveillance Image Analytics Home Sensor Industrial Control In-Home Energy Display Industrial HMI Major Home Appliances Machine Visual Inspection Robotic Appliance Smart Lighting Set Top Boxes Smart Power Socket and Light Switch Small and Medium Appliances Two-way Video Conferencing Smart Speaker Vision, Advanced Sensing and Processing Board Soundbar 　 Surround Sound and Sound Bars Mobile Wireless or Networked Speakers Cable 　 Hearables Technologies Input Device (Mouse, Pen, Keyboard) Voice Assistants Smart Watch Voice Control Wireless Charging Pad 　 Wristband 　 The MYC-C8MMX CPU Module is a minimum system with PMIC, CPU, RAM (DDR4), Flash (eMMC, SPI Flash) and clock, plus an Ethernet PHY chip. A number of peripheral and IO signals are access through two 0.8mm pitch 100-pin board-to-board expansion connectors.                           MYC-C8MMX CPU Module Top-view                                         MYC-C8MMX CPU Module Bottom-view The MYD-C8MMX base board has mainly extended four parts: 1. Audio interface: added audio chip to extend Audio input and output interfaces 2. External power supply part: added one DC-DC power chip 3. Added one USB hub chip to extend 4 USB from the SoC USB interface, separately used for 4G LTE, two USB Host and one USB on expansion header. 4. Extend RTC module through I2C interface Many other peripheral interfaces are brought out for user extension.                                                    MYD-C8MMX Function Block Diagram                                                            MYD-C8MMX Interface Diagram Among so many interfaces, Backlight, LVDS LCD and MIPI interface are relative to display function. The Backlight interface has 6 pins including two power signals, two GND and two GPIO (one is enabled terminal to control the backlight power and another is PWM to control the brightness of backlight.) The two GPIO control terminals are from the GPIO1_01 and 08 of the i.MX 8M Mini. The LVDS LCD and MIPI interface, total 3 interfaces are for display. But actually i.MX 8M Mini only has one MIPI DSI interface. The other two LVDS interfaces are switched from DSI through one DS12LVDS bridge chip, one is single link LVDS and another is dual link LVDS. So, we can only select MIPI DSI display or LVDS display. Also, we can only select single link LVDS or dual link LVDS. MYIR offers optional LVDS based 7-inch LCD Module MY-LVDS070C including capacitive touch screen to work with the MYD-C8MMX board. The display resolution is up to 1024 by 600 pixels.                            MY-LVDS070C 7-inch LCD Module with Capacitive Touch Screen The MYD-C8MMX has one 2.0mm pitch 2*15-pin male expansion header. PDM and SAI are audio relative interfaces which are brought out from the expansion header.

This is a demo of the Nitrogen6X with BD_HDMI_MIPI daughter board. The Nitrogen6X is an i.MX6-based Single Board Computer (SBC) designed for both development and production use.  The BD_HDMI_MIPI daughter board utilizes the Toshiba TC358743XBG HDMI to MIPI CSI part to convert the HDMI signals to MIPI. The BD_HDMI_MIPI can be used with our Nitrogen6X, BD-SL-i.MX6, Nitrogen6_MAX boards as well as the Nitrogen6X_Carrier.  The daughter board can be used for evaluation as well as software development.  Please contact Boundary Devices for custom version. This demo shows the Nitrogen6X running Yocto based on 3.10.17 kernel and displaying the output of our Nitrogen6X_SOM on a 10.1" LG BD101LIC1 display.

NXP i.MX7 CPU, dual-core Cortex-A7 1GHz Up to 2GB DDR3 and 32GB eMMC 3G/LTE modem, WiFi 802.11a/b/g/n, BT 4.1 2x 1000Mbps Ethernet, 4x USB2, RS485, RS232 Support for PoE powered mode Fanless design in aluminum, rugged housing Miniature size – 10.8 x 8.3 x 2.4 cm Designed for reliability and 24/7 operation Wide temperature range of -40C to 85C Mainline Linux kernel and full Linux BPS IOT-GATE-iMX7 is built around the NXP i.MX7 System-on-Chip featuring an advanced ARM Cortex-A7 CPU coupled with a dedicated real-time ARM Cortex-M4 MCU. The SoC is supplemented with up-to 2GB DDR3 and 32GB of on-board eMMC storage.   Featuring a wide range of embedded interfaces, IOT-GATE-iMX7 is a versatile platform for industrial automation and control systems. Dual Gbit Ethernet, 3G/LTE modem, dual-band 802.11a/b/g/n WiFi and Bluetooth 4.1 make IOT-GATE-iMX7 an excellent solution for networking, communications and IoT applications.   IOT-GATE-iMX7 is provided with a full Board Support Package and ready-to-run images for the Linux operating system. The IOT-GATE-iMX7 BSP includes Linux kernel 4.1.15, Yocto Project file-system and U-Boot boot-loader. In addition, CompuLab will support IOT-GATE-iMX7 with mainline Linux and upstream Yocto Project. IOT-GATE-iMX7 spec IOT-GATE-iMX7 evaluation kit IOT-GATE-iMX7 pricing

This webtalk session provides an overview of the new ConnectCore 6 multichip module. The industry’s first SMT multichip module built on the Freescale i.MX6 application processor family. Offering pre-certified and fully integrated wireless connectivity options such as 802.11a/b/g/n and Bluetooth 4.0 plus unique system capabilities such as an independent Kinetis K/L on-module subsystem, built for reliability and long-term availability. The module targets applications in healthcare/medical, transportation, industrial and other markets. Visit the link below to view the webtalk video now: http://www.embedded-know-how.com/boards-a-modules-main/article/45-boards-modules/1699

The Nitrogen6X is a highly integrated development system based on the next generation ARM-Cortex A9 processor from Freescale, the i.MX6. Click here to visit Boundary Devices for full details   See Compatible Products Tab for: 7″ Display SATA Cable 5MP Camera Android Button Board WiFi ADD-ON LVDS Cable for Freescale 10.1″ PCIE DB Available through Arrow Electronics. Cost will be $199 in Production for non-WiFi (October 2012)  

iWave Systems has made Windows Embedded Compact 7 (WEC7) available for Freescale’s i.MX6 SABRE SDP/SDB. All the latest features that WEC7 offers such as Silverlight 3.0, MPEG-4 HD, Expression Blend, Active Sync and also Adobe Flash10.1 are made available on this platform. The WEC7 BSP release supports SATA 3.0, Standard SD, Gigabit Ethernet, LVDS, Touch Panel, HDMI port and also necessary hardware codecs supported by the CPU. Debugging tools like KITL and CETK are also supported.

This the document for SUSPEND and WAKE-UP in IMX8QM-MEK platform Wake up done by following, M4  debug UART A53 debug UART Power Key Source: imx-p9.0.0_2.1.1-auto-ga CONFIGURATION          Disable the default wake-up - RTC Timer (Patch - Disable_auto_wakeup.diff) SUSPEND      1. Command  Line,             # echo mem > /sys/power/state      2. Dumpsys Command                  # dumpsys activity service com.android.car inject-vhal-event 0x11410a00 4,2 WAKE-UP     1. BUTTON          By pressing the power-key SW3 (0.5s)      2. DEBUG UART          Enable debug UART wake-up          # cat ./sys/devices/platform/5a060000.serial/tty/ttyLP0/power/wakeup          disabled          # echo enabled  > ./sys/devices/platform/5a060000.serial/tty/ttyLP0/power/wakeup          TO WAKEUP                   Press the ENTER Key 2 times 3. M4 UART WAKEUP                        Apply the RPMSG patch (L4.14.98.diff)                                        # cat./sys/devices/platform/5a070000.serial/tty/ttyLP1/power/wakeup          disabled          # echo enabled > ./sys/devices/platform/5a070000.serial/tty/ttyLP1/power/wakeup Type some input in M4 Cosole               

NXP i.MX8M-Mini CPU, quad-core Cortex-A53 Up-to 4GB RAM and 128GB eMMC LTE modem, WiFi 802.11ac, Bluetooth 5.0 2x Ethernet, 3x USB2, RS485/RS232, CAN-FD Custom I/O expansion boards Fanless design in aluminum, rugged housing Designed for reliability and 24/7 operation Wide temperature range of -40C to 80C Wide input voltage range of 8V to 36V Debian Linux, Yocto Project and mainline kernel Support for Docker and Microsoft Azure IoT   IOT-GATE-iMX8 is built around the NXP i.MX8M Mini System-on-Chip, featuring an advanced ARM Cortex-A53 CPU. The SoC is supplemented with up-to 4GB LPDDR4 and 128GB of eMMC storage.   Featuring dual Ethernet, CAN-FD, LTE modem, 802.11ac WiFi and Bluetooth 5.0, IOT-GATE-iMX8 is a highly versatile platform for industrial control, networking, communications and IoT applications. Fanless rugged enclosure design, wide range DC input of 8V to 36V and industrial temperature range of -40C to 80C make IOT-GATE-iMX8 an ideal solution for industrial installations and harsh environments.  IOT-GATE-iMX8 is provided with ready-to-run Debian Linux and full Linux Board Support Package. IOT-GATE Linux packages support Docker and Microsoft Azure IoT.   IOT-GATE-iMX8 spec IOT-GATE-iMX8 evaluation kit IOT-GATE-iMX8 pricing

NXP i.MX8M processor family, 1.5GHz Up to 4GB LPDDR4 and 64GB eMMC HDMI 2.0a, LVDS, MIPI-DSI, up to 4096 x 2160 Gbit Ethernet, WiFi 802.11a/b/g/n/ac, BT 4.1 2x PCIe, 2x USB3.0, 4x UART, 90x GPIO Industrial temperature range of -40C to 85C Yocto Linux and Android CompuLab's CL-SOM-iMX8 is a miniature System-on-Module board designed for integration into industrial embedded applications. CL-SOM-iMX8 is built around the new NXP i.MX8M System-on-Chip featuring a quad-core ARM Cortex-A53 CPU coupled with a powerful Vivante GC7000Lite GPU. The SoC is supplemented with up-to 4GB of LPDDR4 and 64GB of on-board eMMC storage. Designed to bring out the full capabilities of the i.MX8M SoC, CL-SOM-iMX8 provides Gbit Ethernet, PCIe, 2 USB3.0 ports, 4 UARTs and up-to 90 GPIOs. Display connectivity is supported with HDMI2.0, LVDS and MIPI-DSI interfaces with resolutions of up-to 4096 x 2160. In addition, CL-SOM-iMX8 features on-board WiFi 802.11ac and Bluetooth 4.1. CL-SOM-iMX8 is provided with full BSPs and ready-to-run images for Linux and Android operating system. CL-SOM-iMX8 BSP includes Linux kernel 4.9, Yocto Project file-system, Android 8.0 and U-Boot boot-loader. CL-SOM-iMX8 Detailed Spec CL-SOM-iMX8 Development Kit CL-SOM-iMX8 Online Pricing

The DA9063 from Dialog Semiconductors is a powerful system PMIC for the next generation of single, dual and quad-core application processors based on the ARM Cortex™ A9 and A15 architecture. The PMIC follows a scalable approach of output currents and rails to supply the entire system and is capable of delivering a total of up to 12A from its six DC-DC converters. The DA9063 simultaneously powers the processor (the core at up to 5A), external memory, wireless communications (WLAN and Bluetooth), GPS and FM receivers, and data modems.  The DC-DC converters can be paralleled to provide 3A and 5A rails. Description: DA9063 is a high current system PMIC suitable for Single, Dual and Quad-core processors used in smartphones, tablets and other handhelds applications that require up to a 5A core processor supply. There are multiple operating modes, five consuming <20μA including a 1.5μA RTC mode with alarm & wake up. A system monitor watchdog is enabled in Active mode. DA9063 contains 6x DC-DC Buck converters designed to use small external 1µH inductors capable of supplying in total up to 12A continuous output (0.3-3.3V). 11x SmartMirror™ programmable LDO regulators rated up to 300mA. All support remote capacitor placement and operate from low 1.5/1.8V input supply; this allows the linear regulators to be cascaded with a suitable buck supply to improve overall system efficiency. A number of LDOs can be configured as current limited bypass-switches to support external peripherals such as external accessory or memory cards. The Buck converters do not require external Schottky diodes, they dynamically optimise their efficiency depending on the load current using an Automatic Sleep Mode (ASM). They incorporate pin and s/w controlled Dynamic Voltage Control (DVC) to support processor load adaptive adjustment of the supply voltage. Processor core leakage reduction can be achieved using external FET switches driven by the rail switch controllers for ultra-fast power domain switching. The DA9063 provides a startup sequencing engine that offers autonomous hardware and software controlled system start-up. Customisable power modes  can also be configured using “Power Commander,” Dialog’s powerful graphical user interface. The ON-key feature detects the button press time and offers configurable key-lock and application shut-down functions. Up to 16 free configurable GPIO pins are able to perform system functions including keypad supervision, application wake-up and timing controlled enable of external regulators/power switches or other ICs. A 10-bit ADC supports voltage and temperature supervision from general purpose inputs including automatic interrupt from comparators and resistor measurement.  Three RGB-LED driver pins are provided with PWM control. LDO8 may be configured as a 6-bit PWM controlled vibration motor driver with automatic battery voltage correction. Features Input supply voltage range up to 5.5v 6 DC-DC Buck Converters with Dynamic Voltage control 2.5A  Buck 2.5A  Buck 2.5A  Buck 1.5A  Buck 1.5A  Buck 1.5A  Buck 3MHz Switching Frequency Enables use of  1.0mm high inductors Integrated Power Switches 11 LDO Regulators with programmable Output 3 low noise LDOs 4 with Dynamic Voltage Control 5 with current limited Switch option Fast controller for 2 Rail Switches Ultra low power 1.5µA Real-Time Clock with alarm, oscillator circuitry with crystal frequency adjustment and controlled signal provision Power Manager with programmable Start-up of internal and external regulators/rail switches and configurable low power modes Support of multiple master applications via two independent Control Interfaces System Monitor including Watchdog Timer Up to 16 free configurable GPIO Pins enable system control from DA9063 while the application is in standby RGB-LED driver (PWM) with autonomous flashing PWM vibration motor driver 10-Bit ADC with 9 Channels and configurable alarm thresholds Regulator Supervision with automatic under and over voltage protection Coin Cell/Super-Capacitor Backup Charger      -40 to +85°C Temperature range 100VFBGA 8.0x8.0x1.0mm (0.8mm pitch) package Block Diagram DA9063: For more information: http://www.dialog-semiconductor.com/products/power-management/DA9063

Hi, RAW is still often used in automotive applications. If you are doing bare metal code and if you use OS (QNX, GreenHills integrity), it is often a pain to boot from NAND. On SABRE AI, you have a NAND socket, this document will present you the basics command to reverse engineer the NAND boot setup of a SABRE AI. KOBS-NG What you can do first is understand kobs-ng application, and try to understand it...sources are available on freescale's GIT: http://sw-git.freescale.net/cgi-bin/gitweb.cgi?p=linux-kobs.git;a=summary Anyway, the sequencing is not obvious... Modified MFGtool (see enclosed archive) What you can do also it to program a NAND flash on a SABRE board for instance and read back the NAND flash. First configure your SABRE AI board: S2: 0001 S1: 0001100000  (I use 8 BBT and FCB to be more secure) BOOT_MODE: 0010 (if your NAND flash is not already programmed, otherwise 0100) Copy my mfgtool (Works only with i.MX6 Solo part), and unzip it. Plug  a micro USB cable and a RS232 cable, configure your hyperterminal as usual. Launch mfgtool and press start: Wait the end of programmation: Note: I did modify ucl2.xml file to have 8 BBT and FCB (see S1 configuration above, and "--search_exponent=3" --> 2^3=8 instead of default 2^2=4 ) and I did add the "-v" option in ucl2.xml file to have the verbose mode (thus memory addresses of FCB, BBT and more are displayed) ---> you have to go on the extreme right of the lines below... depending of the witdth of your screen): <!--burn the uboot to NAND: -->    <CMD   state = "Updater"   type = "push"   body = "send"   file = "files/u-boot-mx6solo-sabreauto-nand.bin" > Sending U-Boot </CMD>   <CMD   state = "Updater"   type = "push"   body = "$ kobs-ng init -v --search_exponent=3 --chip_0_device_path=/dev/mtd0 $FILE" > Flashing Bootloader </CMD> ‍‍‍‍‍‍‍‍‍‍‍ Set BOOT_MODE switches: 0010 and press reset. After u-boot startup press a key in the terminal to stop execution. Now you can explore your NAND! have a look in the enclosed "mx6Solo_RAW_NAND_SABRE_AI_programming_verbose.txt" file, you have all the adressses of BBT, FCB, etc...: Firmware: image #0 @ 0x400000 size 0x2a000 - available 0x600000 Firmware: image #1 @ 0xa00000 size 0x2a000 - available 0x600000 -------------- Start to write the [ FCB ] ----- mtd: erasing @0:0x0-0x80000 mtd: Writing FCB0 [ @0:0x0 ] (10e0) * mtd: Writing FCB1 [ @0:0x40000 ] (10e0) * mtd: erasing @0:0x80000-0x100000 mtd: Writing FCB2 [ @0:0x80000 ] (10e0) * mtd: Writing FCB3 [ @0:0xc0000 ] (10e0) * mtd: erasing @0:0x100000-0x180000 mtd: Writing FCB4 [ @0:0x100000 ] (10e0) * mtd: Writing FCB5 [ @0:0x140000 ] (10e0) * mtd: erasing @0:0x180000-0x200000 mtd: Writing FCB6 [ @0:0x180000 ] (10e0) * mtd: Writing FCB7 [ @0:0x1c0000 ] (10e0) * mtd_commit_bcb(FCB): status 0   -------------- Start to write the [ DBBT ] ----- mtd: erasing @0:0x200000-0x280000 mtd: Writing DBBT0 [ @0:0x200000 ] (1000) * mtd: Writing DBBT1 [ @0:0x240000 ] (1000) * mtd: erasing @0:0x280000-0x300000 mtd: Writing DBBT2 [ @0:0x280000 ] (1000) * mtd: Writing DBBT3 [ @0:0x2c0000 ] (1000) * mtd: erasing @0:0x300000-0x380000 mtd: Writing DBBT4 [ @0:0x300000 ] (1000) * mtd: Writing DBBT5 [ @0:0x340000 ] (1000) * mtd: erasing @0:0x380000-0x400000 mtd: Writing DBBT6 [ @0:0x380000 ] (1000) * mtd: Writing DBBT7 [ @0:0x3c0000 ] (1000) * mtd_commit_bcb(DBBT): status 0‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ to read the NAND, I read it in internal OCRAM ( address is 0x918000 for i.MX6DL and Solo) and then I display it): You can read the DCD of one of the boot image (first one is at address 0x400000 as you can see in the enclosed text file): Firmware: image #0 @ 0x400000 size 0x2a000 - available 0x600000 Firmware: image #1 @ 0xa00000 size 0x2a000 - available 0x600000‍‍‍‍‍‍ So, let's read the begenning of the image... at offset 0x400, you'll see the barker code of the DCD: 0x402000D1: MX6SOLO SABREAUTO U-Boot > nand read 0x918000 0x400000 0x800 NAND read: device 0 offset 0x400000, size 0x800 2048 bytes read: OK MX6SOLO SABREAUTO U-Boot > md 0x918000 0x500 00918000: ea000186 00000000 00000000 00000000 ................ 00918010: 00000000 00000000 00000000 00000000 ................ 00918020: 00000000 00000000 00000000 00000000 ................ 00918030: 00000000 00000000 00000000 00000000 ................ 00918040: 00000000 00000000 00000000 00000000 ................ 00918050: 00000000 00000000 00000000 00000000 ................ 00918060: 00000000 00000000 00000000 00000000 ................ 00918070: 00000000 00000000 00000000 00000000 ................ 00918080: 00000000 00000000 00000000 00000000 ................ 00918090: 00000000 00000000 00000000 00000000 ................ 009180a0: 00000000 00000000 00000000 00000000 ................ 009180b0: 00000000 00000000 00000000 00000000 ................ 009180c0: 00000000 00000000 00000000 00000000 ................ 009180d0: 00000000 00000000 00000000 00000000 ................ 009180e0: 00000000 00000000 00000000 00000000 ................ 009180f0: 00000000 00000000 00000000 00000000 ................ 00918100: 00000000 00000000 00000000 00000000 ................ 00918110: 00000000 00000000 00000000 00000000 ................ 00918120: 00000000 00000000 00000000 00000000 ................ 00918130: 00000000 00000000 00000000 00000000 ................ 00918140: 00000000 00000000 00000000 00000000 ................ 00918150: 00000000 00000000 00000000 00000000 ................ 00918160: 00000000 00000000 00000000 00000000 ................ 00918170: 00000000 00000000 00000000 00000000 ................ 00918180: 00000000 00000000 00000000 00000000 ................ 00918190: 00000000 00000000 00000000 00000000 ................ 009181a0: 00000000 00000000 00000000 00000000 ................ 009181b0: 00000000 00000000 00000000 00000000 ................ 009181c0: 00000000 00000000 00000000 00000000 ................ 009181d0: 00000000 00000000 00000000 00000000 ................ 009181e0: 00000000 00000000 00000000 00000000 ................ 009181f0: 00000000 00000000 00000000 00000000 ................ 00918200: 00000000 00000000 00000000 00000000 ................ 00918210: 00000000 00000000 00000000 00000000 ................ 00918220: 00000000 00000000 00000000 00000000 ................ 00918230: 00000000 00000000 00000000 00000000 ................ 00918240: 00000000 00000000 00000000 00000000 ................ 00918250: 00000000 00000000 00000000 00000000 ................ 00918260: 00000000 00000000 00000000 00000000 ................ 00918270: 00000000 00000000 00000000 00000000 ................ 00918280: 00000000 00000000 00000000 00000000 ................ 00918290: 00000000 00000000 00000000 00000000 ................ 009182a0: 00000000 00000000 00000000 00000000 ................ 009182b0: 00000000 00000000 00000000 00000000 ................ 009182c0: 00000000 00000000 00000000 00000000 ................ 009182d0: 00000000 00000000 00000000 00000000 ................ 009182e0: 00000000 00000000 00000000 00000000 ................ 009182f0: 00000000 00000000 00000000 00000000 ................ 00918300: 00000000 00000000 00000000 00000000 ................ 00918310: 00000000 00000000 00000000 00000000 ................ 00918320: 00000000 00000000 00000000 00000000 ................ 00918330: 00000000 00000000 00000000 00000000 ................ 00918340: 00000000 00000000 00000000 00000000 ................ 00918350: 00000000 00000000 00000000 00000000 ................ 00918360: 00000000 00000000 00000000 00000000 ................ 00918370: 00000000 00000000 00000000 00000000 ................ 00918380: 00000000 00000000 00000000 00000000 ................ 00918390: 00000000 00000000 00000000 00000000 ................ 009183a0: 00000000 00000000 00000000 00000000 ................ 009183b0: 00000000 00000000 00000000 00000000 ................ 009183c0: 00000000 00000000 00000000 00000000 ................ 009183d0: 00000000 00000000 00000000 00000000 ................ 009183e0: 00000000 00000000 00000000 00000000 ................ 009183f0: 00000000 00000000 00000000 00000000 ................ 00918400: 402000d1 27800620 00000000 2780042c .. @ ..'....,..' 00918410: 27800420 27800400 00000000 00000000 ..'...'........ 00918420: 27800000 0002a0a4 00000000 40e001d2 ...'...........@ 00918430: 04dc01cc 74070e02 00000c00 54070e02 .......t.......T 00918440: 00000000 ac040e02 30000000 b0040e02 ...........0.... 00918450: 30000000 64040e02 30000000 90040e02 ...0...d...0.... 00918460: 30000000 4c070e02 30000000 94040e02 ...0...L...0.... 00918470: 30000000 a0040e02 00000000 b4040e02 ...0............ 00918480: 30000000 b8040e02 30000000 6c070e02 ...0.......0...l 00918490: 30000000 50070e02 00000200 bc040e02 ...0...P........ 009184a0: 28000000 c0040e02 28000000 c4040e02 ...(.......(.... 009184b0: 28000000 c8040e02 28000000 60070e02 ...(.......(...` 009184c0: 00000200 64070e02 28000000 70070e02 .......d...(...p 009184d0: 28000000 78070e02 28000000 7c070e02 ...(...x...(...| 009184e0: 28000000 70040e02 28000000 74040e02 ...(...p...(...t 009184f0: 28000000 78040e02 28000000 7c040e02 ...(...x...(...| 00918500: 28000000 00081b02 030039a1 0c081b02 ...(.....9...... 00918510: 1f001f00 10081b02 1f001f00 3c081b02 ...............< 00918520: 16021c42 40081b02 7a017b01 48081b02 B......@.{.z...H 00918530: 4c4e4a4b 50081b02 34333f3f 1c081b02 KJNL...P??34.... 00918540: 33333333 20081b02 33333333 24081b02 3333... 3333...$ 00918550: 33333333 28081b02 33333333 b8081b02 3333...(3333.... 00918560: 00080000 04001b02 25000200 08001b02 ...........%.... 00918570: 30303300 0c001b02 13536b67 10001b02 .300....gkS..... 00918580: 638b6eb6 14001b02 db00ff01 18001b02 .n.c............ 00918590: 40170000 1c001b02 00800000 2c001b02 ...@..........., 009185a0: d2260000 30001b02 23106b00 40001b02 ..&....0.k.#...@ 009185b0: 27000000 00001b02 00001984 1c001b02 ...'............ 009185c0: 32800004 1c001b02 33800000 1c001b02 ...2.......3.... [ETC....] MX6SOLO SABREAUTO U-Boot >‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ Let's check the persistent bit (i.MX6S or DL) PERSIST_SECONDARY_BOOT, reflecting from which image you boot: MX6SOLO SABREAUTO U-Boot > md 0x20D8044 1 020d8044: 40000000    ...@ MX6SOLO SABREAUTO U-Boot >‍‍‍‍‍‍‍‍ Bit 30 is 0, meaning you boot from first image Let's erase one boot image to see it it still boot (you have 2 boot images) MX6SOLO SABREAUTO U-Boot > nand erase 0x400000 0x512 NAND erase: device 0 offset 0x400000, size 0x512 Warning: Erase size 0x00000512 smaller than one erase block 0x00080000 Erasing 0x00080000 instead Erasing at 0x400000 -- 100% complete. OK MX6SOLO SABREAUTO U-Boot >‍‍‍‍‍‍‍‍‍‍‍‍‍‍ Presss the reset button of your board to see if the board still start. If you read the PERSIST_SECONDARY_BOOT persistent bit, you'll see you boot from the second image as bit 30 is active: MX6SOLO SABREAUTO U-Boot > md 0x20D8044 1 020d8044: 40000000    ...@ MX6SOLO SABREAUTO U-Boot >‍‍‍‍‍‍‍‍ If you erase the second image (address 0xa00000, board will not boot as you only have 2 images). What you can do thenis read your FCB (flash configuration) with the following commands in u-boot prompt (sometimes the first read fails! so try again): WARNING: this was for a 2009 u-boot, in newer version (2016 for instance) you have to do a "nand dump" otherwise it will return an error (FAIL -74), see [Uboot] Nand read from offset xxx failed -74  MX6SOLO SABREAUTO U-Boot > nand read 0x918000 0x40000 0x800 NAND read: device 0 offset 0x40000, size 0x800 NAND read from offset 40000 failed -74 0 bytes read: ERROR MX6SOLO SABREAUTO U-Boot > nand read 0x918000 0x40000 0x800 NAND read: device 0 offset 0x40000, size 0x800 2048 bytes read: OK MX6SOLO SABREAUTO U-Boot > md 0x918000 0x100 00918000: fc000000 4346ffff 00002042 3c500100 ......FCB ....P< 00918010: 00000619 10000000 10e00000 00800000 ................ 00918020: 00000000 00000000 00000000 00080000 ................ 00918030: 02000000 02000000 00080000 000a0000 ................ 00918040: 00070000 00000000 00000000 00000000 ................ 00918050: 00000000 00000000 00000000 00000000 ................ 00918060: 00000000 00000000 04000000 0a000000 ................ 00918070: 002a0000 002a0000 02000000 0f400000 ..*...*.......@. 00918080: 00000000 10000000 00000000 00000000 ................ 00918090: 00000000 00000000 00000000 00000000 ................ 009180a0: 00000000 00000000 00000000 00000000 ................ 009180b0: 00000000 00000000 00000000 00000000 ................ 009180c0: 00000000 00000000 00000000 00000000 ................ 009180d0: 00000000 00000000 00000000 00000000 ................ 009180e0: 00000000 00000000 00000000 00000000 ................ 009180f0: 00000000 00000000 00000000 00000000 ................ 00918100: 00000000 00000000 00000000 00000000 ................ 00918110: 00000000 00000000 00000000 00000000 ................ 00918120: 00000000 00000000 00000000 00000000 ................ 00918130: 00000000 00000000 00000000 00000000 ................ 00918140: 00000000 00000000 00000000 00000000 ................ 00918150: 00000000 00000000 00000000 00000000 ................ 00918160: 00000000 00000000 00000000 00000000 ................ 00918170: 00000000 00000000 00000000 00000000 ................ 00918180: 00000000 00000000 00000000 00000000 ................ 00918190: 00000000 00000000 00000000 00000000 ................ 009181a0: 00000000 00000000 00000000 00000000 ................ 009181b0: 00000000 00000000 00000000 00000000 ................ 009181c0: 00000000 00000000 00000000 00000000 ................ 009181d0: 00000000 00000000 00000000 00000000 ................ 009181e0: 00000000 00000000 00000000 00000000 ................ 009181f0: 00000000 00000000 00000000 00000000 ................ 00918200: 00001a1c 0000000e 00000000 00000000 ................ 00918210: 00000000 00000019 00001600 00001600 ................ 00918220: 00000019 0000000f 00000019 00000000 ................ 00918230: 00000000 00000000 00000000 00000000 ................ 00918240: 00000000 00000000 00000000 00000000 ................ 00918250: 00001300 00000f00 00000008 00000008 ................ 00918260: 00001600 00000015 00000000 00001a00 ................ 00918270: 00000000 00000000 00000000 00000000 ................ 00918280: 00000000 00000000 00000000 00000000 ................ 00918290: 00000000 00000000 00000000 00000000 ................ 009182a0: 00000000 00000000 00000000 00000000 ................ 009182b0: 00000000 00000000 00000000 00000000 ................ 009182c0: 00000000 00000000 00000000 00000000 ................ 009182d0: 00000000 00000000 00000000 00000000 ................ 009182e0: 00000000 00000000 00000000 00000000 ................ 009182f0: 00000000 00000000 00000000 00000000 ................ 00918300: 00000000 00000000 00000000 00000000 ................ 00918310: 00000000 00000000 00000000 00000000 ................ 00918320: 00000000 00000000 00000000 00000000 ................ 00918330: 00000000 00000000 00000000 00000000 ................ 00918340: 00000000 00000000 00000000 00000000 ................ 00918350: 00000000 00000000 00000000 00000000 ................ 00918360: 00000000 00000000 00000000 00000000 ................ 00918370: 00000000 00000000 00000000 00000000 ................ 00918380: 00000000 00000000 00000000 00000000 ................ 00918390: 00000000 00000000 00000000 00000000 ................ 009183a0: 00000000 00000000 00000000 00000000 ................ 009183b0: 00000000 00000000 00000000 00000000 ................ 009183c0: 00000000 00000000 00000000 00000000 ................ 009183d0: 00000000 00000000 00000000 00000000 ................ 009183e0: 00000000 00000000 00000000 00000000 ................ 009183f0: 00000000 00000000 00000000 00000000 ................ MX6SOLO SABREAUTO U-Boot >‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ If you read the addresses 0x000000, 0x40000, 0x80000, 0xc0000, 0x100000, 0x140000 or 0x180000 or 0x1c0000 you'll have a copy of the FCB in OCRAM (internal RAM) and then read the OCRAM. You can now try that the replication is working. Thus try to erase FCBs (in my case, with Micron MT29F16G08ABABAWP the minimum I can erase is 2 FCBs due to sector size of 0x80000, check it on your side), for u-boot after 2009 use "nand dump", see https://community.nxp.com/message/885233  : MX6SOLO SABREAUTO U-Boot > nand erase 0x0 0x512 NAND erase: device 0 offset 0x0, size 0x512 Warning: Erase size 0x00000512 smaller than one erase block 0x00080000 Erasing 0x00080000 instead Erasing at 0x0 -- 100% complete. OK MX6SOLO SABREAUTO U-Boot > nand erase 0x80000 0x512 NAND erase: device 0 offset 0x80000, size 0x512 Warning: Erase size 0x00000512 smaller than one erase block 0x00080000 Erasing 0x00080000 instead Erasing at 0x80000 -- 100% complete. OK MX6SOLO SABREAUTO U-Boot > nand erase 0x100000 0x512 NAND erase: device 0 offset 0x100000, size 0x512 Warning: Erase size 0x00000512 smaller than one erase block 0x00080000 Erasing 0x00080000 instead Erasing at 0x100000 -- 100% complete. OK MX6SOLO SABREAUTO U-Boot >‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ You have erase 6 FCB. If you press reset, you normallystill can boot the device (checkswitch S1 is configured like that: 0001100000). You can also read the bad block table. In enclosed "mx6Solo_RAW_NAND_SABRE_AI_programming_verbose.txt" you have addresses of the DBBT: 0x200000, 0x240000, 0x280000, 0x2c0000, 0x300000, 0x340000, 0x380000 and 0x3c0000: -------------- Start to write the [ DBBT ] ----- mtd: erasing @0:0x200000-0x280000 mtd: Writing DBBT0 [ @0:0x200000 ] (1000) * mtd: Writing DBBT1 [ @0:0x240000 ] (1000) * mtd: erasing @0:0x280000-0x300000 mtd: Writing DBBT2 [ @0:0x280000 ] (1000) * mtd: Writing DBBT3 [ @0:0x2c0000 ] (1000) * mtd: erasing mtd: Writing DBBT4 [ @0:0x300000 ] (1000) * mtd: Writing DBBT5 [ @0:0x340000 ] (1000) * mtd: erasing @0:0x380000-0x400000 mtd: Writing DBBT6 [ @0:0x380000 ] (1000) * mtd: Writing DBBT7 [ @0:0x3c0000 ] (1000) * mtd_commit_bcb(DBBT): status 0‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ now read a DBBT in u-boot (as already mentionned, sometimes nand read failed, so try again!): MX6SOLO SABREAUTO U-Boot > nand read 0x918000 0x280000 0x800 NAND read: device 0 offset 0x280000, size 0x800 2048 bytes read: OK MX6SOLO SABREAUTO U-Boot > md 0x918000 0x80 00918000: 00000000 54424244 01000000 00000000 ....DBBT........ 00918010: 00000000 00000000 00000000 00000000 ................ 00918020: 00000000 00000000 00000000 00000000 ................ 00918030: 00000000 00000000 00000000 00000000 ................ 00918040: 00000000 00000000 00000000 00000000 ................ 00918050: 00000000 00000000 00000000 00000000 ................ 00918060: 00000000 00000000 00000000 00000000 ................ 00918070: 00000000 00000000 00000000 00000000 ................ 00918080: 00000000 00000000 00000000 00000000 ................ 00918090: 00000000 00000000 00000000 00000000 ................ 009180a0: 00000000 00000000 00000000 00000000 ................ 009180b0: 00000000 00000000 00000000 00000000 ................ 009180c0: 00000000 00000000 00000000 00000000 ................ 009180d0: 00000000 00000000 00000000 00000000 ................ 009180e0: 00000000 00000000 00000000 00000000 ................ 009180f0: 00000000 00000000 00000000 00000000 ................ 00918100: 00000000 00000000 00000000 00000000 ................ 00918110: 00000000 00000000 00000000 00000000 ................ 00918120: 00000000 00000000 00000000 00000000 ................ 00918130: 00000000 00000000 00000000 00000000 ................ 00918140: 00000000 00000000 00000000 00000000 ................ 00918150: 00000000 00000000 00000000 00000000 ................ 00918160: 00000000 00000000 00000000 00000000 ................ 00918170: 00000000 00000000 00000000 00000000 ................ 00918180: 00000000 00000000 00000000 00000000 ................ 00918190: 00000000 00000000 00000000 00000000 ................ 009181a0: 00000000 00000000 00000000 00000000 ................ 009181b0: 00000000 00000000 00000000 00000000 ................ 009181c0: 00000000 00000000 00000000 00000000 ................ 009181d0: 00000000 00000000 00000000 00000000 ................ 009181e0: 00000000 00000000 00000000 00000000 ................ 009181f0: 00000000 00000000 00000000 00000000 ................ MX6SOLO SABREAUTO U-Boot >‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ Here I have no bad block (it is a SLC RAW NAND flash..). To be sure I have effectively erased 6 FCB, I will erase the 2 last one... thus I will not boot as all FCB tables will be erased(remove the usb cable otherwise mfgtool will restart): MX6SOLO SABREAUTO U-Boot > nand erase 0x180000 0x512 NAND erase: device 0 offset 0x180000, size 0x512 Warning: Erase size 0x00000512 smaller than one erase block 0x00080000 Erasing 0x00080000 instead Erasing at 0x180000 -- 100% complete. OK MX6SOLO SABREAUTO U-Boot >‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ Reset the board... and it will not start as you have erased all the 8 FCB tables... you have to reprogram your board if you want to start again.

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Introduction i.MX6SoloX and i.MX7D SoC contain embedded Cortex-M4 core. In a common use-case, this core runs a firmware loaded by u-boot bootloader. If you however want to debug your application for the Cortex-M4 core, you may need to reload the firmware in the secondary core without restarting Linux running on the Cortex-A core. For this reason, a tool was created: imx-m4fwloader. The project is released as open source under GPL-2.0 licence here: GitHub - NXPmicro/imx-m4fwloader: Tool for loading firmware to M4 core on i.MX6SX and 7D  I hope this tool will help to bring up faster your application for i.MX6SoloX and i.MX7D SoC! How to use this Either use the pre-built version Or use the environment provided to you by Yocto: For example: source /opt/poky/1.8/environment-setup-cortexa9hf-vfp-neon-poky-linux-gnueabi $CC m4fwloader.c -o m4fwloader You get m4fwloader binary... Then you need to build your M4 application and link it to some address. (e.g 0x00910000, try: https://github.com/EmbeddedRPC/erpc-imx-demos/tree/master/MCU/example_rpmsg) Load it using m4fwloader: ./m4fwloader myapp.bin 0x00910000 Optionally use --verbose parameter to see what is written to each registers Warning: Use this tool for debugging only, since it accesses directly the registers from the user space and requires therefore root priviledges! You have been warned... 🙂 Optionally, you can trigger an interrupt using message unit (MU) to the M4 core to get RPMsg started - this is normally done by Linux Kernel during startup: ./m4fwloader kick 0 Whole usage is here: m4fwloader [filename.bin] [0xLOADADDR] [--verbose] # loads new firmware or: m4fwloader stop # holds the auxiliary core in reset or: m4fwloader start # releases the auxiliary core from reset or: m4fwloader kick [n] # triggers interrupt on RPMsg virtqueue n