Overview The purpose of this doument is to introduce how to enable PCIe WiFi into i.MX6 Android release. Environment Setup Hardware: i.MX6 SABRE-SD board Software: Android Jelly Bean 4.2 Software Configurations The source codes of Intel PCIe WiFi have been integrated for i.MX6 SABRE-SD board into i.MX6 Android release. However it's disabled by default. To enable it for i.MX6 SABRE-SD board, you can do the following: Change BOARD_WLAN_VENDOR to INTEL in device/fsl board configuration files. For example, diff --git a/sabresd_6dq/BoardConfig.mk b/sabresd_6dq/BoardConfig.mk index 9c8a32d..912e752 100755 --- a/sabresd_6dq/BoardConfig.mk +++ b/sabresd_6dq/BoardConfig.mk @@ -11,7 +11,7 @@ TARGET_BOOTLOADER_BOARD_NAME := SABRESD PRODUCT_MODEL := SABRESD-MX6DQ # Wifi -BOARD_WLAN_VENDOR                       := ATHEROS +BOARD_WLAN_VENDOR                       := INTEL # for atheros vendor ifeq ($(BOARD_WLAN_VENDOR),ATHEROS) BOARD_WLAN_DEVICE                       := ar6003 @@ -30,6 +30,7 @@ WIFI_COMPAT_MODULE_ARG                         := "" endif #for intel vendor ifeq ($(BOARD_WLAN_VENDOR),INTEL) +BOARD_WLAN_DEVICE                       := INTEL BOARD_HOSTAPD_PRIVATE_LIB               ?= private_lib_driver_cmd BOARD_WPA_SUPPLICANT_PRIVATE_LIB        ?= private_lib_driver_cmd WPA_SUPPLICANT_VERSION                  := VER_0_8_X After changing BOARD_WLAN_VENDOR as "INTEL", the following files will be compiled for intel WiFi: device/fsl-proprietary/pcie-wifi/ external/wpa_supplicant_8 hardware/imx/wlan/intel/ hardware/libhardware_legacy/wifi/wifi_intel.c Enable PCIe WiFi driver in kernel_imx by running "make menuconfig" command: Select "System Type -> Freescale MXC Implementations -> PCI Express support" as "*" Select "Networking support -> Wireless ->  cfg80211 - wireless configuration API" as "*". Then select "Networking support -> Wireless -> Generic IEEE 802.11 Networking Stack (mac80211)" as "*" Select "Device Drivers ->  Network device support -> Wireless LAN -> Intel Wireless WiFi 4965AGN (iwl4965)" as "*" Then run "make" command to build kernel. The followings are the dependencies files to enable above configuration: Kernel configuration: * -> System Type -> Freescale MXC Implementations Select the PCI Express support. Then config intel WIFI driver: Generic IEEE 802.11 Networking Stack (mac80211) used by WIFI devices Symbol: MAC80211 [=y] Type : tristate Prompt: Generic IEEE 802.11 Networking Stack (mac80211) Defined at net/mac80211/Kconfig:1 Depends on: NET [=y] && WIRELESS [=y] && CFG80211 [=y] Location: -> Networking support (NET [=y]) -> Wireless (WIRELESS [=y]) Intel iwl4965 or iwl6300 card driver Symbol: IWL4965 [=y] Type : tristate Prompt: Intel Wireless WiFi 4965AGN (iwl4965) Defined at drivers/net/wireless/iwlegacy/Kconfig:65 Depends on: NETDEVICES [=y] && WLAN [=y] && PCI [=y] && MAC80211 [=y] Location: -> Device Drivers -> Network device support (NETDEVICES [=y]) Then you can follow up the instructions into Android User guide to build Android image. Known Limitation PCIe low power mode is not supported according to BSP release note. So when building in PCIe, the system suspend/resume should be disabled now.

Inside IPU there are two block where color space conversion can be made: IC (Image Converter) and DP (Display processor). On Linux, the CSC parameters are located at IPU (IC and DP) drivers, linux/drivers/mxc/ipu3 folder. All negative coefficients are represented using two's complement. Linux Image Converter driver: The parameters are set on function _init_csc: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/drivers/mxc/ipu3/ipu_ic.c?h=imx_3.14.28_1.0.0_ga static void _init_csc(struct ipu_soc *ipu, uint8_t ic_task, ipu_color_space_t in_format, ipu_color_space_t out_format, int csc_index) { /* * Y = 0.257 * R + 0.504 * G + 0.098 * B + 16; * U = -0.148 * R - 0.291 * G + 0.439 * B + 128; * V = 0.439 * R - 0.368 * G - 0.071 * B + 128; */ static const uint32_t rgb2ycbcr_coeff[4][3] = { {0x0042, 0x0081, 0x0019}, {0x01DA, 0x01B6, 0x0070}, {0x0070, 0x01A2, 0x01EE}, {0x0040, 0x0200, 0x0200}, /* A0, A1, A2 */ }; /* transparent RGB->RGB matrix for combining */ static const uint32_t rgb2rgb_coeff[4][3] = { {0x0080, 0x0000, 0x0000}, {0x0000, 0x0080, 0x0000}, {0x0000, 0x0000, 0x0080}, {0x0000, 0x0000, 0x0000}, /* A0, A1, A2 */ }; /* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));   G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));   B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */ static const uint32_t ycbcr2rgb_coeff[4][3] = { {149, 0, 204}, {149, 462, 408}, {149, 255, 0}, {8192 - 446, 266, 8192 - 554}, /* A0, A1, A2 */ }; ‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ Linux Display Processor driver: The parameters are set on constants (rgb2ycbcr_coeff and ycbcr2rgb_coeff): http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/drivers/mxc/ipu3/ipu_disp.c?h=imx_3.14.28_1.0.0_ga /* Y = R * 1.200 + G * 2.343 + B * .453 + 0.250;   U = R * -.672 + G * -1.328 + B * 2.000 + 512.250.;   V = R * 2.000 + G * -1.672 + B * -.328 + 512.250.;*/ static const int rgb2ycbcr_coeff[5][3] = { {0x4D, 0x96, 0x1D}, {-0x2B, -0x55, 0x80}, {0x80, -0x6B, -0x15}, {0x0000, 0x0200, 0x0200}, /* B0, B1, B2 */ {0x2, 0x2, 0x2}, /* S0, S1, S2 */ }; /* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));   G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));   B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */ static const int ycbcr2rgb_coeff[5][3] = { {0x095, 0x000, 0x0CC}, {0x095, 0x3CE, 0x398}, {0x095, 0x0FF, 0x000}, {0x3E42, 0x010A, 0x3DD6}, /*B0,B1,B2 */ {0x1, 0x1, 0x1}, /*S0,S1,S2 */ };‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

ESAI module in i.MX6D/I.MX6D/I.MX6DL/I.MX6S supports several RESET funtions: Reset ESAI Core, Reset both Transmitter and Receiver, Reset Transmitter individually, Reset Receiver individually, Reset Transmitter FIFO and Reset Receiver FIFO. Below is a simple diagram for these RESET functions, which shows reset object and related register configurations. 1.Reset ESAI Core After setting ESAI_ECT ERST bit to be 1, ESAI core and configuration registers will be reset, but Transmitter and Recevier FIFOs can't be reset by the operation. 2. Reset both Transmitter and Receiver After setting ESAI_PCRC & ESAI_PRRC to be 0x000, Transmitter and Receiver can both be reset, The RESET is also called "Personal Reset" in it's reference manual. About PCRC & PRRC bits functionality, we can see the table: From the table, ESAI_PCRC=0x000 and ESAI_PRRC=0x000 will make ESAI disconnet external ESAI pins, and ESAI's Tranmitter and Receiver can't communicate with external audio codec.  See ESAI_PCRC and ESAI_PRRC register below: ---ESAI_PCRC register ---ESAI_PRRC register There are 12 bits in each register to contorl "DISCONNECTION" OR "CONNECTION" with ESAI pins. So for normal operations of ESAI, these 2 registers can't be changed. 3.Reset Transmitter & Receiver individually By setting ESAI_TCR[TPR]=1, Transmitter can be reset individually, and not affect Receiver. By setting ESAI_RCR[RPR]=1, Receiver can be reset individually, and not affect Transmitter . In reference manual, the reset is called "personal reset / individual reset", actually they means the same thing: --Reset Transmitter individually. --Reset Receiver individually. 4.Reset Transmitter FIFO and Reset Receiver FIFO ---By setting ESAI_TFCR[TFR]=1, Tranmitter FIFIO can be reset. ---By setting ESAI_RFCR[RFR]=1, Receiver FIFO can be reset. The Reset requires ESAI is operational, which means at least one pin is defined as an ESAI pin. NXP TIC team Weidong Sun

NOTE: Always de-power the target board and the aggregator when plugging or unplugging smart sensors from the aggregator. The aggregator portion of the i.MX Power Profiling System sits between the "smart" current sensor boards and the host computer. It provides power and signal connections to each connected sensor board. The communication is done over I2C, where three I2C bus extenders (PCA9518) effectively provide a dedicated bus to each I2C device, to better allow for cabling.  More information will follow... A photo, layout images and schematic attached below.   MBED source for the FRDM-KL25Z is available here: 30848-KL25Z-AGGREGATOR    Smart Sensor Connections At each smart sensor header JP0-JP13, these are the connections provided: 5V: powers the 3.3V regulator on each sensor board 12V: all the gates of all the switching FETs are pulled pulled up to 12V GND: ground connection SCL/TX0: I2C clock line  SDA/RX0: I2C data line  SWD_CLK:  global line for triggering smart sensors to make measurements RESET_B:  global line for resetting all smart sensor boards SWD_IO_n: individual select line for each smart sensor I2C Bus Connection Three I2C bus extenders (PCA9518) provide buffered connections between the FRDM board and all the connected smart sensors. The bus extenders were added to allow for longer cables between the aggregator and the smart sensor boards. Each bus extender has five ports and along with connections that allow extending the bus to more bus extenders. Gate Supply The aggregator contains a boost regulator that boost the 5V input from the FRDM board to 12V. The boosted voltage is fed to each of the smart sensor headers. It's used by the smart sensor board to pull up the gates of the switching FETs above any of the rails under test by at least 4.5V in order to benefit from a lower Rds(on). Caution must be exercised with some older FRDM boards since the 5V from the USB connection passes through diodes with a maximum current of 200mA.  The boost regulator and the load presented by the smart sensor boards may exceed the diode's limit and damage it. (Yes, it's happened... two older FRDM-KL25Z boards were used during development. One of them failed with the diode shorted (~0.05 Ohms), so everything kept working. The other failed with a  short of ~45 Ohms, so it kind of worked but not really...) Application Code for Aggregator  To date, application code has only been developed for the FRDM-KL25Z board. The latest application code resides at: https://os.mbed.com/users/r14793/code/30848-KL25Z-AGGREGATOR/, with the latest binary attached below. SWD Programming of Smart Sensors  Connectors J5 and JP15 are provided as an adapter for programming the smart sensor boards via SWD. JP15 provides power to the smart sensor board, since they have no direct 3.3V input for the KL05Z. An SWD programmer (or suitably modified FRDM-KL05Z board) connects to J5. Both connections use 10-pin 0.05"-spaced ribbon cables. Additionally, when a smart sensor is connected to JP15, J6 provides access to the UART pins of the smart sensor (the I2C pins on the smart sensor also mux out the UART of the KL05Z). No hardware changes are necessary at all; changing the code running on the smart sensor is all that's required. In fact, during the initial prototyping of the smart sensors, the serial UART connection was used instead of I2C. Modify Aggregator To Use SWD Dongle To Program Smart Sensor:  Add a wire as shown on the bottom side of the aggregator board as shown below. This ties 3.3V on the aggregator to the debug header, enabling the voltage level translators on the dongle to communicate with the KL05Z on the smart sensor board.  

The document includes the following contents: (1)document how to port ov5646 to android jb4.2.2 (2) ov5645 driver for Linux 3.0.35 (3) ov5645 schematic based on i.MX6Q/DL (4)ov5645 for android camera HAL   [Note:]      P5V29A-0JG is a camera module based on OV5645, and PAO532-0JG is based on OV5640, both manufactured by NINGBO SUNNY OPOTECH CO.LTD (China), If customer wants to use them on i.MX6 platform, can send me email to ask for datasheets of P5V29A & PAO532 , or discuss corresponding questions on porting.   Email: weidong.sun@freescale.com

Sometime need standalone compile device tree. Only Linux headers and device tree directory are needed.         

Hello there. Here is a good way to use U-boot in an efficient way with custom scripts. The bootscript is an script that is automatically executed when the boot loader starts, and before the OS auto boot process. The bootscript allows the user to execute a set of predefined U-Boot commands automatically before proceeding with normal OS boot. This is especially useful for production environments and targets which don’t have an available serial port for showing the U-Boot monitor. This information can be find in U-Boot Reference Manual.   I will take the example load a binary file in CORTEX M4 of IMX8MM-EVK. In my case, I have the binary file in MMC 2:1 called gpio.bin and I will skip those steps because that is not the goal.   First, you need the u-boot-tools installed in your Linux machine: sudo apt install u-boot-tools   That package provide to us the tool mkimage to convert a text file (.src, .txt) file to a bootscript file for U-Boot.   Now, create your custom script, in this case a simple script for load binary file in Cortex M4: nano mycustomscript.scr  and write your U-Boot commands: fatload mmc 2:1 0x80000000 gpio.bin cp.b 0x80000000 0x7e0000 0x10000 bootaux 0x7e0000   Now we can convert the text file to bootscript with mkimage. Syntax: mkimage -T script -n "Bootscript" -C none -d <input_file> <output_file> mkimage -T script -n "Bootscript" -C none -d mycustomscript.scr LCM4-bootscript   This will create a file called LCM4-bootscript (Or as your called it).   A way to load this bootscript file to U-Boot is using the UUU tool, in U-Boot set the device in fastboot with command: u-boot=> fastboot 0 Then in linux with the board connected through USB to PC run the command: sudo uuu -b fat_write LCM4-bootscript mmc 2:1 LCM4-bootscript   Now we have our bootscript in U-Boot in MMC 2:1.   Finally, we can run the bootscript in U-Boot: u-boot=> load mmc 2:1 ${loadaddr} LCM4-bootscript 158 bytes read in 2 ms (77.1 KiB/s) u-boot=> source ${loadaddr} ## Executing script at 40400000 6656 bytes read in 5 ms (1.3 MiB/s) ## No elf image at address 0x007e0000 ## Starting auxiliary core stack = 0x20020000, pc = 0x1FFE02CD...   And the Cortex M4 booted successfully:    I hope this can helps to you.   Best regards.   Salas.  

In some cases, such as mass production or preparing a demo. We need u-boot environment stored in demo sdcard mirror image.  Here is a way: HW:  i.MX8MP evk SW:  LF_v5.15.52-2.1.0_images_IMX8MPEVK.zip The idea is to use fw_setenv to set the sdcard mirror as the operation on a real emmc/sdcard. Add test=ABCD in u-boot-initial-env for test purpose. And use fw_printenv to check and use hexdump to double confirm it. The uboot env is already written into sdcard mirror(imx-image-multimedia-imx8mpevk.wic). All those operations are on the host x86/x64 PC. ./fw_setenv -c fw_env.config -f u-boot-initial-env Environment WRONG, copy 0 Cannot read environment, using default ./fw_printenv -c fw_env.config Environment OK, copy 0 jh_root_dtb=imx8mp-evk-root.dtb loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bsp_script}; mmc_boot=if mmc dev ${devnum}; then devtype=mmc; run scan_dev_for_boot_part; fi arch=arm baudrate=115200 ...... ...... ...... splashimage=0x50000000 test=ABCD usb_boot=usb start; if usb dev ${devnum}; then devtype=usb; run scan_dev_for_boot_part; fi vendor=freescale hexdump -s 0x400000 -n 2000 -C imx-image-multimedia-imx8mpevk.wic 00400000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| hexdump -s 0x400000 -n 10000 -C imx-image-multimedia-imx8mpevk.wic 00400000 5f a4 9b 97 20 6a 68 5f 72 6f 6f 74 5f 64 74 62 |_... jh_root_dtb| 00400010 3d 69 6d 78 38 6d 70 2d 65 76 6b 2d 72 6f 6f 74 |=imx8mp-evk-root| 00400020 2e 64 74 62 00 20 6c 6f 61 64 62 6f 6f 74 73 63 |.dtb. loadbootsc| 00400030 72 69 70 74 3d 66 61 74 6c 6f 61 64 20 6d 6d 63 |ript=fatload mmc| 00400040 20 24 7b 6d 6d 63 64 65 76 7d 3a 24 7b 6d 6d 63 | ${mmcdev}:${mmc| 00400050 70 61 72 74 7d 20 24 7b 6c 6f 61 64 61 64 64 72 |part} ${loadaddr| 00400060 7d 20 24 7b 62 73 70 5f 73 63 72 69 70 74 7d 3b |} ${bsp_script};| 00400070 00 20 6d 6d 63 5f 62 6f 6f 74 3d 69 66 20 6d 6d |. mmc_boot=if mm| ...... ...... ...... 00401390 76 3d 31 00 73 6f 63 3d 69 6d 78 38 6d 00 73 70 |v=1.soc=imx8m.sp| 004013a0 6c 61 73 68 69 6d 61 67 65 3d 30 78 35 30 30 30 |lashimage=0x5000| 004013b0 30 30 30 30 00 74 65 73 74 3d 41 42 43 44 00 75 |0000.test=ABCD.u| 004013c0 73 62 5f 62 6f 6f 74 3d 75 73 62 20 73 74 61 72 |sb_boot=usb star| 004013d0 74 3b 20 69 66 20 75 73 62 20 64 65 76 20 24 7b |t; if usb dev ${| 004013e0 64 65 76 6e 75 6d 7d 3b 20 74 68 65 6e 20 64 65 |devnum}; then de| flash the sdcard mirror into i.MX8MP evk board emmc to check uuu -b emmc_all imx-boot-imx8mp-lpddr4-evk-sd.bin-flash_evk imx-image-multimedia-imx8mpevk.wic  The first time boot, the enviroment is already there.  How to achieve that: a. fw_setenv/fw_printenv: https://github.com/sbabic/libubootenv.git Note: Please do not use uboot fw_setenv/fw_printenv Compile it on the host x86/x64 PC. It is used on host. b. u-boot-initial-env Under uboot, make u-boot-initial-env Note: Yocto deploys u-boot-initial-env by default c. fw_env.config  imx-image-multimedia-imx8mpevk.wic 0x400000 0x4000 0x400000 0x4000 are from uboot-imx\configs\imx8mp_evk_defconfig CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x400000 Now, you can run  ./fw_setenv -c fw_env.config -f u-boot-initial-env

  Question: How can we generate an ARM DS5 DStream format DDR initialization script using the DRAM Register Programming Aid?  Answer: Some RPAs include a  "DStream .ds file" tab for the ARM DS5 debugger specific commands. The i.MX6UL/ULL/ULZ DRAM Register Programming Aids for example already has this supported. However, the user can easily create  the .ds format from the existing .inc format. The basic steps to convert .inc files to .ds format are as follows: 1)  Replace the one instance of setmem /16 with mem set 2)  In that same line, replace 0x020bc000 = with 0x020bc000 16 3)  Use a Replace All command to change setmem /32 with mem set 4)  Use a Replace All command to change = with 32 5)  Use a Replace All command to change // with # 6)  Save as a .ds file.   Question: When using a 528MHz DRAM Controller interface with a DDR memory of a faster speed bin, which speed bin timing options should one use? Answer: For example, let’s assume our MX6DQ design is using a DDR3 memory from a DDR3-1600 speed bin.  However, the maximum speed of the MMDC interface for the MX6DQ using DDR3 is 528MHz.  Should we use the 1600 speed bin (800MHz clock speed) or the 1066 speed bin (533MHz clock speed)?  In short, the user should use the timings rated for the maximum speed (frequency) with which you are running, in this case DDR3-1066 (533MHz).  In some cases, like when using the MX6DL, the maximum DDR frequency is 400MHz.  In this case, you would want to try and use 800 timings found in the AC timing parameters table.  However, most DDR3 devices have speed bin tables that may go only as low as 1066, in which case you would use the closest speed bin to your operational frequency (i.e. the 1066 speed bin table).     Question: Some timing parameters may specify a min and max number, which should I use? Answer: In most cases, you will want to choose the minimum timings.  Some DRAM controllers may have a tRAS_MAX timing parameter, in which case you would obviously use the maximum tRAS parameter given in the DRAM data sheet. Also, for timing parameters tAONPD and tAOFPD, we also want to use the maximum values given in the DDR3 data sheet. These represent the maximum amount of time the DDR3 device takes to turn on or off the RTT (termination), therefore, we should wait at least this amount of time before issuing any commands or accesses.   Question: Some timing parameters state things like “Greater of 3CK or 7.5ns”; which should I use? Answer: This depends on your clock speed.  Say you are running at 533MHz.  At 533MHz, 7.5ns equates to 4CKs.  In this case, 7.5ns at 533MHz is GREATER than 3CK, so we would use the 7.5ns number, or 4CKs. At 400MHz, 7.5ns equates to 3CKs.  In this case, we’d simply use 3CKs.   Question: I have a design that will throttle the DDR frequency (dynamic frequency scaling).  At full speed, I plan to run at 533MHz, and then I plan to throttle down to say 400MHz whenever possible.  Do I need to re-calculate my 400 MHz timing parameters that were initially set for 533MHz? Answer: It is not necessary to re-calculate timing parameters for 400MHz, and you can re-use the ones for 533MHz.  The timings at 533 MHz are much tighter than 400 MHz, and the key here is to NOT violate timings.  Also, it may be a bit of a hassle maintaining two sets of timing parameters, especially if later in the design, you swap DDR vendors that might require you to re-calculate some timing parameters.  It’s easier to do it once and to come up with a combined worse-case timing parameters for 533MHz, which you know will work at 400MHz.  But, if you don’t mind maintaining two sets of timing parameters, and really want to optimize timings down to the last pico-second for 400MHz, then knock yourself out.   Question: Can I use these Register programming aids for both Fly by and T- Topology ? Answer Yes The DDR register programming aid is agnostic to the DDR layout. The same spreadsheet works for both topologies. We recommend running write leveling calibration for both topologies and the values returned by the Write Leveling routine from the Freescale DDR stress test should be incorporated back to the customer specific initialization script. The DDR stress test also has a feature whereby it evaluates the write leveling values returned from calibration and increments WALAT to 1 if the values exceed a defined limit. The DDR stress test informs the user when the Write Additional latency (WALAT) exceeds the limit and should be increased by 1, and reminds the user to add it back in the customer specific initialization script if required.   WALAT - 0 00000000 WALAT: Write Additional latency. Recommend to clear these bits. Proper board design should ensure that the DDR3 devices are placed close enough to the MMDC to ensure the skew between CLK and DQS is less than 1 cycle.     Question: Can I use the DEFAULT Register programming aid values for MDOR when using an Internal OSC instead of the recommended 32.768 KHZ XTAL ? Answer No, NXP recommends reprogramming these values based on the worse case frequency (Max clock) of the internal OSC of the device to guarantee JEDEC timings are met. Please refer to Internal Oscillator Accuracy considerations for the i.MX 6 Series for more details  

Important: If you have any questions or would like to report any issues with the DDR tools or supporting documents please create a support ticket in the i.MX community. Please note that any private messages or direct emails are not monitored and will not receive a response. i.MX 6/7 Series Family DDR Tools Overview This page contains the latest releases for the i.MX 6/7 series DDR Tools. The tools described on this page cover the following i.MX 6/7 series SoCs: i.MX 6DQP (Dual/Quad Plus) i.MX 6DQ (Dual/Quad) i.MX 6DL/S (Dual Lite/Solo) i.MX 6SoloX i.MX 6SL i.MX 6SLL i.MX 6UL i.MX 6ULL/ULZ i.MX 7D/S i.MX 7ULP The purpose of the i.MX 6/7 series DDR Tools is to enable users to generate and test a custom DRAM initialization based on their device configuration (density, number of chip selects, etc.) and board layout (data bus bit swizzling, etc.). This process equips the user to then proceed with the bring-up of a boot loader and an OS. Once the OS is brought up, it is recommended to run an OS-based memory test (like Linux memtester) to further verify and test the DDR memory interface. The i.MX 6/7 series DDR Tools consist of: DDR Register Programming Aid (RPA) DDR Stress test _________________________________________________________ i.MX 6/7 Series DDR Stress Test The i.MX 6/7 Series DDR stress test tool is a Windows-based software tool that is used as a mechanism to verify that the DDR initialization is operational prior for use in u-boot and OS bring-up. The DDR Stress Test tool can be found here: i.MX 6/7 DDR Stress Test Tool Note that the DDR Stress test tool supports all of the above i.MX SoCs, however, some of the supported i.MX SoCs named in the tool support multiple i.MX SoCs as follows: MX6DQ – when selected, this supports both i.MX 6DQ and i.MX 6DQP (Plus) MX6DL – when selected, this supports both i.MX 6DL and i.MX 6S (i.MX 6DLS family) MX6ULL – when selected, this supports both i.MX 6ULL and i.MX6 ULZ MX7D – when selected, this supports both i.MX 7D and i.MX 7S _____________________________________________________________________________ i.MX 6/7 Series DDR Register Programming Aid (RPA) The i.MX 6/7 series DDR RPA (or simply RPA) is an Excel spreadsheet tool used to develop DDR initialization for a user’s specific DDR configuration (DDR device type, density, etc.). The RPA generates the DDR initialization script for use with the DDR Stress Test tool. For a history of the previous versions of an RPA, refer to the Revision History tab of the respective RPA. To obtain the latest RPAs, please refer to the following links: i.MX 6DQP i.MX6DQP Register Programming Aids i.MX 6DQ i.MX6DQ Register Programming Aids i.MX 6DL/S i.MX6DL Register Programming Aids i.MX 6SoloX i.MX6SX Register Programming Aids i.MX 6SL i.MX6SL Register Programming Aids  i.MX6SLL i.MX6SLL Register Programming Aids i.MX 6UL/ULL/ULZ i.MX6UL/ULL/ULZ DRAM Register Programming Aids i.MX7D i.MX7D DRAM Register Programming Aids i.MX 7ULP i.MX7ULP DRAM Register Programming Aids _____________________________________________________________________________ DRAM Register Programming Aids FAQ    

      The i.MX6UL/LL/LZ processor supports 2 USB OTG interfaces, USB OTG1 and USB OTG2, and each USB interface can be configured as a device, host or dual role mode. On the EVK board of i.MX6UL/LL, USB OTG1 is designed as dual role mode, and USB OTG2 is designed as HOST mode. This is sufficient for most customers.       However, in actual applications, we may need 2 USB HOSTs, and at the same time, we don’t want to use MicroUSB to USB TYPE-AF cable for Host-Device mode conversion. Therefore, the design of the USB circuit needs to meet such requirements: 1. USB device mode We need a USB device to download the linux image to the flash or SD card on the board. 2. 2 USB HOSTs When the system is working normally, we need the board to support 2 USB HOST. i.MX6UL/LL/LZ has only 2 USB ports. How to design to meet this requirement without increasing the USB HUB? The following scheme is used as a reference, and I hope it will be helpful to customers with similar requirement:        The logic and application description of this Diagram:: Default—device mode In the process of debugging the software, we need to use the USB OTG interface to download the linux image, so it must work in device mode. What we need to do is: (1). Pull USB OTG ID up to 3.3V (2). The USB OTG D+/D- signal is switched to the MicroUSB connector. (3). The USB OTG VBUS is provided with 5V power from the external PC USB HOST. Usage:        -Use a jumper for Pin 1 and Pin2, USB OTG ID pin will be pulled up to High.        With the operation, SEL pin of USB Muxer is High, and USB signals are switched to port B, and USB differential signals are connected to MicroUSB connector. At the same time, MIC2026-1YM output is disabled. The USB OTG1 VBUS pin of CPU is supplied by VBUS of MicroUSB connector, that is to say, supplied by PC USB HOST.        In this mode, software engineer can use it to download images to flash on board. Normal Work—Host mode After the software debugging is completed, two HOSTs are needed on the board. At this time, we need to switch the USB OTG1 from device to HOST mode. What we need to do is: (1). Pull USB OTG1 ID down to LOW (2). The USB OTG D+/D- signal is switched to the USB Type-AF connector. (3). Board should supply 5V power for USB device connected USB Type-AF connector. Usage:        -Use a jumper for Pin 2 and Pin3, USB OTG ID pin will be pulled down to Low.        With the operation, USB OTG1 ID pin is pulled down to Low, SEL pin of USB Muxer is also LOW, USB signals are switched to Port A, and connected to USB type-AF connector. At the same time, MIC2026-1YM is enabled , OUTA will output 5V , which will supply USB device connected on USB type-AF connector.   [Note] Users need to pay attention to. When using the jumper with PIN1/2/3, the board needs to be powered off. In other words, when switching between device and host, you need to switch off the power, then power on, and restart the board. The solution can also be used for i.MX processors with USB 2.0 interface.   NXP CAS team Wedong Sun 01/15/2021

Attached is the Kernel image needed to construct the Linux Image i.MX 6Dual/6Quad Power Consumption Measurement Linux Image

ccache is a C compiler cache. ccache can save a large amount of compilation time on recurring builds and builds restarted from a clean repository after make clean or git clean. It is well suited for e.g. u-boot and Linux compilation. Caching the host compiler Caching "native" builds is easily done by adding in the beginning of your $PATH a special directory, which contains links to ccache to override the usual compiler. On e.g. Debian this directory is readily available as /usr/lib/ccache, So you can do:   $ export PATH="/usr/lib/ccache:$PATH" Typical links found in this folder are:   c++ -> ../../bin/ccache   cc -> ../../bin/ccache   g++ -> ../../bin/ccache   gcc -> ../../bin/ccache etc... Caching the cross compiler Caching cross-compiled builds can be done in the same way as native builds, provided you create links of the form e.g. arm-linux-gnueabihf-gcc pointing to ccache. But there is an even more convenient way for those projects, which rely on a $CROSS_COMPILE environment variable (as is the case for e.g. u-boot and Linux). You can prefix the cross compiler with ccache there in e.g. the following way:   $ export CROSS_COMPILE="ccache arm-linux-gnueabihf-" Monitoring efficiency Now that your builds are cached, you might want to see how much is "spared" with this technique. ccache -s will tell you all sorts of statistics, such as:   cache directory                     /home/vstehle/.ccache   cache hit (direct)                 10852   cache hit (preprocessed)            3225   cache miss                         19000   called for link                    33267   called for preprocessing            9463   compile failed                         3   preprocessor error                     1   couldn't find the compiler           117   unsupported source language          921   unsupported compiler option         2167   no input file                      31681   files in cache                     51694   cache size                           1.3 Gbytes   max cache size                       4.0 Gbytes Here you see a somewhat typical 50%/50% hit/miss ratio. Enjoy! See Also ccache is usually supported natively by build systems, such as Buildroot or Yocto.

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-343372 

The default FSL android BSP support 1 SD card slot. If customer need to support more sd slot in android.Please reference below steps. There are two steps need to set up. 1 device/fsl.git NOTE: 1  change the fstab. 2194000 is the address of usdhc2.             2  change the mount point in storage_list.xml diff --git a/sabresd_6dq/fstab.freescale b/sabresd_6dq/fstab.freescale index 7f23edb..1529a27 100644 --- a/sabresd_6dq/fstab.freescale +++ b/sabresd_6dq/fstab.freescale @@ -4,6 +4,7 @@ # specify MF_CHECK, and must come before any filesystems that do specify MF_CHECK /devices/soc0/soc.0/2100000.aips-bus/2198000.usdhc/mmc_host /mnt/media_rw/extsd vfat defaults voldmanaged=extsd:auto +/devices/soc0/soc.0/2100000.aips-bus/2194000.usdhc/mmc_host /mnt/media_rw/extsd_expand vfat defaults voldmanaged=extsd_expand:auto /devices/soc0/soc.0/2100000.aips-bus/2184000.usb/ci_hdrc.0  /mnt/media_rw/udisk vfat defaults voldmanaged=udisk:auto /dev/block/mmcblk3p5    /system      ext4    ro,barrier=1                                                                               wait,verify /dev/block/mmcblk3p4    /data        ext4    nosuid,nodev,nodiratime,noatime,nomblk_io_submit,noauto_da_alloc,errors=panic    wait,encryptable=/dev/block/mmcblk3p9 diff --git a/sabresd_6dq/overlay/frameworks/base/core/res/res/xml/storage_list.xml b/sabresd_6dq/overlay/frameworks/base/core/res/res/xml/storage_list.xml index 3639bdc..c3f5105 100644 --- a/sabresd_6dq/overlay/frameworks/base/core/res/res/xml/storage_list.xml +++ b/sabresd_6dq/overlay/frameworks/base/core/res/res/xml/storage_list.xml @@ -41,6 +41,10 @@               android:storageDescription="@string/storage_sd_card"               android:primary="false"               android:removable="true" /> +    <storage android:mountPoint="/storage/extsd_expand" +             android:storageDescription="@string/storage_sd_card" +             android:primary="false" +             android:removable="true" />      <storage android:mountPoint="/storage/udisk" 2  system/core.git NOTE: mkdir the mount point. build@scmbld2:~/maddev_lp5.1_consolidate_ga_10_30/system/core/rootdir$ git diff diff --git a/rootdir/init.rc b/rootdir/init.rc index 2211cc2..fac37c2 100644 --- a/rootdir/init.rc +++ b/rootdir/init.rc @@ -72,7 +72,9 @@ on init      mkdir /storage 0751 root sdcard_r      mkdir /mnt/media_rw/extsd 0755 system system +    mkdir /mnt/media_rw/extsd_expand 0755 system system      symlink /mnt/media_rw/extsd /storage/extsd +    symlink /mnt/media_rw/extsd_expand /storage/extsd_expand      mkdir /mnt/media_rw/udisk 0755 system system

[中文翻译版] 见附件   原文链接： https://community.nxp.com/docs/DOC-343344 

Question: What does it means by depending on load? Is there a value? This is  related with i.MX6D Answer: The comment about the "load" means the total system load on the 2.5V rail. We understand that people design systems, not just MX6 devices. The documentation confusion stems from the design team changing from allowing customers to use the LDOs to power system devices back to just using the LDOs to power the MX6. Reasons - thermals, and also concern for uncontrolled system noise injection into the MX6 and causing failures.

                For the SPI NOR booting on fuse steps. 1.      Please boot your PCB on uboot and type below command for fuse boot setting. MX6Q SABRESD-MFG U-Boot > imxotp blow --force 5 0x0a000030 MX6Q SABRESD-MFG U-Boot > imxotp read 5 Reading fuse at index: 0x5 Fuse at (index: 0x5) value: 0xA000030 MX6Q SABRESD-MFG U-Boot > imxotp read 6 Reading fuse at index: 0x6 Fuse at (index: 0x6) value: 0x0 MX6Q SABRESD-MFG U-Boot > imxotp blow --force 6 0x10 Current fuse at (index: 0x6) value: 0x0 Blowing fuse at index: 0x6, value: 0x10 Reloading shadow registers... Operation succeeded fuse at (index: 0x6) value: 0x10 MX6Q SABRESD-MFG U-Boot > imxotp read 6 Reading fuse at index: 0x6 Fuse at (index: 0x6) value: 0x10 MX6Q SABRESD-MFG U-Boot > 2.      Set the boot mode for 00 as Boot from fuses 3.      You could see the SPI clock on scope after re power on.

The document descript how to use the win32diskimager to create bootable sdcard.  How to resize sdcard mirror rootfs partition. Ex: fsl-image-validation-imx-imx6qpdlsolox.sdcard