Platform & BSP : i.MX8MPlus EVK , L6.12.3, uboot lf_v2024.04
The attachments enable the i.MX8MPlus pci function in uboot.
lspci in Linux
root@imx8mpevk:~# lspci -nn
00:00.0 PCI bridge [0604]: Synopsys, Inc. DWC_usb3 / PCIe bridge [16c3:abcd] (rev 01)
01:00.0 Ethernet controller [0200]: Marvell Technology Group Ltd. Device [1b4b:2b42] (rev 11)
pci test results in uboot:
u-boot=> pci
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
00.00.00 0x16c3 0xabcd Bridge device 0x04
01.00.00 0x1b4b 0x2b42 Network controller 0x00
u-boot=> pci bar 00.00.00
ID Base Size Width Type
----------------------------------------------------------
0 0x0000000018000000 0x0000000000100000 32 MEM
u-boot=> pci regions 00
Buses 00-01
# Bus start Phys start Size Flags
0 0x0000000000000000 0x000000001ff80000 0x0000000000010000 io
1 0x0000000018000000 0x0000000018000000 0x0000000007f00000 mem
2 0x0000000040000000 0x0000000040000000 0x0000000016000000 mem sysmem
3 0x0000000058000000 0x0000000058000000 0x00000000a8000000 mem sysmem
4 0x0000000100000000 0x0000000100000000 0x00000000c0000000 mem sysmem
u-boot=> pci header 00.00.00
vendor ID = 0x16c3
device ID = 0xabcd
command register ID = 0x0007
status register = 0x0010
revision ID = 0x01
class code = 0x06 (Bridge device)
sub class code = 0x04
programming interface = 0x00
cache line = 0x08
latency time = 0x00
header type = 0x01
BIST = 0x00
base address 0 = 0x18000000
base address 1 = 0x00000000
primary bus number = 0x00
secondary bus number = 0x01
subordinate bus number = 0x01
secondary latency timer = 0x00
IO base = 0x10
IO limit = 0x00
secondary status = 0x0000
memory base = 0x1820
memory limit = 0x1810
prefetch memory base = 0xfff0
prefetch memory limit = 0x0000
prefetch memory base upper = 0x00000000
prefetch memory limit upper = 0x00000000
IO base upper 16 bits = 0x0000
IO limit upper 16 bits = 0x0000
expansion ROM base address = 0x18100000
interrupt line = 0xff
interrupt pin = 0x01
bridge control = 0x0000
u-boot=> pci header 01.00.00
vendor ID = 0x1b4b
device ID = 0x2b42
command register ID = 0x0006
status register = 0x0010
revision ID = 0x11
class code = 0x02 (Network controller)
sub class code = 0x00
programming interface = 0x00
cache line = 0x08
latency time = 0x00
header type = 0x00
BIST = 0x00
base address 0 = 0x1810000c
base address 1 = 0x00000000
base address 2 = 0x1820000c
base address 3 = 0x00000000
base address 4 = 0x00000000
base address 5 = 0x00000000
cardBus CIS pointer = 0x00000000
sub system vendor ID = 0x0000
sub system ID = 0x0000
expansion ROM base address = 0x00000000
interrupt line = 0xff
interrupt pin = 0x01
min Grant = 0x00
max Latency = 0x00
Hi I have an imx8qm, does that need the U-Boot patch in order to enable the PCI/PCIe function in U-Boot?
Hi @xnsmx
No, default uboot support imx8qm.
Hi Zhiming :
Currently, we can correctly scan the host through the patch, but when we use PCI enumeration, it seems we cannot scan other devices. How should we modify this part?
Hi.
I'm using i.mx8mp. Currently I can't use PCI related commands in bootloader.
If I apply this patch, will I be able to use PCI commands in bootloader?
Could you also tell me how to apply the patch?