Time Sensitive Networking(TSN) is an extension to traditional Ethernet networks, providing a set of standards compatible with IEEE 802.1 and 802.3. TSN aims to provide guarantees for deterministic latency and packet loss under congestion, allowing critical and non-critical traffic to be converged in the same network. This document introduces basic concept of Time Sensitive Networking, LS1028 TSN switch and using TSN features on LS1028ARDB. TSN Introduction TSN in LS1028 Using TSN features on LS1028ARDB

Open source software development tools for ARM processors

IPSec Performance Reproducibility Procedure on T1040RDB platform 1. Enable ASF in Linux Kernel           Step 1: Launch the kernel menu using the command: bitbake -c menuconfig virtual/kernel      Step 2: Enable ASF under Device Driver -> Networking device support -> Application Specific Fastpath      Step 3: Build the final binaries that needs to be loaded on T1040RDB using the command : bitbake fsl-image-core NOTE: The ASF modules are compiled as dynamically loadable modules and placed in the ROOTFS under the path /usr/driver/asf/min and /usr/driver/asf/full 2. Steps to boot the board with 2 cores:  (optional) => cpu 2 disable => cpu 3 disable => boot Board configuration after Linux is up A. Enable ip_forwarding and Linux performance parameters echo 1 > /proc/sys/net/ipv4/ip_forward echo 9000 > /proc/sys/net/netfilter/nf_conntrack_udp_timeout echo 9000 >/proc/sys/net/netfilter/nf_conntrack_udp_timeout_stream B. Insmod ASF ko’s cd /usr/driver/asf/min insmod asf.ko insmod asfctrl.ko insmod asfipsec.ko insmod asfctrl_ipsec.ko C. Run fmc command : cd /usr/driver/asf/scripts/fmc/ fmc -s Soft_FragParser.xml -p asf-fman-perf-policy.xml -c asf-cfg-perf-2041.xml -a D. Assign interface IP addresses and routes according to setup. Left DUT: ifconfig fm1-gb0 172.18.18.10 netmask 255.255.0.0 up ifconfig fm1-gb3 200.200.200.10/24 up ifconfig fm1-gb1 172.20.20.10 netmask 255.255.0.0 up ifconfig fm1-gb4 20.20.20.10/24 up route add -net 192.168.1.0/24 gw 172.18.18.2 route add default gw 200.200.200.20 route add -net 172.168.1.0/24 gw 172.20.20.2 route add -net 172.168.2.0/24 gw 20.20.20.20 arp -s 172.18.18.2 00:00:00:00:00:01 (optional) arp -s 172.20.20.2 00:00:00:00:00:02 (optional) Right DUT: ifconfig fm1-gb0 172.19.19.10 netmask 255.255.0.0 up ifconfig fm1-gb3 200.200.200.20/24 up ifconfig fm1-gb1 172.21.21.10 netmask 255.255.0.0 up ifconfig fm1-gb4 20.20.20.20/24 up route add -net 192.168.2.0/24 gw 172.19.19.2 route add default gw 200.200.200.10 route add -net 172.168.2.0/24 gw 172.21.21.2 route add -net 172.168.1.0/24 gw 20.20.20.10 arp -s 172.19.19.2 00:00:00:00:00:02 (optional) arp -s 172.21.21.2 00:00:00:00:00:04 (optional) E. Configure IPSec policies and SAs (attached below that needs to be downloaded to the box via tftp or sftp) Left DUT: ./left_tun-4port-v1.txt Right DUT: ./right_tun-4port-v1.txt F. Switch settings killall -9 l2sw_bin l2sw_bin Using UIO: /dev/uio0 Mapped register memory @ 0xb7b3f000 Chipid: 099530e9 fsl_dpa ethernet.17 fm1-gb0: Err FD status = 0x00040000 fsl_dpa ethernet.18 fm1-gb1: Err FD status = 0x00040000 l2switch> l2switch>mac add 00:00:00:00:00:01 3 [MAC 00:00...00:01 is reachable on port 3] m2switch>mac add 00:00:00:00:00:03 7 l2switch>mac add 00:04:9f:03:30:f6 8 [MAC of fm1-gb0] l2switch>mac add 00:04:9f:03:30:f7 9 [MAC of fm1-gb1] l2switch>mac dump [Displays MACDB of switch (static & Dynamic)] Type VID MAC Address Ports ------ --- ----------------- ----- Static 1 00:00:00:00:00:01 3 Static 1 00:00:00:00:00:03 7 Static 1 00:04:9f:03:30:f6 8 Static 1 00:04:9f:03:30:f7 9 Static entries: 4 Dynamic entries: 0 l2switch> l2switch>^Z [Press ctrl+z to stop the process] [1]+ Stopped(SIGTSTP) l2sw_bin root@t1040rdb:/mnt/sridhar/asf-bins/qos/bin/full# killall -9 l2sw_bin G. Configure IXIA/STC to generate the traffic with 128 flows. H. Start the traffic from both end and verify all the flows are offloaded and packet is going through IPSec ASF. Note: Except switch settings everything is similar to previous performance releases by IDC. I. The ASF flow can be observed using the following command cat /proc/asf/flow_debug Script files PFA in attachment

For QorIQ Processors you could find documents from official website: Submit Form And below document list in this place: SDK/DPAA/Networking: Using QMAN Dedicated and Pool Channels in USDPAA and Linux Kernel LS2085 NADK Based IPSEC Application Communicating with AIOP DPAA Ethernet Interfaces Shared-MAC between two Linux Partitions under Hypervisor(Topaz) IPv6+AES.docx T1040 L2Switch Software Support IPSec demo on T1040RDB hv.dts IPSec on Freescale Hypervisor (Topaz) and T1040 (T1042) Rate limiting in DPAA QorIQ QMan CEETM Implementation in USDPAA Read T2080 XFI link status Shared-MAC and MAC-less Implementation in DPAA Linux Kernel Driver P2020RDB IPV4 forwarding performance test.pdf Set up NAT on QorIQ RDB Set up VLAN on QorIQ RDB SDK/Virtualization: FTF-DES-F1254_QorIQ Device Virtualization.pdf Virtualization Solutions in Freescale Linux SDK(1)– Hypervisor(topaz) Tools/Build/Debug: FTF-DES-F1321-QorIQ-Debug.pptx AMF-DES-T1053 - Open Source Tools Development Tools for ARM® Architectures .pptx AMF-DES-T1052 - QorIQ DevTools for Layerscape Family Products Applications.pptx AMF-SNT-T1045-Freeescale-Solutions-targeting-SDN-NFV-markets-with-ARM64-processors.pptx Modify T2080 rev1.1 MEM_PLL_RAT w/ using QCVS4.1.1 Using external GNU toolchain with CodeWarrior for QorIQ LS series – ARMv7 ISA QorIQ SDK build for T4240QDS - Beginner's guide Introducing the Scenarios Tool QorIQ Linux SDK 1.6 Working With Yocto T4240QDS_Altivec_example_with_MEPL.zip Building uboot/kernel/test-application out of Yocto Changing RootFS in SDK 1.3.2 Adding a new Flash Device to Codewarrior 10.x Building SDK 1.3.2 Boot/Board: LS2085 u-boot Workflow T2080PCIeRDB_SPI_reboot failure.pdf How to Flash/Reflash U-Boot and Linux to a Freescale Digital Networking Board System Boot from SD/MMC Card with SDK 1.6 images Secure boot for Non-PBL Platform Booting from QSPI on LS102xA Firmware update for LS1-TWR Switches on PSC9131RDB Re-flashing the P3041DS Deploying SDK 1.3.2 Solutions: AMF-SNT-T1045-Freeescale-Solutions-targeting-SDN-NFV-markets-with-ARM64-processors.pptx NEXCOM Introduces Appliance Based on Freescale QorIQ T4240 SoC and Aims for Gbps UTM Throughput Others: T4240QDS_Altivec_example_with_MEPL.zip A quick demo setup to toggle hue bulb using LS1021A IoT host processor and MKW20 zigbee QorIQ_Linux_kernel_GPIO_enable.pdf Announcements I2C NCSW Use Case FTF-DES-F1253 Lunch and Learn: Expedite Your Product Development with Linux SDK Backport Technolog Processors/Cores: L1 D-Cache Flushing Using CPC as SRAM

Recently I was handling a problem of E500 Data Cache flush. I have a study on this. Below is a summary/record of the study, here to post it for someone who may be interested in. 1. L1 D-Cache Flushing About Data Cache flush, there’s some description in E500 reference manual as below: Any modified entries in the data cache can be copied back to memory (flushed) by using a dcbf instruction or by executing a series of 12 uniquely addressed load or dcbz instructions to each of the 128 sets. The address space should not be shared with any other process to prevent snoop hit invalidations during the flushing routine. Exceptions should be disabled during this time so that the PLRU algorithm is not disturbed. The following methods can be used to flush a region in the L1 cache: • Perform reads to any 48-Kbyte region, then execute dcbf instructions to that region. Note that a 48-Kbyte region must be used to ensure that the PLRU algorithm flushes all of the cache entries (12 x 128 sets x 32 bits = 48 Kbytes). • Perform reads from any 48-Kbyte region that is guaranteed to not be modified in the L1 cache (for example, a ROM region). • Execute dcbz instructions to any 48-Kbyte scratch section, then invalidate the cache. Note that it is necessary to use a scratch region because some zeroed lines will be cast out. … On the e500v2 the HID0 register contains a field, DCFA (data cache flush assist), that, when set, forces the data cache to ignore invalid sets on miss replacement selection and follow the replacement sequence defined by the PLRU bits. This reduces the series of uniquely addressed load or dcbz instructions to eight per set. The bit should be set just before beginning a cache flush routine and should be cleared when the series of instructions is complete. 2. The Questions As the Data Cache size is 32 Kbytes, why 48 Kbytes region needs to be performed on? The manual uses an equation “12 x 128 sets x 32 bytes = 48 Kbytes” (here I assume it should be 32 bytes instead of 32 bits), it says a series of 12 uniquely addressed load to each of the 128 sets, but there is no explanation why it’s 12, and why uniquely? And more, it mentions the HID0 register filed DCFA. It says setting this field reduces the series of uniquely addressed load to eight per set. Why? This time there are more words “forces the data cache to ignore invalid sets on miss replacement selection and follow the replacement sequence defined by the PLRU bits”, how to understand? 3. Data Cache Basics To answer the questions above, we need to focus on the miss replacement selection algorithm as it refers to. But before this we should be clear about the Data Cache organization first, and know the “invalid sets” status. The E500 reference manual use below figure to describe the L1 D-Cache organization From this figure, we get 128 sets, 8 ways per set, and 32 bytes per way, which is 128 x 8 x 32 = 32 Kbytes. Here a block, also called a line/way, contains 8 words, or 32 bytes. Where a piece of data in memory should be placed into D-Cache? In other words what’s the mapping method between memory and the Cache? Each block is loaded from 8-words boundary, i.e. physical address bits PA[27:31] are zeros. Byte within a block is located by PA[27:31]. The set is selected by physical address bits PA[20:26], totally 2 7 =128, there is one set for each PA[20:26], or we say it’s one to one mapping. The tags consist of physical address bit PA[0:19], there are totally 2 20 kinds of tags but there are only 8 ways in each set, it’s one to multiple mapping. So we need replacement algorithm, in e500 the PLRU (pseudo-least-recently-used) replacement algorithm is used. 4. Miss Replacement In the reference manual it says “This algorithm prioritizes the replacement of invalid entries over valid ones (starting with way 0). Otherwise, if all ways are valid, one is selected for replacement according to the PLRU bit encodings shown in Table 11-8.” This is where the difference happened. Let’s analyze the easy case first, if HID0 register filed DCFA is set, all the ways are treated the same, valid or invalid will be ignored, only PLRU take effect. Assume PLRU bits are all zeros, below table shows the order ways be selected: B0 B1 B2 B3 B4 B5 B6 Ways selected 0 0 0 0 0 0 0 L0 1 1 1 0 0 0 0 L4 0 1 1 0 0 1 0 L2 1 0 1 0 1 1 0 L6 0 0 0 0 1 1 1 L1 1 1 0 0 1 1 1 L5 0 1 1 0 1 0 1 L3 1 0 1 0 0 0 1 L7 After 8 replacements, all the 8 ways are selected. Change PLRU bits to other values it’s still 8 replacements, that’s way it reduce 12 uniquely addressed load to 8. Then why it’s 12 if DCFA field is not set? Assume way 0,1,2,3 are invalid and way 4,5,6,7 are valid, and PLRU bits are all zeros, we have again the table as below: B0 B1 B2 B3 B4 B5 B6 Ways selected 0 0 0 0 0 0 0 L0 1 1 0 1 0 0 0 L1 1 1 0 0 0 0 0 L2 1 0 0 0 1 0 0 L3 1 0 0 0 0 0 0 L4 0 0 1 0 0 1 0 L0 1 1 1 1 0 1 0 L6 0 1 0 1 0 1 1 L2 1 0 0 1 1 1 1 L5 0 0 1 1 1 0 1 L1 1 1 1 0 1 0 1 L7 After 11 replacements, all the 8 ways are selected. Assume way 0,1,2,3,6,7 are invalid and way 4,5 are valid, and PLRU B5 is zero, we have again the table as below: B0 B1 B2 B3 B4 B5 B6 Ways selected - - - - - 0 - L0 1 1 - 1 - 0 - L1 1 1 - 0 - 0 - L2 1 0 - 0 1 0 - L3 1 0 - 0 0 0 - L6 0 0 0 0 0 0 1 L7 0 0 0 0 0 0 0 L0 1 1 1 0 0 0 0 L4 0 1 1 0 0 1 0 L2 1 0 1 0 1 1 0 L6 0 0 0 0 1 1 1 L1 1 1 0 0 1 1 1 L5 After 12 replacements, all the 8 ways are selected. Here 12 is the maximum replacement number, any other case will finish all 8 ways selected within 12 replacements. There are Cache operation code examples in NCSW for e500, including L1 D-Cache flushing, as attached. Also the whole article in attached as individual document.

Sometimes you encoutner thisSD/eMMC issue ,"Card did notrespond to voltage select! ". You could add debug message to see the communication between SD/eMMC and host. #define  DEBUG #define CONFIG_MMC_TRACE  & add debug message in mmc.c (driver/mmc) int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { .. printf("CMD_SEND:%d\n",cmd->cmdidx); printf("\t\tARG\t\t\t0x%08X\n", cmd->cmdarg); .. } => mmcinfo CMD_SEND:0                ARG                     0x00000000             MMC_RSP_NONE CMD_SEND:8 ARG                     0x000001AA           MMC_RSP_R1,5,6,7        0x00000001 CMD_SEND:55 ARG                     0x00000000 MMC_RSP_R1,5,6,7         0x00000001 CMD_SEND:0 ARG                     0x00000000 MMC_RSP_NONE

        A quick demo setup to toggle hue bulb using LS1021A IoT host processor and MKW20 zigbee. Here we make a lighting  demo through two steps setup. The first step is using TWR-KW20 EVB to control hue bulb through PC tool called test tool.  The next step is moving to LS1021 as host processor instead of PC test tool.  We use KW20 USB dongle, LS1021A and Hue Bulb. KW20 USB dongle is configured as Zigbee Coordinator through Beekit and LS1021A connect this KW20 USB dongle, then LS1021A issue On/Off commands to toggle hue bulb. Then you can make a quick demo using Freescale’s LS1021A and MKW20 series

NXP T1040 and T1020 SoC have an 8-port gigabit Ethernet switch integrated on the device. QorIQ SDK includes an L2 Switch user space driver and a small demo application that uses the API provided by the switch driver. The L2Switch demo application is useful to configure switch in T1040. Attached document include steps modify the source code and add command to access switch registers, read or write, in SDK1.9. Before doing this, SDK1.9 needs to be installed and useable.  In the SDK manual, there are description about how to install the SDK, how to prepare host environment and how to setup poky for specific target.

Note (11/25): FAEs slowly replying with FAQs. This section is essentially created to help all Freescale Layerscape users ranging from customers to designers to help provide the best solution to the most frequently encountered questions and  some handy tips & tricks related to Freescale QorIQ Processing Platform products.                        Frequently Asked Questions (FAQ) Tips & Tricks QorIQ LS1 Devices QorIQ LS1 Devices QorIQ LS2 Devices QorIQ LS2 Devices Feel free to browse through the various product FAQs to get answers to most commonly encountered questions on topics like DDR3, Ethernet (eTSEC), Booting, USB, Hardware Spec/Reference Manual and more. Also browse through the tips & tricks to help you with your design. Drop a comment or two on how we can keep building these pages. Also, feel free to give your suggestions on what you feel should be added to the FAQs or to the FAQ section as a whole. We intend the Freescale Community to grow while mutually helping each other and help reduce design times by providing hands-on solution to tricky problems and questions. QorIQ LS1 Devices LS1020A/LS1021A/LS1022A FAQs LS102x FAQs LS102MA/LS1024A FAQs LS102MA/LS1024A Specific FAQs LS1043A FAQs P1020/P1011 Clocking Specific FAQs P1020/P1011 COP/JTAG Specific FAQs P1020/P1011 Ethernet (eTSEC) Specific FAQs P1020/P1011 Hardware Specifications/Reference Manual Specific FAQs P1020/P1011 IBIS Specific FAQs P1020/P1011 Local Bus Specific FAQs P1020/P1011 Memory Controller Specific FAQs P1020/P1011 Reset Configuration Specific FAQs P1020/P1011 SPI Specific FAQs [ top of page ] QorIQ LS1 Devices - Tips & Tricks                Booting P1020/P1011 from On-Chip ROM (eSDHC or eSPI) Booting P1021/P1012 from On-Chip ROM (eSDHC or eSPI) Booting P1022/P1013 from On-Chip ROM (eSDHC or eSPI) Booting to Linux from an SD Card/MMC for P1020/P1011 Booting to Linux from an SD Card/MMC for P1021/P1012 Booting to Linux from an SD Card/MMC for P1022/P1013 Enabling SD Interface on P1010 Reference Design Board Enabling SD Interface on P1023 Reference Design Board Enabling SD Interface on P1024 Reference Design Board Enabling SD Interface on P1025 Reference Design Board Hardware and Design Layout/Guidelines for P1010 DDR3 SRAM Interfaces Hardware and Design Layout/Guidelines for P1023 DDR3 SRAM Interfaces Hardware and Design  Layout/Guidelines for P1024 DDR3 SRAM Interfaces Hardware and Design Layout/Guidelines for P1025 DDR3 SRAM Interfaces [ top of page ] QorIQ LS2 Devices LS2085A FAQs P2010/P2020 Clocking Specific FAQs P2010/P2020 DDR Specific FAQs P2010/P2020 eSDHC Specific FAQs QorIQ LS2 Devices - Tips & Tricks Booting P2010 from On-Chip ROM (eSDHC or eSPI) Booting P2040/P2041 from On-Chip ROM (eSDHC or eSPI) Booting to Linux from an SD Card/MMC for P2010 Booting to Linux from an SD Card/MMC for P2040/P2041 Enabling SD Interface on P2020 Reference Design Board Hardware and Design Layout/Guidelines for P2020 DDR3 SRAM Interfaces [ top of page ]

T2080PCIe_RDB SPI reboot failure problem

This document describes rate limiting solution implementation with QoS features of SJA1105 switch to handle the congestion of competing traffic flows, including the software architecture on TSN platforms, ingress traffic policer, prioritizing configuration, Time-Aware Scheduler in 802.1Qbv engine through SJA1105 switch and using IEEE 1588(Precision Time Protocol) to synchronize the SJA1105 PTP clocks.       Software Solution Architecture on TSN Platform        Ingress Traffic Policer        Prioritizing Configuration        Time-Aware Scheduler         Using IEEE 1588 to Synchronize the SJA1105 PTP Clocks

Secure edge computing solution is required in secure manufacturing, secure Enrollment, secure device monitoring, secure container and application deployment. This documents introduces trust architecture on Layerscape platform, trust software solution and user application development with OpenSSL Engine to offload encrypt/decrypt on hardware secure module.

Many of the QorIQ processors have CPC (L3 CoreNet platform cache), such as P2040, P3041, P4080, B4860 and T1040 etc. CPC is a CoreNet-compliant target device. It could also be configured as memory-mapped SRAM, or combination of cache and SRAM. Here describe how to configure CPC to be SRAM.

This session will take an in-depth look at QorIQ Data Path Acceleration Architecture (DPAA) and how each component interact with each other and the e500mc core. Discussion will include FMAN, QMAN, BMAN, SEC4, PME, SRIO manager and RAID Engine.

Hypervisor Deployment The Freescale embedded hypervisor is a layer of software that enables the efficient and secure partitioning of a multicore system. A system's CPUs, memory, and I/O devices can be divided into groupings or partitions, as shown in the figure below. Each partition is capable of executing a guest operating system. Figure 1. Partitioning with the Hypervisor in a Multicore Environment Hypervisor DTB changes: The partitioning information is defined in hypervisor package file called hv.dts. By default, the hv.dts file has only 2 interfaces and a mac-less interface defined per partition.  For IPSec demo we need to place all the interfaces within the 1st partition and the attached file has the full source code details. To extract the HV DTB source code, use the bitbake command: bitbake -c patch hv-cfg Build the final binaries using the bitbake command: bitbake fsl-image-core The above command would compile all the binaries required (including hv-2p-lnx-lnx.dtb) Now, the kernel, hypervisor image, device tree, hypervisor device tree and ramdisk filesystem can be flashed onto the board. These steps should be done assuming the user already has switched to the alternate bank.             Step 1: Programming Kernel to Flash TFTP the kernel image to RAM, then copy it to the flash address 0xe8020000. Execute the following commands at the U-Boot prompt to program the kernel to flash: =>tftp 1000000 uImage-t1040rdb.bin =>erase e8020000 +$filesize =>cp.b 1000000 e8020000 $filesize Step 2: Programming Ramdisk Filesystem to Flash TFTP the ramdisk file system to RAM, then copy it to the flash at address 0xe9300000. Execute the following commands at U-Boot prompt to program the ramdisk to flash: =>tftp 1000000 fsl-image-core-t1040rdb.ext2.gz.u-boot =>erase e9300000 +$filesize =>cp.b 1000000 e9300000 $filesize Step 3: Programming Hypervisor Image to Flash TFTP the hypervisor images to RAM, then copy it to the flash at address 0xe8700000. Execute the following commands at U-Boot prompt to program the hypervisor image to flash: =>tftp 1000000 hv.uImage =>erase e8700000 +$filesize =>cp.b 1000000 e8700000 $filesize Step 4: Programming Kernel dtb to Flash TFTP the kernel dtb file to ram, then copy it to the flash at address 0xe8800000. Execute the following commands at U-Boot prompt to program the kernel dtb to flash: Target Deployment - for hv-2p mode deployment: =>tftp 1000000 uImage-t1040rdb.dtb =>erase e8800000 +$filesize =>cp.b 1000000 e8800000 $filesize Program "hv-2p-lnx-lnx.dtb" to 0xe8900000 =>tftp 1000000 hv-2p-lnx-lnx.dtb =>erase e8900000 +$filesize =>cp.b 1000000 e8900000 $filesize           Step 5: Booting Up the System As of now, all the DPAA devices on this platform are given to partition 1. The kernel can boot up automatically after the board is powered on with the correct U-Boot environment. The following command can also be used to boot up the board at U-Boot prompt: =>setenv bootargs config-addr=0xfe8900000 console=ttyS0,115200 =>setenv bootcmd 'bootm 0xfe8700000 - 0xfe8800000' =>saveenv =>boot Step 6: Setup IPSec demo as described in the following link IPSec demo on T1040RDB

SPDK (Storage Performance Development Kit) is an optimized storage reference architecture. It is initiated and developed by Intel. SPDK provides a set of tools and libraries for writing high performance, scalable, user-mode storage applications. It achieves high performance by moving all of the necessary drivers into userspace and operating in a polled mode, like DPDK.

I have the p2041rdb Borad. (P2041RDB-PB) I got the vxWorks BSP from the WindRiber site. I read a target.ref file. then compiled the bootrom and kernel. I can the Tffs, SATA, .. but I can't Pcie. shell log -> **************************************************************************************************************************************** >vxBusShow Registered Bus Types:   MII_Bus @ 0x002eb1ec   PCI_Bus @ 0x002eae5c   PLB_Bus @ 0x002eae78 Registered Device Drivers:   ppcIntCtlr at 0x002e92c4 on bus PLB_Bus, funcs @ 0x002e92b8   m85xxTimerDev at 0x002eada8 on bus PLB_Bus, funcs @ 0x002ead8c   fslSata at 0x002eb2f8 on bus PLB_Bus, funcs @ 0x002eb2e0   fslDma at 0x002e9f28 on bus PLB_Bus, funcs @ 0x002e9f1c   epic at 0x002ea0bc on bus PLB_Bus, funcs @ 0x002ea068   dtsec at 0x002eb0d0 on bus PLB_Bus, funcs @ 0x002eb000   ns16550 at 0x002ea4a8 on bus PLB_Bus, funcs @ 0x002ea3d8   ns16550 at 0x002ea460 on bus PCI_Bus, funcs @ 0x002ea3d8   dtsecMdio at 0x002eb2a0 on bus PLB_Bus, funcs @ 0x002eb274   genericPhy at 0x002eb234 on bus MII_Bus, funcs @ 0x002eb228   miiBus at 0x002eb1a4 on bus PCI_Bus, funcs @ 0x002eb148   miiBus at 0x002eb164 on bus PLB_Bus, funcs @ 0x002eb148   m85xxPci at 0x002e9e38 on bus PLB_Bus, funcs @ 0x002e9e2c   m85xxCCSR at 0x002ea134 on bus PLB_Bus, funcs @ 0x002ea128   QorIQFman at 0x002ea270 on bus PLB_Bus, funcs @ 0x002ea254   QorIQBman at 0x002ea214 on bus PLB_Bus, funcs @ 0x002ea1f8   fslGpio at 0x002ea1b8 on bus PLB_Bus, funcs @ 0x002ea19c   QorIQQman at 0x002ea350 on bus PLB_Bus, funcs @ 0x002ea32c   QorIQPciEx at 0x002e9edc on bus PLB_Bus, funcs @ 0x002e9e78   QorIQLaw at 0x002ea2ec on bus PLB_Bus, funcs @ 0x002ea2b0   plbCtlr at 0x002eaea0 on bus PLB_Bus, funcs @ 0x002eae94 Busses and Devices Present:   PLB_Bus @ 0x002fe368 with bridge @ 0x002eaee0     Device Instances:         ppcIntCtlr unit 0 on PLB_Bus @ 0x002ff328 with busInfo 0x00000000         epic unit 0 on PLB_Bus @ 0x002ff428 with busInfo 0x00000000         ns16550 unit 0 on PLB_Bus @ 0x002ff628 with busInfo 0x00000000         ns16550 unit 1 on PLB_Bus @ 0x002ff828 with busInfo 0x00000000         ns16550 unit 2 on PLB_Bus @ 0x002ffa28 with busInfo 0x00000000         ns16550 unit 3 on PLB_Bus @ 0x002ffc28 with busInfo 0x00000000         fslGpio unit 0 on PLB_Bus @ 0x002ffe28 with busInfo 0x00000000         QorIQLaw unit 0 on PLB_Bus @ 0x002fff28 with busInfo 0x0         QorIQBman unit 0 on PLB_Bus @ 0x00300028 with busInfo 0x00000000         QorIQQman unit 0 on PLB_Bus @ 0x00300128 with busInfo 0x00000000         QorIQFman unit 0 on PLB_Bus @ 0x00300228 with busInfo 0x00000000         QorIQPciEx unit 1 on PLB_Bus @ 0x0030d328 with busInfo 0x00000000         dtsec unit 0 on PLB_Bus @ 0x0030d628 with busInfo 0x0         dtsec unit 1 on PLB_Bus @ 0x0030d728 with busInfo 0x0         dtsec unit 2 on PLB_Bus @ 0x0030d828 with busInfo 0x0         dtsec unit 3 on PLB_Bus @ 0x0030d928 with busInfo 0x0         dtsec unit 4 on PLB_Bus @ 0x0030da28 with busInfo 0x0         dtsecMdio unit 0 on PLB_Bus @ 0x0030db28 with busInfo 0x00000000         m85xxTimerDev unit 0 on PLB_Bus @ 0x0030dc28 with busInfo 0x00000000         fslSata unit 0 on PLB_Bus @ 0x0030dd28 with busInfo 0x00000000         fslSata unit 1 on PLB_Bus @ 0x0030de28 with busInfo 0x00000000         fslDma unit 0 on PLB_Bus @ 0x0030df28 with busInfo 0x00000000         fslDma unit 1 on PLB_Bus @ 0x0030e028 with busInfo 0x00000000         miiBus unit 0 on PLB_Bus @ 0x0030e128 with busInfo 0x002fefa8         miiBus unit 1 on PLB_Bus @ 0x00312328 with busInfo 0x002fef68         miiBus unit 2 on PLB_Bus @ 0x00312528 with busInfo 0x002fefe8         miiBus unit 3 on PLB_Bus @ 0x00312728 with busInfo 0x002ff028         miiBus unit 4 on PLB_Bus @ 0x00312928 with busInfo 0x002ff068     Orphan Devices:   MII_Bus @ 0x002fefa8 with bridge @ 0x0030e128     Device Instances:         genericPhy unit 0 on MII_Bus @ 0x0030e228 with busInfo 0x00000000     Orphan Devices:   MII_Bus @ 0x002fef68 with bridge @ 0x00312328     Device Instances:         genericPhy unit 1 on MII_Bus @ 0x00312428 with busInfo 0x00000000     Orphan Devices:   MII_Bus @ 0x002fefe8 with bridge @ 0x00312528     Device Instances:         genericPhy unit 2 on MII_Bus @ 0x00312628 with busInfo 0x00000000     Orphan Devices:   MII_Bus @ 0x002ff028 with bridge @ 0x00312728     Device Instances:         genericPhy unit 3 on MII_Bus @ 0x00312828 with busInfo 0x00000000     Orphan Devices:   MII_Bus @ 0x002ff068 with bridge @ 0x00312928     Device Instances:         genericPhy unit 4 on MII_Bus @ 0x00312a28 with busInfo 0x00000000     Orphan Devices: value = 1 = 0x1 -> pciDeviceShow value = -1 = 0xffffffff **************************************************************************************************************************************** I used rcw file that rcw_5g_1500mhz.bin (RR_PH_0x19)

The flow is on sector 3.4.20.10.4 in QorIQ-SDK-1_7-IC-RevA, but it is wrong. So, please follow the steps in the attachment.

More and more customers are using the Freescale Linux SDK/BSP for customized development, however, some use a stable but old kernel version. This is different from the Freescale publicly released SDK. In order to manage the gap and help apply the Freescale SDK/BSP more efficiently, Freescale provides backported Linux SDK/BSP according to the customer's kernel version requirements. This lecture summarizes the strategy and key technology of the backport, introduces the latest proactive backport model based on git release and will help expedite product development using Freescale Linux releases.

This presentation starts by giving  introduction to SDN (Software Defined Networking) and NFV (Network Function Virtualization) technology.  It provides overview of performance challenges and how Freescale hardware & software solutions help in mitigating the performance challenges.