DPDMUX is a device like DPSW (Switch) which allows switching of packets within the DPAA2 blocks. This application adds DPDMUX support in DPDK, uses LS2088ARDB as an example platform for demonstrating the use case that traffic bifurcation between DPDK and Linux Kernel using DPDMUX on DPAA2 platform.

Sometimes you encoutner thisSD/eMMC issue ,"Card did notrespond to voltage select! ". You could add debug message to see the communication between SD/eMMC and host. #define  DEBUG #define CONFIG_MMC_TRACE  & add debug message in mmc.c (driver/mmc) int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { .. printf("CMD_SEND:%d\n",cmd->cmdidx); printf("\t\tARG\t\t\t0x%08X\n", cmd->cmdarg); .. } => mmcinfo CMD_SEND:0                ARG                     0x00000000             MMC_RSP_NONE CMD_SEND:8 ARG                     0x000001AA           MMC_RSP_R1,5,6,7        0x00000001 CMD_SEND:55 ARG                     0x00000000 MMC_RSP_R1,5,6,7         0x00000001 CMD_SEND:0 ARG                     0x00000000 MMC_RSP_NONE

The Precision Time Protocol (PTP) is a protocol used to synchronize clock throughout a computer network. PTP was originally defined in IEEE1588-2002 standard. To use PTP functionality in DPDK, users can use DPDK example application “ptpclient” present in DPDK source code, ptpclient application uses DPDK IEEE1588 API to communicate with a PTP master clock to synchronize the time on NIC and, optionally, on the Linux system. IEEE1588 Introduction Compile the Application Running the Application Code Explanation

This is the P2020RDB IPV4 forwarding performace test using SmartBit.

This presentation starts by giving  introduction to SDN (Software Defined Networking) and NFV (Network Function Virtualization) technology.  It provides overview of performance challenges and how Freescale hardware & software solutions help in mitigating the performance challenges.

Secure edge computing solution is required in secure manufacturing, secure Enrollment, secure device monitoring, secure container and application deployment. This documents introduces trust architecture on Layerscape platform, trust software solution and user application development with OpenSSL Engine to offload encrypt/decrypt on hardware secure module.

Time Sensitive Networking(TSN) is an extension to traditional Ethernet networks, providing a set of standards compatible with IEEE 802.1 and 802.3. TSN aims to provide guarantees for deterministic latency and packet loss under congestion, allowing critical and non-critical traffic to be converged in the same network. This document introduces basic concept of Time Sensitive Networking, LS1028 TSN switch and using TSN features on LS1028ARDB. TSN Introduction TSN in LS1028 Using TSN features on LS1028ARDB

This application note describes how to write u-boot in SD/MMC card with boot-format application for non-PBL platform. Use QorIQ Configuration Suite (QCS) PBL tool to generate PBL images for Corenet platform SD boot. Deploy Rootfs filesystem to boot Kernel and filesystem from SD/MMC card.

        A quick demo setup to toggle hue bulb using LS1021A IoT host processor and MKW20 zigbee. Here we make a lighting  demo through two steps setup. The first step is using TWR-KW20 EVB to control hue bulb through PC tool called test tool.  The next step is moving to LS1021 as host processor instead of PC test tool.  We use KW20 USB dongle, LS1021A and Hue Bulb. KW20 USB dongle is configured as Zigbee Coordinator through Beekit and LS1021A connect this KW20 USB dongle, then LS1021A issue On/Off commands to toggle hue bulb. Then you can make a quick demo using Freescale’s LS1021A and MKW20 series

When will you have the final version of the ASK append RCX? The final version is already set for mass production. How do you use the crypto engine? The OCF (Open BSD Cryptogrpahic Framework) is a service virtualization layer implemented inside the kernel that provides uniform access to accelerator functionality by hiding card-specific details behind a carefully designed API.  The LS1024A provides an OCF-based cryptographic driver interfacing Linux security applications and the LS1024A Elliptic 1802 crypto accelerator. What is CMM? CMM stands for Conntrack Monitor Module.  It monitors the Linux connection table and adds/removes connection from the PFE connection table. I get an error when adding a bridge entry via CMM. This error usually crops up if a manual bridge command is attempted while the auto-bridge module (ABM) is disabled.  Try enabling the module then make the bridge in Linux.  The ABM will see this and set up PFE appropriately without you having to do any manual bridging commands. What are the power ramping requirements? The power ramping curve of the LS1024A is linear.  Power supplies will begin at almost the same time, but usually from low voltage to high voltage.  Refer to Section 31.2 of the QorIQ LS1024A Data Sheet for further information on this topic. My RTP Relay isn't working properly. Check that the correct sockets have been created properly. How do I make the RGMII work (RGMII delay)? The LS1024A does not have internal RGMII clock/data delays.  The delay element must be enabled in the external device (switch/PHY), or something must be taken care of in layout, which is not recommended.  Typical symptoms are that the GEMAC can only transfer at low speeds (e.g. 10kbps), or the GEMAC can work at 100Mbps/full duplex, but not at 1000Mbps.

Hi all, One of the function of this patch is to add MD5 authentication support in Kernel2.6.35. Another is when user set a specific IPSEC encryption and authentication, it will display the information through console. BTW, I'm using P1010RDB for verification. Share with you guys~ 1.       drivers\crypto\caam\Algapi.c +          #define printf(args...)  printk(args) +          #define printf(args...)  printk(args) . . . 164         switch (authsize * 😎 { 165         case 96: 166         -                              if (ctx->alg_op != OP_ALG_ALGSEL_SHA1) { 167         -                                              dev_err(dev, "h/w doesn't support %d-bit ICV trunc." 168         -                                                              " length with chosen authentication algorithm", 169         -                                                              authsize * 8); 170         -                                              return -EOPNOTSUPP; 171         -                              } 172         -                              ctx->class2_alg_type = AUTH_TYPE_IPSEC_SHA1HMAC_96; +                             if (ctx->alg_op == OP_ALG_ALGSEL_MD5){ +                                              ctx->class2_alg_type = AUTH_TYPE_IPSEC_MD5HMAC_96; +                                             printf("AUTH_TYPE : MD5\n"); +                                             if (ctx->class1_alg_type == CIPHER_TYPE_IPSEC_AESCBC) +                                                            printf("ALO_TYPE : AES\n"); +                                             else if (ctx->class1_alg_type == CIPHER_TYPE_IPSEC_3DESCBC) +                                                            printf("ALO_TYPE : 3DES\n"); +                                             else if (ctx->class1_alg_type == CIPHER_TYPE_IPSEC_DESCBC) +                                                            printf("ALO_TYPE : DES\n"); +                              } +                              else if (ctx->alg_op == OP_ALG_ALGSEL_SHA1){ +                                             ctx->class2_alg_type = AUTH_TYPE_IPSEC_SHA1HMAC_96; +                                             printf("AUTH_TYPE : SHA1\n"); +                             if (ctx->class1_alg_type == CIPHER_TYPE_IPSEC_AESCBC) +                                                            printf("ALO_TYPE : AES\n"); +                             else if (ctx->class1_alg_type == CIPHER_TYPE_IPSEC_3DESCBC) +                                                            printf("ALO_TYPE : 3DES\n"); +                             else if (ctx->class1_alg_type == CIPHER_TYPE_IPSEC_DESCBC) +                                                            printf("ALO_TYPE : DES\n"); +                             } +                             else { +                                             dev_err(dev, "h/w doesn't support %d-bit ICV trunc." +                                              " length with chosen authentication algorithm", +                                              authsize * 8); +                                             return -EOPNOTSUPP; +                              }                                                                break; . . . 1243       static struct caam_alg_template driver_algs[] = { 1244                       /* single-pass ipsec_esp descriptor */ +             { +                             .name = "authenc(hmac(md5),cbc(aes))", +                             .driver_name = "authenc-hmac-md5-cbc-aes-caam", +                             .blocksize = AES_BLOCK_SIZE, +                             .aead = { +                                             .setkey = aead_authenc_setkey, +                                             .setauthsize = aead_authenc_setauthsize, +                                             .encrypt = aead_authenc_encrypt_first, +                                             .decrypt = aead_authenc_decrypt_first, +                                             .givencrypt = aead_authenc_givencrypt_first, +                                             .geniv = "<built-in>", +                                             .ivsize = AES_BLOCK_SIZE, +                                             .maxauthsize = MD5_DIGEST_SIZE, +                                             }, +                             .class1_alg_type = CIPHER_TYPE_IPSEC_AESCBC, +                             .class2_alg_type = AUTH_TYPE_IPSEC_MD5HMAC_96, +                             .alg_op = OP_ALG_ALGSEL_MD5, +                             }, +             { +                             .name = "authenc(hmac(md5),cbc(des3_ede))", +                             .driver_name = "authenc-hmac-md5-cbc-des3_ede-caam", +                             .blocksize = DES3_EDE_BLOCK_SIZE, +                             .aead = { +                                             .setkey = aead_authenc_setkey, +                                             .setauthsize = aead_authenc_setauthsize, +                                             .encrypt = aead_authenc_encrypt_first, +                                             .decrypt = aead_authenc_decrypt_first, +                                             .givencrypt = aead_authenc_givencrypt_first, +                                             .geniv = "<built-in>", +                                             .ivsize = DES3_EDE_BLOCK_SIZE, +                                             .maxauthsize = MD5_DIGEST_SIZE, +                                             }, +                             .class1_alg_type = CIPHER_TYPE_IPSEC_3DESCBC, +                             .class2_alg_type = AUTH_TYPE_IPSEC_MD5HMAC_96, +                             .alg_op = OP_ALG_ALGSEL_MD5, +             }, +             { +                             .name = "authenc(hmac(md5),cbc(des))", +                             .driver_name = "authenc-hmac-md5-cbc-des-caam", +                             .blocksize = DES_BLOCK_SIZE, +                             .aead = { +                                             .setkey = aead_authenc_setkey, +                                             .setauthsize = aead_authenc_setauthsize, +                                             .encrypt = aead_authenc_encrypt_first, +                                             .decrypt = aead_authenc_decrypt_first, +                                             .givencrypt = aead_authenc_givencrypt_first, +                                             .geniv = "<built-in>", +                                             .ivsize = DES_BLOCK_SIZE, +                                             .maxauthsize = MD5_DIGEST_SIZE, +                                             }, +                             .class1_alg_type = CIPHER_TYPE_IPSEC_DESCBC, +                             .class2_alg_type = AUTH_TYPE_IPSEC_MD5HMAC_96, +                             .alg_op = OP_ALG_ALGSEL_MD5, +             }, 1245                       { 1246                                       .name = "authenc(hmac(sha1),cbc(aes))", 1247                                       .driver_name = "authenc-hmac-sha1-cbc-aes-caam", . . 2.       drivers\crypto\caam\compat.h 58           #include <crypto/algapi.h> 59           #include <crypto/aes.h> 60           #include <crypto/des.h> 61           #include <crypto/sha.h> +             #include <crypto/md5.h> 62           #include <crypto/aead.h> 63           #include <crypto/authenc.h> 64           #include <crypto/scatterwalk.h>

This section is essentially created to help all QorIQ Processing Platform users ranging from customers to designers to help provide the best solution to the most frequently encountered questions and  some handy tips & tricks related to QorIQ Processing Platform products.                                                   Frequently Asked Questions (FAQ) Tips & Tricks QorIQ P1 Devices QorIQ P1 Devices QorIQ P2 Devices QorIQ P2 Devices QorIQ P3 Devices QorIQ P3 Devices QorIQ P4 Devices QorIQ P4 Devices QorIQ P5 Devices QorIQ P5 Devices Feel free to browse through the various product FAQs to get answers to most commonly encountered questions on topics like DDR3, Ethernet (eTSEC), Booting, USB, Hardware Spec/Reference Manual and more. Also browse through the tips & tricks to help you with your design. Drop a comment or two on how we can keep building these pages. Also, feel free to give your suggestions on what you feel should be added to the FAQs or to the FAQ section as a whole. We intend the NXP Community to grow while mutually helping each other and by reducing design times by providing hands-on solution to tricky problems and questions. QorIQ P1 Devices P1010/1014 FAQs P1010/P1014 DDR Specific FAQs P1010/P1014 Ethernet (eTSEC) Specific FAQs P1010/P1014 USB Specific FAQs P1020/P1011 FAQs P1020/P1011 Clocking Specific FAQs P1020/P1011 COP/JTAG Specific FAQs P1020/P1011 Ethernet (eTSEC) Specific FAQs P1020/P1011 Hardware Specifications/Reference Manual Specific FAQs P1020/P1011 IBIS Specific FAQs P1020/P1011 Local Bus Specific FAQs P1020/P1011 Memory Controller Specific FAQs P1020/P1011 Reset Configuration Specific FAQs P1020/P1011 SPI Specific FAQs P1021/P1012 FAQs P1021/P1012 eSPI/FLASH Specific FAQs P1021/P1012 Ethernet (eTSEC) Specific FAQs P1021/P1012 Memory Controller/DDR Specific FAQs P1022/P1013 FAQs P1022/P1013 Clocking Specific FAQs P1022/P1013 DDR Specific FAQs P1022/P1013 Hardware    Specifications/Reference Manual Specific FAQs P1022/P1013 PCIe Specific FAQs P1022/P1013 Power Management Specific FAQs P1023/P1017 FAQs P1023/P1017 Clocking Specific FAQs P1023/P1017 DDR Specific FAQs P1023/P1017 PCIe Specific FAQs P1024/P1015 FAQs P1024/P1015 Clocking Specific FAQs P1024/P1015 eSPI/FLASH Specific FAQs P1024/P1015 Ethernet Specific FAQs P1024/P1015 Reset Configuration Specific FAQs P1024/P1015 Software Tools - CodeWarrior Specific FAQs P1025/P1016 FAQs P1025/P1016 Clocking Specific FAQs P1025/P1016 DDR Specific FAQs P1025/P1016 Hardware Specifications/Reference Manual Specific FAQs P1025/P1016 QUICC Engine Specific FAQs [ top of page ] QorIQ P1 Devices - Tips & Tricks                                            Booting P1020/P1011 from On-Chip ROM (eSDHC or eSPI) Booting P1021/P1012 from On-Chip ROM (eSDHC or eSPI) Booting P1022/P1013 from On-Chip ROM (eSDHC or eSPI) Booting to Linux from an SD Card/MMC for P1020/P1011 Booting to Linux from an SD Card/MMC for P1021/P1012 Booting to Linux from an SD Card/MMC for P1022/P1013 Enabling SD Interface on P1010 Reference Design Board Enabling SD Interface on P1023 Reference Design Board Enabling SD Interface on P1024 Reference Design Board Enabling SD Interface on P1025 Reference Design Board Hardware and Design Layout/Guidelines for P1010 DDR3 SRAM Interfaces Hardware and Design Layout/Guidelines for P1023 DDR3 SRAM Interfaces Hardware and Design  Layout/Guidelines for P1024 DDR3 SRAM Interfaces Hardware and Design Layout/Guidelines for P1025 DDR3 SRAM Interfaces [ top of page ] QorIQ P2 Devices P2010/P2020 FAQs P2010/P2020 Clocking Specific FAQs P2010/P2020 DDR Specific FAQs P2010/P2020 eSDHC Specific FAQs P2040/P2041 FAQs P2040/P2041 Clocking Specific FAQs P2040/P2041 Ethernet Specific FAQs P2040/P2041 Local Bus Specific FAQs P2040/P2041 PCIe Specific FAQs P2040/P2041 Pre-Boot Loader/Boot Sequencer Specific FAQs P2040/P2041 USB Specific FAQs P2040/P2041Hardware Specifications/Reference Manual Specific FAQs [ top of page ] QorIQ P2 Devices - Tips & Tricks    Booting P2010 from On-Chip ROM (eSDHC or eSPI) Booting P2040/P2041 from On-Chip ROM (eSDHC or eSPI) Booting to Linux from an SD Card/MMC for P2010 Booting to Linux from an SD Card/MMC for P2040/P2041 Enabling SD Interface on P2020 Reference Design Board Hardware and Design Layout/Guidelines for P2020 DDR3 SRAM Interfaces [ top of page ] QorIQ P3 Devices P3041 FAQs P3041 DDR Specific FAQs P3041 Ethernet Specific FAQs P3041 Hardware Specifications/Reference Manual Specific FAQs P3041 USB Specific FAQs [ top of page ] QorIQ P3 Devices - Tips & Tricks Hardware and Design Layout/Guidelines for P3041 DDR3 SRAM Interfaces [ top of page ] QorIQ P4 Devices                   P4040 FAQs P4040 Clocking Specific FAQs P4040 eSPI/FLASH Specific FAQs P4040 Ethernet Specific FAQs P4040 Reset Configuration Specific FAQs P4040 Software Tools - CodeWarrior Specific FAQs P4080 FAQs P4080 DDR Specific FAQs P4080 Ethernet Specific FAQs P4080 Hardware Specifications/Reference Manual Specific FAQs P4080 USB Specific FAQs [ top of page ] QorIQ P4 Devices - Tip & Tricks Booting P4080 from On-Chip ROM (eSDHC or eSPI) Booting to Linux from an SD Card/MMC for P4080 Hardware and Design Layout/Guidelines for P4040 DDR3 SRAM Interfaces [ top of page ] QorIQ P5 Devices P5020/P5010 FAQs P5020/P5010 COP/JTAG Specific FAQs P5020/P5010 Device Ratings Specific FAQs P5020/P5010 Hardware Specifications/Reference Manual Specific FAQs [ top of page ] QorIQ P5 Devices - Tips & Tricks Booting P5010 from On-Chip ROM (eSDHC or eSPI) Booting to Linux from an SD Card/MMC for P5010 Hardware and Design Layout/Guidelines for P5020 DDR3 SRAM Interfaces [ top of page ]

T4160 Block Diagram

Simple example T4240QDS project that incorporates the Mentor Graphics Embedded Performance Library (MEPL) to add Altivec coding.

Note (11/25): FAEs slowly replying with FAQs. This section is essentially created to help all Freescale Layerscape users ranging from customers to designers to help provide the best solution to the most frequently encountered questions and  some handy tips & tricks related to Freescale QorIQ Processing Platform products.                        Frequently Asked Questions (FAQ) Tips & Tricks QorIQ LS1 Devices QorIQ LS1 Devices QorIQ LS2 Devices QorIQ LS2 Devices Feel free to browse through the various product FAQs to get answers to most commonly encountered questions on topics like DDR3, Ethernet (eTSEC), Booting, USB, Hardware Spec/Reference Manual and more. Also browse through the tips & tricks to help you with your design. Drop a comment or two on how we can keep building these pages. Also, feel free to give your suggestions on what you feel should be added to the FAQs or to the FAQ section as a whole. We intend the Freescale Community to grow while mutually helping each other and help reduce design times by providing hands-on solution to tricky problems and questions. QorIQ LS1 Devices LS1020A/LS1021A/LS1022A FAQs LS102x FAQs LS102MA/LS1024A FAQs LS102MA/LS1024A Specific FAQs LS1043A FAQs P1020/P1011 Clocking Specific FAQs P1020/P1011 COP/JTAG Specific FAQs P1020/P1011 Ethernet (eTSEC) Specific FAQs P1020/P1011 Hardware Specifications/Reference Manual Specific FAQs P1020/P1011 IBIS Specific FAQs P1020/P1011 Local Bus Specific FAQs P1020/P1011 Memory Controller Specific FAQs P1020/P1011 Reset Configuration Specific FAQs P1020/P1011 SPI Specific FAQs [ top of page ] QorIQ LS1 Devices - Tips & Tricks                Booting P1020/P1011 from On-Chip ROM (eSDHC or eSPI) Booting P1021/P1012 from On-Chip ROM (eSDHC or eSPI) Booting P1022/P1013 from On-Chip ROM (eSDHC or eSPI) Booting to Linux from an SD Card/MMC for P1020/P1011 Booting to Linux from an SD Card/MMC for P1021/P1012 Booting to Linux from an SD Card/MMC for P1022/P1013 Enabling SD Interface on P1010 Reference Design Board Enabling SD Interface on P1023 Reference Design Board Enabling SD Interface on P1024 Reference Design Board Enabling SD Interface on P1025 Reference Design Board Hardware and Design Layout/Guidelines for P1010 DDR3 SRAM Interfaces Hardware and Design Layout/Guidelines for P1023 DDR3 SRAM Interfaces Hardware and Design  Layout/Guidelines for P1024 DDR3 SRAM Interfaces Hardware and Design Layout/Guidelines for P1025 DDR3 SRAM Interfaces [ top of page ] QorIQ LS2 Devices LS2085A FAQs P2010/P2020 Clocking Specific FAQs P2010/P2020 DDR Specific FAQs P2010/P2020 eSDHC Specific FAQs QorIQ LS2 Devices - Tips & Tricks Booting P2010 from On-Chip ROM (eSDHC or eSPI) Booting P2040/P2041 from On-Chip ROM (eSDHC or eSPI) Booting to Linux from an SD Card/MMC for P2010 Booting to Linux from an SD Card/MMC for P2040/P2041 Enabling SD Interface on P2020 Reference Design Board Hardware and Design Layout/Guidelines for P2020 DDR3 SRAM Interfaces [ top of page ]

What IDE is recommended for programming the LS1020A/LS1021A/LS1022A? The LS1 series is optimized for CodeWarrior, whose latest version, for ARMv7 can be found at http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=CW-LS-ARM7&fsrch=1. What is the LS102xA product family's enablement schedule up to 2016? The launch calendar for the LS102xA family is shown in the figure below. Can one CodeWarrior license cover both LS102x QDS and TWR? The full CW product can be used with either the TWR or QDS board through the CW-TAP probe. Does CodeWarrior for LS1 support flash (NOR/NAND) programming? Yes, CodeWarrior supports both NOR and NAND programming for QDS and TWR. Over what power range is LS102x designed for? LS102x is designed for operation under 3W.  Its ability to yield over 5000 Coremarks at a frequency of up to 1GHz separates the LS102x family from competitors in delivering improved performance without increased power consumption. How fast does the LS102x family run? The LS102x family can run between 600 MHz and and 1 GHz. What endianness does LS102x follow? The LS1 is based on the ARMv7 architecture, which is natively little-endian.  However, ARMv7 supports big-endian using the CPC15 register.  More significantly, many LS1 peripherals, like Ethernet and integrated flash controller (IFC), follow big-endian.  Therefore, LS1 is really a mixed-endian system and one must be mindful of a peripheral's endianness when programming the LS1.

ARM Cortex A57 and A53 L1/L2 cache error reporting The attached patch adds error detection for A53 and A57 cores. Hardware error injection is supported on A53. Software error injection is supported on both. For hardware error injection on A53 to work, proper access to L2ACTLR_EL1, CPUACTLR_EL1 needs to be granted by EL3 firmware. This is done by making an SMC call in the driver. Failure to enable access disables hardware error injection. For error interrupt to work, another SMC call enables access to L2ECTLR_EL1. Failure to enable access disables interrupt for error reporting.   CPU Memory Error Syndrome and L2 Memory Error Syndrome registers can be used for checking L1 and L2 memory errors. However, only A53 supports double-bit error injection to L1 and L2 memory. This driver uses the hardware error injection when available, but also provides a way to inject errors by software. Both A53 and A57 supports interrupt when multi-bit errors happen.   To use hardware error injection and the interrupt, proper access needs to be granted in ACTLR_EL3 (and/or ACTLR_EL2) register by EL3 firmware SMC call. Correctable errors do not trigger such interrupt. This driver uses dynamic polling internal to check for errors. The more errors detected, the more frequently it polls. Combining with interrupt, this driver can detect correctable and uncorrectable errors. However, if the uncorrectable errors cause system abort exception, this driver is not able to report errors in time.     Building PPA Image Please make sure the PPA source which you are using includes commit 781d7b513c2b44e7, PPA source code in LSDK later than1809, which includes this commit, so you could use PPA image provided in LSDK 1809 or the later release. In addition, You need to enable "dbg" when building PPA. If you use LSDK build environment, please add "dbg" in ppa build command in packages/firmware/Makefile as the following, then rebuild ppa with command "$ flex-builder -c ppa -m ls1043ardb" and get ppa image in build/firmware/ppa/soc-ls1043/ppa.itb. socname=`echo $(MACHINE)|tr -cd [:digit:]` && \ ./build rdb-fit dbg ls$$socname && cp soc-ls$$socname/build/obj/ppa.itb $(FBDIR)/build/firmware/ppa/soc-ls$$socname && \ If you want build PPA manually with the standalone Toolchain, you could build PPA image with the command "./build prod rdb-fit dbg ls1043". Please deploy PPA image at 0x60400000 on NOR flash(the current bank).   L1/L2 cache error detection and correction EDAC feature verification   NXP LSDK 19.03 devel localhost login: root Password: Last login: Fri May 17 00:11:26 UTC 2019 on ttyS0 Welcome to NXP LSDK 19.03 devel (GNU/Linux 4.14.16-dirty aarch64)    * Support:        https://www.nxp.com/lsdk  * Documentation:  https://lsdk.github.io setting 31 rows and 111 columns root@localhost:~# ls /sys/devices/system/edac/cpu_cache/ cpu_cache0  l1_ce_sw_inject  l1_ue_sw_inject  l2_ue_hw_inject  log_ce  panic_on_ue device      l1_ue_hw_inject  l2_ce_sw_inject  l2_ue_sw_inject  log_ue  poll_msec   root@localhost:~#  echo 1 > /sys/devices/system/edac/cpu_cache/l1_ue_sw_inject root@localhost:~# [   74.831916] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 0 [   74.831916] ' echo 1 > /sys/devices/system/edac/cpu_cache/l1_ue_hw_inject^C root@localhost:~# echo 1 > /sys/devices/system/edac/cpu_cache/l1_ue_hw_inject [   80.192338] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 1 [   80.192338] ' root@localhost:~# root@localhost:~# root@localhost:~# echo 1 > /sys/devices/system/edac/cpu_cache/l1_ue_sw_inject root@localhost:~# [  109.647966] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 0 [  109.647966] ' [  109.659012] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 1 [  109.659012] '   root@localhost:~# echo 1 > /sys/devices/system/edac/cpu_cache/l1_ue_sw_inject root@localhost:~# [  136.271980] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 0 [  136.271980] ' [  136.283027] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 1 [  136.283027] '   root@localhost:~# echo 1 > /sys/devices/system/edac/cpu_cache/l1_ue_hw_inject [  157.352298] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 2 [  157.352298] ' root@localhost:~# echo 1 > /sys/devices/system/edac/cpu_cache/l2_ue_sw_inject root@localhost:~# [  183.375947] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L2 'Fatal error(s) on CPU 0 [  183.375947] '   root@localhost:~#  echo 1 > /sys/devices/system/edac/cpu_cache/l2_ue_hw_inject [  186.928679] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L2 'Fatal error(s) on CPU 0 [  186.928679] ' root@localhost:~# [  191.055944] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L2 'Fatal error(s) on CPU 0 [  191.055944] '   root@localhost:~# dmesg | grep EDAC [    1.819380] EDAC MC: Ver: 3.0.0 [    3.423554] EDAC DEVICE0: Giving out device to module edac-a53 controller cortex_edac_l1_l2: DEV edac-a53 (POLLED) [   74.831898] EDAC cortex_edac_l1_l2: CPU 0 L1-I Tag RAM error(s) detected [   74.831910] EDAC cortex_edac_l1_l2: CPU 0 L1 fatal error(s) detected (0x8000000080000000) [   74.831916] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 0 [   80.192307] EDAC cortex_edac_l1_l2: CPU 1 L1-D Data RAM error(s) detected [   80.192326] EDAC cortex_edac_l1_l2: CPU 1 L1 fatal error(s) detected (0x8000000089000002) [   80.192338] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 1 [  109.647919] EDAC cortex_edac_l1_l2: CPU 0 L1-I Tag RAM error(s) detected [  109.647938] EDAC cortex_edac_l1_l2: CPU 0 L1 fatal error(s) detected (0x8000000080000000) [  109.647942] EDAC cortex_edac_l1_l2: CPU 1 L1-I Tag RAM error(s) detected [  109.647955] EDAC cortex_edac_l1_l2: CPU 1 L1 fatal error(s) detected (0x8000000080000000) [  109.647966] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 0 [  109.659012] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 1 [  136.271933] EDAC cortex_edac_l1_l2: CPU 0 L1-I Tag RAM error(s) detected [  136.271951] EDAC cortex_edac_l1_l2: CPU 0 L1 fatal error(s) detected (0x8000000080000000) [  136.271956] EDAC cortex_edac_l1_l2: CPU 1 L1-I Tag RAM error(s) detected [  136.271969] EDAC cortex_edac_l1_l2: CPU 1 L1 fatal error(s) detected (0x8000000080000000) [  136.271980] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 0 [  136.283027] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 1 [  157.352268] EDAC cortex_edac_l1_l2: CPU 2 L1-D Data RAM error(s) detected [  157.352287] EDAC cortex_edac_l1_l2: CPU 2 L1 fatal error(s) detected (0x8000000089180002) [  157.352298] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 2 [  183.375931] EDAC cortex_edac_l1_l2: CPU 0 L2 fatal error(s) detected (0x8000000080000000) [  183.375947] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L2 'Fatal error(s) on CPU 0 [  186.928662] EDAC cortex_edac_l1_l2: CPU 0 L2 fatal error(s) detected (0x80000000910c4058) [  186.928679] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L2 'Fatal error(s) on CPU 0 [  191.055928] EDAC cortex_edac_l1_l2: CPU 0 L2 fatal error(s) detected (0x80000000910d0868) [  191.055944] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L2 'Fatal error(s) on CPU 0 root@localhost:~#

IPSec Performance Reproducibility Procedure on T1040RDB platform 1. Enable ASF in Linux Kernel           Step 1: Launch the kernel menu using the command: bitbake -c menuconfig virtual/kernel      Step 2: Enable ASF under Device Driver -> Networking device support -> Application Specific Fastpath      Step 3: Build the final binaries that needs to be loaded on T1040RDB using the command : bitbake fsl-image-core NOTE: The ASF modules are compiled as dynamically loadable modules and placed in the ROOTFS under the path /usr/driver/asf/min and /usr/driver/asf/full 2. Steps to boot the board with 2 cores:  (optional) => cpu 2 disable => cpu 3 disable => boot Board configuration after Linux is up A. Enable ip_forwarding and Linux performance parameters echo 1 > /proc/sys/net/ipv4/ip_forward echo 9000 > /proc/sys/net/netfilter/nf_conntrack_udp_timeout echo 9000 >/proc/sys/net/netfilter/nf_conntrack_udp_timeout_stream B. Insmod ASF ko’s cd /usr/driver/asf/min insmod asf.ko insmod asfctrl.ko insmod asfipsec.ko insmod asfctrl_ipsec.ko C. Run fmc command : cd /usr/driver/asf/scripts/fmc/ fmc -s Soft_FragParser.xml -p asf-fman-perf-policy.xml -c asf-cfg-perf-2041.xml -a D. Assign interface IP addresses and routes according to setup. Left DUT: ifconfig fm1-gb0 172.18.18.10 netmask 255.255.0.0 up ifconfig fm1-gb3 200.200.200.10/24 up ifconfig fm1-gb1 172.20.20.10 netmask 255.255.0.0 up ifconfig fm1-gb4 20.20.20.10/24 up route add -net 192.168.1.0/24 gw 172.18.18.2 route add default gw 200.200.200.20 route add -net 172.168.1.0/24 gw 172.20.20.2 route add -net 172.168.2.0/24 gw 20.20.20.20 arp -s 172.18.18.2 00:00:00:00:00:01 (optional) arp -s 172.20.20.2 00:00:00:00:00:02 (optional) Right DUT: ifconfig fm1-gb0 172.19.19.10 netmask 255.255.0.0 up ifconfig fm1-gb3 200.200.200.20/24 up ifconfig fm1-gb1 172.21.21.10 netmask 255.255.0.0 up ifconfig fm1-gb4 20.20.20.20/24 up route add -net 192.168.2.0/24 gw 172.19.19.2 route add default gw 200.200.200.10 route add -net 172.168.2.0/24 gw 172.21.21.2 route add -net 172.168.1.0/24 gw 20.20.20.10 arp -s 172.19.19.2 00:00:00:00:00:02 (optional) arp -s 172.21.21.2 00:00:00:00:00:04 (optional) E. Configure IPSec policies and SAs (attached below that needs to be downloaded to the box via tftp or sftp) Left DUT: ./left_tun-4port-v1.txt Right DUT: ./right_tun-4port-v1.txt F. Switch settings killall -9 l2sw_bin l2sw_bin Using UIO: /dev/uio0 Mapped register memory @ 0xb7b3f000 Chipid: 099530e9 fsl_dpa ethernet.17 fm1-gb0: Err FD status = 0x00040000 fsl_dpa ethernet.18 fm1-gb1: Err FD status = 0x00040000 l2switch> l2switch>mac add 00:00:00:00:00:01 3 [MAC 00:00...00:01 is reachable on port 3] m2switch>mac add 00:00:00:00:00:03 7 l2switch>mac add 00:04:9f:03:30:f6 8 [MAC of fm1-gb0] l2switch>mac add 00:04:9f:03:30:f7 9 [MAC of fm1-gb1] l2switch>mac dump [Displays MACDB of switch (static & Dynamic)] Type VID MAC Address Ports ------ --- ----------------- ----- Static 1 00:00:00:00:00:01 3 Static 1 00:00:00:00:00:03 7 Static 1 00:04:9f:03:30:f6 8 Static 1 00:04:9f:03:30:f7 9 Static entries: 4 Dynamic entries: 0 l2switch> l2switch>^Z [Press ctrl+z to stop the process] [1]+ Stopped(SIGTSTP) l2sw_bin root@t1040rdb:/mnt/sridhar/asf-bins/qos/bin/full# killall -9 l2sw_bin G. Configure IXIA/STC to generate the traffic with 128 flows. H. Start the traffic from both end and verify all the flows are offloaded and packet is going through IPSec ASF. Note: Except switch settings everything is similar to previous performance releases by IDC. I. The ASF flow can be observed using the following command cat /proc/asf/flow_debug Script files PFA in attachment