What IDE is recommended for programming the LS1020A/LS1021A/LS1022A? The LS1 series is optimized for CodeWarrior, whose latest version, for ARMv7 can be found at http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=CW-LS-ARM7&fsrch=1. What is the LS102xA product family's enablement schedule up to 2016? The launch calendar for the LS102xA family is shown in the figure below. Can one CodeWarrior license cover both LS102x QDS and TWR? The full CW product can be used with either the TWR or QDS board through the CW-TAP probe. Does CodeWarrior for LS1 support flash (NOR/NAND) programming? Yes, CodeWarrior supports both NOR and NAND programming for QDS and TWR. Over what power range is LS102x designed for? LS102x is designed for operation under 3W.  Its ability to yield over 5000 Coremarks at a frequency of up to 1GHz separates the LS102x family from competitors in delivering improved performance without increased power consumption. How fast does the LS102x family run? The LS102x family can run between 600 MHz and and 1 GHz. What endianness does LS102x follow? The LS1 is based on the ARMv7 architecture, which is natively little-endian.  However, ARMv7 supports big-endian using the CPC15 register.  More significantly, many LS1 peripherals, like Ethernet and integrated flash controller (IFC), follow big-endian.  Therefore, LS1 is really a mixed-endian system and one must be mindful of a peripheral's endianness when programming the LS1.

The T1023WALN board supports AQR105 only. Adding this patch file for AQR106 support.

The NCSW - NetComm Software - is a package to help speed development on Freescale PowerQUICC and QorIQ processor platforms. It contains NCDD - NetComm Device Drivers - and some other components. Here take P3041 I2C supported in version GA_4.7 as an example to analyze the NetComm Software structure and device driver usage. CW PA 10.3 is used to be compatible for the use case code.

T2080 rev1.1 has fixed the MEM_PLL_RAT issue. but, the set flow is different than T2080 rev1.0. The flow is in the attached doc.

When will you have the final version of the ASK append RCX? The final version is already set for mass production. How do you use the crypto engine? The OCF (Open BSD Cryptogrpahic Framework) is a service virtualization layer implemented inside the kernel that provides uniform access to accelerator functionality by hiding card-specific details behind a carefully designed API.  The LS1024A provides an OCF-based cryptographic driver interfacing Linux security applications and the LS1024A Elliptic 1802 crypto accelerator. What is CMM? CMM stands for Conntrack Monitor Module.  It monitors the Linux connection table and adds/removes connection from the PFE connection table. I get an error when adding a bridge entry via CMM. This error usually crops up if a manual bridge command is attempted while the auto-bridge module (ABM) is disabled.  Try enabling the module then make the bridge in Linux.  The ABM will see this and set up PFE appropriately without you having to do any manual bridging commands. What are the power ramping requirements? The power ramping curve of the LS1024A is linear.  Power supplies will begin at almost the same time, but usually from low voltage to high voltage.  Refer to Section 31.2 of the QorIQ LS1024A Data Sheet for further information on this topic. My RTP Relay isn't working properly. Check that the correct sockets have been created properly. How do I make the RGMII work (RGMII delay)? The LS1024A does not have internal RGMII clock/data delays.  The delay element must be enabled in the external device (switch/PHY), or something must be taken care of in layout, which is not recommended.  Typical symptoms are that the GEMAC can only transfer at low speeds (e.g. 10kbps), or the GEMAC can work at 100Mbps/full duplex, but not at 1000Mbps.

CodeWarrior Development Suite for Networking Applications to support software development on QorIQ Layerscape devices.

This is the P2020RDB IPV4 forwarding performace test using SmartBit.

Here is the vlan set up folw on P1010RDB.

We’re glad to announce the FSL Community BSP 1.7 (codename Dizzy); it has been a busy release cycle with some new boards support added. In total we now support 42 boards from several vendors. During the 1.7 release cycle, a new SoC family support (QorlQ Layerscape1) has been included and the application and graphical stack support (better Wayland, Qt5 and Chromium support to enumerate some) has been greatly extended. This all has been accomplished with way less changes on the core BSP layer (53% less commits) which enforces the compromise of FSL Community BSP with long term quality and support. Another worth citing news is regarding the release notes. It is available online and gives an overview of supported boards, available version for default and optional packages and known issues at time of the release. The release notes has been completely reworked and extended in this release. It now offers a PDF version (for viewing and printing) alongside with the regular online one.

QorIQ is a important contributor to the Internet of Things with devices such as the LS1 Gateway.  Read more about the Internet of Things! Freescale Expands System Power Management Portfolio to Its QorIQ LS1 Processors for a Secure Internet of Things

This is a QorIQ T1040RDB and T2080RDB SDK1.7 IPv6 +AES test guide.

Simple example T4240QDS project that incorporates the Mentor Graphics Embedded Performance Library (MEPL) to add Altivec coding.

If you are using Freescale QorIQ networking processors, and struggling with complicated and heavy work to analyze your code, there is something that can help --- Freescale Scenarios tool. You can make things simpler, and work more efficiently, right now. This article provides a short tour of the tool and provides in section one a brief  introduction to this tool, section two installation - section three getting started guide - section four a simple example – and finally in section five instructions for where you can find more docs and information. Thanks to Ed Martinez for the great support to this article! Please download the article attached for details.

NEXCOM 1U network security appliance the NSA 5640 is designed for advanced Unified Threat Management (UTM) solutions with multi-Gigabit throughput. Featuring the Freescale multicore QorIQ T4240 SoC and high-speed networking and interconnect interfaces, the NSA 5640 addresses the escalating cyber threats fueled by rising network communication, bandwidth-hungry activities and number and complexity of Internet-based attacks.

Here is the NAT set up flow on P1010RDB.

Hello everyone， I have P1010 + FPGA control board. FPGA chip is mounted on the P1010's IFC interface. FPGA and P1010 is isolated by isolate buffer chip. One Norflash chip is also mounted on the P1010's IFC interface too. The file system built on Norflash. The OS read files from file system at any time are correct. Unfortunately, Once the FPGA is running, The OS write file to the file system will cause file system failure. But if the FPGA stop running, the write operate there will be no errors. I use the test fpga code which just have 1 logic and have nothing input or output pin, all pin . O, Who encountered such a issues? How it happened?

I recently tried to update U-boot on the PSC9131RDB and struggled for a while with the DIP switches on the board. I thought I'd write up a few pointers in case you try to attempt this yourself. DIP switches for the PSC9131RDB are described on Infocenter here: http://www.freescale.com/infocenter/topic/QORIQSDK/4227333.html A couple of points about the switches and jumpers worth considering: Make sure you read the solder mask on the board. The switches are numbered upside down from what you might expect. SW6[3:4] describe how the JTAG chain is setup on the board. The Starcore and Power cores can be chained in the same scan chain, or separated. If this is set to 11, a side effect is that the NAND flash is write protected. Input clock to the 9131 can either be 66Mhz or 100MHz. Images are built to a specific input clock, so make sure you are using an image for the clock your board is set to. Jumper J16 (near the SMA connectors) configured the input clock to the processor. If the jumper is on, the input clock is 66MHz. If it is off, it's 100MHz. The clock PLL ratios are multiples of the input clock. CCB clock = the input clock * a multipler. The core frequency = CCB clock * multiplier. All of the multiplers are located in the DIP switches and must be changed if you move from an image built for 66MHz to an image built for 100MHz. For example: For a 66MHz input clock, my CCB multiplier = 6:1, so my CCB clock = 400MHz. My core multiplier = 2:1, so my core frequency = 400MHz * 2 = 800MHz. If I were to just switch the input clock to 100MHz with these settings, I'd be running my CCB at 100*6 = 600MHz, and my core at 1.2GHz (which violates the processor's spec's!). Lastly, the board is built with both SPI and NAND flash. You can boot from either. It's either / or, and the images are built differently, so make sure you have the correct image for what you're attempting. If you happen to have an image burnt into both of the flash devices (SPI and NAND) you may select which to use at boot through SW4[ROM_LOC]. This can be set to 0b0110 for SPI, or 0b1001 for NAND.