2S TDM Master: Persistent 1-slot downward shift during continuous DMA streaming 1. Test Configuration I2S configured as TDM Master, DSP mode with short WS 8 slots per frame, 32-bit per slot, frame length = 256 bit Using fsl_i2s_dma driver Dual-buffer ping-pong transfer FreeRTOS task waits on a semaphore from the DMA callback, fills the buffer, then calls I2S_TxTransferSendDMA to re-submit Test data pattern: fixed 0x000Axxxx (upper 16 bits = 0x000A, lower 16 bits contain slot index and sample sequence number) 2. Persistent One-Slot Downward Shift (100% Reproducible) Logic analyzer captures show: Transmitted data is consistently shifted down by exactly one slot Data intended for Slot 0 appears in the physical Slot 1 position Data intended for Slot 1 appears in the physical Slot 2 position By extension, data intended for Slot 7 appears in Slot 0 of the next frame (or is lost) This shift is stable after the stream starts; it does not drift further over time and remains a fixed 1-slot offset 3. Startup Data Misalignment (Intermittent) The logic analyzer occasionally observes: After the WS frame sync pulse, the DATA line remains at low level (all zeros) for a period After a blank interval of 1~3 frames, valid test data suddenly appears Once the blank interval ends, the data still exhibits the 1-slot offset described in item 2 Xanderwangx_0-1780141578772.png Audio(PDM | I2S | SAI) Re: 2S TDM Master: Persistent 1-slot downward shift during continuous DMA streaming Hello @Xanderwangx ,
Thank you for your post. Could you please let us know which NXP MCU you are using? Also, are you working with one of our evaluation boards or a custom board? Are you using the SDK example code, or is this based on your own implementation? If it is your own code, would you be able to share it with us for further analysis?
BR
Celeste Re: 2S TDM Master: Persistent 1-slot downward shift during continuous DMA streaming Hello @Xanderwangx ,
Thank you for your reply. However, the RT family is not within my support scope. I mainly support MCX and Kinetis family. Also, this is MCX channel, not for RT product.
Could you please create a new post under i.MX RT Crossover MCUs - NXP Community? The RT support team will be able to assist you there.
BR
Celeste
Re: 2S TDM Master: Persistent 1-slot downward shift during continuous DMA streaming MCU: MIMXRT685-EVK (i.MX RT685) Board: Custom product board based on RT685. I am using Loop DMA mode with ping-pong buffers. The DMA is configured with I2S_TransferSendLoopDMA() using 2 descriptors. In the DMA callback, I fill the next buffer and the loop continues automatically. void I2S1_TDM_Init(void)
{
I2S_Type *base = I2S1;
/* I2S Configuration */
i2s_config_t cfg;
I2S_TxGetDefaultConfig(&cfg);
cfg.masterSlave = kI2S_MasterSlaveNormalMaster;
cfg.mode = kI2S_ModeDspWsShort; /* TDM = DSP mode */
cfg.divider = 24576000 / (TDM_SAMPLE_RATE * TDM_SLOT_NUM * TDM_SLOT_WIDTH);
cfg.dataLength = TDM_SLOT_WIDTH; /* 32-bit */
cfg.frameLength = TDM_FRAME_LENGTH; /* 256-bit */
cfg.oneChannel = false;
cfg.position = 0;
cfg.wsPol = true; /* DSP A or B */
I2S_TxInit(base, &cfg);
/* Enable 8 slots (Primary + 3 Secondary Channels) */
/* Note: Using 4 channels to cover 8 slots with 32-bit data */
I2S_EnableSecondaryChannel(base, kI2S_SecondaryChannel1, false, 32 * 2);
I2S_EnableSecondaryChannel(base, kI2S_SecondaryChannel2, false, 32 * 4);
I2S_EnableSecondaryChannel(base, kI2S_SecondaryChannel3, false, 32 * 6);
/* DMA Loop Transfer Setup */
DMA_Init(DMA0);
DMA_EnableChannel(DMA0, I2S_TX_DMA_CH);
DMA_SetChannelPriority(DMA0, I2S_TX_DMA_CH, kDMA_ChannelPriority3);
DMA_CreateHandle(&dma_handle, DMA0, I2S_TX_DMA_CH);
I2S_TxTransferCreateHandleDMA(base, &i2s_handle, &dma_handle,
I2S1_Callback, tdm_xfer);
I2S_TransferInstallLoopDMADescriptorMemory(&i2s_handle, tdm_desc, 2);
if (I2S_TransferSendLoopDMA(base, &i2s_handle, &tdm_xfer[0], 2)
!= kStatus_Success) {
while (1); /* Fails if TDM_FRAMES * 8 > DMA_MAX_TRANSFER_COUNT(1024) */
}
} The slot offset is random across power cycles, not fixed.I also tried disable interrupts before and after the DMA transfer to force synchronization, but slot misalignment still occurs. Does I2S_TransferSendLoopDMA() guarantee frame-aligned DMA startup on RT685? If not, how to force alignment to WS boundary? i.MX-RT600
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