For S32G274A multicore scenario, bl2_w_dtb.s32 is flashed into QSPI FLASH, How to build & flash FIP For multicore scenario, bl2_w_dtb.s32 is flashed into QSPI FLASH, FIP image is meant to be flashed info eMMC. 1>Is it sdcard type fip image that should be flashed? 2>Where should FIP image go? RAW area or first partition of eMMC? 3>How to build such ATF images? Re: For S32G274A multicore scenario, bl2_w_dtb.s32 is flashed into QSPI FLASH, How to build & fl Hello, @wansp  Thanks for your reply. 1. Yes, the booting image struct changed a lot since BSP42, on BSP46, sorry that you may have to obey the rules that mentioned in the BSP46.0 UM for flashing the image to the QSPI/SD. 2. I have checked the code in TFA of BSP46, seems the settings you mentioned is deprecated. BR Chenyin Re: For S32G274A multicore scenario, bl2_w_dtb.s32 is flashed into QSPI FLASH, How to build & fl BSP46 is really brand-new. It seems that BSP42 & BSP46 are dealing with FIP's eMMC flashing differently (RAW data access vs. by partition), which may make BSP upgrade hard. For BSP42, I prefer make both BL2 & FIP in QSPI. Since they are similar, can the be the same copy? Am I using the right ATF compile commands? Is FIP_QSPI_OFFSET still valid for BSP46? Re: For S32G274A multicore scenario, bl2_w_dtb.s32 is flashed into QSPI FLASH, How to build & fl Hello, @wansp  1. For BSP before BSP43(say BSP42), the A53 bootloader(TFA/uboot) would be built to a standalone image(fip.bin, images for SD/eMMC boot), in this case, the same binary should be flashed to both SD card/emmc and QSPI for booting from M7 bootloader(multicore boot specified in AN13750). The building command could be the same mentioned in BSP42.0 UM for SD boot building. 2. For BSP 43 and later, the A53 bootloader(TFA/uboot) would be built to generate two images(bl2 and fip), in this case, the bl2 should be flashed to the QSPI, while the fip one could be flashed to the eMMC/SD as specified by the BSP46.0 UM. The building command could be also the same mentioned in BSP46.0 UM for SD boot building. 3. The AN13750 is based on very early version BSP, the steps/tips/descriptions for booting are still referenceable, but some details for certain version software operation may be outdated, I suggest following the corresponding BSP UM for different scenarios. BR Chenyin Re: For S32G274A multicore scenario, bl2_w_dtb.s32 is flashed into QSPI FLASH, How to build & fl BSP46 UM seems easier to understand. I drew two diagrams for two scenarios: 1>BL2 in QSPI, FIP in EMMC 2>both BL2 & FIP in QSPI Am I using the right ATF compile commands? For both BL2 & FIP in QSPI case, does any compile option exist to declare its offset in QSPI FLASH? Re: For S32G274A multicore scenario, bl2_w_dtb.s32 is flashed into QSPI FLASH, How to build & fl Hello, @wansp  Thanks for the confirmaiton. 1. Yes 2. It is different for BSP42 and BSP46, on BSP42, there is only fip file existed, which would be flashed to /sdx; on BSP46, there would be both bl2 and fip binaries, the fip would be flashed to /sdx1. 3. For building the fip images, you may directly following the specific BSP UM to manually built, but note that for multi-core boot purpose(as AN13750 suggested), the tfa part may need to be built with the following modification: BR Chenyin Re: For S32G274A multicore scenario, bl2_w_dtb.s32 is flashed into QSPI FLASH, How to build & fl Two versions are in consideration: BSP42 & BSP46 It seems that they are different: 1>BSP46 user manual has this: make CROSS_COMPILE=/path/to/your/toolchain/dir/bin/aarch64-none-linux-gnu- \ ARCH=aarch64 PLAT= BL33= \ FIP_LOCATION=mmc the FIP is flashed to partition 0 & MBR partition scheme is required. as a common data partition, it may be influenced by operations on other partitions, which may hurt reliability. 2>in BSP42 user manual, parameter FIP_MMC_OFFSET seems for this purpose: make CROSS_COMPILE=/path/to/your/toolchain/dir/bin/aarch64-none-linux-gnu- \ ARCH=aarch64 PLAT= BL33= \ FIP_MMC_OFFSET=0x5400 since absolute offset is used, it seems to be using RAW area. But how to flash the original image into the RAW area? Re: For S32G274A multicore scenario, bl2_w_dtb.s32 is flashed into QSPI FLASH, How to build & fl Hello, @wansp  Thanks for your post. May I know which version BSP you are referring to ? BR Chenyin Re: For S32G274A multicore scenario, bl2_w_dtb.s32 is flashed into QSPI FLASH, How to build & fl BSP46 UM tells: “The accepted values for FIP_LOCATION are: mmc, qspi or memory." If FIP_LOCATION=qspi, BL2 should know where to find FIP. If FIP_QSPI_OFFSET is deprecated, I think BSP46 should provide similar mechanism or has some unspoken default settings. Re: For S32G274A multicore scenario, bl2_w_dtb.s32 is flashed into QSPI FLASH, How to build & fl Hello, @wansp  From my understanding, the default building commands, like: make CROSS_COMPILE=/path/to/your/toolchain/dir/bin/aarch64-none-linux-gnu- \ ARCH=aarch64 PLAT= BL33=  FIP_ALIGN=64  could generate correct bl2 and fip images for multicore boot. You may flash the bl2 part to the QSPI, and replace the FIP part of the default SD/mmc image with the newly generated one, then the bootloader is able to find the correct M7 application and A53 bootloader(bl2) and bring them up. If there are still issues, feel free to share all logs for your steps and console prints, we will help to check them. BR Chenyin

S32DS 牌照消失 S32DS 许可证丢失，需要激活，但旧激活码无效。如何解决这个问题？ Re: S32DS licence disappear 请参考此页面和我的个人资料许可证状态。 Re: S32DS licence disappear DS 3.5 ，我的执照状态。 Re: S32DS licence disappear 你好 能否请您提供试图安装的 S32DS 版本？ 顺祝商祺！ Peter Re: S32DS licence disappear Ds 3.5 Re: S32DS licence disappear 你好、 我检查了您的账户，您的许可证是有效的。您尝试过离线激活吗？ https://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/HOWTO-Activate-S32-Design-Studio/ta-p/1128340 Re: S32DS licence disappear 是的，我试过. 结果和其他信息，请参考我的其他回复。 我找不到我的驾照 . @jiri_kral Re: S32DS licence disappear 我使用了其他激活有效代码，也显示了该错误。请参考我的其他回复。 @jiri_kral @petervlna Re: S32DS licence disappear 我的个人资料中没有许可证激活码，请查看。 Re: S32DS licence disappear 你好 这个问题是否仍然有效，或者你是否设法让它运行了？ 顺祝商祺！ Peter

グリーンVIP 1.3.0GVP_RTU_1_C1_VM2 の生成に失敗しました こんにちは、専門家さん。 GVP_RTU_1_C1_VM2 の元のプロジェクトを開くと、以下のようなエラーが表示されています しかし、.mexからファイルを見ると、それが /RTOS_R52/Os/OsCounter_0 です。しかし、GUI インターフェースでは何も参照できません。ご協力いただけませんか?ありがとう！ BR、 キャサリン グリーン_VIP Re: GreenVIP 1.3.0 GVP_RTU_1_C1_VM2 generation failed こんにちは@Catherine 、 問題を追跡するために Jira チケットを作成しました。GreenVIP チームができるだけ早く返信します。 Re: GreenVIP 1.3.0 GVP_RTU_1_C1_VM2 generation failed こんにちは@Catherine 、 この問題をリクエストしたお客様はいますか? よろしくお願いします、 ラドゥ

MAYA W161 Wi-Fi SDIO 驱动程序内存使用情况 我叫小岛 DKojima。希望你收到这条信息时一切安好。 我们目前正在开发一种产品，需要最终确定其内存地图。如果有人有在 RTOS 上为 MAYA-W161 制作 Wi-Fi (SDIO) 驱动程序的经验，请与我分享 ROM 和 RAM 内存使用情况。 很抱歉占用您的时间，如果您能提供这方面的任何信息，我将不胜感激。提前感谢您的热心帮助。 通信& 控制（I3C | I2C | SPI | FlexCAN | 以太网 | FlexIO） Re: MAYA W161 Wi-Fi SDIO driver memory usage 亲爱的丹尼尔 非常感谢你的答复。 由于本部门没有开发环境，我们将探索其他方法。 亲切的问候， DKojima Re: MAYA W161 Wi-Fi SDIO driver memory usage 您好， 我建议您看看在哪里可以找到Wi-Fi 软件驱动程序。 Daniel。

MCXA346 DMA channel link Hello. I'm trying to modify the official routine frdmmcxa346_edma3_channel_link to make the memory carry once again and have configured the source and destination addresses, but after the first carry is complete, starting the second carry, it won't start, attached is my modified program. Looking forward to a reply! Thank you! MCXA Re: MCXA346 DMA channel link Hi Your understanding is correct. It is indeed what I wanted to do. The reason why I want to try this example is that I want to use DMA and ADC together. I want to achieve the function of synchronous acquisition of 3 ADCs. Currently, I have accomplished this using a certain method. The three ADCs use the timer to trigger for synchronous acquisition, and a DMA channel is configured for each ADC. In the DMA channel interrupt, it is determined whether the current data acquisition is completed. This means that there are three ADCs corresponding to three DMA channels. After the DMA transfer is completed, since it is a 3-channel operation, there will be three DMA channel interrupt service functions. 1. I want to reduce the number of DMA interrupts from three to one in order to lower the system load. 2. Since it is a synchronous collection, it is impossible to determine which DMA transfer was completed first. Therefore, it is necessary to check whether all three channels have been completed. I have studied the channel joint function of DMA. Can I achieve the above function by using 3 minor loops and 1 major loop? This way, there will only be one DMA channel interruption, and it can ensure that each ADC data is successfully transferred. I'm not sure if my understanding is correct. Please let me know if I'm wrong. Thank you. Re: MCXA346 DMA channel link Hi @346500452  I use a translate tool to support you, I understood that you want to modify the example to do more than one transfer, but your code gets stuck waiting the g_Transfer_Done to set. Let me know if something is missing in translation.  You need to modify the EDMA_PrepareTransfer params, please review the function brief and params. If you are not interested in the Channel Link functionality, I recommend you review the edma3_memory_to_memory examples instead.  Re: MCXA346 DMA channel link Hi @346500452  Thanks for confirming the translation and giving more details about your goal. You are correct you could accomplish it with 3 minor loops and 1 major loop, my recommendation is to channel link with Minor and Major loops to trigger the 3 eDMA configs simultaneously but only enable one channel major loop interrupt.  At the interrupt you could review the other 2 eDMA status to know if they finished the transfer. 

‎ライセンスの有効期限が近づいています。S32 Design Studio for ARM v2.2 アクティベーションコードを再アクティベートする必要があります 有効期限が近づいています 製品: S32 Design Studio for ARM v2.2 アクティベーションコード: 8F7C-1117-AEEF-85A6              Re: ‎The licence expires soon, S32 Design Studio for ARM v2.2 S32 Design Studio for Arm V2.0 のライセンスを延長できますか? 0055-F166-922B-FF1C Re: ‎The licence expires soon, S32 Design Studio for ARM v2.2 それは私のせいです。助けてくれてありがとう Re: ‎The licence expires soon, S32 Design Studio for ARM v2.2 私のライセンスは延長されないと思います、 ライセンス検証をチェックし続けると、次のステップに進めず、ほぼ停止します 助けが必要です（ライセンスの延長を確認してください） Re: ‎The licence expires soon, S32 Design Studio for ARM v2.2 こんにちは、 S32DS ライセンスが延長されました。

QNXがNXPに登場 こんにちは、サポートチームの皆様 評価ボード S32G-VNP-RDB3 で QNX イメージを起動することに関する質問があります。QNX ソフトウェア センターから参照イメージを入手できます。 QNX BSPビルドプロセスの出力は.uiです。ファイル。 すでに Linux Yocto BSP パッケージが動作しており、これをビルドして SD ブートを使用しました。これは.sdカードです正常に起動しているイメージ。Linux イメージ ファイルの代わりに QNX イメージを使用しようとしましたが、起動しません。 以下の質問があります:- QNX を起動するには、Linux Yocto ビルドから u-boot または ATF に変更を加える必要がありますか? 起動するには QNX イメージ形式に何か変更が必要ですか? PS: QNX ビルドから生成された生のファイルのブートも試みました。起動もしませんでした。 Re: QNX bring up in NXP Silicon Signalsで試してみるといいでしょう Re: QNX bring up in NXP こんにちは@shebin 、 QNX は NXP 製品ではないため、それに関する情報はあまりありません。そうは言っても、役に立つかもしれないアプリケーション ノートがあります: AN14355 は、 S32G3 製品ページでいつでも入手できます。このドキュメントの目的は、QNX で PFE を使用する方法を説明することですが、uboot と ATF を設定してフラッシュする方法、および SD カードを設定する方法を説明するセクションがいくつかあります。セクション4「前提条件」 、 「5「コンポーネント」」 、および5.2.4「準備された SD カードのサンプル パーティション」を確認してください。確実に動作させるために、ドキュメントに記載されているコンポーネント バージョンを使用することを強くお勧めします。 一部の手順は PFE のコンポーネントを構成するためのものであるため、スキップできる可能性があります。 この情報で問題が解決したかどうかお知らせください。

S32DS for ARM 2.2 ライセンス延長 ライセンスの有効期限が切れましたが、延長できません。S32ds for Arm v2.2 ライセンスの延長を手伝っていただけますか? よろしくお願いします。 アクティベーションコード: EBE6-6A64-C479-7B7A 製品: S32 Design Studio for ARM v2.2

i2s Bridge 演示代码 在 i2s 应用中，我需要实现全双工数据输入和数据输出，但演示代码为此使用了两个独立的 i2s 组。 是否有办法使用 WS + SCK + DATA_IN + DATA_OUT 的配置实现全双工 i2s？ Re: i2s Bridge demo code 嗨，@Libra、 非常感谢您关注我们的产品并使用我们的社区。 请查阅 RT685 用户手册，每个 Flexcomm I²S 接口一次只能配置一个方向--发送 (TX) 或接收 (RX)。 如果要实现全双工，则需要使用两个 Flexcomm，一个配置为 TX，另一个配置为 RX。   顺祝商祺！ MayLiu

secure boot on imx8m plus on Android14 BSP I want to enable the secure boot on imx8m plus board with Android 14 BSP, such that the board will always boot on our signed keys only. i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Re: secure boot on imx8m plus on Android14 BSP pls refer to this document firstly https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Steps-for-single-secure-boot-for-Android-BSP/ta-p/2157256 Re: secure boot on imx8m plus on Android14 BSP I have followed the steps given in the PDF and generated the keys like:  SRK1_sha256_1024_65537_v3_ca_key.der SRK1_sha256_1024_65537_v3_ca_key.pem SRK1_sha256_1024_65537_v3_usr_key.der SRK1_sha256_1024_65537_v3_usr_key.pem SRK1_sha256_2048_65537_v3_ca_key.der SRK1_sha256_2048_65537_v3_ca_key.pem SRK2_sha256_1024_65537_v3_ca_key.der SRK2_sha256_1024_65537_v3_ca_key.pem SRK2_sha256_2048_65537_v3_ca_key.der SRK2_sha256_2048_65537_v3_ca_key.pem SRK3_sha256_2048_65537_v3_ca_key.der SRK3_sha256_2048_65537_v3_ca_key.pem SRK4_sha256_2048_65537_v3_ca_key.der SRK4_sha256_2048_65537_v3_ca_key.pem and also the CSF, IMG and CA. the private keys are openssl x509 -in crts/SRK1_sha256_2048_65537_v3_ca_crt.pem -text -noout | grep Subject Subject: CN = SRK1_sha256_2048_65537_v3_ca Subject Public Key Info: X509v3 Subject Key Identifier:  openssl x509 -in crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem -text -noout | grep Issuer Issuer: CN = SRK1_sha256_2048_65537_v3_ca openssl rsa -in keys/SRK1_sha256_2048_65537_v3_ca_key.pem -check Enter pass phrase for keys/SRK1_sha256_2048_65537_v3_ca_key.pem: RSA key ok Are all these keys ready to flash on imx8m plus smarc som? Re: secure boot on imx8m plus on Android14 BSP did you generate SRK table already? Re: secure boot on imx8m plus on Android14 BSP yes, SRK Hash TableSRK Hash TableSRK Hash TableSRK Hash TableSRK Hash Table the SRK Hash table is generated successfully from the keys Re: secure boot on imx8m plus on Android14 BSP ok, then you can refer to the chapter 3.1.2.2 Signing bootloader images and 3.1.2.3 Signing the MCU firmware of enclosed file Re: secure boot on imx8m plus on Android14 BSP I have burned the fuses on my imx8m plus board, but unable to get the signed image or flashing,  how to recover and find the correct igned image for flashig? Re: secure boot on imx8m plus on Android14 BSP I am unable to sign the correct image on my imx8m plus board after fusing the keys permanently on the board! 

リセットで止まる 私は S32M24x EVB を使っていますが、コントローラーがリセット状態のままになっています。搭載デバッガーを使用しています。 リセット LED が常にハイになっているのがわかり、コントローラーで何もフラッシュできません。 私はDesign Studioを使用しており、「実行中のターゲットにアタッチ」を有効にして試してみましたが、搭載デバッガーは攻撃できますが、停止またはリセットできず、しばらくするとアタッチメントも壊れているようです。 「arm-none-eabi-gdb.exe」を直接使用して試してみましたが、デバイスは保護されており、ソフト リセットに失敗したと表示されます。 ハードウェアもチェックしましたが、コンポーネントは損傷していませんでした。 実行中のプログラムのフラッシュ構成ワードは次のとおりです。 .section .flash_config, "a" .long 0xFFFFFFFF ; 8 bytes backdoor comparison key .long 0xFFFFFFFF ; .long 0xFFFFFFFF ; 4 bytes program flash protection bytes .long 0xFFFF7FFE ; FDPROT:FEPROT:FOPT:FSEC(0xFE = unsecured) そしてフラッシュセクションは - MEMORY { int_flash_config : ORIGIN = 0x00000400, LENGTH = 0x00000010 } SECTIONS { .flash_config ALIGN(4) : > int_flash_config } この状況の原因は何でしょうか? また、コントローラを再び正常に動作させる方法は何でしょうか? 前もって感謝します！！！ Re: Stuck in Reset この問題は、起動時にフラッシュ構成ワードがクリアされたために発生しました。 Re: Stuck in Reset こんにちは@Satyajit_Patil オシロスコープを使用してリセット信号を確認していただけますか?リセットピンを直接測定し、観察した波形の画像を共有します。リセット ラインが図のように切り替わる、添付の信号と同様の信号が表示されることが予想されます。 さらに、私や同様の現象を経験している他のお客様に効果があったプロセスを試していただけますか?MCU を再フラッシュするには、点滅例を使用してフラッシュを試行しながらリセット ボタンを押し続けます。失敗する可能性があり、再試行するかどうかを尋ねられます。その場合は、リセット ボタンを放し、そのプロンプトの下で再度プログラムのロードを試みてください。これを実行すると、プログラムは正常にロードされ、ボードが回復するはずです。 上記の手順を試しても問題が解決しない場合は、お知らせください。 BR、ヴェインB

RW612 BLE Radio Tests FW We are using a BLE module that hosts the NXP-RW612 MCU together with Zephyr. In order to obtain radio approvals for products, MCU vendors usually provide a dedicated BLE RadioTest FW sample for this purpose.  Sometimes also client side/PC software  is provided. Questions: 1) Where can I find "BLE RadioTest FW sample" for the NXP-RW612 MCU? 2) Do NXP also provide client side/PC SW for radio testing, if so where can I find it? Re: RW612 BLE Radio Tests FW Hi, Let me check what is the process for this in Zephyr. Regards, Daniel. Re: RW612 BLE Radio Tests FW Hi, Sorry for the late reply. I am still waiting for feedback. Regards, Daniel. Re: RW612 BLE Radio Tests FW Thank you very much for the update Daniel. This is quite an important topic, as we would be unable to sell our upcoming NXP RW612 based products without regional radio approvals. Best regards Tonny Re: RW612 BLE Radio Tests FW Hi @tobg , Hope you are doing well. You can use the shell example and perform DTM (Direct Test Mode). For the DUT in transmitter mode, you could use the following command on DUT side: bt hci-cmd 08 34 00ff0002   For the reference device in receiver mode, you could use: bt hci-cmd 08 33 000200   After completing the test, with the following command on both devices to stop the test: bt hci-cmd 08 1F   For your reference, you can check this Application Note: https://www.nxp.com/docs/en/application-note/AN14163.pdf   Hope this helps. If you have any question, please let us know! Regards, Ricardo Re: RW612 BLE Radio Tests FW Thanks a lot Riccardo. I was aware of the DTM mode sample, but not the application note. Thanks! I am a bit unsure if this FW will cover all requirements for e.g. FCC approval. What I had hoped for, was a reference to sample FW/SW alike what is described in this application note RF Test Mode on FreeRTOS but for Zephyr. Note that this describes radio testing on all radio types (BLE, Wifi) supported by the NXP RW612 Do NXP provide such? Regards Tonny Re: RW612 BLE Radio Tests FW Hi @tobg , Thanks for the update. At the moment, for RW612 + Zephyr there is no combined Radio Test firmware similar to the FreeRTOS RF Test Mode. The available option remains using BLE DTM via the Zephyr shell example, and AN14163 is currently the only reference available for BLE radio testing on RW612. Hope this helps. Best Regards, Ricardo Re: RW612 BLE Radio Tests FW Instead of using the linux hcitool as indicated in AN14163 you can use NXP's own NXP Test Tool 12 for Windows. This tool provides a nice GUI with all relevant HCI available. https://www.nxp.com/design/design-center/development-boards-and-designs/frdm-development-boards/connectivity-tool-suite:CONNECTIVITY-TOOL-SUITE

FlexPWM interrupt not triggering in Zephyr while SDK example works as expected Zephyr 4.3.0 MCUExpresso SDK 2.16 Application note used for Example AN14196 Board used mcx_n9xx_evk/mcxn947/cpu0 Description: I am trying to replicate an NXP SDK FlexPWM example in Zephyr OS. The main goal is to reproduce the SDK behavior where: A simple PWM signal is generated using the FlexPWM peripheral. A callback (interrupt handler) is executed after a specified number of PWM edges are counted(Via E-capture). SDK Behavior (Working): Using the SDK pwm.c example, the PWM signal is generated correctly. The FlexPWM interrupt fires as expected. The callback function executes once the configured number of edges is reached. Zephyr Behavior (Issue): Using Zephyr, I am able to successfully generate the PWM signal with the FlexPWM peripheral. However, the FlexPWM interrupt is never triggered , and the callback function is never executed. (IRQ_CONNECT(120, 0, FLEXPWM1_SUBMODULE0_IRQHandler, NULL, 0); was used to connect the interrupt line to IRQHandler  ) Debugging and Investigation Done So Far: I compared the FlexPWM register configurations between: The SDK example (pwm.c) The Zephyr application (main.c) All relevant register values appear to match during the peripheral setup phase. I disabled Zephyr power management to ensure the CPU is not entering a low-power state by adding following configs    CONFIG_PM=n CONFIG_PM_DEVICE=n This change did not affect the behavior—the interrupt is still not triggered. PWM output on the pin is correct, which suggests the peripheral clocking and basic configuration are working. Question / Request for Help: Are there any Zephyr-specific requirements for enabling FlexPWM interrupts (e.g., IRQ configuration, ISR registration, clock gating, or NVIC setup) that differ from the SDK? Is there anything additional that must be done in Zephyr to ensure FlexPWM interrupts are properly routed and handled? Are there known limitations or missing support for FlexPWM edge-count interrupts in Zephyr? Any guidance on how to correctly enable and handle FlexPWM interrupts in Zephyr would be greatly appreciated. Thank you. Re: FlexPWM interrupt not triggering in Zephyr while SDK example works as expected Hello @wima88  After building, please check the .config file to confirm that the interrupt is enabled. Also you can send it to me, I help you check.   Thank you.    BR Alice     Re: FlexPWM interrupt not triggering in Zephyr while SDK example works as expected Hi Alice ,  I Scan the .config and could not find any red flags their. I upload the .config as well(had to rename since .config is not supported).  After further investigation into the Zephyr base setup, I noticed the following behavior difference between Zephyr and the MCUX SDK: Even though the FlexPWM register configuration and values are identical between Zephyr and the SDK, the interrupt is never triggered by the peripheral itself in Zephyr after initialization. In the MCUX SDK, I can observe that the SM0STS register bits CFB0 and CFB1 are being set periodically, which results in the expected interrupt behavior. In Zephyr, these same status bits (SM0STS->CFB0 and SM0STS->CFB1) are never set, even though: The peripheral setup is identical The PWM output is correct During the initial peripheral setup, these bits are automatically set once on both the SDK and Zephyr sides, and both environments execute the IRQ handler once during this initial setup. However, after this initial IRQ execution, the interrupt status bits are never toggled again in Zephyr, and no further interrupts occur. In contrast, the MCUX SDK continues to toggle these status bits periodically as expected, resulting in repeated interrupt callbacks. This suggests that while the initial interrupt path is functional in Zephyr, the FlexPWM peripheral does not continue generating interrupt events afterward, despite identical register configuration. Any insight into why the FlexPWM status bits (CFB0/CFB1) are not being set in Zephyr, or whether additional Zephyr-specific handling is required to enable periodic interrupt generation, would be greatly appreciated. Re: FlexPWM interrupt not triggering in Zephyr while SDK example works as expected Hello @wima88  Thanks for your patience. I confirmed with our internal Zephyr expert. In your project, you are using the MCUXpresso SDK driver instead of the Zephyr driver. This may cause potential conflicts. Your application uses Flexcomm1 submodule 0, which is also enabled in the Zephyr devicetree for the FRDM‑MCXN947 board. If it is enabled, Zephyr will initialize the FlexPWM driver in the startup code before main() executes. Therefore, if you choose to configure FlexPWM in your application as you are doing now, you should disable the FlexPWM node in the devicetree to avoid conflicts. Thank you. BR Alice Re: FlexPWM interrupt not triggering in Zephyr while SDK example works as expected Thank you. I understand that their may be a conflict because Zephyr initializes the FlexPWM driver before main() executes. However, I need to verify something: if I'm correct, Zephyr's devicetree is also handling the pin mux configuration through pinctrl. If I disable the flexpwm1 node in the devicetree to avoid the conflict, would I then need to manually set up the pin mux configuration in my application code, or will the pinctrl settings remain active even with the node disabled?   Wimansha  Re: FlexPWM interrupt not triggering in Zephyr while SDK example works as expected Hello @wima88  ”if I'm correct, Zephyr's devicetree is also handling the pin mux configuration through pinctrl. If I disable the flexpwm1 node in the devicetree to avoid the conflict, would I then need to manually set up the pin mux configuration in my application code, “ ->> Yes. BR Alice

PCF85063AT/AAZ 操作系统升旗 大家好 我在执行PCF85063AT/AAZ RTC 时 遇到一个问题。 我们目前使用的是 Oring 配置的双通道电源： 下面是扎根：1 号和 2 号引脚用于石英，8 号引脚用于 VDD 问题在于，当 3.3V 升高时，会触发信号操作系统（振荡器停止）标志。我们在二极管后面添加了 RC 滤波器，以降低开关噪声。 然而，操作系统的旗帜仍不时升起。 我们最终测量了石英，发现它在 power_up 期间受到了干扰（以下是石英一侧参考 GND 的测量值） 我们想知道是否有办法保护石英，还有其他我们看不到的问题。 我们正在考虑使用 4 引脚石英，而不是目前使用的 2 引脚石英。 我们还在考虑噪音也来自GND，在这种情况下，也许可以考虑使用环形屏蔽罩。 你们中有人遇到过类似的问题吗？ 我们将不胜感激。   Re: PCF85063AT/AAZ OS raising flag 你好，我们使用的是 7pF 配置。我们通过读取相应的寄存器，确认已正确设置。这也是默认配置。 Re: PCF85063AT/AAZ OS raising flag 你好 该设备具有内部振荡器，需要 32.768 kHz 的外部石英晶体。还提供 CL = 7 pF 或 CL = 12.5 pF 的可选集成振荡器负载电容。   在这种情况下，选择的负载电容是什么？ Re: PCF85063AT/AAZ OS raising flag 感谢您的确认。在这种情况下，建议 尽可能靠近 RTC 的 VDD 引脚放置一个 100 nF 的陶瓷电容。 再添加一个 10 µF 电容以帮助平滑上电顺序。 考虑使用 LC 滤波器，而不仅仅是 RC 滤波器，以更好地降低高频噪声。 如果环境噪音，请像我们的评估板一样使用带屏蔽功能的 4 引脚晶体，这有助于最大限度地减少外部干扰。 我还建议通过以下链接查看该文件： https://www.nxp.com/docs/en/user-guide/UM10301.pdf

S32DS 许可已过期 你好，我的 ARM v2.2 版 S32 Design Studio 许可证已经过期。能帮我扩展一下吗？ 配送编号：199868897 到期日期：2026 年 1 月 9 日 产品：适用于 ARM v2.2 的 S32 Design Studio 谢谢。 激活 | 安装 | 许可 | 安装程序下载 Re: S32DS License Expired 你好、 您的 S32DS 许可证已延期。请使用旧代码重新激活 S32DS。

SJA1105 in Linux, all 5 ports through PHY interfaces? Hi, I'm working on a project based around a SMARC format computer-on-a-module with a Rockchip RK3399 CPU. On the same motherboard we have a SJA1105 switch. The CPU runs Linux (5.4) and uses the NET_DSA_SJA1105 driver. Our CPU needs to communicate with other devices over Ethernet so the CPU needs to be connected to the switch. In the SJA1105 datasheet and in the Linux kernel device tree examples the host cpu is always connected to the switch as a fixed link directly over xMII. (https://www.kernel.org/doc/Documentation/devicetree/bindings/net/dsa/sja1105.txt) We cannot do this as our SMARC module only gives us pin output from the RK3399 Ethernet integrated PHY, we do not have physical access directly to the xMII interface on the CPU no matter how much we would want to. Also in the SJA1105 datasheet it says the following: "Note that Ethernet connectivity to the host processor is only needed if the system has to support AVB operation or other bridge management protocols such as STP/RSTP. If such operations are not needed, all the ports can be used for data traffic." Since we don't need AVB or STP/RSTP and since we anyway don't have access to the cpu xMII interface we have decided to just use the switch as a normal 5-port switch with PHY interfaces on every port. 4 ports where the PHY's actually goes to real RJ45 connectors and one port where the PHY is hardwired in the circuit board to the PHY that we get from our CPU on the SMARC board. This would give us a Linux device tree looking something like this: (only SJA1105 relevant part shown, indentation also became screwed when pasted here) &spi2 { status = "okay"; #address-cells = <1>; #size-cells = <0>; num-cs = <2>; cs-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>, <&gpio1 RK_PA3 GPIO_ACTIVE_LOW>; sja1105_1: sja1105@1 { status = "okay"; reg = <1>; #address-cells = <1>; #size-cells = <0>; clocks = <&ethswitch_osc>; compatible = "nxp,sja1105t"; spi-max-frequency = <25000000>; fsl,spi-cs-sck-delay = <1000>; fsl,spi-sck-cs-delay = <1000>; spi-cpha; pinctrl-names = "default"; pinctrl-0 = <&ethswitch_pins>; reset-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { /* Implicit "sja1105,role-mac;" */ label = "eth0"; phy-handle = <&rmii_phy0>; phy-mode = "rmii"; reg = <0>; }; port@1 { /* Implicit "sja1105,role-mac;" */ label = "lan1"; phy-handle = <&rmii_phy1>; phy-mode = "rmii"; reg = <1>; }; port@2 { /* Implicit "sja1105,role-mac;" */ label = "lan2"; phy-handle = <&rmii_phy2>; phy-mode = "rmii"; reg = <2>; }; port@3 { /* Implicit "sja1105,role-mac;" */ phy-handle = <&rmii_phy3>; label = "lan3"; phy-mode = "rmii"; reg = <3>; }; port@4 { /* Implicit "sja1105,role-mac;" */ phy-handle = <&rmii_phy4>; label = "lan4"; phy-mode = "rmii"; reg = <4>; }; }; }; }; This devicetree is valid and compiles, however during the probe the NET_DSA_SJA1105 fails because it cannot find a HOST CPU port (as we have not specified one). This error comes from net/dsa/dsa2.c *dsa_tree_find_first_cpu(struct dsa_switch_tree *dst) so it's not specific to sja1105 part of the driver but rather deeper in the Linux Distributed Switch Architecture. In all devicetree examples there is always one port configured as host cpu connected with fixed link over xMII, for example like this: port@4 { /* Internal port connected to eth2 */ ethernet = <&enet2>; phy-mode = "rgmii"; reg = <4>; /* Implicit "sja1105,role-phy;" */ fixed-link { speed = <1000>; full-duplex; }; }; If I try to modify my device tree to have the ports look something more like this: ports { #address-cells = <1>; #size-cells = <0>; port@0 { /* Implicit "sja1105,role-phy;" */ ethernet = <&gmac>; phy-mode = "rmii"; reg = <0>; fixed-link { speed = <100>; full-duplex; }; }; port@1 { /* Implicit "sja1105,role-mac;" */ label = "lan1"; phy-handle = <&rmii_phy1>; phy-mode = "rmii"; reg = <1>; }; port@2 { /* Implicit "sja1105,role-mac;" */ label = "lan2"; phy-handle = <&rmii_phy2>; phy-mode = "rmii"; reg = <2>; }; port@3 { /* Implicit "sja1105,role-mac;" */ phy-handle = <&rmii_phy3>; label = "lan3"; phy-mode = "rmii"; reg = <3>; }; port@4 { /* Implicit "sja1105,role-mac;" */ phy-handle = <&rmii_phy4>; label = "lan4"; phy-mode = "rmii"; reg = <4>; }; }; Then the driver is satisfied and probes successfully and sets up the SJA1105 switch. Ports 1-4 work but port 0 (where CPU is connected via a PHY) does of course not work as it's now configured as xMII would be directly connected to it when in reality we have a PHY there in between the SJA1105 and the host CPU. Is this a limitation the the DSA SJA1105 Linux driver, that you always must configure a fixed link over xMII? Can I somehow configure directly from the device tree that i DO NOT wish to have a dedicated cpu host port at all but rather just 5 normal ports (of which one then happens to so be connected to the CPU via a PHY...) Or can I configure the CPU host port to be there as a fixed-link, but explicitly specify that there is actually a PHY there also and not a xMII interface? I have tried dozens and dozens of combinations and still not found any way to configure this so that it will work with our supposedly very simple setup. Am I just missing something really obviously simple here? Any ideas how to proceed? Or is this just not possible with the Linux DSA SJA1105 driver? Regards Re: SJA1105 in Linux, all 5 ports through PHY interfaces? @kalamata @Sabeur were you able to arrive at a solution to this issue. I am running into a similar situation with Toradex imx8mp SoM.  Re: SJA1105 in Linux, all 5 ports through PHY interfaces? @kalamata @Sabeur Did you arrive at a solution to this issue? I am running in a similar problem but with Toradex Verdin IMx8mp SoM. Re: SJA1105 in Linux, all 5 ports through PHY interfaces? Hi,  I see the phy-mode and phy-handle for the port 0: port@0 { /* Implicit "sja1105,role-mac;" */ ethernet = <&gmac>; label = "eth0"; phy-handle = <&rmii_phy0>; phy-mode = "rmii"; reg = <0>; }; This is how the device tree should look like. Also, the gmac node should contain &gmac {     phy-handle = <&rmii_gmac_phy>;     phy-mode = "rmii"; }; best regards, Sabeur Re: SJA1105 in Linux, all 5 ports through PHY interfaces? Hi Kalamata,  Thanks for the details.  So my assumptions were correct.  You should be able to specify phy-handle and phy-mode for the connected MAC interfaces. It was tested virtually, means MAC -> PHY - > --- <- PHY <- MAC from 5.3 Kernel version. (see 0e27921816ad99f78140e0c61ddf2bc515cc7e22). So this is the right way to describe this kind of HW connection in the device tree. Regards,  Sabeur Re: SJA1105 in Linux, all 5 ports through PHY interfaces? Hi Sabeur, Thank you for the reply! Is the above data path possible in your setup ? Yes, we are using exactly that setup: (CPU) Mac - Phy - Phy - Switch Mac (see attachments) Has the Rockchip RK3399 CPU an internal PHY ? Yes, it has an internal PHY, and we are stuck using this internal PHY, as it's the only thing coming out from the Advantech ROM-5780 SMARC module where our CPU is located, so we could not use the CPU MAC interface directly even if we wanted to. See attached pictures for how our setup differs from the typical setup suggested by the SJA1105 datasheet. We have an Advantech ROM-5780 Computer-on-a-chip module (i.e. a Rockchip RK3399 CPU) packaged in SMARC format. The Rockchip RK3399 has an integrated PHY interface and that is what we have access to on the output pins on the SMARC module. We do NOT have physical access to the MAC pins of the RK3399 Ethernet controller as they are not coming out via the SMARC module, so we are stuck using the RK3399 PHY interface. Therefore on the 5:th port on the SJA1105 where we intend to connect our CPU we have a PHY controller (just like we have on ports 1-4) and that PHY controller is permanently wired to the PHY controller coming out of the RK3399 CPU. Regards, Kalamata Re: SJA1105 in Linux, all 5 ports through PHY interfaces? Hi, Theoretically it should be possible however, i will not work out of the box because the expected setup is to have a direct link. The data path which can work is: Mac - Phy - Phy - Switch Mac. In this case you will need to modify the DSA kernel and specify Phy handle and Phy mode for both CPU Mac and Switch Mac. Now the question is: is the above data path possible in your setup ? Has the Rockchip RK3399 CPU an internal PHY ? Best regards, Sabeur Re: SJA1105 in Linux, all 5 ports through PHY interfaces? The PHY-to-PHY back to back is possible. You have to use the phy-handle property. You can also bypass auto-negotiation and set a fix speed with the "fixed-link" property in devicetree bindings. If you are having problem and you suspect your devicetree configuration is correct, kindly check the control path interface (SPI/I2C/MDIO).

iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi，NXP支持专家， 我们参考iMX93EVK 设计了一块板子，只使用了LVDS连接LCD，请问：   uboot传什么启动参数 bootargs 到Linux kernel?   怎么修改 include\configs\imx93_evk.h ? Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi Zhiming_Liu, uboot指定一下fdtfile就行 请问怎么修改代码来实现 指定 fdtfile呢？谢谢 Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi @OscarLi  uboot里只需要指定内核使用的fdtfile为这个dtb就行。不需要其他参数。另外这个里面的屏幕参数需要根据实际的屏幕改一下。menuconfig不需要改，如果简单一点的话，你就直接改imx93-11x11-evk-boe-wxga-lvds-panel.dts，然后uboot指定一下fdtfile就行。 Best Regards, Zhiming Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi Zhiming_Liu,     你好，      Hi, 你们想要内核使用LVDS对吗？ 如果是想要驱动内核里的LVDS，参考内核设备树就行。 linux-imx/arch/arm64/boot/dts/freescale/imx93-11x11-evk-boe-wxga-lvds-panel.dts     我们想通过LVDS显示，不太明白你的回答。 1. 我们的iMX6DL板子，通过LVDS显示，uboot传bootargs包含 video 参数，iMX93的uboot不需要传video参数吗？ 2.  imx93-11x11-evk-boe-wxga-lvds-panel.dts需要修改吗？  把imx93-11x11-evk-boe-wxga-lvds-panel.dts编译成 dtb，只烧录这1个dtb文件到 EMMC ？ 编译 Linux Kernel ,  menuconfig  需要修改吗？ Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi, 你们想要内核使用LVDS对吗？ 如果是想要驱动内核里的LVDS，参考内核设备树就行。 linux-imx/arch/arm64/boot/dts/freescale/imx93-11x11-evk-boe-wxga-lvds-panel.dts at lf-6.12.y · nxp-imx/linux-imx Best Regards, Zhiming Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 嗨， @Zhiming_Liu ， uboot 规范 fdtfile imx93-11x11-evk-boe-wxga-lvds-panel.dtb，显示屏自由格式，波形显示量 lvds 时钟拉腿，无时间波形（所有信号均为波形） Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi, @Zhiming_Liu       我们板子的 DDR 与NXP iMX93EVK同型号，只是容量为 1GB（EVK 为2GB）， u-boot imx93_evk.h #define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x40000000 /* 改成了 1GB DDR */  还是 DDR: 3733MTS Training FAILED 能不能禁用这个DDR校准？ Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi @OscarLi  你们用的对应引脚都正确设置了吗？上电过程正确吗？ Best Regards, Zhiming Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi @OscarLi  布线不同也需要重新校准。 Best Regards, Zhiming Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi @OscarLi  出现这个错Training FAILED说明是DDR校准有问题。如果你们不是EVK，需要通过Config Tool校准并生成新的DDR时序文件，然后替换进uboot里的DDR时序。Config Tool的使用可以参考这个文章：https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX93-DDR-setting-and-config-tool-usage/ta-p/1759391 Best Regards, Zhiming Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi, @Zhiming_Liu ,    LVDS信号线连接正确，LCD屏连接 iMX6DL 能正常显示。  不管是 u-boot 2023.04还是 2025.04， make imx93_9x9_qsb_defconfig配置，然后编译后，用imx-mkimage生成flash.bin 才能在我们的板子上启动，我们参照 iMX93EVK设计的硬件原理图。 使用 make imx93_11x11_evk_defconfig配置，就会出现如下错误，M33 prepare ok 后就没有输出信息了。  U-Boot SPL 2023.04 (Jan 13 2026 - 10:22:53 +0800) SOC: 0xa1009300 LC: 0x2040010 PMIC: Over Drive Voltage Mode DDR: 3733MTS Training FAILED M33 prepare ok    Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 你好，@刘志明 U-Boot 2025.04-g4ddbad60eff3-dirty(Jan 14 2026 - 11:05:46 +0800) RESET 状态：POR CPU：1700 MHz 时的恩智浦 i.MX93 (52) Rev1.1 A55 CPU：33C 时的工业温度等级（-40C 至 105C）型号：恩智浦 i.MX93 11X11 EVK 主板 动态随机存取存储器(DRAM)：1 GiB optee optee：OP-TEE api uid 不匹配 optee 由 NXP yocto 生成，怎么修改这个 api uid 不匹配，谢谢？ Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi @OscarLi  现在板子起来的了吗？能正常进入内核了吗？ Best Regards, Zhiming Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi, @Zhiming_Liu  能够正常挂载 rootfs。 请教另一个问题， 我们板子上的 EMMC 是 8GB，但是文件系统只使用了4GB，想把另外的4GB用来存数据， 使用NXP yocto制作rootfs时，是不是能把文件系统占用的空间改大到8GB， 还是有另外的方法能够使用剩余的4GB ?  谢谢 root@imx93evk:/# fdisk -l Disk /dev/mmcblk0: 7.28 GiB, 7818182656 bytes, 15269888 sectors Units: sectors of 1 * 512 = 512 bytes Sector size (logical/physical): 512 bytes / 512 bytes I/O size (minimum/optimal): 512 bytes / 512 bytes Disklabel type: dos Disk identifier: 0x076c4a2a Device Boot Start End Sectors Size Id Type /dev/mmcblk0p1 * 16384 540671 524288 256M c W95 FAT32 (LBA) /dev/mmcblk0p2 540672 7835157 7294486 3.5G 83 Linux ------------------------------------------------------------------ Re: iMX93EVK -- uboot传什么启动参数 bootargs 为了使用LCD，通过LVDS连接 Hi @OscarLi  在conf/local.conf中使用下面的宏： IMAGE_ROOTFS_EXTRA_SPACE = "4000000" https://docs.yoctoproject.org/singleindex.html#term-IMAGE_ROOTFS_EXTRA_SPACE Best Regards, Zhiming

VR5510 BUCKx 电气规格和 LDO2 不稳定性 Hello 我正在寻找有关 VR5510 BUCK 性能的信息：我想在模拟应用中使用它们，其中低压差线性稳压器(LDO) 是正确的选择：但是 VR5510 低压差线性稳压器(LDO) 在某些情况下可能会处于极限电流。我找不到任何有关 BUCK 电压纹波规格的信息（指我正在使用的建议输出滤波器）。有可能拥有吗？我在论坛上发现，其他 VR 都有此类信息，但 VR5510 没有。 我在将 VR5510 与 SJA1110 配套使用时遇到一个问题。长话短说：如果 SJA1110 保持在硬 RESET 状态然后我从外部电源为 VR5510 加电，连接到 VDDIO 1.8V MII 电源轨道的 LDO2 就会不稳定地启动，产生 2.2V 而不是 1.8V（我认为如果不受某些 SJA1110 内部钳位的限制，电压可以升至 Vin 3.3V） 附上了恩智浦 SJA1110-EVM 板的原理图部分，这正是我在定制板上使用的。 我正在使用 VR5510 内部电压监测器监测 1.8V 电压，在这种情况下，VR5510 PGOOD 永远不会因为检测到过压而改变状态。 非常奇怪的是，如果我断开 PGOOD 引脚与 SJA1110 HARD RESET 引脚的连接，我就没有问题了，PMIC 与 SJA1110 一起成功启动。 LDO2 是否有可能因输出负载电流过高而进入不稳定状态，并且再也无法恢复？OTP 程序每 4 秒自动重试一次，但 VR5510 从不重试。 谢谢 enrov 电源解决方案 Re: VR5510 BUCKx electrical specification and LDO2 instability 你好，恩里科、 感谢您提出有关 VR5510 的问题。   VR5510 的 BUCKx 输出纹波规格为峰峰值 1% 。   请确认您使用的是哪个 VR5510 部件号？ 如果 vmonX 未用于 LDO2 电压监控，则在 LDO2 过压 (OV) 的情况下无法钳位 PGOOD。请注意，VR5510 没有用于 低压差线性稳压器(LDO) 轨道的内部电压监测器。   这个问题是出现在所有模块上，还是只出现在某个模块上？如果所有模块都能重现该问题，我建议与 SJA1110 工程师跟进，检查该问题是否也能在 SJA1110 EVB 上重现。 如果 LDO2 工作在过载状态，预计故障将是 UV（欠压），而不是 OV（过压）。 作为故障排除步骤，请断开 LDO2 负载并检查设备是否正常启动。此外，我建议测量 LDO2 和 VPRE 网络的阻抗，确保它们在正常范围内。   BRs, Tomas Re: VR5510 BUCKx electrical specification and LDO2 instability 你好，托马斯、 好的，谢谢。 为了结束 LDO 的话题，对于 VR5510，是否有可能用外部镇流器电阻器并联 LDO2 和 LDO3（看起来功率相同），让它们共享略高于最大 400 毫安（短暂）的电流，从而将电压控制在一定范围内？ 或者，你能否告诉我，在噪声很重要的模拟应用中，三buckS变流器是否可以用作LDO的替代方案？(这是因为我问的是预期输出电压纹波）。 我正在开始一项新的应用，希望使用 VR5510 为一些高速 ADC 和运算放大器（几十 MHz 的应用范围）供电。 谢谢 恩里科 Re: VR5510 BUCKx electrical specification and LDO2 instability 你好，托马斯 ，感谢您的答复。 深入分析后发现，LDO2 是由不受控制的外部电压驱动的，电压从 1.8 升至 2.2。由于我正在使用VREF监视LDO2，因此从未钳位过PGOOD。 问题似乎出在 SJA 方面，我唯一的好奇心是想知道 LDO2 是否会不稳定，以及它是否能将输入电压转换为输出电压。我同意您说的过载与 UV 有关这一点，但我没有看到 UV。 只是为了分享：VR5510（我使用的是 AMMA0 和 AMBA0 版本）似乎不是问题的根源。但是，任何有关 LDO 稳定性和不稳定性行为的建议都是可以接受的。 致敬 Re: VR5510 BUCKx electrical specification and LDO2 instability 你好，恩里科、 如果 LDO 稳压器的外部元件在规定范围内，则不应存在不稳定的风险。我们通常认为，除非专门将低压差线性稳压器(LDO)配置为负载开关模式，否则低压差线性稳压器(LDO)的输入无法直接转发到输出。 BRs, Tomas Re: VR5510 BUCKx electrical specification and LDO2 instability 你好，恩里科、 VR5510 上的 LDO2 和 LDO3 不能并联使用。 通常，不建议将 BuckX 输出用作 ADC 的直接参考。为此，我们建议在 BuckX 之后添加一个外部低压差线性稳压器(LDO)。 BRs, Tomas

#TJA1104 SAF9000 OM7 RTDとのドライバ統合 こんにちは、 私はQuantum (SAF9000) OM7の お客様 アプリケーション サポート エンジニアとして働いています。 現在、弊社の お客様 (Hirschmann) は SGMII インターフェースに関する問題に直面しています。TX 極性が逆になっているように見えますが、ボードは CONFIG レジスタを通じてこれを修正することを想定し、このように設計されました。 彼らは # TJA1104デバイスを使用しており、システムとの互換性を確保するために適切なドライバを統合したいと考えています。 TJA1104 ドライバーを既存のRTD ドライバーと統合する方法をお客様にご案内してサポートしていただけますか? ご返信よろしくお願いします。 よろしくお願いいたします。 ナガ・セギレディ AA SW - 外部デバイス Re: #TJA1104 Driver integration with SAF9000 OM7 RTD こんにちは、 AASW チームは、Quantum のコンテキストでこのコンポーネントに対する SW サポートのリクエストを受け取りませんでした。CES チーム (Florea Simona または Salam Zeidan が対応可能) までお問い合わせください。 Re: #TJA1104 Driver integration with SAF9000 OM7 RTD こんにちは、ナガさん 昨日、Simona Florea と話をしましたが、最新情報に基づいて、Quantum プロジェクトのコア チームである Harm Voss (APM) と Ron Leenders (RTE) に連絡することを強くお勧めします。 Re: #TJA1104 Driver integration with SAF9000 OM7 RTD こんにちは、 情報をいただきありがとうございました。 サポートについては、@Florea Simona または Salam Zeidan に連絡しました。 よろしくお願いいたします。 ナガ・セギレディ

#TJA1104 Driver integration with SAF9000 OM7 RTD Hello, I am working as Customer application support engineer for Quantum (SAF9000) OM7. Our customer(Hirschmann) is currently facing an issue with the SGMII interface. The TX polarity appears to be reversed, and their board was designed this way with the expectation of correcting it through the CONFIG register. They are using the #TJA1104 device and now would like to integrate the appropriate drivers to ensure compatibility with their system.  Could you please support the customer by guiding them on how to integrate the TJA1104 drivers with the existing RTD drivers? Thank you very much! Best Regards, Naga Segireddy AA SW - External Device Re: #TJA1104 Driver integration with SAF9000 OM7 RTD Hello, The AASW team didn't received any request for SW support for this component in context of Quantum. Please address to the CES team (possible @Florea Simona or Salam Zeidan) Re: #TJA1104 Driver integration with SAF9000 OM7 RTD Hello, Thank you very much for the information. I have contacted @Florea Simona or Salam Zeidan for the support. Best Regards, Naga Segireddy Re: #TJA1104 Driver integration with SAF9000 OM7 RTD Hi Naga, I spoke with Simona Florea yesterday, and based on the latest information, I strongly recommend reaching out to the Quantum project core team: Harm Voss (APM) and Ron Leenders (RTE).