WDOG32 Interrupt Not Triggering Before Reset on i.MX8ULP Hello, I am working on the i.MX8ULP and trying to use the WDOG32 in interrupt mode before it triggers a reset. Even though I have configured the watchdog with interrupt enabled, it is still behaving as a normal watchdog — it resets the system directly without generating an interrupt. void WDOG0_IRQHandler(void)
{
PRINTF("Watchdog IRQ triggered! Count = %u\r\n", wdog_irq_count);
/* Clear interrupt flag */
WDOG32_ClearStatusFlags(WDOG0, kWDOG32_InterruptFlag);
wdog_irq_count++;
SDK_ISR_EXIT_BARRIER;
}
/* Get default configuration */
WDOG32_GetDefaultConfig(&config);
/* Enable interrupt mode */
config.enableInterrupt = true;
config.timeoutValue = WDOG_TIMEOUT_VALUE;
NVIC_EnableIRQ(WDOG0_IRQn);
for (temp = 0; temp < DELAY_TIME; temp++)
{
__NOP();
}
/* Initialize WDOG32 with config */
WDOG32_Init(WDOG0, &config);
while(1)
{
} I have attached full wdog32.c file also in that watchdog IRQ i have put watchdog refresh but still it is resetting after timeout occurs. Are there any additional initialization needed for WDOG32 interrupt mode and in this i only required interrupt not reset is it possible? i.MX8ULP Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP Hi, @Bio_TICFSL Have you checked with the EVK to bootup on 0.9V when watchdog is resetting? Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP Hi, @Bio_TICFSL I have tested with the EVK using the watchdog example code at the default high frequency, and it boots fine. However, when I lower the voltage to 0.9V (as in my earlier code snippet), after a watchdog timeout occurs the core gets stuck during bootup. If you have tested this on the EVK at 0.9V. Could you please share the exact code/configuration that you used on the EVK for this test? Regards, Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP Hi,
The code is fine I just looking something that decrease the voltage, because ~9.0 volts boot ok with the EVK.
Regards Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP Hii, @Bio_TICFSL status = UPOWER_ChngRTDDomBias(DRIVE_MODE_UD);
assert(status == 0);
status = UPOWER_ChngPmicVoltage(PMIC_BUCK2, PMIC_VOLTAGE_0_9V);
if (status == 0)
{
status = UPOWER_GetPmicVoltage(PMIC_BUCK2, &voltage);
if (status == 0 && voltage == PMIC_VOLTAGE_0_9V)
{
// success
}
else
{
assert(false);
}
}
else
{
assert(false);
} During debugging I found that: When the PMIC is set to 0.9V in ARBB mode, after a watchdog reset the core gets stuck during boot. If I increase the PMIC voltage to 1.0V or 1.1V, the reset and boot work fine, even at lower frequencies. I need to keep the PMIC voltage at 0.9V to save power, but with this setting the system cannot reliably boot after a watchdog reset. 👉 What might be causing this issue at 0.9V, and are there any recommended changes or workarounds to ensure the core can boot properly after a reset at this voltage? Any help or guidance would be appreciated. Re: WDOG32 on ARBB mode of cortex-M33 after reset bootup issue on i.MX8ULP On the Cortex-M33 of the i.MX8ULP, I have configured the M33 core to run in ARBB mode. When the watchdog timeout occurs, it tries to reset the core. However, during the reboot process the core seems to get stuck, because before the reset the code had switched the M33 into ARBB mode, which runs at a lower frequency. What modifications are required so that if the core is running in ARBB mode and a watchdog reset occurs, it can successfully boot up again? Re: WDOG32 Interrupt Not Triggering Before Reset on i.MX8ULP Hii, @Bio_TICFSL I am able to use the watchdog in non-interrupt mode, and it is resetting the system as expected. However, I require the watchdog interrupt mode, and I am not sure about the correct configuration steps for enabling and handling the interrupt. Can you please guide me on how to enable WDOG32 in interrupt mode so that my code actually enters the WDOG32 IRQ handler before reset? Re: WDOG32 Interrupt Not Triggering Before Reset on i.MX8ULP Hello,
Yes, it should be possible according to Reference Manual, look at chapter 9.1.7 Power mode details (real-time domain):
As you can see all the necessary components to WDOG0 are available during ARBB mode, but maybe there is the possibility that uPower is gating clock of this WDOG or maybe of entire PBRIDGE0.
Please take a look to the uPower Firmware User's Guide.
Regards
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