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MCUXpresso SDK 2.12.1 RT Platform: UM11441 Getting Started with NXP-based Wireless Modules Wireless module combinations from Tables 2 and 3 are not updated with the latest SDK 2.12.1 in the user manual UM11441. Major updates in Table 2 and Table 3: u-blox modules are supported only on rt1060 Murata modules are only tested with i.MX RT1060 EVKB and i.MX RT1040 EVK platforms Modified Murata modules names Renamed i.MX RT685S EVK to IMXRT685-AUD-EVK Please refer to the attached PDF for updated information.
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Apply Arduino virtual adapter into compatible header This article was written for MCUXpresso Config tools v12 and older. Newer MCUXpresso Config tools can map Arduino expansion boards into compatible expansion headers automatically, without the need for any virtual adapter and even with possibility to utilize all the spare pins! This tutorial shows how to apply and use the appropriate Arduino virtual adapter file (virtual adapters are attached) to utilize Arduino compatibility across different expansion headers. Benefit Virtual adapter board files allow users of the Pins tool from the MCUXpresso Config tools suite to use the expansion board file intended for a standard Arduino expansion header with other NXP expansion headers that are compatible with the Arduino standard but not mechanically identical (for example, they use two rows of pins). Arduino-compatible expansion headers Freedom Header (Kinetis FRDM boards) LPCXpresso V3 (LPC boards) LPCXpresso V3 Mirrored Normally, such expansion headers are treated as different in the Pins tool, but the virtual adapter file transforms the current board header into the standard Arduino header so the user can apply the expansion boards referencing the standard Arduino header. For details on the expansion board, see Creating expansion board definition file for Arduino Multifunction shield.   Step 1: Open the Expansion Header view Open the Expansion Header view if it is not open. In the standalone MCUXpresso Config tools, select the command Views > Expansion header  In the MCUXpresso IDE, select the command Window > Show view > Expansion Header  Step 2: Apply the Arduino virtual adapter file The application of the virtual adapter file is the same as the application of the expansion board definition file. Use the attached virtual adapter files. Press the “Apply expansion board” button Locate the virtual adapter file and confirm Select if you want to create the functional group (recommended) Choose which names you would like to use in your source code Apply the expansion board Step 3: Switch to the newly created header Choose the Arduino adapter header option and select the newly created “Arduino adapter” header. Using the “+” button, select and apply an expansion board intended for the standard single-row Arduino header, and it will be connected to appropriate pins automatically.
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MBDT for MPC57xx - Frequently Asked Questions General Installer and Setup  External mode External mode example wouldn't compile after update  Others MPC57xx MBD Toolbox not appears in Simulink Library Browser  Peripherals Apps Motor Control BMS Request for HSD/LSD/MSDI Communication Examples for MPC5775B BMS and VCU Reference Design 
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StarCore DSP FAQs How can I distinguish between various MSC8154/MSC8156 devices? My configuration sets up the L2 unified cache/M2 memory to 256KB of M2 and 256 KB of L2 cache. Does this mean L2 cache is 8 ways of 32 KB each? Does an M3 ECC event trigger an interrupt? The L2 cache features 4 L2 software prefetch channels. Are there 4 software prefetch channels per core or is this the total number per device? Do I need an I2C serial EEPROM for loading of the Reset Configuration Word (RCW)? How does MSC8156 MAPLE-B TVPE support Viterbi and Turbo decoding? I want to use the Debug and Profiling Unit (DPU) in the MSC8156 to log information into the virtual trace buffer. I have set up the DPU registers for core 0. How do I set up the DPU for the other cores 1/2/3/4/5 since there is only one set of DPU registers? I only need to reset an individual core in the MSC8156. How can I do that? The MSC8156 Reference Manual shows the default DDR1 and DDR2 memory address spaces are 512 MB. How do I change the memory space to 1 GB? What is the maximum heat sink attachment force to avoid damaging the solder balls? What does the NO_INC bit indicate in the DMA buffer descriptor BD_ATTR field? When would you use this? If a MSC8156 DMA port A or B bus error happens, i.e., DMAERR[PAE] or DMAERR[PBE] bit is set, can I clear these bits and continue with the DMA operation? If a DMA BD size 0 error occurs, i.e., DMAERR[BDSZ] is set, to indicate that the buffer descriptor field BD_SIZE is cleared, how can I tell which DMA channel is associated with the error? How can I distinguish between various MSC8154/MSC8156 devices? You can read the System Part and Revision ID Register (SPRIDR) from address  to get the part ID and revision ID numbers. Device             SPRIDR[PARTID] MSC8154                0x8304 MSC8154EC           0x831C MSC8154E             0x830C MSC8156               0x8302 MSC8156EC           0x831A MSC8156E             0x830A Revision           SPRIDR[REVID] Rev. 1                       0x0000 Rev. 2                       0x0001 [ return to top ] My configuration sets up the L2 unified cache/M2 memory to 256KB of M2 and 256 KB of L2 cache.  Does this mean L2 cache is 8 ways of 32 KB each? No. The L2/M2 is 512 KB, arranged in 8 ways of 64 KB each way. In your configuration, the L2 cache becomes 4 ways. Each way is still 64 KB. [ return to top ] Does an M3 ECC event trigger an interrupt? M3 memory is ECC-protected so a single-bit error is detected and corrected, therefore an interrupt is not necessary. [ return to top ] The L2 cache features 4 L2 software prefetch channels.  Are there 4 software prefetch channels per core or is this the total number per device? The L2 cache is private for each core, therefore the 4 software prefetch channels are per core. Each core configures its own set of L2 software prefetch registers. Each core can only configure its own L2. The L2 software prefetch registers cannot be configured externally from the DSP subsystem. [ return to top ] Do I need an I2C serial EEPROM for loading of the Reset Configuration Word (RCW)? No, there are other options for loading of the RCW besides the I2C serial EEPROM. Multiplexed RCW loading option(RCW_SRC[0:2]=000) - all 64-bits of the RCW are loaded in four passes using the external pins RC[15:0]  using the /RCW_LSEL[0:3] pins as lane select signals. Reduced RCW loading option (RCW_SRC[0:2]=011) - some bits of the RCW are latched from external pins and some bits are loaded from default hard-coded values. [ return to top ] How does MSC8156 MAPLE-B TVPE support Viterbi and Turbo decoding? Turbo and Viterbi decoding are supported by MSC8156 MAPLE-B TVPE in same µcode. You can initialize the Maple with one TVPE standard, plus some Viterbi parameters. Then you can use different Buffer Descriptors for Turbo and Viterbi. Note that MAPLE-B doesn't support multiple Turbo standards with the same µcode because Maple µcode is standard specific and a µcode re-load is required to switch from one standard to another. So supporting a mixture of users of different standard in real time cannot be done with current MAPLE-B.  Turbo and Viterbi decoding are supported in same µcode, since Viterbi decoding parameters are fully configurable and are not standard related. [ return to top ] I want to use the Debug and Profiling Unit (DPU) in the MSC8156 to log information into the virtual trace buffer. I have set up the DPU registers for core 0. How do I set up the DPU for the other cores 1/2/3/4/5 since there is only one set of DPU registers? Each DSP subsystem includes a DPU. Each core can access its own DPU registers using the same physical addresses. [ return to top ] I only need to reset an individual core in the MSC8156. How can I do that? All cores are reset together. There is not a method to reset a particular core in the MSC8156. [ return to top ] The MSC8156 Reference Manual shows the default DDR1 and DDR2 memory address spaces are 512 MB. How do I change the memory space to 1 GB? The MSC8156 Reference Manual shows the DDR address spaces as follows: 0x40000000–0x5FFFFFFF      DDR1 Memory (default value)                                               512 M 0x60000000–0x7FFFFFFF      Reserved.  Used for DDR1 memory if configured for 1 GB.      512 M 0x80000000–0x9FFFFFFF      DDR2 Memory (default value)                                               512 M 0xA0000000–0xBFFFFFFF     Reserved. Used for DDR2 memory if configured for 1 GB.       512 M After reset, the default DDR1 and DDR2 memory space is 512 MB. To increase to 1GB DDR memory range, you need to configure the CLASS registers as follows: For DDR1 memory controller, change C0EAD5 from the reset value of 0x0005FFFF to 0x0007FFFF [ return to top ] What is the maximum heat sink attachment force to avoid damaging the solder balls? Detailed information about the Flip-Chip Plastic Ball Grid Array (FC-PBGA) package type devices (MSC8144 and MSC8156) can be found in this document FC-PBGAPRES.pdf The maximum heat sink attachment force is 4 Newtons (10 lb force). [ return to top ] What does the NO_INC bit indicate in the DMA buffer descriptor BD_ATTR field? When would you use this? You can set NO_INC if you want to transfer to or from the same address. The address will not be incremented. For example, if you want to fill memory with data from a single memory location, you will need to set NO_INC for the source. However, the destination will have the NO_INC bit cleared. [ return to top ] If a MSC8156 DMA port A or B bus error happens, i.e., DMAERR[PAE] or DMAERR[PBE] bit is set, can I clear these bits and continue with the DMA operation? A port error will freeze the DMA channel so clearing the error bit has no effect. In this case, the DMA channel needs to be reinitialized before it can be used again. [ return to top ] If a DMA BD size 0 error occurs, i.e., DMAERR[BDSZ] is set, to indicate that the buffer descriptor field BD_SIZE is cleared, how can I tell which DMA channel is associated with the error? The DMAERR register does not indicate which channel accessed the BD with size 0. However, you can check the DMACHCRx registers to determine which channel did not finish the transfer by checking if the active ACT bit is high. A channel that does not encounter the error will finish (ACT bit gets cleared). [ return to top ] .
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视频 - 云开发教程 1/6:安装和配置适用于 MQX 的 iDigi 连接器 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 适用于 MQX 的 iDigi 连接器的视频教程 1/6:安装和配置适用于 MQX 的 iDigi 连接器(1/6) - iDigi 设备云 更多信息及免费下载请访问: http://www.freescale.com/webapp/sps/site/prod_summary.jsp? code=KINETIS_IDIGI_M2M
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Power Architecture 的新服务包发布!(Windows)〜 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> QorIQ处理平台的优势已融入众多应用领域!例如,网络、移动无线基础设施、自动化功能、医疗应用等等! 这样,您就可以更轻松地将高性能通信、基站和计算系统推向市场 先进的工具、多核、加速器、安全性等等。 一些服务包已经发布,以增强您在这项技术上的设计能力。其中第四个是与 Power Architecture Processors v10.1.2 一起介绍的。服务。 此次改进主要应用在以下设备中: P4040 DS  裸机支持 U-boot 调试 P4080 DS  裸机支持 U-boot 调试 P3041 DS 九头蛇  Linux 内核和应用程序调试 P3041 DS 超级九头蛇  Linux 内核和应用程序调试     Power Architecture Processors v10.1.2 新增并改进了更多功能 在发行说明中了解它们! 立即下载Windows 版 Service Pack 4 !   你更喜欢Linux 版本? 概述
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Video - Cloud Development Tutorial 5/6: Enabling Remote Firmware Update (K60) Tutorial 5 of 6 for the iDigi Connector for MQX: Enabling iDigi Remote Firmware Update (5 of 6) - iDigi Device Cloud More information and free download at http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=KINETIS_IDIGI_M2M
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Developer’s Serial Bootloader. for M68HC08, HCS08, ColdFire and Kinetis MCUs by: Pavel Lajsner, Pavel Krenek, Petr Gargulak Freescale Czech System Center Roznov p.R., Czech Republic The developer's serial bootloader offers to user easiest possible way how to update existing firmware on most of Freescale microcontrollers in-circuit. In-circuit programming is not intended to replace any of debuging and developing tool but it serves only as simple option of embedded system reprograming via serial asynchronous port or USB. The developer’s serial bootloader supported microcotrollers includes 8-bit families HC08, HCS08 and 32-bit families ColdFire, Kinetis. New Kinetis families include support for K series and L series. This application note is for embedded-software developers interested in alternative reprogramming tools. Because of its ability to modify MCU memory in-circuit, the serial bootloader is a utility that may be useful in developing applications. The developer’s serial bootloader is a complementary utility for either demo purposes or applications originally developed using MMDS and requiring minor modifications to be done in-circuit. The serial bootloader offers a zero-cost solution to applications already equipped with a serial interface and SCI pins available on a connector. This document also describes other programming techniques: FLASH reprogramming using ROM routines Simple software SCI Software for USB (HC08JW, HCS08JM and MCF51JM MCUs) Use of the internal clock generator PLL clock programming EEPROM programming (AS/AZ HC08 families) CRC protection of serial protocol option NOTE: QUICK LINKS The Master applications user guides: Section 10, Master applications user guides. The description of Kinetis version of protocol including the changes in user application: Section 7, FC Protocol, Version 5, Kinetis. The quick start guide how to modify the user Kinetis application to be ready for AN2295 bootloader: Section 7.8, Quick guide: How to prepare the user Kinetis application for AN2295 bootloader. Full application note and  software attached. Freedom Development Platform Kinetis K Series MCUs Kinetis L Series MCUs Re: Developer’s Serial Bootloader. Hi, link is broken, can you fix it please? Re: Developer’s Serial Bootloader. Is there any support for the 9s12 parts?  It would seem to be a good fit. Bob Re: Developer’s Serial Bootloader. https://community.freescale.com/thread/38615?start=210&tstart=0 Re: Developer’s Serial Bootloader. Where I can find this bootloader for CW? I need implement it on KwikStick its running on K40X256VLQ. I have downloaded this version for IAR and can build it with iar but can't build debug version, so any help is good from you guys. When I try to build debug version with iar I get this error " Error[Li005]: no definition for "main" [program entry] Error[Lp014]: cannot fit "Section .text (bootloader.o #21)" (min size 0x5a0, alignment 0x4) into any of the ranges <[0x00000040-0x000003ff],  [0x00000410-0x000008ff]> Error while running Linker " I tried to edit project->options->debugger->runto __main but with no success. Re: Developer’s Serial Bootloader. Hi, Yes it is available for Kinetis K, L and M series. Re: Developer’s Serial Bootloader. Hi All, Is it available for Kinetis? Thanks. Re: Developer’s Serial Bootloader. Hello. Anyone know when it will be available the Serial Bootloader for Kinetis, for CodeWarrior 10.3? Thank you. Fernando. Re: Developer’s Serial Bootloader. CodeWarrior 10.4 is out. Any idea when the Serial Bootloader for Kinetis will be available? Thanks.. Joe Re: Developer’s Serial Bootloader. Actually I tried to enforce EWARM to jump to __main instead of main, but debugger report error as well. I forgot to mentioned in my previous post. I know supporting different compilers + mcu + boards + configurations are messy and difficult work. Re: Developer’s Serial Bootloader. Hi All, New version of the bootloader includes support for CodeWarrior 10.3 for all Kinetis families will be available in the next weeks. Pavel Krenek AN2295 developer Re: Developer’s Serial Bootloader. Hi, classic main function is not included in the bootloader source code, we used __main as you mentioned. This function has the same functionality. Re: Developer’s Serial Bootloader. It covers too many micros in one package. I doubt if you guys have enough time to test the code. Re: Developer’s Serial Bootloader. I use AN2295 for Kinetis KL25Z FRDM as bootloader. I can build it successfully, but its debugger reports following message: The stack plug-in failed to set a breakpoint on "main". The stack window will not be able to display stack contents. You can change this setting in the Tools>Options dialog box. Actually I can not find main(void), but I do find __main(void) in bootloader.c How can I fix it? Re: Developer’s Serial Bootloader. I heard freescale was suppose to release the software for the kinetis but I have not seen it. Still waiting. Re: Developer’s Serial Bootloader. Is there some gays to use this docment to do it sucessful Re: Developer’s Serial Bootloader. Same here. I am struggling to convert this over to CW 10.3 for the TWR-K20D50M using either CWC-compiler or the GNU-compiler. Has anyone succeeded with that yet? Re: Developer’s Serial Bootloader. I am struggling a little trying to convert this over to Codewarrior 10.2 and a K70. Has there been any work done on that yet? Or even a CW10.3 version? Re: Developer’s Serial Bootloader. It would be fantastic if a Codewarrior 10.x version were to be available. I am having a little difficulty figuring out the conversion. Linker files, etc. Thank you very much for posting this. P
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准备好使用和编译您的飞思卡尔 RS08 了吗? <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 关于MCU开发工作室和RS08工具存在一些问题。希望本参考手册能够解答所有问题 快来吧!   作为文档的一个小预览,我将解释RS08 Build Tools 参考手册描述了用于飞思卡尔 8 位 MCU(微控制器单元)芯片系列的 ANSI-C/C++ 编译器。此外,本文档还包含以下主题供您( CodeWarrior用户)参考: • 使用编译器。 它显然描述了如何运行编译器,该编译器由前端(依赖于语言)和后端(依赖于硬件)组成,并生成特定于 RS08 的目标代码。您可能已经知道,编译器的主要目标是将源代码(例如 C 源代码文件)转换为目标代码文件,以便链接器进一步处理。(所有概念均在手册中进行了详细讨论)   • ANSI-C 库参考。 描述编译器如何使用 ANSI-C 库,它可以帮助您理解和生成一个全新的库,并逐步指导您构建完成工作所需的所有工具!   • 附录。 包含各种常见问题、故障排除和技术说明的列表,以解决过程中出现的任何不便。   跟随 如果有任何疑问请联系 DebuggerGuys ! 概述
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Enhancing Audio Playback with NXP's Essential Audio Processing Library NXP's Essential Audio Processing (EAP) software library is available on several NXP platforms to help enhance the audio playback of your product. With support for several audio algorithms such as static equalizer, dynamic bass boost, limiter, 3D effect and more, EAP provides a great audio experience for users. To permit easy and fast enablement, NXP's EAP library is available in the MCUXpresso SDK with integrated examples, and an associated Audio Tuning Tool that enables you to easily tune and simulate EAP behavior without any hardware. Join this session for an overview of EAP and its features. Presenters: Christophe Boulant, Voice & Audio TEC Team, NXP Shelby Unger, MCU Ecosystem Product Marketer, NXP Arm® Processors i.MX Applications Processors Software & Tools
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Vector Packet Processing(VPP) IPSEC Implementation in LSDK 20.12 The VPP platform is an extensible framework that provides out-of-the-box production quality switch/router functionality. This document introduces Vector Packet Processing(VPP), creating VPP IPsec configuration scripts, building VPP v20.05 in LSDK 20.12, executing VPP IPsec on LS1046ARDB and LS2088ARDB platforms
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How to compile and execute custom applications on a Layerscape board This topic explains steps to compile and execute Hello World program (in C) on a Layerscape board. Similarly, you can execute other custom applications on your board. Create a Hello World program in C.  Copy this file (.c) on a Ubuntu machine (using WinSCP). Run the following command to convert the .c file into a binary file. $ aarch64-linux-gnu-gcc <.c file> -o For example: $ aarch64-linux-gnu-gcc Hello_World.c -o Hello_World Note: You can use this command in the same directory in which .c file is present or provide path of this file. Connect to the board console on which you want to execute the custom application via terminal and boot the board with LITB. Note: It is suggested to boot the board with Tiny Linux for executing custom application.  => tftp 0xa0000000 lsdk2004_yocto_tiny_LS_arm64.itb Using e1000#0 device TFTP from server 192.168.3.1; our IP address is 192.168.3.142 Filename 'lsdk2004_yocto_tiny_LS_arm64.itb'. Load address: 0xa0000000 Loading: ################################################################# ################################################################# ##################################################### 4.3 MiB/s done Bytes transferred = 37030212 (2350944 hex) => bootm 0xa0000000#lx2160ardb ## Loading kernel from FIT Image at a0000000 ... Using 'lx2160ardb' configuration Trying 'kernel' kernel subimage Description: ARM64 Kernel Created: 2021-02-03 6:01:29 UTC Type: Kernel Image Compression: gzip compressed Data Start: 0xa00000d0 Data Size: 14086432 Bytes = 13.4 MiB When Tiny Linux boots, enable Ethernet to download the HelloWorld program on the board. To see the available networks. root@TinyLinux:~# ifconfig -a eth0 Link encap:Ethernet HWaddr 68:05:ca:2b:2c:ca BROADCAST MULTICAST MTU:1500 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) Interrupt:114 Memory:90460c0000-90460e0000 lo Link encap:Local Loopback inet addr:127.0.0.1 Mask:255.0.0.0 inet6 addr: ::1/128 Scope:Host UP LOOPBACK RUNNING MTU:65536 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) sit0 Link encap:UNSPEC HWaddr 00-00-00-00-31-00-6C-6F-00-00-00-00-00-00-00-00 NOARP MTU:1480 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:0 (0.0 B) Enable the Ethernet connection. # ifconfig netmask up For example: root@TinyLinux:~# ifconfig eth0 192.168.3.121 netmask 255.255.255.0 up Set the gateway IP and ping the server to test the connection. # route add default gw # ping For example: root@TinyLinux:~# route add default gw 192.168.3.1 root@TinyLinux:~# ping 192.168.3.1 PING 192.168.3.1 (192.168.3.1): 56 data bytes 64 bytes from 192.168.3.1: seq=0 ttl=64 time=0.479 ms 64 bytes from 192.168.3.1: seq=1 ttl=64 time=0.204 ms Download the HelloWorld binary file on your board. For example: root@TinyLinux:~# scp [email protected]:/tftpboot/LX2160ARDB/HelloWorld . Execute the HelloWorld application. root@TinyLinux:~# ./HelloWorld Hello, World!
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UART Emulation Using the FTM or TPM Introduction Even with the prevalence of universal asynchronous receiver/transmitter (UART) peripherals on microcontrollers (MCUs), bit banged UART algorithms are still used.  The reasons for this vary from application to application.  Sometimes it is simply because more UARTs are needed than the selected device provides.  Maybe application or layout restrictions require certain pins to be used for the UART functions but the device does not route UART pins to the required package pins.  Maybe the application requires a non-standard or proprietary UART scheme. Whatever the reason, there are applications where a bit banged UART is used and is typically a pure software implementation (a timer is used and the MCU core controls a GPIO pin directly).  A better alternative may be to use Flextimer (FTM) or Timer/PWM Module (TPM) to take advantage of the features of these peripherals and possibly offload the CPU.  This document will explain and provide a sample application of how to emulate a UART using the FTM or TPM peripheral.  A Kinetis SDK example (for the TWR-K22F120M and FRDM-K22F platforms) and a baremetal legacy code example (for the FRDM-KL26Z) are provided here. UART protocol Before creating an application to emulate a UART, the UART protocol and encoding must be understood. The UART protocol is an asynchronous protocol that typically includes a start bit, payload (of 7-10 data bits), and a stop bit but does allow for many variations on the number of stop bits and what/how to transfer the data.  For this document and application example, the focus will be UART transmission that follows 1 start bit, 8 data bits, 1 stop bit, no parity, and no flow control.  The data will be transmitted least significant bit (LSB) first.  The following image is a block diagram of this transmission. However, this doesn't specify what the transmission looks like electrically. The figure below shows a screenshot of an oscilloscope capture of a UART transmission.  The data transmitted is 0x55 or a "U" in the ASCII representation. Notice that the transmission line is initially a logic high, and then transitions low to signal the start of the transmission.  The transmission line must stay low for one bit width for the receiver to detect it.  Then there are 8 data bits, followed by 1 stop bit.  In the case shown above, the data bits are 0x55 or 0b0101_0101.  Remember that the transmissions are sent LSB first, so the screenshot shows 1-0-1-0-1-0-1-0.  The last transition high marks the beginning of the stop bit and the line remains in that state until the start of the next transmission.  The receiver, being asynchronous, does not require any type of identifying transition to mark the end of the stop bit. FTM/TPM configuration The first question many may ask when beginning a project like this is "How do I configure the FTM/TPM when emulating a UART".  The answer to this depends on the aspect of this problem you are trying to solve.  Transmitting and receiving characters require two different configurations.  Transmission requires a configuration that manipulates the output pin at specific points in time.  Receiving characters requires a configuration that samples the receive pin and measures the time between pin transitions.  The FTM and TPM have the modes listed in the following table: The FTM and TPM have four different modes that manipulate an output:  Output compare (no pulse), Output compare (with pulse), Edge-aligned PWM, and Center-aligned PWM.  Neither PWM mode is ideal for the requirements of the application.  This is because the PWM modes are designed to produce a continuous waveform and are always going to return to the initialized state once during the cycle of the waveform.  However, the UART protocol may have continuous 1's or 0's in the data without pin transitions between them. The output compare mode (high-true or low-true pulse modes) is designed to only manipulate the pin once, and only produces pulses that are one FTM/TPM clock cycle in duration.  So this is obviously not desirable for the application.  The output compare mode (Set/Clear/Toggle on match) is promising.  This mode manipulates the output pin every cycle.  There are three different options:  clear output on match, set output on match, and toggle output on match.  Neither "clear output on match" nor "set output on match" are ideal as either would require configuration changes during the transmission of a character.  The "toggle output on match", however, can be used and is the selected configuration mode for this sample application. To receive characters, there is only one mode that is intuitive:  "the input capture mode".  This mode records the timer count value on an edge transition of the selected input pin.  Similar to the output compare mode chosen for the transmit functionality, the input capture mode has three sub-modes:  capture on rising edge, capture of falling edge, and capture on either edge.  It is clear from the descriptions that capture on either edge should be selected. Transmit encoding The selection of the FTM/TPM mode is moderately intuitive, but using this mode to emulate a UART transmission is not.  There are two issues that make this a little tricky. 1) The output pin is initialized low. However, the UART protocol needs the pin to begin in a logical high state. 2) The pin transitions on every cycle provided the channel value is less than the value of the MOD register. Due to continuous strings of 1's or 0's, it is necessary to have periods where the pin does not transition. Both of these points have workarounds. Output pin initialization For the first issue, the channel interrupt is first enabled and the channel value register is loaded with a value much less than the value in the MOD register.  Then in the channel interrupt service routine, the pin is sampled to ensure that it is in the logic high state and the channel interrupt is disabled (and will not be re-enabled throughout the life of the application).  The code for this interrupt service routine is as follows. Output pin control For the second issue, a method of not transitioning the pin value while allowing the timer to continue counting normally is necessary.  The Output Compare mode uses the channel value register to determine when the pin transition occurs.  If a value greater than MOD is written to the channel value register, the channel value will never match the count register and thus, a pin transition will never occur.  So, when a series of continuous 1's or 0's need to be transmitted, a value greater than the value in the MOD register can be written to the channel value register to keep the output pin in its current state. However, when a value greater than MOD is written to the channel value register, no channel match will occur (which means channel interrupts will not occur).  So the timer overflow interrupt must be used to continue writing values.  This requires the updates to be output pin to be planned ahead of time and makes the transmission algorithm a little tricky.  The following diagram displays when which values should be written to the channel value register at which points in time to generate the appropriate pulses. Writing a function to translate a number into the appropriate series of MOD/2 and MOD+1 values can be a little tricky. To do this, we must first notice that MOD/2 needs to be written when changes on the transmission pin are need and MOD+1 needs to be written when pin transmissions are not desired.   So, what logical function can we use to determine when a change has happened?  XOR is the correct answer.  So what two values need to be XOR'd together?  One value is obviously the value that we want to send.  But what is the second value?  It turns out that the second value is a shifted version of the value that we want to send.  Specifically, the second value is the desired value to send shifted to the left by one.  (You can think of it as sort of a "future" value of the desired value).  The following pictures show how to determine the queue to use for the transmission. Receive decoding The receive functionality has an advantage over the transmit functions in that it is possible to use DMA for the reception of characters.  This is because the receive function takes advantage of the input capture functionality of the FTM / TPM and therefore can use the channel match interrupt.  The example application provided with this document implements a DMA method and a non-DMA method for reception. First, the non-DMA method will be discussed. Before discussing the specifics of gathering the input pulse widths, some details of the receive pin need to be discussed. Detecting the start bit The receive pin needs to be able to determine when the start of the packet transmission begins.  To do this, the receive pin is configured as an FTM / TPM pin. At the same time, the GPIO interrupt functionality is configured on the same pin for a falling edge interrupt.  The GPIO interrupt capabilities are enabled in any digital mode, so the GPIO interrupt will still be able to be routed to the Nested Vector Interrupt Controller (NVIC).  The pin interrupt is used to start the FTM / TPM clock when a new character reception begins. In the GPIO interrupt for this pin, the FTM / TPM counter register is reset and the clock to the FTM / TPM is turned on.  The code for the GPIO interrupt service routine is shown below.  Receiving characters without DMA Now, when receiving characters and not using DMA, the first thing to understand is that the Interrupt Service Routine (ISR) will be used and it will mainly be used to record the captured count values.  The interrupt service routine also tracks the current receive character length and resets the counter register.  This is so that the values in the receive queue reflect the time since the last pin transition.  The interrupt function for the non-DMA application is shown below. Notice that the first two actions in the ISR are resetting the count register, and clearing the channel event interrupt flag.  Then the channel value is stored in the receive pulse width array (this is simply an array that holds the receive pulse widths of the current character being received).  Next, recvQueueLength, the variable which holds the current length of the character being received, is updated to reflect the latest character length.  The next step is to determine if the full character has been received.  This is determined by comparing recvQueueLength to the RECV_QUEUE_THRESH, which is the threshold as determined by multiplying the number of expected bits by the expected bit width plus another bit width (for the start bit).  If the recvQueueLength is greater than the RECV_QUEUE_THRESH, then a semaphore is set, recvdChar, to indicate that a full character has been received.  The FTM / TPM clock is turned off, and the pin interrupt functionality of the receive pin is enabled.  The final step in the interrupt routine is to increment the receive queue index, recvQueueIndex.  This variable points to the current entry in the receive queue array. Using DMA to receive characters When using DMA, the receive FTM / TPM interrupt is much different. The interrupt routine simply needs to clear the channel interrupt flag, stop the FTM / TPM timer, disable the DMA channel, and set the received character semaphore.  The character is then decoded outside of the interrupt routine.  The interrupt function when using DMA is shown below: Decoding the received pulse widths Once the array of pulse widths has been populated, the received character needs to be translated into a single number.  This varies slightly when using DMA and when not using DMA. However, the basic principle is the same.  The number of bits in a single entry is determined by dividing by the expected bit width and this is translated into a temporary array that contains 1's and 0's, and then that is used to shift in the appropriate number of 1's and 0's into the returned char variable.  A temporary array is needed because the values are shifted into the UART LSB first, so the bit must be physically flipped from the first entry to the last.  There is no logical operation that will do this automatically. The algorithm to perform this translation is shown below.  In this algorithm, note that recvPulseWidth is the array that contains the raw count value of the pulse width.  The array tempRxChar holds the decoded character in reverse order and rxChar is a char variable that holds the received character. Conclusion This document provides an overview of the UART protocol and describes a method for creating a software UART using the timing features of the FTM or TPM peripheral.  This method allows for accurate timing and while not relying entirely on the CPU and the latency associated with the interrupt and the GPIO pins.  The receive function is open to further optimization by using DMA, which can provide further unloading of the CPU. Kinetis Hardware Support Kinetis K Series MCUs Kinetis L Series MCUs Kinetis V Series MCUs
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MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 此MQX演示重新使用标准 MQX web_hvac 演示,使用 GT202 Wi-Fi 模块,设置为 SoftAP 模式。此示例展示了 MQX RTCS、DHCP 服务器和 Web 服务器在Kinetis MCU中运行,并采用 Atheros 驱动程序。客户端将能够连接到软接入点 (SoftAP),获取 IP 地址,然后使用 Web 浏览器查看 web_hvac 网页。用户指南包含在 ZIP 文件中。 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 此MQX演示重新使用标准 MQX web_hvac 演示,使用 GT202 Wi-Fi 模块,设置为 SoftAP 模式。此示例展示了 MQX RTCS、DHCP 服务器和 Web 服务器在Kinetis MCU中运行,并采用 Atheros 驱动程序。客户端将能够连接到软接入点 (SoftAP),获取 IP 地址,然后使用 Web 浏览器查看 web_hvac 网页。用户指南包含在 ZIP 文件中。 通信基础设施 回复:MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 我遇到了同样的问题:这取决于您安装哪个“补丁”......您没有带有 FRDMK22 补丁的文件(FSLMQX4.1_PATCH_GT202_3.0.2CS.exe 和 Setup_MQX4.1_GT202_3.0.2CS.exe)但我有这个带有 QCA4004.MQX.exe 补丁的文件)。 如果有人能分享所需的确切补丁(名称和链接)以及应用它们的顺序,那就太完美了! 回复:MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 对我来说,目前还没有,即使经过了很多小时(几天......) 该演示与 IAR 和 FRDM K22 完美兼容,甚至与 .bin 兼容重建(throughput_demo)。 但之后,FRDM K64、MQX4.1 和 CW10.6 就没有任何进展了…… 如果有人有更好的结果,请分享:smileywink: 回复:MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 大家好, 你们中有人成功地使用带有 FRDM-K64F 板和 Kinetis Studio 环境的 GT-202 使这个示例工作吗? 回复:MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 你好,克里夫 我想在我的项目中包含一个 GT202 模块,但是遇到了问题。我正在使用 FRDMK64F 板和 MQX 4.1。我使用开发环境Kinetis Design Studio 3.0。您的移民运气好吗?你能在这个过程中帮助我吗? 谢谢克里夫 凯文·卡塞尔 回复:MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 嗨,托马斯 您是否按照用户指南中的步骤添加了 Qualcomm Wi-Fi 模块所需的 MQX 补丁? 回复:MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 嗨,克里夫, 你自己有取得什么进步吗?我发现自己也处于类似的境地。令人沮丧的是,直接与 Kinetis 开发板接口、运行 Freescale 操作系统的开发板尚未移植到 Kinetis Development Studio 中使用。 Larry 回复:MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 嗨,chinniwhites, 抱歉,我不清楚在哪里可以找到 web_hvac。web_hvac 演示是 MQX v4.1.1 及更早版本中包含的标准 MQX 演示。它位于 \demo\web_hvac。按照安装 GT202 PDK 的说明进行操作时,一步是安装 MQX v4.1.0。完成该步骤后,web_hvac demo 将包含在安装中。 当您安装 GT202 PDK 时,它不会修改 web_hvac 演示。它仍然是MQX安装中提供的原始演示。之前我解释过,此页面上的 SoftAP 演示基于 web_hvac 演示,然后进行了修改以使用 GT202 模块和 SoftAP 功能。如果您想查看 GT202 的更新 web_hvac,您可以使用此 SoftAP 演示作为示例。 由于此页面位于 DemoLab 社区空间,因此 MQX 支持团队不会注意到此处发布的评论。如果您对此 SoftAP 演示有任何疑问,请告诉我。如果您有其他有关 MQX 的问题,最好在https://community.freescale.com/community/mqx中创建新的讨论 谢谢! 回复:MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 嗨,克里夫, 看起来您指的是KSDK v1.1.0<>以下。Kinetis 软件开发套件 (KSDK) 是一个驱动程序、堆栈和 RTOS(如 MQX)库。Kinetis Design Studio (KDS)<> 是我们用于构建 Kinetis 应用程序的工具链。下面引用的示例位置是 KSDK 的一部分。 web_hvac 示例来自 MQX 与 KSDK 集成之前的 MQX 安装。目前是 MQX v4.1.1 或更早版本。当您按照 GT202 PDK 的安装说明进行操作时,您会发现 web_hvac 演示安装在 \Freescale_MQX_4_1\demo\web_hvac。我相信有计划将 web_hvac 演示移植到 KSDK 的 MQX,但它并不包含在最新的 KSDK v1.1.0 中。 然而,您应该知道GT202驱动程序尚未移植到KSDK。GT202 驱动程序和 PDK 是使用 MQX v4.1.0 开发的。如果您选择将 GT202 与 KSDK 一起使用,则需要移植驱动程序并使用 KSDK SPI 和 GPIO 外设驱动程序。或者,如果您使用 MQX v4.1,GT202 驱动程序已经为您移植。 谢谢! 回复:MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 嗨,克里夫, 是的,这个 SoftAP 演示项目使用 IAR,因为 GT202 MQX 示例项目使用 IAR。我不知道其他工具链的 GT202 MQX 示例项目。 但如您所知,MQX 包含一个用于 KDS 的 FRDM-K64F BSP 项目。您可以修改该项目并将 Atheros 驱动程序添加到 GT202 的 BSP。您可以使用 FRDM-K22F 的 GT202 示例 BSP 作为参考。为了集成驱动程序,还需要对提供的 BSP 文件进行一些更改。与 MQX 安装中的原始 FRDM-K22F BSP 文件相比,您可以找到对 GT202 FRDM-K22F BSP 文件所做的更改。然后在您的 K64 BSP 中进行类似的更改。 SoftAP 应用程序示例基于 MQX 中包含的 web_hvac 演示。该演示还包含针对 FRDM-K64F 的 KDS 项目。因此,您的应用程序可以从该演示项目开始,然后从 SoftAP 演示中复制源文件。使用 BSP 中的 GT202 驱动程序,您可以构建此 SoftAP 应用程序。 希望有帮助。谢谢 回复:MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 嗨,chinniwhites, 在 MQX 中,您可以在 BSP 中启用多个 ENET 设备。但我不知道有哪个例子可以证明 GT202 和有线以太网的兼容性。 我建议您在 MQX Space 中发布一个新问题,以便 MQX 支持人员能够了解并做出回应。 https://community.freescale.com/community/mqx 谢谢! 回复:MQX Wi-Fi SoftAP 演示 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 这确实很合适。我希望尽快在 IoTT 上线它!iot.freescale.com
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Landzo:スパイダーマンショーとソリューションブリーフィング <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> LandzoのLan Zhouによる発表 深センのDwF Kinetis MCUs Based on ARM® Technology (2015年1月27日)で発表 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> LandzoのLan Zhouによる発表 深センのDwF Kinetis MCUs Based on ARM® Technology (2015年1月27日)で発表
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RD56F801XACIM: Design of an ACIM Vector Control Drive Reference Design using the 56F801X Overview Features General: General Benefits: Performance: Communications: Visual Interface: Block Diagram Board Design Resources Overview This drive application allows vector control of an AC Induction Motor (ACIM) running in a closed-speed loop without a speed/position sensor at a low cost and serves as an example of AC induction vector control drive design using an NXP ®  56F8013 with Processor Expert ®  software support. ACIM is ideal for appliance and industrial applications This design uses sensorless FOC to control an ACIM using the 56F8013 device, which can accommodate the sensorless FOC algorithm The motor control system is flexible enough to implement complex motion protocols while it drives a variable load. The system illustrates the features of the 56F8013 in motor control Features General: The motor control algorithm employs Stator-Flux-Oriented Control (SFOC) Power stage switches are controlled by Space Vector Pulse Width Modulation (SVPWM) No position information devices or stator flux measurement are used, a sensorless speed method is employed The motor is capable of forward and reverse rotation and has a speed range from 50rpm to 3000rpm The user controls motion profiles, rotation direction, and speed. The RS-232 communication supports further R&D by enabling the easy tuning of control parameters The motor drive system is designed to create minimal acoustic noise Active power factor correction which reduces the negative effects of the load on the power grid in conducted noise and imaginary power Design is low cost General Benefits: Improved End System Performance Energy savings Quieter operation Improved EMI performance System Cost savings Enhanced Reliability Performance: Input voltage: 85 ~265VAC Input frequency: 45 ~65HZ Rating bus voltage: 350V Rating output power: 500W Switch frequency of PFC switch: 100KHZ Switch frequency of inverter: 10KHZ Power factor: >95% Efficiency: >90% Communications: RS232 port for communication with optoisolation Visual Interface: Multi-segment LED indicators Block Diagram Board Design Resources Legacy Designs
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RD56F8300LCSM: Low-Cost Soft Modem Reference Design using the NXP DSC Overview Features Block Diagram Board Design Resources Overview This reference design shows the simplicity of a soft modem design, how few resources of the processor it takes, and how well it performs on USA average lines. This design omits the standard telecommunications Codec, instead of using PWM for output and ADC for input. Since both peripherals are readily available on one 56F8300/100 series device, along with more processing power than required from the single core, the design is a true one-chip, one-core system that includes telecommunications ability with room for even more system functionality. Ideal for advanced motion control, home appliances, medical monitoring, fire and security systems, power management, smart relays, and POS terminals. Features Hybrid architecture facilitates implementation of V.21 and V.22bis modem, control, and signal processing functions in one chip Consumes only 7.5 MIPS for the modem function - Only 15K words of Flash for the complete modem application and test harness High-performance, secured Flash memory eliminates the need for external storage devices Extended temperature range allows for operation of non-volatile memory in harsh environments Flash memory emulation of EEPROM eliminates the need for external non-volatile memory 32-bit performance with 16-bit code density On-chip voltage regulator and power management reduces overall system cost Off-chip memory expansion capabilities allow for glueless interfacing with the additional memory of external devices, without sacrificing performance Boots directly from Flash, providing additional application flexibility High-performance PWM with programmable fault capability simplifies design and promotes compliance with safety regulations PWM and ADC modules are tightly coupled to reduce processing overhead; only one of each is used by the modem General purpose input/output (GPIO) pins support application-specific needs Simple in-application Flash memory programming via Enhanced OnCE or serial communication Block Diagram Board Design Resources Legacy Designs Re: RD56F8300LCSM: Low-Cost Soft Modem Reference Design using the NXP DSC When purchasing ducting material online, it's essential to verify the specifications to ensure they meet your project needs. Look for detailed product descriptions, including dimensions, materials, and temperature ratings.
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RD56F80PMSVC: Sensorless PM Motor Drive for H-axis Washer Reference Design Using MC56F80xx Overview Features Block Diagram Board Design Resources Overview This reference design is for a sensorless permanent magnet (PM) motor drive single-chip solution based on the NXP® DSC56F80XX digital signal controller (DSC). An electronically controlled three phase PM motor provides a unique feature set with the higher efficiency and power density This application presents a motor control technique of PM motor without a need to use a rotor position transducer This technique particularly targets horizontal axis (H-axis) washing machine with belt drive in fractional horsepower range A designer reference manual provides a detailed description of the application, including the design of the hardware and the software Features Designed to fit into consumer and industrial applications MC56F80XX digital signal controller 3-phase AC/BLDC High Voltage Power Stage Board 1-phase line input 110/230VAC 50/60Hz Apliance PM motor Initial rotor position detection Full torque at motor start-up Field weakening Application based on C-callable library functions (GFLIB, GDFLIB, MCLIB, ACLIB) Current control loop Speed control loop with Field weakening Flash: ~ 6KB, RAM ~ 1.5KB FreeMASTER based control pages Block Diagram Board Design Resources Legacy Designs
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RDDSCSHSSR: Sensorless High-Speed SR Motor Drive for Vacuum Cleaners Reference Design using an MC56F8013 Overview Features Block Diagram Design Resources Overview The Sensorless High-Speed SR Motor Control Reference Design based on the NXP® low-cost MC56F8013 digital signal controller (DSC) deals with a 2-phase switch reluctance (SR) motor sensorless drive for vacuum cleaners and other air movement applications. The application is a speed-open loop SR drive without any position or speed sensor needs Uses a sensorless control method based on current peak detection and a patented start-up algorithm (Patent No. US6448736 B1) The control technique allows the SR motor more than 100 000 RPM The application is primarily for vacuum cleaners, although it can be used for any application with a high-speed drive (50 000 RPM) Features High-speed 2-phase SR motor sensorless control based on a current peak detection Designed for vacuum cleaner applications Capable of running SR motors at more than 100.000 RPM (tested with SR motor designed for 60 000 RPM) Single direction rotation enabled by asymmetric of 2-phase SR motor Speed open loop Start-up from any position using alignment and patented algorithm (Patent No. US6448736 B1) Start-up time and maximum speed depends on SR motor parameters Manual interface and FreeMASTER control page for monitoring, control and tuning Block Diagram Design Resources Legacy Designs
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K-70およびK-24コネクティビティ <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
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