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eIQ Toolkit TfLite 变流器失败,没有错误消息 我正在尝试使用int8量化将对象检测模型从tensorflow转换为tflite,但发现变流器失败了,没有任何错误消息。此外,模型工具只能在 h5 中加载模型,而不能在 keras v3 中加载,也不能以 saved_model 的形式加载。 我在其他帖子中看到最近有人使用该工具取得了成功,所以我不知道问题出在哪里,如果相关的话,该模型是来自 ultralytics 的 yolov8。 如有任何见解,将不胜感激。 eGUI Re: eiQ Toolkit TFLite Converter failing without error message 你好 如果你的模型使用的是 TfLite 内置程序本身不支持的 TensorFlow 运算符,请启用 tf.lit e.opsset.select_TF_OPS,并确保 Flex 委托在 i.MX 的 TfLite 运行时中可用。   性能和准确性: 在针对 8 位整数进行了优化的硬件(如 i.MX 中的 NPU)上,全整数量化可以显著缩小模型大小并提高推理速度。 不过,要仔细评估对模型准确性的影响,必要时调整代表性数据集或量化策略。   您可以查看应用程序注释 AN13699,了解如何转换为 int8。 https://www.nxp.com/docs/en/application-note/AN13699.pdf   此致    
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How does GUI guider update the project to 1.8.0? The popup asks to update the project created under version 1.7.0 to 1.8.0, my current version is 1.10.0, first of all how do I update it to 1.8.0? and secondly does updating it to 1.8.0 make it possible to open it in the 1.10.0 version? A million thanks! Re: GUI guider 如何更新项目到1.8.0? Hi @Suuu, Due to changes on the GUI Guider toolchain, all projects created on v1.7.x must be upgraded to 1.8.x before updating them to any other subsequent version. Please first download v1.8.0, import your project to that version, and then follow the same process with 1.10.0. There is no need to go through 1.9.0. Note that you will be prompted this message on each upgrade step: Make sure to click OK to update the project, I recommend keeping the backup enabled just in case. BR, Edwin. Re: GUI guider 如何更新项目到1.8.0? I imported the project created in 1.8.1 into 1.10.1, and after the backup was completed, it kept showing an upgrade failure message.
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以太网发射器在接收器端仅传递 UUUU 58 次 以太网代码工作 EMAC 初始化,但在接收器端只传递了 58 次 U,没有传递我的字符串 请检查我的代码,并对我的代码缓冲区值进行更正,如何才能更改输出 UUU?
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Debian flex-installer fails to download boot image. I am walking through the Debian guide UG10155 with the i.MX 8M Mini EVK. I was able to successfully install Debian following that guide about 3 months ago. Now however, I am seeing an issue when I run flex-installer on the board from tinylinux: root@TinyLinux:~# flex-installer -i pf -d /dev/mmcblk1 /dev/mmcblk1: 61 GB Partitioning /dev/mmcblk1 ... [ 158.701442] udevd[466]: inotify_add_watch(6, /dev/mmcblk1p1, 10) failed: No such file or directory Formatting partitions ... /dev/mmcblk1p1 contains a ext4 file system labelled 'boot' last mounted on Fri Mar 9 13:21:57 2018 /dev/mmcblk1p2 contains a ext4 file system labelled 'data2' last mounted on Fri Mar 9 13:21:57 2018 /dev/mmcblk1p3 contains a ext4 file system labelled 'data3' last mounted on Fri Mar 9 13:21:57 2018 [ 215.423287] EXT4-fs (mmcblk1p1): mounted filesystem c6ecb438-3958-415c-82db-36a3f29b9caa r/w with ordered data mode. Quota mode: none. [ 215.599368] EXT4-fs (mmcblk1p2): mounted filesystem abc39eb0-fd7f-4bf8-ba1e-f2db7d1f1df5 r/w with ordered data mode. Quota mode: none. [ 215.768426] EXT4-fs (mmcblk1p3): mounted filesystem 98d2bd5b-7762-4c8e-bd34-073176858089 r/w with ordered data mode. Quota mode: none. Model: SD SMTC (sd/mmc) Disk /dev/mmcblk1: 62.5GB Sector size (logical/physical): 512B/512B Partition Table: msdos Disk Flags: Number Start End Size Type File system Flags 1 273MB 810MB 537MB primary ext4 2 811MB 9400MB 8590MB primary ext4 3 9402MB 62.5GB 53.1GB primary ext4 partition and format /dev/mmcblk1 [Done] root@TinyLinux:~# flex-installer -i auto -d /dev/mmcblk1 -m imx8mmevk /dev/mmcblk1: 61 GB The requested URL http://www.nxp.com/lgfiles/sdk/lsdk2506/boot_IMX_arm64_lts_6.6.52.tar.zst returned error 301 root@TinyLinux:~# In my desktop browser I can post the link and the file will download. However, flex-installer does not appear to handle redirects and instead just fails. Can someone from NXP please provide the ability to directly download these files and also to browse a directory so as to see which files are actually available for download, with regards to the Debian installation process but also any other firmware content? I don't mind signing in to access it but the way these documents are written, we are impeded sometimes by the lack of explicit clarity. (I will offer direct feedback within the User Guide system on that point). Meanwhile I suppose my question is this: How can I make the flex-installer program work with the files in the guide if they are redirected? i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Linux Re: Debian flex-installer fails to download boot image. I can download http on my network. The issue is that the flex-installer does not seem to be capable of following the server's re-directs to https. Thanks to another friend we were able to find that using the -u switch with https://www.nxp.com/lgfiles/sdk/lsdk2506 worked. But that brings me to another question: Why does NXP not allow a directory listing on the URL so we can actually see what files are available and versions? Instead, we have to make assumptions and use trial and error to join the links together... Also the SC Card from Windows guide does NOT include the additional usage information that is in the SD Card from Linux guide. This makes an erroneous assumption that users of Windows will first read the Linux documentation and then move on to the Windows documentation. But obviously, users on a Windows desktop will not first click the Linux guide link, so they will have insufficient information and the guide will not work for them exactly as it is written. Please have NXP update the UG10155 guide online to separate the flex-installer usage data and introduction to a separate page that says "read this first" and THEN allow them to click the link to the Windows guide or the Linux guide. Re: Debian flex-installer fails to download boot image. Hi, Thank you for your interest in NXP Semiconductor products, The requested SW packages should be downloaded without issues, I would look to your network settings since those packages are downloaded over HTTP, not HTTPS. Your network could disable HTTP requests. Flex-installer helps downloading the packages from the website, you can manually copy to board from the direct links. Regards
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イーサネット トランスミッタはレシーバ側で58回UUUUのみを通過させる イーサネットコードはEMACの初期化で動作しますが、レシーバ側ではUが58回しか渡されません。文字列が渡されません。コードをチェックして、コードバッファ値の修正方法を教えてください。出力UUUを変更するにはどうすればよいでしょうか。変更するにはどうすればよいでしょうか。この問題の解決策を教えてください。
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RW610ベースのカスタムボードを外部フラッシュでプログラムできない RW610 チップをベースにしたカスタム開発ボードを持っています。FRDM-RW612 ボードの Jlink アダプターを使用してファームウェアを書き込もうとしています (最終的には MCU-Link に移行する予定です)。 何らかの理由で、アドレス 0x0、サイズ 0x130000 で RAM のみが宣言されたデフォルトのメモリ構成は、デバッグ モードで正常に動作します。しかし、メモリ構成に外部フラッシュ アドレスを追加するとすぐに動作しなくなります。メモリ モニターでも、範囲全体のデータは表示されません。 試した範囲の 1 つのスクリーンショットを添付しました。 Re: Unable to program RW610-based custom board with External Flash こんにちは、 @snjy はい、弊社の SAE がすでにお役に立てたとのこと、うれしく思います。 私たちはあなたの問題をできるだけ早く解決するという同じ目標を持っています。 SO、このCASEは一旦閉じさせていただきます。引き続き私からの支援が必要な場合は、遠慮なく新しいCASEを作成してください。 よろしくお願いいたします。 Christine。 Re: Unable to program RW610-based custom board with External Flash こんにちは、クリスティン。 この件でお待ちいただいて申し訳ございません。私はこの問題について NXP SAE のリーダーとコネクテッドし、サポートでこの問題に対処してきました。助けてくれてありがとう。 Re: Unable to program RW610-based custom board with External Flash こんにちは、 @snjy このCASEに関して他に何かCANはありますか? 数日間フィードバックをいただいていないため、このCASEは 1 日後に自動的に閉じられることをご承知おきください。 このCASEに関してまだサポートが必要な場合は、お気軽にご連絡ください。   よろしくお願いいたします。 Christine。 Re: Unable to program RW610-based custom board with External Flash こんにちは、 @snjy 問題はすでに解決しましたか? このCASEに関して、まだ私の側からのサポートが必要ですか? もしそうであれば、電子メールで私の要求した情報を提供していただけますか? (プロジェクト情報を保護するために、コミュニティで共有しないでください。) よろしくお願いいたします。 Christine。 Re: Unable to program RW610-based custom board with External Flash こんにちは、 @snjy メールをいただきありがとうございます。 すでに受け取って社内で確認したところ、NDA 番号はまだアクティブかつ有効です。 弊社の製品マネジメントチームと連携して進めることができるよう、プロジェクト情報をメールで提供していただけますか? ご参考までに、当社はお客様のプロジェクトの年間収益に応じて安全なファイルへのアクセスを許可します。許可が得られるかどうかは保証できません。しかし、信じてください。私はこの件に関してあなたをサポートするために最善を尽くします。 ご理解いただきありがとうございます。また、ご不便をおかけしましたことを改めてお詫び申し上げます。 プロジェクト: アプリケーション: ユースCASEの説明: どのディストリビューターがサポートしていますか? NXP のお問い合わせは誰ですか? プロジェクト年間取引量: よろしくお願いいたします。 Christine。 Re: Unable to program RW610-based custom board with External Flash こんにちは、 @snjy すでに弊社との NDA に署名していただいているとのこと、素晴らしいですね。 NDA番号を教えていただけますか?次に、TSR の同僚に NDA がまだ有効かどうかを確認するよう依頼します。 また、ご参考までに、一部の安全なファイルにはアクセス申請が必要なため、お客様にとって不便であることは承知しております。もしよろしければ、プロジェクトに関する詳細情報をお知らせください。SO、弊社の製品マネジメントチームと連携して、安全なファイル アクセスを進めるためのプロセスを開始CAN。ちなみに、当社はお客様のプロジェクトの年間収益に応じて安全なファイルへのアクセスを許可します。したがって、許可が得られるかどうかは保証できません。しかし、信じてください。私はこの件に関してあなたをサポートするために最善を尽くします。 あなたのプロジェクト情報を保護するために、あなたのプロジェクト情報を私のプライベートな仕事用メール( [email protected] )に送信してください。 ご理解いただきありがとうございます。また、ご不便をおかけしましたことを改めてお詫び申し上げます。 NXPについて名: 位置: プロジェクト: NDA番号: アプリケーション: ユースCASEの説明: どのディストリビューターがサポートしていますか? NXP のお問い合わせは誰ですか? プロジェクト年間取引量:   許可されたとしても、カスタム ボードを使用しているため、ハードウェア側の変更を確認する必要があります。必要であれば、回路図を私と共有していただければ、外部フラッシュ接続部分の確認をお手伝いCANます。   よろしくお願いいたします。 Christine。 Re: Unable to program RW610-based custom board with External Flash こんにちは、クリスティン。 RW610をベースにしたカスタムボードを使用しています。EVKボードを使用していません。 AN13869 にアクセスするために NXP とすでに NDA を締結しており、私に連絡してきた営業エンジニアの 1 人に転送しましたが、まだ返答がありません。 あなたが参照しているリンクを見つけましたが、私たちが使用しているメモリ チップ (Spansion S25FL256L) はサポートされていません。 文書のリクエストを調べていただければ助かります。同時に、役立つ場合は NDA 文書を DM で送信することもCANます。 Re: Unable to program RW610-based custom board with External Flash こんにちは、 @snjy 弊社のRW61X EVKボードをご利用いただいておりますか? お客様がご利用いただいているのは、NXP RW61X EVKボードではなく、RW610チップをベースにしたカスタム開発ボードだと記憶しています。ご確認いただけますようお願いいたします。 すでにこの AN:AN13869 にアクセスしていますか?それともまだアクセスを申請中ですか?この AN は安全なファイル管理下にあるためです。 ご参考までに、この AN では、FlexSPI フラッシュ インターフェース上の MX25U51245GZ が削除され、同じフラッシュ パッドに W25Q512NW が取り付けられる例が示されています。2 つのフラッシュ デバイスは同じ動作電圧でピン間の互換性があるため、他のハードウェアの変更は必要ありません。 ただし、RW61X EVK ボードではなくカスタム開発ボードを使用している場合は、ハードウェアの変更が必要かどうかも確認する必要があります。 https://github.com/nxp-appcodehub/an-frdmrw612-module-migration-guide?tab=readme-ov-file このガイドは、開発者がアプリケーションを FRDM-RW612 ボードからモジュールベースのボードに移行するのに役立ちます。モジュールベースのボードを使用していますか?あるいは、 COB方式でカスタム ボードを設計していますか? よろしくお願いいたします。 Christine。 Re: Unable to program RW610-based custom board with External Flash すいません! 申し訳ありませんが、ここに追加させていただきます。 また、私はその問題を知っているかもしれないと思います。Spansion S25FL256Lを使用していますが、直接サポートされていません。新しいフラッシュメモリの追加方法についてより詳しい情報が記載されているAN13869ドキュメントをリクエストしました。 https://github.com/nxp-appcodehub/an-frdmrw612-module-migration-guide?tab=readme-ov-fileを調べたところ、RW610 で動作させるにはボード用に新しいメモリ構成を作成する必要があることがわかりました。 あるいは、同様のものがすでに存在すると思われる場合は、ご指導ください。   Re: Unable to program RW610-based custom board with External Flash こんにちは、 @snjy スクリーンショットを私と共有するのを忘れましたか? この問題に関する詳しい情報を提供していただければ、より適切なサポートを提供できます。 よろしくお願いいたします。 Christine。 Re: Unable to program RW610-based custom board with External Flash こんにちは、 @snjy スクリーンショットを私と共有するのを忘れましたか? この問題に関する詳しい情報を提供していただければ、より適切なサポートを提供できます。 よろしくお願いいたします。 Christine。
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Installation Instructions S32 Design Studio 3.6.4 Hi, Is there an installation manual for 3.6.4 on Linux? There is one for 3.5 that describes a number of dependencies that must be installed. Thanks. Re: Installation Instructions S32 Design Studio 3.6.4 Hi,  please see attached document. 
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Copy: RTD Linker Input Sections for S32K3xx This post is a copy from here I have a question about the linker input sections for the RTDs (Build Version: S32K3_RTD_6_0_0_QLP04_D2508_ASR_REL_4_7_REV_0000_20250822). There is an input section named '.mcal_const_no_cacheable' and it is located to the memory region 'int_sram_no_cacheable'. I am a bit confused, because I would expect 'const' data in the FLASH and not in the RAM.  Is there a reason for mapping it into the RAM?  Thanks, in advanced for your help.  Priority: MEDIUM RTD S32DS Source: NXP Internal Re: Copy: RTD Linker Input Sections for S32K3xx Hi @Luis_Garabo , Yes, const normally resides in FLASH/ROM but it can be put in RAM with setting Read-Only in MPU and RTD's linker file, like this: In RTD drivers, as long as I know, they didn't really use const_no_cache, but if the customer want to use it, they completely set access right to that memory region. Best regards, Nhi
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MC9S12C64 ADC question MC9S12C64, CW V5.9.0, absolute assembler. In my program I want to read 5 channels in 8 bit resolution at different points in my program. When I test it on a test program I set an output when the conversion starts, and clear it when the conversion is finished for each channel in succession. Then I record this on my digital signal analyzer to see how long each channel conversion takes. The conversion on Ch0 takes 7.41uS, which is about what I expected. However, each of the next channels take  6uS longer than the previous one. Ch0 - 7.41uS, Ch1 - 13.42uS, Ch2 - 19.41uS, Ch3 - 25.45uS, ch4 - 31.41uS, Ch5 - 37.41uS. I'm assuming I have done something wrong in my ADC set up but I can't seem to find it. Any suggestions would be appreciated. Regards, Robert  Re: MC9S12C64 ADC question Hi Robert, We don't have any interrupt execution time specification, but you may refer to the reference manual of the core. https://www.nxp.com/webapp/Download?colCode=S12CPUV2 7.5.3 Interrupt Recognition Figure 7-1. Exception Processing Flow Diagram I would recommend that you measure it in your setup. If you use the interrupts, the core will not be blocked in a loop polling the flags, this is the advantage of it. It also depends on other interrupt and their priorities. Regards, Daniel Re: MC9S12C64 ADC question OK. I finally figured out where I was going wrong, (revised code attached), but now I have a question. Depending on how many conversions I want, the processing time varies like this: 2 conversions ~7.42uS, 4 conversions ~8.41uS, 8 conversions ~10.41uS, 16 conversions ~14.41uS. I am assuming that the more conversions I do, the better the accuracy, but I have to balance this with speed of conversion. I am sampling the channels at specific times in the main loop. Every time I sample a channel I have to wait for the conversion to complete. Instead of waiting, I could enable the conversion complete interrupt and read the register and save it to the appropriate variable within the interrupt. So my question is, how much time would it take to service the interrupt and which method would be most efficient, waiting for the conversion completion or servicing conversion complete interrupt? Regards, Robert Re: MC9S12C64 ADC question I've made some progress, but I still have a problem. With my revised code, (attached) All the ADC channels will work, but the processing time per channel is ~37 uS, which is unacceptable. If I change ATDCTL3 to 0x08, only channel 0 will convert at ~7 uS, but I get nothing on the other channels. I've tried about all the different combinations of settings I can think of to solve this but so far no joy. Any suggestions would be appreciated. Regards, Robert Re: MC9S12C64 ADC question Hi Daniel, Oh my, another stupid error on my part. I changed ATDCTL3 to 0x08 but now my program just does the conversion for channel 0 then stalls at line 268, waiting for the conversion complete flag. There must be something else involved as well. Regards, Robert Re: MC9S12C64 ADC question Hi Robert, It should be 0x08 for 1 conversion though. Re: MC9S12C64 ADC question Hi Daniel, Thanks so much for your response. Indeed, that was a typo error on my part. I changed to ATDCTL3 = 0x10. Now the program hangs at line 275. brclr ATDSTAT1,#%00000100*. The conversion complete flag for channel 2 doesn't seem to be setting for some reason. Regards, Robert Re: MC9S12C64 ADC question Hi @roberthiebert, I just briefly checked the code, it seems you selected 8 conversions in a sequence. movb #$00,ATDCTL3 ; %00010000, 1 conversion ATDCTL3 = 0x00
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Convert Raw File to Jpeg( in i.MX8MP). My purpose is to convert Raw File to Jpeg in i.MX8MP. I am using encoder_test in imx-test-lf-5.15.32_2.0.0. There is no JPEG in mxc_isi_out_format(in kernel isi), so the following error occurs. "isi-m2m 32e00000.isi:m2m_device: mxc_isi_m2m_s_fmt_vid_cap, format is not support!" Is it possible to fix the problem? Or should I use another method? Re: Convert Raw File to Jpeg( in i.MX8MP). current imx8mp HW doesn't have such convert function, customer needs do it by their own SW
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[S32DS for Platform v3.5] How to erase a specific area by P&E debugger Hello team, Can you please explain how to erase the specific area (i.e. 0x10000000--0x1001FFFF) in the S32DS v3.5 by a P&E debugger? Best regards, James Re: [S32DS for Platform v3.5] How to erase a specific area by P&E debugger Hi Julián, Thank you for your answer. Best regards, James Re: [S32DS for Platform v3.5] How to erase a specific area by P&E debugger Hi  @james-lee, Unfortunately, there is still no support for erase option in P&E plugin. The workaround is to upload an empty binary file, as discussed in this community post: How to Erase Flash with S32DS, PEMICRO and MPC5777M - NXP Community (and this HOWTO as well: HOWTO: MPC5777C - Low/Mid Flash block erase via PE Micro - NXP Community) or to use external tools as discussed in this other post: how to erase the whole d-flash every time with PE micro - NXP Community There is also the Non-Volatile Memory Preservation option: Solved: Debug interface without erasing memory - NXP Community Best regards, Julián 
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I want to speed up jpeg decoding in i.MX RT Hi community. I need faster JPEG decoding on i.MX RT1170 EVK. I measured the jpeg decoding time of the sample software sd_jpeg_cm7. It uses 23msec to decode a 480x272 jpeg image, but I would like to speed this up. The request requires about a 3x speedup. Do you have any ideas? Best regards. Re: I want to speed up jpeg decoding in i.MX RT Hi @Ryo_Aoki ,   Thank you for your interest in the NXP MIMXRT product, I would like to provide service for you.   About the decoding, you can refer to this application note: https://www.nxp.com/docs/en/application-note/AN12562.pdf It contains some performance information.   So,if you want to speed up, I think, you can copy the code to the internal TCM or OCRAM, it will faster than the external flash running result. Wish it helps you! If you still have question about it, please kindly let me know. Best Regards, Kerry
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Pythonコードを暗号化して、ドアコントローラーシステムのリレーを安全に制御するにはどうすればよいですか? ドアコントローラーのリレーを切り替える役割を担うPythonスクリプトを暗号化する方法を提案してください。目標は、スクリプトのロジックを保護し、不正アクセスや改ざんを防ぎ、許可されたユーザーまたはシステムのみがリレーを制御できるようにすることです。焦点は、特にアクセス制御の自動リレーカテゴリで使用されるドアのリレー制御システムとインターフェースするコードを保護することです。スペックをご確認ください。 NFC制御マシンアクセス  Re:Pythonコードを暗号化して、ドアコントローラーシステムのリレーを安全に制御するにはどうすればよいですか? K64120を使用しています
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rpmsg-lite porting on our MCU(RISC-V platform ) hello,           I have a question about rpmsg-lite porting: Is it possible to use rpmsg-lite to encapsulate the mailbox as shared memory? That is, if there is only a small amount of data (e.g. less than 256 bytes), the mailbox will be used as shared memory to transfer the data, and if the data is larger than 256 bytes, it will still use the original shared memory used by rpmsg-lite, but it will still use the original API interface to initialize, create endpoints, and send the data (which may involve modifying the code). Is this approach feasible? #rpmsg-lite #FDRM-MCXN947SDK  Core and Memory FRDM-Training Re: rpmsg-lite porting on our MCU(RISC-V platform ) hi,         Thanks. In the demo of multicore rpmsg-lite pingpong communication using the SDK for the FRDM-MCXN947 board, I found that after the master core bootstraps the remote core to start, the remote core does rpmsg_lite_remote_init() first, then notifies the master core, and then the remote core waits for connection (rpmsg_lite_wait_for_ link_up()). During this time the master core waits (while()). After the master core is initialized rpmsg_lite_master_init(), the remote core makes the connection and creates the endpoint, then notifies the master that it is ready to send data. In use, I commented out the notification as well as the wait code and found that the master and remote cores can also link-up and communicate, what is the reason for this? Is it because the master system clock is slower than the remote ?         In addition, I would like to ask, if our MCU does not have such a notification mechanism, how to ensure that the master and slave cores are link-up and can communicate? Thanks & Regards yzs Re: rpmsg-lite porting on our MCU(RISC-V platform ) Hi @yzs  Yes, i think your approach is feasible. The buffer address (desc.addr) in a Virtio ring (vring) can point to a different memory region, such as a mailbox, while the desc, avail, and used structures remain in shared memory. BR Harry Re: rpmsg-lite porting on our MCU(RISC-V platform ) Hi, @Harry_Zhang         Thanks for answering question. My idea is to modify to point the buffer address of desc.addr to mailbox, but desc, avail, used in vring are still maintained in shared memory, is this possible? Because considering the limited space in mailbox, just 256 Bytes. Thanks & Regards yzs Re: rpmsg-lite porting on our MCU(RISC-V platform ) Hi @yzs  Yes, your approach is indeed feasible, and it’s possible to modify the rpmsg-lite framework to utilize the mailbox as shared memory for small data transfers, while still falling back to traditional shared memory for larger transfers. BR Harry
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sCheck 之后需要再次进行哪些初始化 你好,我发现在 s32k312 上执行 sCheck 之后必须再次调用 Platform_Init(),否则 intm 可能无法工作。我认为 sCheck 可能会更改检查的一些设置并保持不变。我是否应该调用所有初始化函数来重置外围设备?如Mcu_Init()、Mcl_Init()、Rm_Init()。
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Pegoda Smart Card Reader Based on PN7642 Hi Sir, Can we have a firmware source code of Pegoda Smart Card Reader? We'd like to design a reader based Pegoda Smart Card Reader. Also, is the SDK including driver, firmware update utility, programing interface guidance and sample code ready? The operating systems are WIndows and Linux. Thanks, Eric Fu Re: Pegoda Smart Card Reader Based on PN7642 Hi Kelly, Thank you. How about the shared SDK and firmware for PN7642 itself(not talking about the Pegoda)? We want to use the shared SDK and firmware and want to make sure if the USB is included. I guess yes after I check there is a CCID related example code in the share SDK. Please help confirm that. Thanks, Eric Fu Re: Pegoda Smart Card Reader Based on PN7642 About the CCID driver for Linux that can be supported by PN7642, can you share the file and link? Ans: The CCID driver under Linux is standard and does not need to be provided separately. You can install it yourself. Re: Pegoda Smart Card Reader Based on PN7642 Hello @Eric12285  PN7642 is an NFC forum certified solution. May I check if the USB interface is included in the certified configuration? And does the shared firmware on the website cover this? Ans: Pegoda 3 is NFC Forum certified, Pegoda3 is a complete standalone product, USB is included in it. Re: Pegoda Smart Card Reader Based on PN7642 Sorry, correct my questions. PN7642 is an NFC forum certified solution. May I check if the USB interface is included in the certified configuration? And does the shared firmware on the website cover this? About the CCID driver for Linux that can be supported by PN7642, can you share the file and link? Thanks, Eric Fu Re: Pegoda Smart Card Reader Based on PN7642 Thanks, Kelly PN7642 is an NFC forum certified solution. May I check if the USB interface is included in the certified configuration? And does the shared firmware on the website cover this? About the CCID interface protocol, does the share firmware cover this for both Windows and Linux? Thanks, Eric Fu Re: Pegoda Smart Card Reader Based on PN7642 Hello @Eric12285  Firmware source code of Pegoda Smart Card Reader should be not available for the user. But PN7642 SDK is open source, you can download on the product page.  Single-Chip Solution with High-Performance NFC Reader, Customizable MCU and Security Toolbox | NXP Semiconductors
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[Security] CSEC with keys Dear NXPs: IC:S32K142 I need to determine whether there is a key in NVM in a scenario, and I hope to get such judgment from the register, rather than the software recording the flag itself. How can I know from the CSEc register that the key has been imported? Re: [Security] CSEC with keys Hi @Gideon  CSEc does not provide information if a key is loaded or not. It's up to user to do the tracking of keys. The only indirect way I can see: try to use a key. If a key is not loaded yet, you should get ERC_KEY_EMPTY error. Regards, Lukas
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S32K3 FLASH write Hi, everyone I am using the first core of the S32K358 chip to program, I want to put the BOOTLOADER program in the memory of PFLASH0, and then put the APP program in the memory of PFLASH1, can the APP run properly? Re: S32K3 FLASH write Thank you for your reply. Re: S32K3 FLASH write It doesn't matter which master accesses a flash block. There's simple rule - if a block is being erased or programmed, it's now allowed to access this block. Only other blocks can be accessed at that time. Regards, Lukas Re: S32K3 FLASH write Hi,@lukaszadrapa, Thank you for your reply, I want to know if the first core of the S32K358 chip can read-while-write all four code? Re: S32K3 FLASH write Hi @DouDou1  Yes, there's no problem with this setup. There are four code flash blocks and read-while-write is supported between these blocks. Regards, Lukas
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NX5P3090 FAULT pin voltage with Vin=0V Hello. I am using the NX5P3090 USB power switch and would like to pull the open-drain FAULT output to a 1.8V supply that can be present even if there is no input to the switch (Vin=0V). Will the presence of 1.8V at the FAULT pin (through a 47kohm pullup) when Vin=0V cause any undesirable behavior in the switch? I see that there is a 6V absolute limit on this pin but it isn't clear to me if this applies when Vin=0V. Thank you.  -Jason Re: NX5P3090 FAULT pin voltage with Vin=0V OK thank you.  -Jason Re: NX5P3090 FAULT pin voltage with Vin=0V Hi  1.8v pull up for this FAULT pin will be no problem without VIN.
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How can I allocate the whole Ethernet to the SRAM and my application to SDRAM? Hi, I'm trying to build an application that uses FreeRTOS, lwip stack, and mbedtls stack. I'm using the MIMXRT1064-EVK with version 2.15.000 of the SDK. I am assigning Heap, Stack, *(NonCacheable.init) and *(NonCacheable) to the SRAM_DTC. Also, my application requires a lot of working memory, so I allocated the Global data placement to the SDRAM. Naturally, the following settings have been completed to use the SDRAM. > add symbols : SKIP_SYSCLK_INIT and XIP_BOOT_HEADER_DCD_ENABLE=1 > modify ethernetif0_init() : SDK_ALIGN to AT_NONCACHEABLE_SECTION_ALIGN However, as mentioned in the post below, this setup is problematic because there are some troubles when the Ethernet tries to get some resources from the SDRAM. (the SDRAM as BOARD_SDRAM or NCACHE_REGION) https://community.nxp.com/t5/i-MX-Processors/iMXRT1024-Ethernet-MAC-not-transmitting-data/m-p/1770206/highlight/true#M216974 How can I allocate the whole Ethernet to the SRAM and my application to SDRAM? Also, is it okay to allocate the Ethernet resources to SRAM_OC? Thanks in advance. Re: How can I allocate the whole Ethernet to the SRAM and my application to SDRAM? To make Ethernet work with SDRAM, the following measures are required: The ENET_INT pin on the MIMXRT1064-EVK board is pulled up (R309) and down (R152). In this state, the GPIO1_Combined_0_15_IRQHandler() interrupt will occur at irregular intervals even if nothing is being done. If you remove R152, the sporadic GPIO1_Combined_0_15_IRQHandler() interrupts will no longer occur. And the GPIO1_Combined_0_15_IRQHandler() interrupt will only be raised if the Ethernet link is up or down. Re: How can I allocate the whole Ethernet to the SRAM and my application to SDRAM? > The variables in my communication application were assigned to SDRAM, but the communication stopped midway as before. The cause was that the stack size of my application task was insufficient. I was using event groups for event triggers in my application tasks. The data in the event group object was corrupted because the application's local array was redundantly allocated to the memory region referenced by the event group object. When the problem occurred, the Heap Usage (FreeRTOS) display showed that there was sufficient memory. Be careful with the stack size required by local variables. By modifying it, my application data related to IP communication was placed in SDRAM and it worked properly. Re: How can I allocate the whole Ethernet to the SRAM and my application to SDRAM? Thanks for your reply, Kerry when I commented out as per your instructions, it stopped at the Ethernet link up detection in the initial settings. Unfortunately, my problem could not be resolved. Re: How can I allocate the whole Ethernet to the SRAM and my application to SDRAM? Hi @atm2024 ,   As I know, if you put all the lwip to the SDRAM, some data need to use the none cache buffer, you can try to disable the cache on your side, whether it have any improvement or not?  in the  void BOARD_ConfigMPU(void) // SCB_EnableDCache(); // SCB_EnableICache(); Try it again.   If you still have question about it, please kindly let me know. Best Regards, Kerry Re: How can I allocate the whole Ethernet to the SRAM and my application to SDRAM? Thanks for the reply, Kerry The IDE I'm using is MXUXpresso IDE v11.9.0 [Build 2144]. This is the previous memory configuration. MCU settings > Memory detailsMCU settings > Memory details Managed Linker ScriptManaged Linker Script When the Global data placement was set to BOARD_SDRAM, the TLS communication stopped midway after repeating several times. So I set the Global data placement to SRAM_OC2. This is the current memory configuration. Managed Linker ScriptManaged Linker Script The Image built with this configuration has no SDRAM allocated. So I changed my application's send and receive buffers to global variables. And I specified __attribute__((section("SDRAM.bss"))) for those global variables. The variables in my communication application were assigned to SDRAM, but the communication stopped midway as before. Is it not possible to allocate not only the lwIP middleware but also my application data related to IP communication to SDRAM? I appreciate your help. Re: How can I allocate the whole Ethernet to the SRAM and my application to SDRAM? Hi @atm2024  Thank you for your interest in the NXP MIMXRT product, I would like to provide service for you. Now, which demo you are using in the SDK? This one? SDK_2_15_000_EVK-MIMXRT1064\boards\evkmimxrt1064\lwip_examples\lwip_httpssrv_mbedTLS\freertos You want to copy:Heap, Stack, *(NonCacheable.init) and *(NonCacheable) to the SRAM_DTC. This is easy, you just need to modify the related data aread to the DTCM. You want to generate your code in the SDRAM, and the data in the internal TCM or OCRAM. It's OK, but you need to make sure the current internal RAM is enough to put your related data. Please tell me which IDE you are using now? Then, I can help you to check the details. Please also tell me your current memory modification or configuration, that will also helps to me to check your situation. Please also tell me your test result. About your question: 1.How can I allocate the whole Ethernet to the SRAM and my application to SDRAM? =>Answer: change the app to internal SDRAM, I don't know which IDE you are using, if it is the mcuxpresso, you can check the linker to RAM. then in the memory, let the first memory as SDRAM. Then, to the stack, heap, *(NonCacheable.init) and *(NonCacheable), select the memory to the internal DTC, ITC. 2. Also, is it okay to allocate the Ethernet resources to SRAM_OC? =>Answer: If the OCRAM is large enough, then you can! Just need to check your code size, I am afraid it is not enough. Wish it helps you! Any updated information, please kindly let me know. Best Regards, Kerry
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