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mrcanhubk344 柔性扫描仪问题 专家你好,我正在使用 板 MRCANHUB K344 但遇到了问题,尽管打开了 STB 和 EN 引脚,但无法在逻辑分析器中接收数据。然后将黄色和白色电缆连接到逻辑分析仪。希望你们能检查一下我的压缩测试程序,哪里出错了,我是否需要使用 MRCANHUBK344 提供的无人机罐术语? Re: MRCANHUBK344 FLEXCAN PROBLEM 你好、 我用的也是这种连接方式。在只连接 Saleae 逻辑系统的情况下,我仍能看到 CAN 信息,因为没有 ACK,也没有连接 CAN 节点。 连接 PCAN 工具后,我看到每 200 毫秒传输一次信息 在代码中,我忽略了";" on while loop BR, Petr Re: MRCANHUBK344 FLEXCAN PROBLEM 谢谢您,但按照您上面说的配置后,我仍然出现 can 错误,能否请您检查一下这样的接线是否正确,我将 can0A 连接到 Logic,can0B 与无人机 can term 连接......如果我能看到您是如何用 MRCANHUBK344 进行接线测试的,将会很有帮助。 Re: MRCANHUBK344 FLEXCAN PROBLEM 您好, Siul2_Dio_Ip_WritePin的用法是错误的。您应该 如果在引脚工具中定义了引脚标签,则可以使用 如果您只连接逻辑分析仪,那么终端(例如:......否则将看不到 CAN 信息。此外,由于逻辑分析器不接受消息,因此它将重复发送,并且您永远不会通过wh ile语句来检查传输。此外,在使用 TX 轮询模式时,你需要反复调用 flexcan_IP_MainFunctionWrite。它可以用作 最后,不要使用 FIRC 作为 CAN 协议时钟,而应选择 FXOSC 或系统时钟。 经过上述更改并终止了总线,我使用分析器看到了这条总线 BR, Petr    
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关于在 MIMXRT11170-EVKB 板上使用 flashloader 的文档 您好, 我正在使用 MIMXRT1170-EVKB 板试用 SDK 提供的 evkbmimxrt1170_flashloader 示例。但是,关于如何使用它在闪存中加载二进制图像或所需工具的文档不多。 我尝试使用 blhost 用户指南:https://www.nxp.com/docs/en/user-guide/MCUBLHOSTUG.pdf和其他一些指南: https://www.nxp.com/docs/en/user-guide/MBOOTQSPIUG.pdf https://www.nxp.com/docs/en/user-guide/MBOOTDEMOUG.pdf 但它似乎并不针对该示例或其用例。 以下是我到目前为止尝试过的命令顺序,但刷新后它无法启动到新镜像: blhost -p COM29 -- get-property 0x19 9 Ping responded in 1 attempt(s) Inject command 'get-property' Response status = 10205 (0x27dd) kStatusMemoryNotConfigured blhost -p COM29 -- fill-memory 0x20000000 4 0xCF900001 Ping responded in 1 attempt(s) Inject command 'fill-memory' Successful generic response to command 'fill-memory' Response status = 0 (0x0) Success. blhost -p COM29 -- configure-memory 9 0x20000000 Ping responded in 1 attempt(s) Inject command 'configure-memory' Successful generic response to command 'configure-memory' Response status = 0 (0x0) Success. blhost -p COM29 -- fill-memory 0x20000000 4 0xC0000006 Ping responded in 1 attempt(s) Inject command 'fill-memory' Successful generic response to command 'fill-memory' Response status = 0 (0x0) Success. blhost -p COM29 -- configure-memory 9 0x20000000 Ping responded in 1 attempt(s) Inject command 'configure-memory' Successful generic response to command 'configure-memory' Response status = 0 (0x0) Success. blhost -p COM29 -- get-property 0x19 9 Ping responded in 1 attempt(s) Inject command 'get-property' Response status = 0 (0x0) Success. Response word 1 = 31 (0x1f) Response word 2 = 805306368 (0x30000000) Response word 3 = 65536 (0x10000) Response word 4 = 256 (0x100) Response word 5 = 4096 (0x1000) Response word 6 = 65536 (0x10000) FlexSPI NOR Attributes: Start Address = 0x30000000 Total Size = 64 MB Page Size = 256 bytes Sector Size = 4 KB Block Size = 64 KB blhost -p COM29 -- flash-erase-region 0x30000000 0x100000 Ping responded in 1 attempt(s) Inject command 'flash-erase-region' Successful generic response to command 'flash-erase-region' Response status = 0 (0x0) Success. blhost -p COM29 -- write-memory 0x30000400 evkbmimxrt1170_lwip_dhcp_enet_qos_freertos_cm7.bin Ping responded in 1 attempt(s) Inject command 'write-memory' Preparing to send 132632 (0x20618) bytes to the target. Successful generic response to command 'write-memory' (1/1)100% Completed! Successful generic response to command 'write-memory' Response status = 0 (0x0) Success. Wrote 132632 of 132632 bytes. C:\Users\tonyjosi\Documents\Work\FE3.0_WS\Tasks\7 RT1170 MCU\BL blhost -p COM29 -- reset Re: Documentation on using flashloader on MIMXRT1170-EVKB board 你好@tj787、 感谢您关注恩智浦 MIMXRT 系列! 有关 Flashloader 的确切文档,请参阅此在线版本: 1.https://mcuxpresso.nxp.com/mcuxsdk/latest/html/middleware/mcu_bootloader/docs/iMXRT1170_Manufacturing_User_Guide/index.html 2.https://mcuxpresso.nxp.com/mcuxsdk/latest/html/middleware/mcu_bootloader/docs/iMXRT1170_Flashloader_Release_Notes/index.html 虽然它非常详细,但为了更快地实现目标,我建议首先使用主机进行测试。官方的MCUXpresso安全配置工具和第三方开源的McubootUtility(来自GitHub)现已推出。两者的核心都是利用 blhost 和 flashloader。 使用主机软件执行相关操作,然后通过日志检索详细的执行过程和命令。这将有助于加快您的开发和使用。 致以最诚挚的问候, Gavin Re: Documentation on using flashloader on MIMXRT1170-EVKB board 你好@tj787、 感谢您的更新! 我确认新版 SDK 中确实缺少这个文件。您可以下载 SDK 2.16.000,在文件夹路径中找到它。 我会在内部报告这个问题。谢谢! 致以最诚挚的问候, Gavin Re: Documentation on using flashloader on MIMXRT1170-EVKB board 谢谢,我已 从 https://mcuxpresso.nxp.com/dashboard 下载 SDK_25.12.00_MIMXRT1170-EVKB(压缩包中包含 McuBoot、MCU 启动),但在 SDK 文档的版本内容部分列出的位置中找不到所需的工具 elftosb 或 MfgTool2.exe。我正在从正确的位置下载 SDK,还是工具的位置发生了变化? Re: Documentation on using flashloader on MIMXRT1170-EVKB board 是否有可能将闪存加载器嵌入闪存中的普通应用程序映像中,当需要用新映像更新应用程序映像时,让应用程序从 RAM 中执行嵌入的闪存加载器? Re: Documentation on using flashloader on MIMXRT1170-EVKB board 谢谢 我能够使用 MCUXpresso 安全配置工具启动映像。 使用闪存加载器示例程序,我可以直接写入图像,而无需更改 BOOT_SEL 引脚。在没有闪存加载器的情况下,我必须将 BOOT_SEL 引脚改为 SDP 模式,才能使用工具编程新映像。有没有办法在 BOOT_SEL 引脚仍保持 SDP 模式时执行图像?我尝试过 RESET PWR,但它需要将 BOOT_SEL 移回内部启动模式才能执行新映像。 另外,闪存加载器或内部引导加载器是否支持通过 SPI 或 CAN 接口而不是 USB/UART 进行编程?
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Documentation on using flashloader on MIMXRT1170-EVKB board Hi, I'm using the MIMXRT1170-EVKB board to try the evkbmimxrt1170_flashloader example provided with the SDK. However, there isn't much documentation on how to use it to load the flash with binary images or the tools required. I tried using the blhost user guide: https://www.nxp.com/docs/en/user-guide/MCUBLHOSTUG.pdf and few others: https://www.nxp.com/docs/en/user-guide/MBOOTQSPIUG.pdf https://www.nxp.com/docs/en/user-guide/MBOOTDEMOUG.pdf but it doesn't seem specific to the example or its use cases. Following is the sequence of commands I have tried so far, but it doesn't boot to the new image after flashing: blhost -p COM29 -- get-property 0x19 9 Ping responded in 1 attempt(s) Inject command 'get-property' Response status = 10205 (0x27dd) kStatusMemoryNotConfigured blhost -p COM29 -- fill-memory 0x20000000 4 0xCF900001 Ping responded in 1 attempt(s) Inject command 'fill-memory' Successful generic response to command 'fill-memory' Response status = 0 (0x0) Success. blhost -p COM29 -- configure-memory 9 0x20000000 Ping responded in 1 attempt(s) Inject command 'configure-memory' Successful generic response to command 'configure-memory' Response status = 0 (0x0) Success. blhost -p COM29 -- fill-memory 0x20000000 4 0xC0000006 Ping responded in 1 attempt(s) Inject command 'fill-memory' Successful generic response to command 'fill-memory' Response status = 0 (0x0) Success. blhost -p COM29 -- configure-memory 9 0x20000000 Ping responded in 1 attempt(s) Inject command 'configure-memory' Successful generic response to command 'configure-memory' Response status = 0 (0x0) Success. blhost -p COM29 -- get-property 0x19 9 Ping responded in 1 attempt(s) Inject command 'get-property' Response status = 0 (0x0) Success. Response word 1 = 31 (0x1f) Response word 2 = 805306368 (0x30000000) Response word 3 = 65536 (0x10000) Response word 4 = 256 (0x100) Response word 5 = 4096 (0x1000) Response word 6 = 65536 (0x10000) FlexSPI NOR Attributes: Start Address = 0x30000000 Total Size = 64 MB Page Size = 256 bytes Sector Size = 4 KB Block Size = 64 KB blhost -p COM29 -- flash-erase-region 0x30000000 0x100000 Ping responded in 1 attempt(s) Inject command 'flash-erase-region' Successful generic response to command 'flash-erase-region' Response status = 0 (0x0) Success. blhost -p COM29 -- write-memory 0x30000400 evkbmimxrt1170_lwip_dhcp_enet_qos_freertos_cm7.bin Ping responded in 1 attempt(s) Inject command 'write-memory' Preparing to send 132632 (0x20618) bytes to the target. Successful generic response to command 'write-memory' (1/1)100% Completed! Successful generic response to command 'write-memory' Response status = 0 (0x0) Success. Wrote 132632 of 132632 bytes. C:\Users\tonyjosi\Documents\Work\FE3.0_WS\Tasks\7 RT1170 MCU\BL blhost -p COM29 -- reset Re: Documentation on using flashloader on MIMXRT1170-EVKB board Hi @tj787 , Thanks for your interest in NXP MIMXRT series! For the exact documentation on Flashloader, you can refer to this online version: 1. https://mcuxpresso.nxp.com/mcuxsdk/latest/html/middleware/mcu_bootloader/docs/iMXRT1170_Manufacturing_User_Guide/index.html 2. https://mcuxpresso.nxp.com/mcuxsdk/latest/html/middleware/mcu_bootloader/docs/iMXRT1170_Flashloader_Release_Notes/index.html Although it is highly detailed, to achieve your goals more quickly, I recommend first testing with a host computer. The official MCUXpresso Secure Provisioning Tool and the third-party open-source MCUBootUtility (from GitHub) are available. Both utilize blhost and flashloader at their core. Use the host computer software to perform relevant operations, then retrieve detailed execution processes and commands via the log. This will help accelerate your development and usage. Best regards, Gavin Re: Documentation on using flashloader on MIMXRT1170-EVKB board Hi @tj787 , Thanks for the update! I confirmed that this file is indeed missing from the new SDK version. You can download SDK 2.16.000 to find it in the folder path. I will report this issue internally. Thank you! Best regards, Gavin Re: Documentation on using flashloader on MIMXRT1170-EVKB board Thanks, I have downloaded SDK_25.12.00_MIMXRT1170-EVKB from https://mcuxpresso.nxp.com/dashboard (with MCUBoot, MCU Boot included in the zip), but the required tools elftosb or MfgTool2.exe are not found in the location listed in the release contents section of the docs in the SDK. I'm I downloading the SDK from the correct location, or did the location of the tools change? Re: Documentation on using flashloader on MIMXRT1170-EVKB board Is it possible to have the flashloader embedded inside a normal application image in flash memory and let the application execute the embedded flashloader from the RAM when there is a need to update the app image with a new image? Re: Documentation on using flashloader on MIMXRT1170-EVKB board Thank you I was able to use MCUXpresso Secure Provisioning Tool to boot images. Using the flashloader example program, I can write images directly without changing the BOOT_SEL pins. Without the flashloader, I have to change the BOOT_SEL pins to SDP mode to use the tools to program new images. Is there a way to execute the image when the BOOT_SEL pins still held at SDP mode? I tried PWR reset, but it needs BOOT_SEL to be moved back to internal boot mode to get the new image executed. Also, does the flashloader or internal bootloader support programming via SPI or CAN interface rather than USB/UART? 
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iMX95 neutron eIQ converter for 6.12.3_1.0.0 Hello, I am using an iMX95 with the BSP: 6.12.3_1.0.0.  I can't move from that BSP, and I am trying to run tensorflow-lite examples, CPU only works, but when using NPU I get the following: # python3 label_image.py -e /usr/lib64/libneutron_delegate.so -m /tmp/converted.tflite Loading external delegate from /usr/lib64/libneutron_delegate.so with args: {} INFO: NeutronDelegate delegate: 1 nodes delegated out of 4 nodes with 1 partitions. Error in cpuinfo: prctl(PR_SVE_GET_VL) failed INFO: Created TensorFlow Lite XNNPACK delegate for CPU. Warning: microcode version mismatch! 0xcebb80a (expected 0x24d93dcf) Warm-up time: 0.8 ms Inference time: 0.4 ms 0.000000: toilet tissue 0.000000: starfish 0.000000: zebra 0.000000: sorrel 0.000000: guinea pig I have been trying multiple neutron converters, but I always get the firmware mismatch. I can't really find the one for 6.12.3, can you help me by pointing me which eIQ version has it?  Thanks, Roberto Re: iMX95 neutron eIQ converter for 6.12.3_1.0.0 Hi @Chavira , Ok I found the real issue, without using any custom model following your guidance, I get everything on 0 but no firmware mismatch: # python3 label_image.py -e /usr/lib64/libneutron_delegate.so Loading external delegate from /usr/lib64/libneutron_delegate.so with args: {} INFO: NeutronDelegate delegate: 29 nodes delegated out of 31 nodes with 1 partitions. Error in cpuinfo: prctl(PR_SVE_GET_VL) failed INFO: Created TensorFlow Lite XNNPACK delegate for CPU. Warm-up time: 56.6 ms Inference time: 0.3 ms 0.000000: toilet tissue 0.000000: starfish 0.000000: zebra 0.000000: sorrel 0.000000: guinea pig After upgrading only the neutron firmware (and tf neutron delegate) to 6.12.20, the error is gone, so probably there was something wrong with the older firmware. Also it took a lot of time loading everything before inference. Anyway, I think I am just able to upgrade this section of the BSP and move on. Thank you.  Re: iMX95 neutron eIQ converter for 6.12.3_1.0.0 Hi @robertogs21, Thank you for contacting NXP Support! Our reference examples do not require model conversion specifically for the NPU. If you are using a different model, you must first quantize the model to INT8 before performing the conversion using eIQ. This step is required for compatibility with the NPU delegate. If you are only following our provided demos, no additional conversion step is needed. You can run the demo directly using the following command: python3 label_image.py --ext_delegate /usr/lib/libneutron_delegate.so This command enables execution using the Neutron delegate. For more details about this demo and model requirements, please refer to the Machine Learning User Guide, which provides a complete explanation of the workflow and supported configurations. Best regards, Chavira
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Problems with the PFE MAC debugging of the S32G274 I am currently debugging PFEMAC using my own board. Now I have encountered a problem. When I initialize the serdes in the APP program, the PFEMAC communication is normal. Since I want to start both the M core and the A core simultaneously, I need to move the serdes initialization to the bootloader. However, when I put the serdes initialization in the bootloader and remove the serdes initialization from the APP, and start the M core alone, the PFEMAC stops working properly. I wonder how else I can troubleshoot this issue? Re: Problems with the PFE MAC debugging of the S32G274 1. I checked the bootloader and APP here the PHI0 configuration is the same, also both checked under the control of the MCU; 2. Eth_43_PFE_PreInit(NULL_PTR) this function I found that no matter whether called or not are still able to communicate; M core of the APP initialization only left Eth_Pfe_Init_IRQ() ; Eth_43_PFE_Init(NULL_PTR); for (iface = 0U; iface < ETH_43_PFE_NUM_CONTROLLER_CFG; iface++) { Eth_43_PFE_SetControllerMode(iface, ETH_MODE_ ACTIVE); }, and there is also the initialization of PFE in the lwip stack static void gmacif_low_level_init(struct netif *netif). 3. The PFE MAC0 is used, and I am connecting to the switch's network cable with my laptop to see if I can ping the s32g274's IP to judge, our oscilloscope can't measure the signal waveform of the SGMII Re: Problems with the PFE MAC debugging of the S32G274 Hi, sdx111 Thank you for your response! 1. You can check if this PHI0 is configured consistently in Clock Configuration, which is the Serdes reference clock object, and if the clock is configured again in the M-core, checking the box Under the control of the MCU may configure the clock again, resulting in an impact on the initialization of the previous Serdes. 2. PFE related initialization should be checked as well. what other APP initialization configurations do you keep for the M core? According to the manual, the call to the function Eth_43_PFE_PreInit(NULL_PTR) should be made before the clock initialization of the PFE, and if you call it after that, the M-core may have problems if it then adjusts the clock initialization of the PFE. 3. How did you perform the signal test and did you use PFE_MCA0 or PFE_MAC1? Is it convenient to test the SGMII signals before and after the SJA1110? BR Joey. Re: Problems with the PFE MAC debugging of the S32G274 1.When booting the M7 APP in bootloader, the clock initialization will not be kept in the M7 APP, it is just that I am debugging the PFE MAC now, and it is going to be removed in the end. 2.The .c and .h files of serdes configurations in the bootloader are copied directly from the app. 3.I have observed the same reference clock in the M7 APP through debugging the bootloader and M7 APP to observe the reference clock of serdes is the same Re: Problems with the PFE MAC debugging of the S32G274 Hi ,sdx111 Thank you for the detailed information, I understand your needs. 1. Is there a need for you to keep the clock initialization in the M7 application when the bootloader starts the M7 application? 2. Please check whether the configuration of serdes in the bootloader is exactly the same as the configuration in the M7 app before porting. 3. Between the bootloder and the M7 application, check that the Serdes reference clock is consistent. BR Joey. Re: Problems with the PFE MAC debugging of the S32G274 It's based on the recommendation that I put the clock and pin initialization of all peripherals into the bootloader already, and now only the PFE MAC doesn't work properly. If I change back to putting the initialization back into the app, I'm not sure if I'll get any other new problems. So I am trying to put the serdes initialization into the bootloader to make sure the PFE MAC still works, and now the phenomenon is not working properly, and want to find the cause and deal with it, which is the purpose of this thread I brought up. Re: Problems with the PFE MAC debugging of the S32G274 1. I debugged the PFE MAC all by booting the M7 separately, I didn't want to try to keep the serdes initialization in the M7 application, what I wanted to solve is why it doesn't work after moving the serdes initialization to the bootloader. Re: Problems with the PFE MAC debugging of the S32G274 Hi, sdx111 1. You can try bootloder to boot the M7 separately to rule out potential conflicts, as the recommendation is to implement clock and pin initialization in the bootloader for easy resource management, if you try to keep the initialization content in the M7 application, make sure that no conflict exists. 2. if the dual-core is activated, it will affect the A core as well >>>The A-nucleus conflict is then preliminarily ruled out. BR Joey. Re: Problems with the PFE MAC debugging of the S32G274 Ran only M-core programs Re: Problems with the PFE MAC debugging of the S32G274 hi,sdx111 After initializing the serdes in the APP, and then performing the clock initialization, normal communication can be achieved. >>>这个测试您使用的是bootloader启动的M核,还是只跑了M核程序呢? BR Joey Re: Problems with the PFE MAC debugging of the S32G274 After initializing the serdes in the APP, and then performing the clock initialization, normal communication can be achieved. However, in this case, if the dual-core is activated, it will affect the A core as well. Re: Problems with the PFE MAC debugging of the S32G274 hi,sdx111 Thank you for your reply. 1.After SerDes is initialized, MUX for SerDes clocks provided to PFE/GMAC has to be changed again. Because when the MUX switches the source clock, the source clock must be ready, which is the hardware limitation. 2.If you still have the clock initial in the M7 application when you use the bootloader to boot M 7 core. Could you have a test to put Serdes initial in M7 app for using the bootloader to boot?  BR Joey Re: Problems with the PFE MAC debugging of the S32G274 I performed the clock initialization in the M7 core. After the serdes initialization, I also included the clock initialization. From the screenshot of the bootloader above, the function is SysDal_McuPlatformInitSeq(); It included the initialization of the clock, but it still didn't work. Also, I would like to know why a second clock initialization is required after the serdes is initialized? Re: Problems with the PFE MAC debugging of the S32G274 hi,sdx111 Thank you for your reply. Do you have the clock initial in the M7 application? After you initialed the Serdes, you should consider do the second the clock initial in the bootloader.  BR Joey Re: Problems with the PFE MAC debugging of the S32G274 1.PFE version: 1.2.0, RTD version: 4.0.2, bootloader: 4.0.0 2.Our M7 kernel application program was developed based on the PFE lwip demonstration program and was debugged on our development board. It includes LLCE, but LLCE is for CAN. 3.Yes, currently I'm only debugging the M7. Re: Problems with the PFE MAC debugging of the S32G274 hi,sdx111 Thank you for contacting us. Could you share more information with me? 1.What is the version of PFE/RTD/bootloader are you using? 2.What is your M7 application? is it the LLCE demo application? 3.when I put the serdes initialization in the bootloader and remove the serdes initialization from the APP, and start the M core alone, the PFEMAC stops working properly.  >>>Do you only use the bootloader to boot the M7 for the Serdes testing? not have the A core using? BR Joey Re: Problems with the PFE MAC debugging of the S32G274 1. After initializing the SerDes, the SerDes clock MUX provided to the PFE/GMAC must be changed again because the source clock must be ready when the MUX switches the source clock, which is a hardware limitation. As mentioned here, the SerDes clock MUX supplied to the PFE/GMAC must be changed again, can you tell me in detail what registers are included? Re: Problems with the PFE MAC debugging of the S32G274 hi ,sdx111 Thank you for your response! I will help you test it on my end and also discuss your issue with internal experts and will get back to you as soon as I have the results! BR Joey.
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imx8mp eqos & sja1105p vlan filter issue Hi, nxp term. Our custom board architecture consists of an imx8mp-evk and an sja1105P switch chip. The imx8mp's eqos network card is connected to the third port of the switch as the host, and the other four sub-ports are connected to four devices. Each device sends L2 layer data packets. I'm now adding VLAN port isolation to isolate the four sub-ports from each other, but adding VLANs causes the following kernel error. [ 100.613807] invalid VLAN protocol: 0xdadb [ 100.617909] WARNING: CPU: 0 PID: 16 at net/8021q/vlan.h:48 vlan_do_receive+0x158/0x3c0 [ 100.625843] Modules linked in: [ 100.628904] CPU: 0 UID: 0 PID: 16 Comm: ksoftirqd/0 Tainted: G W 6.12.49-g351428da8283-dirty #10 [ 100.639085] Tainted: [W]=WARN [ 100.642054] Hardware name: NXP i.MX8MPlus EVK board (DT) [ 100.647368] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 100.654337] pc : vlan_do_receive+0x158/0x3c0 [ 100.658615] lr : vlan_do_receive+0x158/0x3c0 [ 100.662894] sp : ffff8000823f3930 [ 100.666207] x29: ffff8000823f3930 x28: 0000000000000001 x27: ffff8000823f39c0 [ 100.673359] x26: 000000000000a888 x25: 0000000000000000 x24: 0000000000000000 [ 100.680506] x23: 0000000000000000 x22: ffff0000d1388800 x21: ffff0000d096d000 [ 100.687655] x20: ffff8000823f39c0 x19: ffff0000d1388800 x18: 0000000000000006 [ 100.694802] x17: ffff0000d0035900 x16: 0000000000000000 x15: ffff8000823f34ef [ 100.701954] x14: ffff800082004d40 x13: 626461647830203a x12: 6c6f636f746f7270 [ 100.709102] x11: ffff800082004d40 x10: 0000000000000323 x9 : ffff80008205cd40 [ 100.716251] x8 : 0000000000017fe8 x7 : 00000000fffff000 x6 : ffff80008205cd40 [ 100.723397] x5 : 0000000000000000 x4 : 0000000000000000 x3 : 0000000000000000 [ 100.730546] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff0000d0271140 [ 100.737697] Call trace: [ 100.740145] vlan_do_receive+0x158/0x3c0 [ 100.744079] __netif_receive_skb_core.constprop.0+0x48c/0x1000 [ 100.749928] __netif_receive_skb_list_core+0xe8/0x220 [ 100.754992] netif_receive_skb_list_internal+0x1a8/0x2c0 [ 100.760313] napi_gro_receive+0xdc/0x1bc [ 100.764244] gro_cell_poll+0x54/0xa8 [ 100.767824] __napi_poll+0x38/0x180 [ 100.771320] net_rx_action+0x158/0x2c0 [ 100.775079] handle_softirqs+0x100/0x244 [ 100.779011] run_ksoftirqd+0x3c/0x4c [ 100.782596] smpboot_thread_fn+0x20c/0x234 [ 100.786697] kthread+0x110/0x114 [ 100.789933] ret_from_fork+0x10/0x20 [ 100.793516] ---[ end trace 0000000000000000 ]--- This is my device tree. &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; phy-mode = "rgmii-id"; status = "okay"; dsa,member = <0 2>; }; &ecspi1 { #address-cells = <1>; #size-cells = <0>; fsl,spi-num-chipselects = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; // assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; // assigned-clock-rates = <&clk IMX8MP_SYS_PLL1_80M>; cs-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; status = "okay"; sja1105p@0 { #address-cells = <1>; #size-cells = <0>; compatible = "nxp,sja1105p"; firmware_name = "sja1105p_cfg.bin"; /// optional spi-max-frequency = <0x1E8480>; // 25 000 000 0x17d7840 // 2000 000 spi-cpha; reg = <0x0>; status = "okay"; dsa,ethernet = <&eqos>; dsa,num-ports = <5>; dsa,num-cpu-ports = <1>; dsa,member = <0 0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; label = "swp1"; phy-mode = "rgmii-id"; rx-internal-delay-ps = <2000>; tx-internal-delay-ps = <2000>; fixed-link { speed = <1000>; full-duplex; }; }; port@1 { reg = <1>; label = "swp2"; phy-mode = "rgmii-id"; rx-internal-delay-ps = <2000>; tx-internal-delay-ps = <2000>; fixed-link { speed = <1000>; full-duplex; }; }; port@2 { reg = <2>; label = "cpu"; ethernet = <&eqos>; phy-mode = "rgmii-id"; rx-internal-delay-ps = <2000>; tx-internal-delay-ps = <2000>; fixed-link { speed = <1000>; full-duplex; }; }; port@3 { reg = <3>; label = "swp3"; phy-mode = "rgmii-id"; rx-internal-delay-ps = <2000>; tx-internal-delay-ps = <2000>; fixed-link { speed = <1000>; full-duplex; }; }; port@4 { reg = <4>; label = "swp4"; phy-mode = "rgmii-id"; rx-internal-delay-ps = <2000>; tx-internal-delay-ps = <2000>; fixed-link { speed = <1000>; full-duplex; }; }; }; }; };   My netplan settings. network: version: 2 renderer: networkd ethernets: end0: dhcp4: true optional: true swp1: {} swp2: {} swp3: {} swp4: {} end1: {} bridges: br0: interfaces: [swp1, swp2, swp3, swp4] dhcp4: no addresses: - 172.24.172.10/24 parameters: stp: false forward-delay: 0 nameservers: addresses: [8.8.8.8, 114.114.114.114] My port isolation settings. #!/bin/bash ethtool -K end1 rx-vlan-filter off echo "Enabling VLAN filtering on br0..." ip link set dev br0 type bridge vlan_filtering 1 echo "Clearing default VLAN 1 from ports..." bridge vlan del dev br0 vid 1 self for i in {1..4}; do bridge vlan del dev swp$i vlan 1 done echo "Assigning isolated VIDs to ports..." bridge vlan add dev swp1 vid 11 pvid untagged bridge vlan add dev swp2 vid 12 pvid untagged bridge vlan add dev swp3 vid 13 pvid untagged bridge vlan add dev swp4 vid 14 pvid untagged echo "Configuring CPU port (br0) to accept all VIDs..." bridge vlan add dev br0 vid 11 untagged self bridge vlan add dev br0 vid 12 untagged self bridge vlan add dev br0 vid 13 untagged self bridge vlan add dev br0 vid 14 untagged self bridge vlan add dev br0 vid 10 pvid untagged self bridge vlan add dev swp1 vid 10 bridge vlan add dev swp2 vid 10 bridge vlan add dev swp3 vid 10 bridge vlan add dev swp4 vid 10 i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Linux Yocto Project Re: imx8mp eqos & sja1105p vlan filter issue Hi, Thank you for your interest in NXP Semiconductor products, Can you share your setup schematics? I don't understand the setup with i.MX 8MP EVK and SJA1105 switch. Share your BSP version, please. Also, share the results of switch ports network activity without VLAN, are ports active? Regards
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S32K146は、ブートローダー/アプリケーションを使用してファームウェアを更新した後、保護され、消去できなくなります。 NXPサポートチーム様 現在、NXP S32K146 MCU 上でブートローダベースのファームウェア更新メカニズムを開発しています。開発中に、特定のファームウェア イメージをフラッシュした後にデバイスが保護され、消去できなくなるという重大な問題が発生しています。 私たちのセットアップでは、ブートローダーとアプリケーション アーキテクチャを使用します。MCU は最初は期待どおりに動作し、ファームウェアの更新も正常に機能します。ただし、アプリケーションを複数回フラッシュした後、またはアプリケーションをベース (ブートローダ以外) リンカー構成に切り替えると、デバイスはセキュリティ保護された状態になります。この状態では、connect-under-reset を使用しても大量消去が失敗し、デバッガーは接続できません。J-Link は、デバイスが保護されており、コアを停止できないことを報告し、これにより、それ以上のフラッシュとファームウェアの検証がブロックされます。 使用される MCU は S32K146 であり、JTAG 経由で SEGGER J-Link V9 デバッガーを使用しています。 以下は、このプロジェクトで使用されるフラッシュ メモリのレイアウトです。 ブートローダーリンカー構成: MEMORY { m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010 m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0 m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x0000F000 } アプリケーション リンカーの構成: MEMORY { m_interrupts (RX) : ORIGIN = 0x00010000, LENGTH = 0x00000400 m_flash_config (RX) : ORIGIN = 0x00010400, LENGTH = 0x00000010 m_text (RX) : ORIGIN = 0x00010410, LENGTH = 0x000EFBF0 m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x0000F000 } ベースアプリケーションリンカー構成(ブートローダーなし): MEMORY { m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010 m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0 m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x0000F000 } フラッシュ コンフィギュレーション フィールドの正しい処理、ブートローダとアプリケーションの分離のための推奨リンカー レイアウト、意図しないフラッシュ セキュリティ ロックを防止する方法、および S32K146 MCU で信頼性の高いファームウェア更新メカニズムを実装するためのベスト プラクティスについてご指導をお願いいたします。 あなたのサポートは、この問題を解決し、ファームウェアの検証を安全に進めるのに役立ちます。 ご協力ありがとうございました。 よろしくお願いします、 パンディヤンT ファームウェア エンジニア。 Re: S32K146 becomes secured and not erasable after firmware update using bootloader/application こんにちは@Panidiyan_T ご提供いただいたリンクファイルの設定に問題は見つかりませんでした。 そしてあなたのアプローチは最も一般的です。 ブートローダとアプリケーション コードがフラッシュ内に存在する場合は、ブートローダでチップ セキュリティとフラッシュ データ保護機能を構成することをお勧めします。ブートローダが破損するのを防ぐために、ブートローダ コード領域のデータ保護を構成することもお勧めします。
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iMX8 Inline Encryption Engine How can I configure the IEE to encrypt/decrypt DDR content on the fly on the i.MX8QXP MEK board? I couldn't find any information in the MEK BSP. What is the best practice? Is this configured in the Device Tree? Or at the U-Boot level via a special iee command? Is there maybe an application note about it? Any advice is welcome. Re: iMX8 Inline Encryption Engine Hello, @reinerseifried  I hope you are doing very well. We have not Documentation to share, but it should be enough enabling the:  config BLK_INLINE_ENCRYPTION = y. Please take a look to the inline-encryption.rst. Best regards, Salas. Re: iMX8 Inline Encryption Engine Hi Manuel, I probably expressed myself incorrectly. I did not mean “disk encryption,” but rather DDR in the sense of Double Data Rate Random Access Memory, also known as DRAM. There is even an erratum, ERR010909, for the controller, which literally states: “IEE operation is limited to DRAM, OCRAM and FlexSPI memory space only.” This IEE function is exactly what we want to apply to DRAM. Best regards, Reiner Re: iMX8 Inline Encryption Engine Hello @reinerseifried  Thank you, It was my misunderstood. Please take a look to the sc_fw_port. (System Controller Firmware Porting guide). There is described how to use it: You can download it here: Embedded Linux for i.MX Applications Processors. Then follow the instructions to build and get the documentation. Best regards, Salas.
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S32K1 vdd falling low voltage POR clear situation S32K1 vdd falling low voltage POR clear situation 1. Abstract This document primarily aims to explain the situation where the POR flag in the RCM_SSRS of the S32K1 chip is cleared, and to explain the setting status of the reset pin and the POR and LVD bits when VDD is powered down. This article is written because some customers, when using the RCM_SSRS reset flag to determine the corresponding RAM initialization conditions, have made incomplete considerations, leading to component failures in actual projects. They mistakenly believe that as long as the SSRS POR flag is not cleared by software writing a 1 after power-on, the POR bit will remain indefinitely. In reality, even after power-on, if subsequent power fluctuations cause VDD to drop to LVD/LVR and trigger a reset, the POR flag may still be automatically cleared by the chip.   2. Document content This article mainly categorizes VDD power-down scenarios into three main types: (1) VDD drops below the minimum LVR value but above VPOR, and then power is  back to normal VDD. In this case, reset flag POR=0 and LVD=1 in RCM_SSRS. (2) VDD drops below LVD, above LVR, and LVDRE=0. In this case, reset flag POR=1 and LVD=1 in RCM_SSRS. (3) VDD drops below LVD, above LVR, and LVDRE=1. In this case, reset flag POR=0 and LVD=1 in RCM_SSRS. The schematic diagram is as follows: 3. Test result on S32K116 board
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MCSPTE1AK116 (S32K116 + GD3000): Can CAN0 TX/RX be used with the motor driver board attached? Integr Hello, I’m working with the MCSPTE1AK116 kit (S32K116 + GD3000) using the BLDC 6-step sensorless example. My goal is to implement dual-axis control using two boards connected via CAN (each board controls one motor), where CAN commands update the motor speed setpoint. On an EVB project (CAN PAL example), I already verified board-to-board CAN communication with LED indication and UART logging. Now I want to port the CAN logic into the MCSPTE1AK116 motor example project and integrate it as “CAN RX → motor speed(setpoint) update”. However, I previously experienced a pin conflict where UART signals overlapped with GD3000-related signals, so I’m concerned that CAN might face similar issues. I’d like advice on the following: With the GD3000 motor driver board attached, are CAN0 TX/RX pins actually available/usable on MCSPTE1AK116? Which S32K116 pins are routed to CAN_TX/RX on this kit, and what transceiver (e.g., UJA1169) is used? Could the motor driver board occupy or reroute those pins in a way that prevents CAN from working? Are there any jumpers/resistors/board settings required to enable CAN when the motor driver board is installed? When adding CAN to the BLDC 6-step sensorless example, what are the typical resource conflicts to watch for (interrupts/timers/ADC, etc.)? The 6-step example heavily uses PWM timers, capture/compare, ADC triggering, PIT/LPTMR, and interrupt priorities. Are there known conflict points (especially interrupt priority or timing) that can destabilize motor operation when CAN RX is added? Recommended software pattern for CAN handling in motor control? My plan is to avoid any blocking calls (delay, UART blocking send, etc.) inside CAN RX ISR. Instead, the ISR only updates flags/buffers, and the motor control loop (e.g., 1 ms task) applies setpoint updates. Is this the recommended approach? If there is any reference documentation for CAN0 pin routing/transceiver schematic/jumper settings on MCSPTE1AK116, or any example of integrating CAN into the motor control demo safely, I would appreciate your guidance. Thank you Re: MCSPTE1AK116 (S32K116 + GD3000): Can CAN0 TX/RX be used with the motor driver board attached? In Thank you for the helpful answer. Re: MCSPTE1AK116 (S32K116 + GD3000): Can CAN0 TX/RX be used with the motor driver board attached? In Hi, see my feedbacks below... With the GD3000 motor driver board attached, are CAN0 TX/RX pins actually available/usable on MCSPTE1AK116? A: yes,  CAN0 TX/RX pins are still available Which S32K116 pins are routed to CAN_TX/RX on this kit, and what transceiver (e.g., UJA1169) is used? A: CAN_TX/RX on PTE5/PTE4 are used and connected to SBC's (UJA1169) CAN transceiver. CAN bus signals are available on J13 header Could the motor driver board occupy or reroute those pins in a way that prevents CAN from working? A: No, there is no conflict with above pins used. Are there any jumpers/resistors/board settings required to enable CAN when the motor driver board is installed? A: No jumpers are needed. The board/SBC must be powered by external 12V. SBC should be ideally kept in default Forced Normal mode, unless SPI setting will be needed to enable its  transceiver. When adding CAN to the BLDC 6-step sensorless example, what are the typical resource conflicts to watch for (interrupts/timers/ADC, etc.)? A: check chapter 4.3.4. Application timing and interrupts of the kit AN13000 for resource utilization The 6-step example heavily uses PWM timers, capture/compare, ADC triggering, PIT/LPTMR, and interrupt priorities. Are there known conflict points (especially interrupt priority or timing) that can destabilize motor operation when CAN RX is added? A: heavy bus traffic can most probably affect motor control timing, but if CAN ISR will be kept as short as possible and its priority set to do not preempt critical motor control ISR, then it can be used.  Recommended software pattern for CAN handling in motor control? My plan is to avoid any blocking calls (delay, UART blocking send, etc.) inside CAN RX ISR. Instead, the ISR only updates flags/buffers, and the motor control loop (e.g., 1 ms task) applies setpoint updates. Is this the recommended approach? A: yes it can be considered as good approach. Also polling handling can be tested. Similar as FreeMASTER, where polling control is used. If there is any reference documentation for CAN0 pin routing/transceiver schematic/jumper settings on MCSPTE1AK116, or any example of integrating CAN into the motor control demo safely A: You can simply check S32K116EVB schematic for CAN connection. Unfortunately I am not aware of motor control demo integrating CAN communication. You can refer to available SDK demo examples for CAN implementation. BR, Petr
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i.MX8QXP CM4 support on Zephyr v4.3.0 Some customer need to run Zephyr on i.MX8QXP CM4, but there is no support on Zephyr mainline(v4.3.0) This article will share the porting based on Zephyr v4.3.0. For i.MX8QM CM4, please refer this link: https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX8QM-CM4-0-support-on-Zephyr-v4-3-0/ta-p/2296962 samples/hello_world/ samples/synchronization Add pd_ignore_unused in bootargs before entering Linux. For the OpenAMP communication, need to refer this Zephyr application. https://github.com/nxp-real-time-edge-sw/heterogeneous-multicore/blob/main/apps/rpmsg_str_echo/zephyr/main.c
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RT1170 の LPUART1 BREAK 検出に関する問題 NXPサポートチーム様 現在、UART 通信用の LPUART1 を搭載した SDK を使用して RT1170 を開発しています。Send BREAK の検出で問題が発生しており、ご指導をいただきたいと思います。 問題の説明: LINブレーク検出(LBKDE)とLBKDIEを有効にすると: PC からの Send BREAK 信号が MCU で正常に検出されます (LBKDIF フラグが設定されます)。 ただし、通常の UART データ通信は機能しません。 通常の UART モードで RX と TX が正常に動作しています。 スコープ測定により、Send BREAK 中に PC の TX ラインが予想される期間 (約 2100 ミリ秒) にわたって低いままであることが示されます。 質問: RT1170 LPUART ではこの動作が想定されていますか? 通常の UART 通信を許可しながら、PC の BREAK 送信を検出する推奨方法はありますか? RT1170 で正常な UART データ受信を維持しながら、PC からの Send BREAK を確実に検出する方法についてご指導いただければ幸いです。 ご協力ありがとうございます。 よろしくお願いいたします。 Re: Issue with LPUART1 BREAK Detection on RT1170 NXPサポートチーム様 前回のご説明と RT1170 リファレンス マニュアルへの参照をありがとうございます。 RM の説明に基づくと、 LBKDE = 1の場合、 LIN ブレーク検出回路が有効になり、受信データが RX FIFO に書き込まれないため、通常の UART 受信が意図的に無効になることがわかります。この動作は想定内のものであると認識しています。 ただし、可能な代替案や推奨される解決策に関して追加の質問をしたいと思います。 私たちの要件 PC からのSend BREAK条件を検出します (USB-UART 経由)。 同時に、通常の UART データの送受信を継続します。 LIN プロトコル スタックは必要ありません。これは、同期または制御信号として BREAK が使用される一般的な UART 通信です。 私たちが観察したもの LBKDE = 1の場合 LIN BREAKが正しく検出されます(LBKDIFが設定されます)。 RM で説明されているように、通常の UART RX データはブロックされます。 LBKDE = 0の場合 通常の UART RX は正常に動作します。 私たちの質問 LBKDE を有効にせずに、通常の UART RX をアクティブに保ちながらSend BREAK を検出するために RT1170 でサポートまたは推奨される方法はありますか? フレーミング エラー (FE) + RX FIFO フラッシュの使用は、非 LIN UART BREAK 検出に対する意図された回避策と考えられますか? 一般的な UART 通信で LBKDE を使用する場合、エラッタ、文書化されていない設定、またはハードウェアの制限はありますか? このユースケースがサポートされていない場合は、 RT1170 LPUART がデザイン上、LIN BREAK 検出と通常の UART 受信を同時にサポートしていないことを確認してください。 このシナリオについてご確認いただくか、推奨されるベストプラクティスがあればお知らせください。 今後ともどうぞよろしくお願い申し上げます。 よろしくお願いいたします。 Re: Issue with LPUART1 BREAK Detection on RT1170 こんにちは@dskim2さん、 NXP MIMXRTシリーズにご興味をお持ちいただきありがとうございます。 あなたが説明した現象は予想されたものです。RM からの以下の説明を参照してください。 さらに、弊社の同僚の 1 人が、お客様にとって役立つ可能性のある同様の機能を実装しました。 1. https://community.nxp.com/t5/NXP-Designs-Knowledge-Base/RT1170-LIN-driver-development-and-stack-porting/ta-p/1356144 2. https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Use-RT1060-STAT-LBKDE-to-detect-Lin-quot-break-quot-but-cannot/mp/1458242 よろしくお願いします、 ギャビン
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BSDL file FS32K142HAT0MLHT I find a BSDL file for the FS32K142HAT0MLHT 64LQFP Can someone send it to me? Thanks Re: BSDL file FS32K142HAT0MLHT Thanks for the information. I've already opened a ticket. How long does it take for you to respond? Thanks Massimo Re: BSDL file FS32K142HAT0MLHT Hello, Here is the guide how to rise a ticket. Materials as BSDL files are under controlled distribution, therefore the ticket is necessary. https://community.nxp.com/t5/Qonverge/How-I-could-create-a-Service-Request/m-p/481342 Best regards, Peter Re: BSDL file FS32K142HAT0MLHT Hi, could you please provide me with an email address where I can send this message? I've never opened a ticket. I need the bsdl file to test the component with Boundary Scan Test on the Agilent 3070 platform. Thanks. Re: BSDL file FS32K142HAT0MLHT Hello, Sure, but not via public community, Please rise a request ticket via NXP.com support and we will send it to you. Best regards, Peter Re: BSDL file FS32K142HAT0MLHT Hello, It is usually withing a day. If there is delay you can post here the ticket number and I will check it. Best regards, Peter
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GUIガイドでメモリ使用量を確認する こんにちは。GUI ガイドのプロジェクトが使用するメモリの量を確認しようとしています。アプリケーションでこれに簡単にアクセスする方法はありますか?iMX91プロセッサを使用しています。ありがとう! Re: look at memory usage in gui guider こんにちは、 GUI Guider v1.10.1 ユーザー ガイドを参照して、「メモリ モニター」機能を確認することをお勧めします。 よろしくお願いいたします。
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imx8ulp-evk: Yocto 5.2 (L6.12.49) build failure with tensorflow-lite-vx-delegate / litert-vx-delegat Hello, I am building imx-image-full for i.MX8ULP EVK using NXP Yocto 5.2 (kernel L6.12.49) and encounter build failures related to tensorflow-lite-vx-delegate and litert-vx-delegate. Both packages fail during the download/verify step when fetching kleidiai from Arm GitLab, resulting in a SHA256 checksum mismatch. The issue is reproducible for: tensorflow-lite-vx-delegate (2.19.0) litert-vx-delegate (1.2.0) It appears that the upstream kleidiai archive content has changed while keeping the same commit hash, causing the checksum defined in the recipes to be invalid. Full build logs for both packages are attached below. Questions: Is this a known issue in Yocto 5.2? Is there an official fix or updated checksum? Thanks in advance. i.MX8ULP Yocto Project Re: imx8ulp-evk: Yocto 5.2 (L6.12.49) build failure with tensorflow-lite-vx-delegate / litert-vx-del $ bitbake tensorflow-lite-vx-delegate -c cleansstate $ bitbake tensorflow-lite-vx-delegate -c patch $ cd build/tmp/work/armv8a-poky-linux/tensorflow-lite-vx-delegate/2.19.0/sources-unpack/tfgit $ patch -p1 <0001-Fix-source-sha256-mismatch-issue-for-KleidiAI.patch $ bitbake tensorflow-lite-vx-delegate Re: imx8ulp-evk: Yocto 5.2 (L6.12.49) build failure with tensorflow-lite-vx-delegate / litert-vx-del I ran into the same tensorflow-lite build failure related to kleidiai on Yocto for the frdm-imx93 board. Here is my solution: cd sources/meta-imx patch -Np1 -i 0001-Fixed-KleidiAI-sha256-mismatch.patch This solution does not patch tensorflow itself. I think this is a clearer solution. Re: imx8ulp-evk: Yocto 5.2 (L6.12.49) build failure with tensorflow-lite-vx-delegate / litert-vx-del Thank you for the suggestion. Instead of modifying the downloaded source directly, I applied the workaround properly via a custom meta layer. After applying this change, the build issue of tensorflow-lite-vx-delegate is resolved successfully. However, litert-vx-delegate still fails with the same kleidiai SHA256 checksum mismatch during the download step. Do you have any suggestion for litert-vx-delegate, or is there a separate fix planned for this package? Re: imx8ulp-evk: Yocto 5.2 (L6.12.49) build failure with tensorflow-lite-vx-delegate / litert-vx-del Please refer to the attached patch.
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[IMX8MP][DWE] 广角鱼眼畸变校正 引擎的澄清 摘自 IMX8MPRM,第 1 版,2021 年 6 月: 广角鱼眼畸变校正 引擎不能用作独立组网 (SA) 模块。 1.这是硬件限制(共享时钟控制等)吗? 2.这是软件限制吗,因为用户空间栈(isp-imx)不支持这种用例? 2.是否可以使用 isi_0 或 isp_0 将 RAW8 GRAYSCALE 转换为与 dwe 兼容的格式? Re: [IMX8MP][DWE] Dewarp Engine clarification 我还想同时使用正常视频和去噪视频。您能帮我解决这个问题吗? Re: [IMX8MP][DWE] Dewarp Engine clarification 来自 iMX8MP_CAMERA_DISPLAY_GUIDE.pdf 图 17(见下文)。看来广角鱼眼畸变校正输出是图像信号处理器的单独输出,人们应该能够与访问 /dev/video0 设备节点上的 ISP 输出并行访问该输出。 这种理解是否正确?如果是,我该如何访问 广角鱼眼畸变校正 的输出?我已经激活了广角鱼眼畸变校正 但我只能看到 /dev/video0 设备节点。  欢迎使用 广角鱼眼畸变校正 的任何用法示例。 谢谢   Re: [IMX8MP][DWE] Dewarp Engine clarification 我已经给您发了邮件,并给出了详细答复,请查看您的邮箱 Re: [IMX8MP][DWE] Dewarp Engine clarification 我还想同时使用正常视频和去噪视频。您能帮我解决这个问题吗?
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Can you select multiple controls and modify their properties in a unified way? As the question, with version 1.10.0 actually verified that it is not possible to modify the properties uniformly by selecting multiple controls. This is a very effective feature when modifying the properties of multiple controls in a unified way, if not, can it be added to the next version? Thanks for the reply. Re: 能否选中多个控件统一修改属性 Hi @xiaowan  Thanks for your information. I will report your suggestions to the GUI GUider team. BR Harry
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S32K396-BGA-DC1 ethernet connectivity Looking into using Ethernet on S32K396 and investigating the options of getting connected. We bought S32K396-BGA-DC1 with S32X-MB under the assumption that we would be able to use the T1S PHY that is available on S32X-MB, but S32K396-BGA-DC1 by default wires the PHY signals to a separate PHY connection and not the MB connectors, which coincidentally also destroys many of the provided examples such as SPI etc. It is not entirely obvious where the strapping resisitors on the S32K396-BGA-DC1 board is for rewiring to use the MB connection instead. Only gerbers is provided under design resources, and it appears to be missing net & component information making it unnecessarily hard to navigate the board design. Is there any more easily digestable design resource for the board? Alternatively, which PHY boards are available that works with the PHY connector on S32K396-BGA-DC1? Re: S32K396-BGA-DC1 ethernet connectivity Yes I meant 100BASE-T1. I have managed to locate the resistors. Just very time consuming when having to to search the board visually with no searchable metadata. Availability of the TJA1103-SDBR board is a bit low. I assume TJA1104-SDBR would work as well even if we are not using MACSEC. Re: S32K396-BGA-DC1 ethernet connectivity Hello @Henrik-Wires , Just to clarify that there's no T1S PHY on S32X-MB. There's 100BASE-T1 TJA1103. Yes, S32K396's EMAC is routed to the SABRE connector by default. Regarding PCB, there's no more files available. However, strapping resistors can be located thanks to white labels on PCB. Alternatively, https://www.nxp.com/part/TJA1103-SDBR fits the SABRE connector on S32K396-BGA-DC1 . TJA1103-SDBR needs to be in rev-RMII mode to generate clock on TXC -> add jumper 2-3 to CONFIG4. Best regards, Pavel Re: S32K396-BGA-DC1 ethernet connectivity Hello @Henrik-Wires , Yes, TJA1104-SDBR should work as well as TJA1103-SDBR. Best regards, Pavel Re: S32K396-BGA-DC1 ethernet connectivity Thanks for the reminder to check CONFIG. The default config as delivered is "different".
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