S32K1 vdd falling low voltage POR clear situation
1. Abstract
This document primarily aims to explain the situation where the POR flag in the RCM_SSRS of the S32K1 chip is cleared, and to explain the setting status of the reset pin and the POR and LVD bits when VDD is powered down. This article is written because some customers, when using the RCM_SSRS reset flag to determine the corresponding RAM initialization conditions, have made incomplete considerations, leading to component failures in actual projects. They mistakenly believe that as long as the SSRS POR flag is not cleared by software writing a 1 after power-on, the POR bit will remain indefinitely. In reality, even after power-on, if subsequent power fluctuations cause VDD to drop to LVD/LVR and trigger a reset, the POR flag may still be automatically cleared by the chip.
2. Document content
This article mainly categorizes VDD power-down scenarios into three main types:
(1) VDD drops below the minimum LVR value but above VPOR, and then power is back to normal VDD. In this case, reset flag POR=0 and LVD=1 in RCM_SSRS.
(2) VDD drops below LVD, above LVR, and LVDRE=0. In this case, reset flag POR=1 and LVD=1 in RCM_SSRS.
(3) VDD drops below LVD, above LVR, and LVDRE=1. In this case, reset flag POR=0 and LVD=1 in RCM_SSRS. The schematic diagram is as follows:
3. Test result on S32K116 board
