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Installation Instructions S32 Design Studio 3.6.4 Hi, Is there an installation manual for 3.6.4 on Linux? There is one for 3.5 that describes a number of dependencies that must be installed. Thanks. Re: Installation Instructions S32 Design Studio 3.6.4 Hi,  please see attached document. 
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Copy: RTD Linker Input Sections for S32K3xx This post is a copy from here I have a question about the linker input sections for the RTDs (Build Version: S32K3_RTD_6_0_0_QLP04_D2508_ASR_REL_4_7_REV_0000_20250822). There is an input section named '.mcal_const_no_cacheable' and it is located to the memory region 'int_sram_no_cacheable'. I am a bit confused, because I would expect 'const' data in the FLASH and not in the RAM.  Is there a reason for mapping it into the RAM?  Thanks, in advanced for your help.  Priority: MEDIUM RTD S32DS Source: NXP Internal Re: Copy: RTD Linker Input Sections for S32K3xx Hi @Luis_Garabo , Yes, const normally resides in FLASH/ROM but it can be put in RAM with setting Read-Only in MPU and RTD's linker file, like this: In RTD drivers, as long as I know, they didn't really use const_no_cache, but if the customer want to use it, they completely set access right to that memory region. Best regards, Nhi
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MC9S12C64 ADC question MC9S12C64, CW V5.9.0, absolute assembler. In my program I want to read 5 channels in 8 bit resolution at different points in my program. When I test it on a test program I set an output when the conversion starts, and clear it when the conversion is finished for each channel in succession. Then I record this on my digital signal analyzer to see how long each channel conversion takes. The conversion on Ch0 takes 7.41uS, which is about what I expected. However, each of the next channels take  6uS longer than the previous one. Ch0 - 7.41uS, Ch1 - 13.42uS, Ch2 - 19.41uS, Ch3 - 25.45uS, ch4 - 31.41uS, Ch5 - 37.41uS. I'm assuming I have done something wrong in my ADC set up but I can't seem to find it. Any suggestions would be appreciated. Regards, Robert  Re: MC9S12C64 ADC question Hi Robert, We don't have any interrupt execution time specification, but you may refer to the reference manual of the core. https://www.nxp.com/webapp/Download?colCode=S12CPUV2 7.5.3 Interrupt Recognition Figure 7-1. Exception Processing Flow Diagram I would recommend that you measure it in your setup. If you use the interrupts, the core will not be blocked in a loop polling the flags, this is the advantage of it. It also depends on other interrupt and their priorities. Regards, Daniel Re: MC9S12C64 ADC question OK. I finally figured out where I was going wrong, (revised code attached), but now I have a question. Depending on how many conversions I want, the processing time varies like this: 2 conversions ~7.42uS, 4 conversions ~8.41uS, 8 conversions ~10.41uS, 16 conversions ~14.41uS. I am assuming that the more conversions I do, the better the accuracy, but I have to balance this with speed of conversion. I am sampling the channels at specific times in the main loop. Every time I sample a channel I have to wait for the conversion to complete. Instead of waiting, I could enable the conversion complete interrupt and read the register and save it to the appropriate variable within the interrupt. So my question is, how much time would it take to service the interrupt and which method would be most efficient, waiting for the conversion completion or servicing conversion complete interrupt? Regards, Robert Re: MC9S12C64 ADC question I've made some progress, but I still have a problem. With my revised code, (attached) All the ADC channels will work, but the processing time per channel is ~37 uS, which is unacceptable. If I change ATDCTL3 to 0x08, only channel 0 will convert at ~7 uS, but I get nothing on the other channels. I've tried about all the different combinations of settings I can think of to solve this but so far no joy. Any suggestions would be appreciated. Regards, Robert Re: MC9S12C64 ADC question Hi Daniel, Oh my, another stupid error on my part. I changed ATDCTL3 to 0x08 but now my program just does the conversion for channel 0 then stalls at line 268, waiting for the conversion complete flag. There must be something else involved as well. Regards, Robert Re: MC9S12C64 ADC question Hi Robert, It should be 0x08 for 1 conversion though. Re: MC9S12C64 ADC question Hi Daniel, Thanks so much for your response. Indeed, that was a typo error on my part. I changed to ATDCTL3 = 0x10. Now the program hangs at line 275. brclr ATDSTAT1,#%00000100*. The conversion complete flag for channel 2 doesn't seem to be setting for some reason. Regards, Robert Re: MC9S12C64 ADC question Hi @roberthiebert, I just briefly checked the code, it seems you selected 8 conversions in a sequence. movb #$00,ATDCTL3 ; %00010000, 1 conversion ATDCTL3 = 0x00
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Convert Raw File to Jpeg( in i.MX8MP). My purpose is to convert Raw File to Jpeg in i.MX8MP. I am using encoder_test in imx-test-lf-5.15.32_2.0.0. There is no JPEG in mxc_isi_out_format(in kernel isi), so the following error occurs. "isi-m2m 32e00000.isi:m2m_device: mxc_isi_m2m_s_fmt_vid_cap, format is not support!" Is it possible to fix the problem? Or should I use another method? Re: Convert Raw File to Jpeg( in i.MX8MP). current imx8mp HW doesn't have such convert function, customer needs do it by their own SW
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[S32DS for Platform v3.5] How to erase a specific area by P&E debugger Hello team, Can you please explain how to erase the specific area (i.e. 0x10000000--0x1001FFFF) in the S32DS v3.5 by a P&E debugger? Best regards, James Re: [S32DS for Platform v3.5] How to erase a specific area by P&E debugger Hi Julián, Thank you for your answer. Best regards, James Re: [S32DS for Platform v3.5] How to erase a specific area by P&E debugger Hi  @james-lee, Unfortunately, there is still no support for erase option in P&E plugin. The workaround is to upload an empty binary file, as discussed in this community post: How to Erase Flash with S32DS, PEMICRO and MPC5777M - NXP Community (and this HOWTO as well: HOWTO: MPC5777C - Low/Mid Flash block erase via PE Micro - NXP Community) or to use external tools as discussed in this other post: how to erase the whole d-flash every time with PE micro - NXP Community There is also the Non-Volatile Memory Preservation option: Solved: Debug interface without erasing memory - NXP Community Best regards, Julián 
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I want to speed up jpeg decoding in i.MX RT Hi community. I need faster JPEG decoding on i.MX RT1170 EVK. I measured the jpeg decoding time of the sample software sd_jpeg_cm7. It uses 23msec to decode a 480x272 jpeg image, but I would like to speed this up. The request requires about a 3x speedup. Do you have any ideas? Best regards. Re: I want to speed up jpeg decoding in i.MX RT Hi @Ryo_Aoki ,   Thank you for your interest in the NXP MIMXRT product, I would like to provide service for you.   About the decoding, you can refer to this application note: https://www.nxp.com/docs/en/application-note/AN12562.pdf It contains some performance information.   So,if you want to speed up, I think, you can copy the code to the internal TCM or OCRAM, it will faster than the external flash running result. Wish it helps you! If you still have question about it, please kindly let me know. Best Regards, Kerry
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Pythonコードを暗号化して、ドアコントローラーシステムのリレーを安全に制御するにはどうすればよいですか? ドアコントローラーのリレーを切り替える役割を担うPythonスクリプトを暗号化する方法を提案してください。目標は、スクリプトのロジックを保護し、不正アクセスや改ざんを防ぎ、許可されたユーザーまたはシステムのみがリレーを制御できるようにすることです。焦点は、特にアクセス制御の自動リレーカテゴリで使用されるドアのリレー制御システムとインターフェースするコードを保護することです。スペックをご確認ください。 NFC制御マシンアクセス  Re:Pythonコードを暗号化して、ドアコントローラーシステムのリレーを安全に制御するにはどうすればよいですか? K64120を使用しています
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rpmsg-lite porting on our MCU(RISC-V platform ) hello,           I have a question about rpmsg-lite porting: Is it possible to use rpmsg-lite to encapsulate the mailbox as shared memory? That is, if there is only a small amount of data (e.g. less than 256 bytes), the mailbox will be used as shared memory to transfer the data, and if the data is larger than 256 bytes, it will still use the original shared memory used by rpmsg-lite, but it will still use the original API interface to initialize, create endpoints, and send the data (which may involve modifying the code). Is this approach feasible? #rpmsg-lite #FDRM-MCXN947SDK  Core and Memory FRDM-Training Re: rpmsg-lite porting on our MCU(RISC-V platform ) hi,         Thanks. In the demo of multicore rpmsg-lite pingpong communication using the SDK for the FRDM-MCXN947 board, I found that after the master core bootstraps the remote core to start, the remote core does rpmsg_lite_remote_init() first, then notifies the master core, and then the remote core waits for connection (rpmsg_lite_wait_for_ link_up()). During this time the master core waits (while()). After the master core is initialized rpmsg_lite_master_init(), the remote core makes the connection and creates the endpoint, then notifies the master that it is ready to send data. In use, I commented out the notification as well as the wait code and found that the master and remote cores can also link-up and communicate, what is the reason for this? Is it because the master system clock is slower than the remote ?         In addition, I would like to ask, if our MCU does not have such a notification mechanism, how to ensure that the master and slave cores are link-up and can communicate? Thanks & Regards yzs Re: rpmsg-lite porting on our MCU(RISC-V platform ) Hi @yzs  Yes, i think your approach is feasible. The buffer address (desc.addr) in a Virtio ring (vring) can point to a different memory region, such as a mailbox, while the desc, avail, and used structures remain in shared memory. BR Harry Re: rpmsg-lite porting on our MCU(RISC-V platform ) Hi, @Harry_Zhang         Thanks for answering question. My idea is to modify to point the buffer address of desc.addr to mailbox, but desc, avail, used in vring are still maintained in shared memory, is this possible? Because considering the limited space in mailbox, just 256 Bytes. Thanks & Regards yzs Re: rpmsg-lite porting on our MCU(RISC-V platform ) Hi @yzs  Yes, your approach is indeed feasible, and it’s possible to modify the rpmsg-lite framework to utilize the mailbox as shared memory for small data transfers, while still falling back to traditional shared memory for larger transfers. BR Harry
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sCheck 之后需要再次进行哪些初始化 你好,我发现在 s32k312 上执行 sCheck 之后必须再次调用 Platform_Init(),否则 intm 可能无法工作。我认为 sCheck 可能会更改检查的一些设置并保持不变。我是否应该调用所有初始化函数来重置外围设备?如Mcu_Init()、Mcl_Init()、Rm_Init()。
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Pegoda Smart Card Reader Based on PN7642 Hi Sir, Can we have a firmware source code of Pegoda Smart Card Reader? We'd like to design a reader based Pegoda Smart Card Reader. Also, is the SDK including driver, firmware update utility, programing interface guidance and sample code ready? The operating systems are WIndows and Linux. Thanks, Eric Fu Re: Pegoda Smart Card Reader Based on PN7642 Hi Kelly, Thank you. How about the shared SDK and firmware for PN7642 itself(not talking about the Pegoda)? We want to use the shared SDK and firmware and want to make sure if the USB is included. I guess yes after I check there is a CCID related example code in the share SDK. Please help confirm that. Thanks, Eric Fu Re: Pegoda Smart Card Reader Based on PN7642 About the CCID driver for Linux that can be supported by PN7642, can you share the file and link? Ans: The CCID driver under Linux is standard and does not need to be provided separately. You can install it yourself. Re: Pegoda Smart Card Reader Based on PN7642 Hello @Eric12285  PN7642 is an NFC forum certified solution. May I check if the USB interface is included in the certified configuration? And does the shared firmware on the website cover this? Ans: Pegoda 3 is NFC Forum certified, Pegoda3 is a complete standalone product, USB is included in it. Re: Pegoda Smart Card Reader Based on PN7642 Sorry, correct my questions. PN7642 is an NFC forum certified solution. May I check if the USB interface is included in the certified configuration? And does the shared firmware on the website cover this? About the CCID driver for Linux that can be supported by PN7642, can you share the file and link? Thanks, Eric Fu Re: Pegoda Smart Card Reader Based on PN7642 Thanks, Kelly PN7642 is an NFC forum certified solution. May I check if the USB interface is included in the certified configuration? And does the shared firmware on the website cover this? About the CCID interface protocol, does the share firmware cover this for both Windows and Linux? Thanks, Eric Fu Re: Pegoda Smart Card Reader Based on PN7642 Hello @Eric12285  Firmware source code of Pegoda Smart Card Reader should be not available for the user. But PN7642 SDK is open source, you can download on the product page.  Single-Chip Solution with High-Performance NFC Reader, Customizable MCU and Security Toolbox | NXP Semiconductors
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[Security] CSEC with keys Dear NXPs: IC:S32K142 I need to determine whether there is a key in NVM in a scenario, and I hope to get such judgment from the register, rather than the software recording the flag itself. How can I know from the CSEc register that the key has been imported? Re: [Security] CSEC with keys Hi @Gideon  CSEc does not provide information if a key is loaded or not. It's up to user to do the tracking of keys. The only indirect way I can see: try to use a key. If a key is not loaded yet, you should get ERC_KEY_EMPTY error. Regards, Lukas
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S32K3 FLASH write Hi, everyone I am using the first core of the S32K358 chip to program, I want to put the BOOTLOADER program in the memory of PFLASH0, and then put the APP program in the memory of PFLASH1, can the APP run properly? Re: S32K3 FLASH write Thank you for your reply. Re: S32K3 FLASH write It doesn't matter which master accesses a flash block. There's simple rule - if a block is being erased or programmed, it's now allowed to access this block. Only other blocks can be accessed at that time. Regards, Lukas Re: S32K3 FLASH write Hi,@lukaszadrapa, Thank you for your reply, I want to know if the first core of the S32K358 chip can read-while-write all four code? Re: S32K3 FLASH write Hi @DouDou1  Yes, there's no problem with this setup. There are four code flash blocks and read-while-write is supported between these blocks. Regards, Lukas
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NX5P3090 FAULT pin voltage with Vin=0V Hello. I am using the NX5P3090 USB power switch and would like to pull the open-drain FAULT output to a 1.8V supply that can be present even if there is no input to the switch (Vin=0V). Will the presence of 1.8V at the FAULT pin (through a 47kohm pullup) when Vin=0V cause any undesirable behavior in the switch? I see that there is a 6V absolute limit on this pin but it isn't clear to me if this applies when Vin=0V. Thank you.  -Jason Re: NX5P3090 FAULT pin voltage with Vin=0V OK thank you.  -Jason Re: NX5P3090 FAULT pin voltage with Vin=0V Hi  1.8v pull up for this FAULT pin will be no problem without VIN.
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How can I allocate the whole Ethernet to the SRAM and my application to SDRAM? Hi, I'm trying to build an application that uses FreeRTOS, lwip stack, and mbedtls stack. I'm using the MIMXRT1064-EVK with version 2.15.000 of the SDK. I am assigning Heap, Stack, *(NonCacheable.init) and *(NonCacheable) to the SRAM_DTC. Also, my application requires a lot of working memory, so I allocated the Global data placement to the SDRAM. Naturally, the following settings have been completed to use the SDRAM. > add symbols : SKIP_SYSCLK_INIT and XIP_BOOT_HEADER_DCD_ENABLE=1 > modify ethernetif0_init() : SDK_ALIGN to AT_NONCACHEABLE_SECTION_ALIGN However, as mentioned in the post below, this setup is problematic because there are some troubles when the Ethernet tries to get some resources from the SDRAM. (the SDRAM as BOARD_SDRAM or NCACHE_REGION) https://community.nxp.com/t5/i-MX-Processors/iMXRT1024-Ethernet-MAC-not-transmitting-data/m-p/1770206/highlight/true#M216974 How can I allocate the whole Ethernet to the SRAM and my application to SDRAM? Also, is it okay to allocate the Ethernet resources to SRAM_OC? Thanks in advance. Re: How can I allocate the whole Ethernet to the SRAM and my application to SDRAM? To make Ethernet work with SDRAM, the following measures are required: The ENET_INT pin on the MIMXRT1064-EVK board is pulled up (R309) and down (R152). In this state, the GPIO1_Combined_0_15_IRQHandler() interrupt will occur at irregular intervals even if nothing is being done. If you remove R152, the sporadic GPIO1_Combined_0_15_IRQHandler() interrupts will no longer occur. And the GPIO1_Combined_0_15_IRQHandler() interrupt will only be raised if the Ethernet link is up or down. Re: How can I allocate the whole Ethernet to the SRAM and my application to SDRAM? > The variables in my communication application were assigned to SDRAM, but the communication stopped midway as before. The cause was that the stack size of my application task was insufficient. I was using event groups for event triggers in my application tasks. The data in the event group object was corrupted because the application's local array was redundantly allocated to the memory region referenced by the event group object. When the problem occurred, the Heap Usage (FreeRTOS) display showed that there was sufficient memory. Be careful with the stack size required by local variables. By modifying it, my application data related to IP communication was placed in SDRAM and it worked properly. Re: How can I allocate the whole Ethernet to the SRAM and my application to SDRAM? Thanks for your reply, Kerry when I commented out as per your instructions, it stopped at the Ethernet link up detection in the initial settings. Unfortunately, my problem could not be resolved. Re: How can I allocate the whole Ethernet to the SRAM and my application to SDRAM? Hi @atm2024 ,   As I know, if you put all the lwip to the SDRAM, some data need to use the none cache buffer, you can try to disable the cache on your side, whether it have any improvement or not?  in the  void BOARD_ConfigMPU(void) // SCB_EnableDCache(); // SCB_EnableICache(); Try it again.   If you still have question about it, please kindly let me know. Best Regards, Kerry Re: How can I allocate the whole Ethernet to the SRAM and my application to SDRAM? Thanks for the reply, Kerry The IDE I'm using is MXUXpresso IDE v11.9.0 [Build 2144]. This is the previous memory configuration. MCU settings > Memory detailsMCU settings > Memory details Managed Linker ScriptManaged Linker Script When the Global data placement was set to BOARD_SDRAM, the TLS communication stopped midway after repeating several times. So I set the Global data placement to SRAM_OC2. This is the current memory configuration. Managed Linker ScriptManaged Linker Script The Image built with this configuration has no SDRAM allocated. So I changed my application's send and receive buffers to global variables. And I specified __attribute__((section("SDRAM.bss"))) for those global variables. The variables in my communication application were assigned to SDRAM, but the communication stopped midway as before. Is it not possible to allocate not only the lwIP middleware but also my application data related to IP communication to SDRAM? I appreciate your help. Re: How can I allocate the whole Ethernet to the SRAM and my application to SDRAM? Hi @atm2024  Thank you for your interest in the NXP MIMXRT product, I would like to provide service for you. Now, which demo you are using in the SDK? This one? SDK_2_15_000_EVK-MIMXRT1064\boards\evkmimxrt1064\lwip_examples\lwip_httpssrv_mbedTLS\freertos You want to copy:Heap, Stack, *(NonCacheable.init) and *(NonCacheable) to the SRAM_DTC. This is easy, you just need to modify the related data aread to the DTCM. You want to generate your code in the SDRAM, and the data in the internal TCM or OCRAM. It's OK, but you need to make sure the current internal RAM is enough to put your related data. Please tell me which IDE you are using now? Then, I can help you to check the details. Please also tell me your current memory modification or configuration, that will also helps to me to check your situation. Please also tell me your test result. About your question: 1.How can I allocate the whole Ethernet to the SRAM and my application to SDRAM? =>Answer: change the app to internal SDRAM, I don't know which IDE you are using, if it is the mcuxpresso, you can check the linker to RAM. then in the memory, let the first memory as SDRAM. Then, to the stack, heap, *(NonCacheable.init) and *(NonCacheable), select the memory to the internal DTC, ITC. 2. Also, is it okay to allocate the Ethernet resources to SRAM_OC? =>Answer: If the OCRAM is large enough, then you can! Just need to check your code size, I am afraid it is not enough. Wish it helps you! Any updated information, please kindly let me know. Best Regards, Kerry
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i.MX Yocto Project User's Guide for Kirkstone yocto project release Dear Experts, I'm searching for the i.MX (i.MX6ULL) Yocto Project User's Guide for the Kirkstone release of the Yocto Project. Could someone kindly provide me with a link to download the aforementioned document? Thanks & regards, Ravikumar Re: i.MX Yocto Project User's Guide for Kirkstone yocto project release Hi @Chavira  Thanks for your information. Regards, Ravikumar  Re: i.MX Yocto Project User's Guide for Kirkstone yocto project release Hi @Embedded-world! Thank you for contacting NXP Support! You can download the documentation and pre-built images for our boards at the link below : https://www.nxp.com/design/design-center/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applications-processors:IMXLINUX Best Regards! Chavira
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如何在不连接开发板的情况下在 IDE 中运行“hello world”应用程序演示? 我是 NXP 主板的新手。 我安装了 MCUXpresso IDE,但现在我没有电路板。我安装了 SDK 并为主板创建了项目“hello world”。我建立了我的项目。如何在不连接开发板的情况下在 IDE 中运行“hello world”应用程序演示? 我可以在 IDE 中创建一个简单的 C/C++ 项目,构建并运行它吗? 回复:如何在不连接开发板的情况下在 IDE 中运行“hello world”应用程序演示? @Alex_Wang 我还有一个问题。我是否可以使用 MIMXRT1060-EVKB 在 tflm_cifar10 中运行 Opencv(我想在 Opencv 中使用一些调整大小的方法)。如果可以,请帮我配置它。谢谢。 回复:如何在不连接开发板的情况下在 IDE 中运行“hello world”应用程序演示? @Alex_Wang 更改内存映射后,错误不再发生。但模拟运行的时间更长,并没有输出任何东西。也许 Keil/MDK 中 MIMXRT-1060 EVKB 的模拟出了问题。 回复:如何在不连接开发板的情况下在 IDE 中运行“hello world”应用程序演示? @Alex_Wang 我遵循了您的指南,但是在使用模拟器调试时,出现了与“写入”权限相关的错误,如下所示。 *** 警告:使用 ARM Cortex-M4 模拟器。ARM Cortex-M7 特定功能未建模! 运行时代码大小限制:32K 加载“ram_0x1400_release\\hello_world.out” *** 错误 65:0xFFFFFFF4 处访问冲突:没有“写入”权限 我创建了 .ini文件来修复它在 0xFFFFFFF4 处的访问冲突 - Keil 论坛 - 支持论坛 - Arm 社区,但它不起作用。 你对我有什么建议吗?谢谢。 回复:如何在不连接开发板的情况下在 IDE 中运行“hello world”应用程序演示? @Alex_Wang 感谢您的快速回复。我将按照以下步骤检查它是否有效。 回复:如何在不连接开发板的情况下在 IDE 中运行“hello world”应用程序演示? @Alex_Wang 谢谢。您是否有关于在 Keil uvision 模拟器中运行 SDK 示例的教程? 据我了解,首先我需要下载适用于 Keil/MDK 的 MCUXpresso SDK,然后在 Keil(模拟器)中以调试模式运行。是吗? 回复:如何在不连接开发板的情况下在 IDE 中运行“hello world”应用程序演示? @Alex_Wang 我可能是看了MIMXRT1060-EVK 的教程,里面提到了 SW7。它使用 SW7 来设置启动模式。MIMXRT1060 -EVK 入门 | 恩智浦半导体 当然,谢谢。对于 MIMXRT1060-EVKB,我们需要使用 SW4。 回复:如何在不连接开发板的情况下在 IDE 中运行“hello world”应用程序演示? @Alex_Wang 感谢您提供详细信息。 回复:如何在不连接开发板的情况下在 IDE 中运行“hello world”应用程序演示? @Alex_Wang 谢谢。我们正在购买 Mimrt1060。我不记得该董事会的具体名称。我看到 mimrt1060 有两个版本:evk 和 evkb。MIMXRT1060-EVK / EVKB 之间有什么区别? 回复:如何在不连接开发板的情况下在 IDE 中运行“hello world”应用程序演示? @ErichStyger谢谢你的帮助。 @Alex_Wang谢谢。我还有一个问题。当我通过微型 USB 电缆将开发板连接到 PC 进行调试时(具体来说,我将运行 TF Lite 模型),我是否需要通过 DC IN 5V 为开发板供电?据我了解,调试时不需要通过 DC IN 5V 为电路板供电。它仅适用于电路板的独立工作。 回复:如何在不连接开发板的情况下在 IDE 中运行“hello world”应用程序演示? 是的,您可以这样做(但当然不能使用 NXP SDK,因为它适用于目标板/设备)。 您可以使用主机 GNU gcc 编译器/调试器(单独安装)并使用 IDE 构建和调试应用程序,就像任何其他 Eclipse 发行版一样。事实是,您不是在进行交叉开发,而是在进行原生开发。 对于“真正的嵌入式”开发,您需要一个开发板或模拟器,例如QUEMU( https://www.qemu.org/ )。
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HID(W):LIBUSB_ERROR_PIPE ----i.mx9352 A1 Hi, We am using i.mx9352 A1 model. we are unable to port the BSP file due to some error is coming as given below ======================================================= Success 0 Failure 1 1:2 1/ 1 [HID(W):LIBUSB_ERROR_PIPE ] SDPS: boot -f imx-boot-imx93evk-sd.bin-flash_singleboot ============================================================================= Could you provide solution for that error Thanks, Vivek Re: HID(W):LIBUSB_ERROR_PIPE ----i.mx9352 A1 Hi @Binh_Hoang  Kindly check the voltage as per Table 29 of NXP hardware design guide and check  the VDD_SOC_0V8 at SOC end. Thanks Re: HID(W):LIBUSB_ERROR_PIPE ----i.mx9352 A1 Hi @vivek5676, I'm facing the same issue. Could you please let me know which change is needed for this case? Please give me more details.  Thank you in advance, Binh Re: HID(W):LIBUSB_ERROR_PIPE ----i.mx9352 A1 My problem get resolved after changes done in hardware.  
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FXLS8967AF Datasheet error: SENS_CONFIG1 default value descriptions The current datasheet listed on the website is Rev 1.5 of Mar 11, 2022: https://www.nxp.com/products/sensors/accelerometers/2g-4g-8g-16g-low-power-12-bit-digital-accelerometer:FXLS8967AF Table 47 shows that the SENS_CONFIG1 register default value depends on the BT_MODE pin: This affects the FSR and ACTIVE fields. The Table 48 descriptions fail to mention this, and use inconsistent options for the 2 fields: The description of FSR uses the BT_MODE=VDD default value, 01; The description of ACTIVE uses the BT_MODE=GND default value, 0 Re: FXLS8967AF Datasheet error: SENS_CONFIG1 default value descriptions Hello andrewneil, I hope all is great with you. Thank you for using the NXP communities. Correct, I also think that Table 48 doesn't mention this. It is not clear. I just wanted to let you know that I have already shared your feedback with the corresponding team. Thank you very much for your comments. Regards, David
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Receive DMX512 on LPUART1 S32k146 Hi all, I'm trying to read DMX512 Messages with the LPUART1 (PTC8, PTC9) from the S32k146.  The data is generated by a Slesa-U9 and could be measured and decoded from the oszillator as UART. My problem is, that as GPIO I can receive the data, but as LPUART there is no data in the LPUART1->Data Register. So my question is, if there's any existing project for receiving DMX on a S32k microcontroller.  If not, can you please help me and find my mistake?  Best regards Sandra Re: Receive DMX512 on LPUART1 S32k146 Hi @12914A, Currently there are no DMX512 examples for the S32K1xx's devices. If no data is being received, make sure the LPUART module is being correctly configured for the DMX protocol, as start bits, parity, baud rate, stop bits, etc. You can find inside the AN5413: S32K1xx Series Cookbook an example application for UART over registers. This example performs a simple UART 9600 baud transfer to a COM port on a PC. You could try sending singular bytes to test communication. Best regards, Julián
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S32G274A FlexRay Nodes Not Coldstarting Hi there, I am trying to get 2x S32G274A boards to communicate with each other over their LLCE Flexray. I am using the LLCE Node1 and Node2 code from the examples and am able to get them to work with default network settings. However, when I change the setting to the settings of the FlexRay network I need to interface with, they don't get past their initialization and don't go into FR_POCSTATE_NORMAL_ACTIVE. Attached is the network settings I am trying to use. Further, their state reports that they are in FR_STARTUP_INTEGRATION_LISTEN, when I would expect them to be in one of the COLDSTART_* states. Much appreciate any help! David Network Settings I'm trying to Use: Re: S32G274A FlexRay Nodes Not Coldstarting Resolved. pKeySlotID can't be the same across nodes. Payload length of Individual Buffers and static slot paylength must match in configuration. Re: S32G274A FlexRay Nodes Not Coldstarting Hi, We might be misunderstanding the overall inquiry, if so, we do apologize. We understand that you are able to run the NXP example with the S32G no problem, but once you change the network settings, it fails, is this correct? Furthermore, we understand that if you adapt our network to the one already configured under Config Tools, you are able to run the example successfully, is this correct? If so, then we understand that there is a problem with the overall configuration, but not with the example itself nor S32G. Are you able to confirm that your network settings are working without the S32G?  As for sharing your settings, we understand that, if Config Tools is not generating an error, they are "correct". You need to pair correctly your nodes, since FlexRay is a more delicate communication protocol, in which your configurations need to be perfectly matched. Again, under the example and using only S32G we understand that you are seeing no problems. An additional note is that the FlexRay Host interface has the following compliance [Page 2628, S32G2 Reference Manual, Rev. 8, February 2024]: "The FlexRay communication controller implements the FlexRay Communications System Protocol Specification, Version 2.1 Rev A." Just to confirm that your other interface is also complaint. More information on regards of the available features (i.e. data rate) for the FlexRay controller under the S32G can be found under Chapter 56 FlexRay Communication Controller (FlexRay) [Page 2833, S32G2 Reference Manual, Rev. 8, February 2024] Please, let us know. Re: S32G274A FlexRay Nodes Not Coldstarting I should add, with the default network config, I can see bits on the bus directly after Fr_43_LLCE_StartCommunication(FrConf_FrController_FrController_0); when I start only 1 of the nodes. But with my new network config, this is not the case. Therefore, the FlexRay controller must not be starting its communication correctly even though it doesn't return an error.
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