S32K312 FlexCan的问题 亲爱的NXP社区工作人员你好，目前我想将S32K312的Flex CAN0配置为enhanced Rx FIFO和DMA接收CAN2.0和CANFD报文，我参考了社区中的所有示例，现在仍然存在发送正常，但是无法接收到消息的问题。能否麻烦您帮我查看一下我的初始化过程是否存在问题，以及中断回调函数是否正确配置呢？ Re: S32K312 FlexCan的问题 这些都是一致的，我试一下把源工程的其余模块一个个移植去正常运行的测试工程能不能找到问题。 Re: S32K312 FlexCan的问题 Hi@Django_007 排查下工程的一些选项，例如工程的编译优先级是不是一样的 Re: S32K312 FlexCan的问题 enhanced_test是我新建的测试工程。 Re: S32K312 FlexCan的问题 我将flexcan相关的代码和.mex的配置移植到一个新的工程之后却能正常运行，但是我检查了很多次这两个项目并没有什么不同，您有什么思路吗？ Re: S32K312 FlexCan的问题 好的我再创建一个工程尝试一下 Re: S32K312 FlexCan的问题 Hi@Django_007 好吧，我今天来不及帮你处理了，明天我再帮你看下。 或者我建议你创建一个新的工程，对照链接中的demo重新做个测试demo，看看是不是有什么地方自己的工程中疏漏了，如果还没有成功，你再把你创建的这个新的demo发给我，我帮你看下。 Re: S32K312 FlexCan的问题 还是没有解决，刚刚我测试时没注意发送的是MB配置接受的ID，enhanced RxFIFO配置接受的ID的CAN报文还是无法接收。 Re: S32K312 FlexCan的问题 Hi@Django_007 解决了？什么问题？ Re: S32K312 FlexCan的问题 Hi@Django_007 我测试了你的代码，总体是没有任何问题的。你的代码里面mask是使用“Individual Mask Type.” 我简单的帮你改了下方便你测试。 1.0xface，拓展帧 2.0x01,标准帧，这里我将mask设置为全1, 3.新增0x12,标准帧 中断里面你需要为每个MB重新调用FlexCAN_Ip_Receive，否则你无法启动下一次接收的 附件是我测试的截图，关于mask的设置原理参考下面我之前写的文档，自己去深入的研究下 https://community.nxp.com/t5/S32K-Knowledge-Base/S32K1xx-FlexCAN-Mask-Setting-Demo/ta-p/1519753 Re: S32K312 FlexCan的问题 抱歉，上传工程花费了一些时间，非常感谢您能抽空解决我的问题。 Re: S32K312 FlexCan的问题 Hi@Django_007 完整的测试工程贴上来，你提供的这两个文档我也没看到你使能中断之类的 Re: S32K312 FlexCan的问题 对不起，我已经被这个问题困扰一周了，这些示例我都有参考，并且在debug配置过程中返回的结果都是正常的，但是我发送can报文给MCU却无法接收到消息。 Re: S32K312 FlexCan的问题 Hi@Django_007 在这个S32K论坛里面，类似的问题至少有几十个，你自己下次多尝试搜索一下。 这里我给出我们knowledge base上的demo,你可以去参考（其实还可以搜到很多类似的） https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-FlexCAN-Ip-TX-RX-EnhanceRXFIFO-DMA-test-S32DS3-5/ta-p/2015832

刷新 BSP42 映像后，S32G499ARDB3 上未检测到以太网接口 大家好， 在构建并刷新BSP42映像后，我遇到了S32G499ARDB3板上的以太网接口问题。以下是问题的详细信息： 硬件设置： 主板：S32G499ARDB3 物理连接：主板通过以太网电缆连接到路由器，并且主板上的以太网LED亮起。 问题描述： eth0 未检测到链接。 没有接口 /etc/network中的文件 目录。 网络不可达，并且没有为主板分配 IP 地址。 采取的步骤： 成功构建并刷新 BSP42 图像。 验证物理以太网连接（电缆和路由器）。 检查eth0是否存在 使用命令 ifconfig 查看网卡，发现有 eth0 但是没有分配 ip 问题： 在刷新 BSP42 映像之后或之前，是否需要任何其他配置来启用以太网接口？ 是否有特定的程序来生成或配置/etc/network/interface S32G499ARDB3 板的文件？ 该主板上是否存在任何已知问题或以太网连接解决方法？ 提前致谢，如有任何帮助，我们将不胜感激

Ethernet Interface Not Detected on S32G499ARDB3 After Flashing BSP42 Image Hello all,  I am encountering an issue with the Ethernet interface on the S32G499ARDB3 board after building and flashing the BSP42 image. Below are the details of the problem: Hardware Setup: Board: S32G499ARDB3 Physical Connection: The board is connected to a router via an Ethernet cable, and the Ethernet LED on the board is illuminated. Issue Description: The eth0 link is not being detected. There is no interfaces file in /etc/network directory. The network is unreachable, and no IP address is assigned to the board. Steps Taken: Built and flashed the BSP42 image successfully. Verified the physical Ethernet connection (cable and router). Checked for the presence of the eth0 interface using command ifconfig , and found the eth0 but not assigned ip Questions: Are there any additional configurations required to enable the Ethernet interface after or before flashing the BSP42 image? Is there a specific procedure to generate or configure the /etc/network/interface file for the S32G499ARDB3 board? Are there any known issues or workarounds Ethernet connectivity on this board? Thanks in advance, and any help will be appreciated Re: Ethernet Interface Not Detected on S32G499ARDB3 After Flashing BSP42 Image Hi @MohamedAbdelslam, Please refer to the Linux BSP 42.0 User Manual for S32G3 platforms at chapter 7 I recommend you read the sections: 7.1 Prerequisites 7.2 Ethernet Hardware Support on S32G3 7.3.3 Linux Ethernet support  7.3.4 Build by Auto Linux BSP Let me know if you have any questions about the content.

LX2160ARDB-REV2 は無効な設定から起動します ,xmap 7 こんにちはチーム xspi でボードを起動したいのですが、「Board: LX2160AE Rev2.0-RDB,ボードバージョン:O、無効な設定から起動、xmap:ログに7インチ。 NOTICE: BL2: v2.4(release): NOTICE: BL2: Built : 10:26:27, Sep 3 2024 NOTICE: UDIMM CBD32D4S2S8MR-8 NOTICE: DDR PMU Hardware version-0x1210 NOTICE: DDR PMU Firmware vision-0x1001 (vA-2019.04) NOTICE: DDR4 UDIMM with 1-rank 64-bit bus (x8) NOTICE: 8 GB DDR4, 64-bit, CL=22, ECC off NOTICE: BL2: Booting BL31 NOTICE: BL31: v2.4(release): NOTICE: BL31: Built : 10:26:26, Sep 3 2024 NOTICE: Welcome to lx2160ardb BL31 Phase U-Boot 2021.04 (Sep 03 2024 - 10:26:20 +0800) SoC: LX2160AE Rev2.0 (0x87361020) Clock Configuration: CPU0(A72):2200 MHz CPU1(A72):2200 MHz CPU2(A72):2200 MHz CPU3(A72):2200 MHz CPU4(A72):2200 MHz CPU5(A72):2200 MHz CPU6(A72):2200 MHz CPU7(A72):2200 MHz CPU8(A72):2200 MHz CPU9(A72):2200 MHz CPU10(A72):2200 MHz CPU11(A72):2200 MHz CPU12(A72):2200 MHz CPU13(A72):2200 MHz CPU14(A72):2200 MHz CPU15(A72):2200 MHz Bus: 750 MHz DDR: 3200 MT/s Reset Configuration Word (RCW): 00000000: 5883833c 24580058 00000000 00000000 00000010: 00000000 0c010000 00000000 00000000 00000020: 01e001a0 00002580 00000000 1800064e 00000030: 08250400 00000001 00000000 00000000 00000040: 00000000 00000000 00000000 00000000 00000050: 00000000 00000000 00000000 00000000 00000060: 00000000 00000000 00027088 00000000 00000070: 00a80031 00150032 Model: NXP Layerscape LX2160ARDB Board Board: LX2160AE Rev2.0-RDB, Board version: O, boot from invalid setting, xmap: 7 FPGA: v255.255 SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz VID: Bus 0 has no device with address 0x63 VID: Couldn't read sensor abort VID adjustment core voltage not adjusted DRAM: 7.9 GiB DDR 7.9 GiB (DDR4, 64-bit, CL=22, ECC off) PCA: failed to select proper channel Using SERDES1 Protocol: 8 (0x8) Using SERDES2 Protocol: 5 (0x5) Using SERDES3 Protocol: 0 (0x0) SERDES3[PRTCL] = 0x0 is not valid PCIe1: pcie@3400000 disabled PCIe2: pcie@3500000 disabled PCIe3: pcie@3600000 Root Complex: no link PCIe4: pcie@3700000 disabled PCIe5: pcie@3800000 disabled PCIe6: pcie@3900000 disabled WDT: Started with servicing (30s timeout) MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from SPIFlash... SF: Detected mx25um51245g with page size 256 Bytes, erase size 16 KiB, total 64 MiB *** Warning - bad CRC, using default environment EEPROM: Invalid ID (ff ff ff ff) In: serial_pl01x Out: serial_pl01x Err: serial_pl01x SEC0: RNG instantiated Net: Warning: DPMAC3@usxgmii (eth0) using random MAC address - 5e:df:5d:a5:7a:98 Warning: DPMAC4@usxgmii (eth1) using random MAC address - a2:e1:07:33:60:c7 Warning: DPMAC5@25g-aui (eth2) using random MAC address - 5a:a6:ad:bc:e1:7e Warning: DPMAC6@usxgmii (eth3) using random MAC address - fa:e3:56:29:f3:12 Warning: DPMAC17@rgmii-id (eth4) using random MAC address - 92:c0:55:9f:c2:a0 Warning: DPMAC18@rgmii-id (eth5) using random MAC address - ce:ea:c1:c9:d2:3d eth0: DPMAC3@usxgmii, eth1: DPMAC4@usxgmii, eth2: DPMAC5@25g-aui, eth3: DPMAC6@usxgmii, eth4: DPMAC17@rgmii-id, eth5: DPMAC18@rgmii-id SF: Detected mx25um51245g with page size 256 Bytes, erase size 16 KiB, total 64 MiB device 0 offset 0x640000, size 0x80000 SF: 524288 bytes @ 0x640000 Read: OK device 0 offset 0xa00000, size 0x300000 SF: 3145728 bytes @ 0xa00000 Read: OK device 0 offset 0xe00000, size 0x100000 SF: 1048576 bytes @ 0xe00000 Read: OK crc32+ fsl-mc: Booting Management Complex ... SUCCESS fsl-mc: Management Complex booted (version: 10.30.0, boot status: 0x1) Hit any key to stop autoboot: 0 SF: Detected mx25um51245g with page size 256 Bytes, erase size 16 KiB, total 64 MiB device 0 offset 0x6c0000, size 0x40000 SF: 262144 bytes @ 0x6c0000 Read: OK device 0 offset 0xd00000, size 0x100000 SF: 1048576 bytes @ 0xd00000 Read: OK starting USB... Bus usb3@3100000: Register 200017f NbrPorts 2 Starting the controller USB XHCI 1.00 Bus usb3@3110000: Register 200017f NbrPorts 2 Starting the controller USB XHCI 1.00 scanning bus usb3@3100000 for devices... 1 USB Device(s) found scanning bus usb3@3110000 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found Device 0: unknown device MMC: no card present switch to partitions #0, OK mmc1(part 0) is current device Scanning mmc 1:1... Found U-Boot script /lx2160ardb_boot.scr 1372 bytes read in 5 ms (267.6 KiB/s) ## Executing script at 80000000 30659072 bytes read in 110 ms (265.8 MiB/s) 49935 bytes read in 6 ms (7.9 MiB/s) ## Flattened Device Tree blob at 90000000 Booting using the fdt blob at 0x90000000 Loading Device Tree to 000000009fff0000, end 000000009ffff30e ... OK fsl-mc: Deploying data path layout ... WARNING: Firmware returned an error (GSR: 0x3f) Starting kernel ... どうすればこの問題を解決できますか? ありがとうございます Re: LX2160ARDB-REV2 は無効な設定から起動します、xmap 7 board/freescale/lx2160a/lx2160a.c の次のソース コードを参照してください。 sw = QIXIS_READ(アーチ); printf("ボード バージョン: %c, ブート元 ", (sw & 0xf) - 1 + 'A'); if (src== BOOT_SOURCE_SD_MMC) { puts("SD\n"); } else if (src== BOOT_SOURCE_SD_MMC2) { puts("eMMC\n"); } その他 { sw = QIXIS_READ(brdcfg[0]); sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK; スイッチ(SW){ ケース0: ケース4: puts("FlexSPI DEV#0\n"); 壊す; ケース1: puts("FlexSPI DEV#1\n"); 壊す; ケース2: ケース3: puts("FlexSPI EMU\n"); 壊す; デフォルト： printf("無効な設定、xmap: %d\n", sw); 壊す; } これは、CPLD レジスタ BRDCFG0 が正しく読み取られなかったことを意味します。 「3.44」の項を参照してください。Board Configuration 0 (BRDCFG0)」と記載されています。

LX2160ARDB-REV2 从无效设置启动，xmap 7 大家好 我想通过 xspi 启动主板，但我看到“主板：LX2160AE Rev2.0-RDB，主板版本：O，从无效设置启动，日志中显示“xmap：7”。 NOTICE: BL2: v2.4(release): NOTICE: BL2: Built : 10:26:27, Sep 3 2024 NOTICE: UDIMM CBD32D4S2S8MR-8 NOTICE: DDR PMU Hardware version-0x1210 NOTICE: DDR PMU Firmware vision-0x1001 (vA-2019.04) NOTICE: DDR4 UDIMM with 1-rank 64-bit bus (x8) NOTICE: 8 GB DDR4, 64-bit, CL=22, ECC off NOTICE: BL2: Booting BL31 NOTICE: BL31: v2.4(release): NOTICE: BL31: Built : 10:26:26, Sep 3 2024 NOTICE: Welcome to lx2160ardb BL31 Phase U-Boot 2021.04 (Sep 03 2024 - 10:26:20 +0800) SoC: LX2160AE Rev2.0 (0x87361020) Clock Configuration: CPU0(A72):2200 MHz CPU1(A72):2200 MHz CPU2(A72):2200 MHz CPU3(A72):2200 MHz CPU4(A72):2200 MHz CPU5(A72):2200 MHz CPU6(A72):2200 MHz CPU7(A72):2200 MHz CPU8(A72):2200 MHz CPU9(A72):2200 MHz CPU10(A72):2200 MHz CPU11(A72):2200 MHz CPU12(A72):2200 MHz CPU13(A72):2200 MHz CPU14(A72):2200 MHz CPU15(A72):2200 MHz Bus: 750 MHz DDR: 3200 MT/s Reset Configuration Word (RCW): 00000000: 5883833c 24580058 00000000 00000000 00000010: 00000000 0c010000 00000000 00000000 00000020: 01e001a0 00002580 00000000 1800064e 00000030: 08250400 00000001 00000000 00000000 00000040: 00000000 00000000 00000000 00000000 00000050: 00000000 00000000 00000000 00000000 00000060: 00000000 00000000 00027088 00000000 00000070: 00a80031 00150032 Model: NXP Layerscape LX2160ARDB Board Board: LX2160AE Rev2.0-RDB, Board version: O, boot from invalid setting, xmap: 7 FPGA: v255.255 SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz VID: Bus 0 has no device with address 0x63 VID: Couldn't read sensor abort VID adjustment core voltage not adjusted DRAM: 7.9 GiB DDR 7.9 GiB (DDR4, 64-bit, CL=22, ECC off) PCA: failed to select proper channel Using SERDES1 Protocol: 8 (0x8) Using SERDES2 Protocol: 5 (0x5) Using SERDES3 Protocol: 0 (0x0) SERDES3[PRTCL] = 0x0 is not valid PCIe1: pcie@3400000 disabled PCIe2: pcie@3500000 disabled PCIe3: pcie@3600000 Root Complex: no link PCIe4: pcie@3700000 disabled PCIe5: pcie@3800000 disabled PCIe6: pcie@3900000 disabled WDT: Started with servicing (30s timeout) MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from SPIFlash... SF: Detected mx25um51245g with page size 256 Bytes, erase size 16 KiB, total 64 MiB *** Warning - bad CRC, using default environment EEPROM: Invalid ID (ff ff ff ff) In: serial_pl01x Out: serial_pl01x Err: serial_pl01x SEC0: RNG instantiated Net: Warning: DPMAC3@usxgmii (eth0) using random MAC address - 5e:df:5d:a5:7a:98 Warning: DPMAC4@usxgmii (eth1) using random MAC address - a2:e1:07:33:60:c7 Warning: DPMAC5@25g-aui (eth2) using random MAC address - 5a:a6:ad:bc:e1:7e Warning: DPMAC6@usxgmii (eth3) using random MAC address - fa:e3:56:29:f3:12 Warning: DPMAC17@rgmii-id (eth4) using random MAC address - 92:c0:55:9f:c2:a0 Warning: DPMAC18@rgmii-id (eth5) using random MAC address - ce:ea:c1:c9:d2:3d eth0: DPMAC3@usxgmii, eth1: DPMAC4@usxgmii, eth2: DPMAC5@25g-aui, eth3: DPMAC6@usxgmii, eth4: DPMAC17@rgmii-id, eth5: DPMAC18@rgmii-id SF: Detected mx25um51245g with page size 256 Bytes, erase size 16 KiB, total 64 MiB device 0 offset 0x640000, size 0x80000 SF: 524288 bytes @ 0x640000 Read: OK device 0 offset 0xa00000, size 0x300000 SF: 3145728 bytes @ 0xa00000 Read: OK device 0 offset 0xe00000, size 0x100000 SF: 1048576 bytes @ 0xe00000 Read: OK crc32+ fsl-mc: Booting Management Complex ... SUCCESS fsl-mc: Management Complex booted (version: 10.30.0, boot status: 0x1) Hit any key to stop autoboot: 0 SF: Detected mx25um51245g with page size 256 Bytes, erase size 16 KiB, total 64 MiB device 0 offset 0x6c0000, size 0x40000 SF: 262144 bytes @ 0x6c0000 Read: OK device 0 offset 0xd00000, size 0x100000 SF: 1048576 bytes @ 0xd00000 Read: OK starting USB... Bus usb3@3100000: Register 200017f NbrPorts 2 Starting the controller USB XHCI 1.00 Bus usb3@3110000: Register 200017f NbrPorts 2 Starting the controller USB XHCI 1.00 scanning bus usb3@3100000 for devices... 1 USB Device(s) found scanning bus usb3@3110000 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found Device 0: unknown device MMC: no card present switch to partitions #0, OK mmc1(part 0) is current device Scanning mmc 1:1... Found U-Boot script /lx2160ardb_boot.scr 1372 bytes read in 5 ms (267.6 KiB/s) ## Executing script at 80000000 30659072 bytes read in 110 ms (265.8 MiB/s) 49935 bytes read in 6 ms (7.9 MiB/s) ## Flattened Device Tree blob at 90000000 Booting using the fdt blob at 0x90000000 Loading Device Tree to 000000009fff0000, end 000000009ffff30e ... OK fsl-mc: Deploying data path layout ... WARNING: Firmware returned an error (GSR: 0x3f) Starting kernel ... 我该如何解决这个问题？ 谢谢！ 回复：LX2160ARDB-REV2 从无效设置启动，xmap 7 请参考 board/freescale/lx2160a/lx2160a.c 中的以下源代码 sw = QIXIS_READ(arch); printf("主板版本: %c, 从 ... 启动, (sw & 0xf) - 1 + 'A'); 如果（src == BOOT_SOURCE_SD_MMC）{ 放入(“SD\n”); } 否则，如果（src== BOOT_SOURCE_SD_MMC2）{ 放入（“eMMC \n”）； } 别的 { sw = QIXIS_READ(brdcfg[0]); sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK; 开关（sw）{ 案例 0： 案例 4： 放入（“FlexSPI DEV#0\n”）； 休息; 情况 1： 放入（“FlexSPI DEV#1\n”）； 休息; 情况 2： 情况 3： 放入（“FlexSPI EMU \n”）； 休息; 默认： printf("无效设置，xmap: %d\n", sw); 休息; } 这意味着 CPLD 寄存器 BRDCFG0 未被正确读取。 请参阅“3.44请参阅附件中的“主板配置 0 (BRDCFG0)”。

LX2160ARDB-REV2 boot from Invalid setting ,xmap 7 Hi Team I want to start the Board through xspi, but I see "Board: LX2160AE Rev2.0-RDB, Board version: O, boot from invalid setting, xmap: 7" in the log. NOTICE: BL2: v2.4(release): NOTICE: BL2: Built : 10:26:27, Sep 3 2024 NOTICE: UDIMM CBD32D4S2S8MR-8 NOTICE: DDR PMU Hardware version-0x1210 NOTICE: DDR PMU Firmware vision-0x1001 (vA-2019.04) NOTICE: DDR4 UDIMM with 1-rank 64-bit bus (x8) NOTICE: 8 GB DDR4, 64-bit, CL=22, ECC off NOTICE: BL2: Booting BL31 NOTICE: BL31: v2.4(release): NOTICE: BL31: Built : 10:26:26, Sep 3 2024 NOTICE: Welcome to lx2160ardb BL31 Phase U-Boot 2021.04 (Sep 03 2024 - 10:26:20 +0800) SoC: LX2160AE Rev2.0 (0x87361020) Clock Configuration: CPU0(A72):2200 MHz CPU1(A72):2200 MHz CPU2(A72):2200 MHz CPU3(A72):2200 MHz CPU4(A72):2200 MHz CPU5(A72):2200 MHz CPU6(A72):2200 MHz CPU7(A72):2200 MHz CPU8(A72):2200 MHz CPU9(A72):2200 MHz CPU10(A72):2200 MHz CPU11(A72):2200 MHz CPU12(A72):2200 MHz CPU13(A72):2200 MHz CPU14(A72):2200 MHz CPU15(A72):2200 MHz Bus: 750 MHz DDR: 3200 MT/s Reset Configuration Word (RCW): 00000000: 5883833c 24580058 00000000 00000000 00000010: 00000000 0c010000 00000000 00000000 00000020: 01e001a0 00002580 00000000 1800064e 00000030: 08250400 00000001 00000000 00000000 00000040: 00000000 00000000 00000000 00000000 00000050: 00000000 00000000 00000000 00000000 00000060: 00000000 00000000 00027088 00000000 00000070: 00a80031 00150032 Model: NXP Layerscape LX2160ARDB Board Board: LX2160AE Rev2.0-RDB, Board version: O, boot from invalid setting, xmap: 7 FPGA: v255.255 SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz VID: Bus 0 has no device with address 0x63 VID: Couldn't read sensor abort VID adjustment core voltage not adjusted DRAM: 7.9 GiB DDR 7.9 GiB (DDR4, 64-bit, CL=22, ECC off) PCA: failed to select proper channel Using SERDES1 Protocol: 8 (0x8) Using SERDES2 Protocol: 5 (0x5) Using SERDES3 Protocol: 0 (0x0) SERDES3[PRTCL] = 0x0 is not valid PCIe1: pcie@3400000 disabled PCIe2: pcie@3500000 disabled PCIe3: pcie@3600000 Root Complex: no link PCIe4: pcie@3700000 disabled PCIe5: pcie@3800000 disabled PCIe6: pcie@3900000 disabled WDT: Started with servicing (30s timeout) MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from SPIFlash... SF: Detected mx25um51245g with page size 256 Bytes, erase size 16 KiB, total 64 MiB *** Warning - bad CRC, using default environment EEPROM: Invalid ID (ff ff ff ff) In: serial_pl01x Out: serial_pl01x Err: serial_pl01x SEC0: RNG instantiated Net: Warning: DPMAC3@usxgmii (eth0) using random MAC address - 5e:df:5d:a5:7a:98 Warning: DPMAC4@usxgmii (eth1) using random MAC address - a2:e1:07:33:60:c7 Warning: DPMAC5@25g-aui (eth2) using random MAC address - 5a:a6:ad:bc:e1:7e Warning: DPMAC6@usxgmii (eth3) using random MAC address - fa:e3:56:29:f3:12 Warning: DPMAC17@rgmii-id (eth4) using random MAC address - 92:c0:55:9f:c2:a0 Warning: DPMAC18@rgmii-id (eth5) using random MAC address - ce:ea:c1:c9:d2:3d eth0: DPMAC3@usxgmii, eth1: DPMAC4@usxgmii, eth2: DPMAC5@25g-aui, eth3: DPMAC6@usxgmii, eth4: DPMAC17@rgmii-id, eth5: DPMAC18@rgmii-id SF: Detected mx25um51245g with page size 256 Bytes, erase size 16 KiB, total 64 MiB device 0 offset 0x640000, size 0x80000 SF: 524288 bytes @ 0x640000 Read: OK device 0 offset 0xa00000, size 0x300000 SF: 3145728 bytes @ 0xa00000 Read: OK device 0 offset 0xe00000, size 0x100000 SF: 1048576 bytes @ 0xe00000 Read: OK crc32+ fsl-mc: Booting Management Complex ... SUCCESS fsl-mc: Management Complex booted (version: 10.30.0, boot status: 0x1) Hit any key to stop autoboot: 0 SF: Detected mx25um51245g with page size 256 Bytes, erase size 16 KiB, total 64 MiB device 0 offset 0x6c0000, size 0x40000 SF: 262144 bytes @ 0x6c0000 Read: OK device 0 offset 0xd00000, size 0x100000 SF: 1048576 bytes @ 0xd00000 Read: OK starting USB... Bus usb3@3100000: Register 200017f NbrPorts 2 Starting the controller USB XHCI 1.00 Bus usb3@3110000: Register 200017f NbrPorts 2 Starting the controller USB XHCI 1.00 scanning bus usb3@3100000 for devices... 1 USB Device(s) found scanning bus usb3@3110000 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found Device 0: unknown device MMC: no card present switch to partitions #0, OK mmc1(part 0) is current device Scanning mmc 1:1... Found U-Boot script /lx2160ardb_boot.scr 1372 bytes read in 5 ms (267.6 KiB/s) ## Executing script at 80000000 30659072 bytes read in 110 ms (265.8 MiB/s) 49935 bytes read in 6 ms (7.9 MiB/s) ## Flattened Device Tree blob at 90000000 Booting using the fdt blob at 0x90000000 Loading Device Tree to 000000009fff0000, end 000000009ffff30e ... OK fsl-mc: Deploying data path layout ... WARNING: Firmware returned an error (GSR: 0x3f) Starting kernel ... How can I solve this problem? Thanks Re: LX2160ARDB-REV2 boot from Invalid setting ,xmap 7 Hi yipingwang  Thank you for your help. I don't know why the value read from the register BRDCFG0(050h) is 0xFF. Do you have any other suggestions to help me solve the problem? BR Re: LX2160ARDB-REV2 boot from Invalid setting ,xmap 7 Please refer to the following source code in board/freescale/lx2160a/lx2160a.c sw = QIXIS_READ(arch); printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A'); if (src== BOOT_SOURCE_SD_MMC) { puts("SD\n"); } else if (src== BOOT_SOURCE_SD_MMC2) { puts("eMMC\n"); } else { sw = QIXIS_READ(brdcfg[0]); sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK; switch (sw) { case 0: case 4: puts("FlexSPI DEV#0\n"); break; case 1: puts("FlexSPI DEV#1\n"); break; case 2: case 3: puts("FlexSPI EMU\n"); break; default: printf("invalid setting, xmap: %d\n", sw); break; } It means CPLD register BRDCFG0 wasn't read correctly. Please refer to section "3.44 Board Configuration 0 (BRDCFG0)" in the attached document.

FS2633 复位始终为低 亲爱的团队， 我们使用电源芯片MFS2633AMDE4ADR2为S32K396（BGA289）供电。LDO1为3.45V，LDO2为5V，Vpre为6V，但GPIO1为低，GPIO2为高，RESET引脚始终保持低。即使将 Debug 引脚连接到 VBOS（调试模式），RESET 引脚仍然保持低电平。可能是什么原因？ 回复：FS2633 复位始终为低 亲爱的， 非常感谢！ 根据推荐值，输入和输出电容设计是令人满意的。 按照您的第二个建议，从电路中的H桥芯片中移除负载。VLDO1恢复正常(3.3V)，并且重置功能也正常运行。 谢谢！！ 回复：FS2633 复位始终为低 谢谢！在调试模式下运行 FS26 也会影响 RESET 吗？我们测试了过压标志VLDO1，将其设置为1（过压），实际电压为3.46V。为什么不是3.3V，而且那么高呢？

About vdd5v_irq interrupt for imx28 SOC Hi All,   I want to know how can the vdd5v_irq interrupt be triggered.   We have some devices that are not working properly  in the field site. These devices all use the DC power supply. i.MX2x Re: About vdd5v_irq interrupt for imx28 SOC Hello, In the vdd5v_irq , the USB On the Go,  protect the whole micro for high voltage, we don;t have a test but it works. Rgards

EVK 无法运行到主代码，调试模式下出现堆栈溢出 我首先使用 RT685 EVK 板。我导入了SDK示例代码，代码构建成功。我使用 SEGGER J-Link 探针进行调试，程序闪存没有问题。但代码如下： 在地址“0x1c04a”处中断，没有可用的调试信息，或者在程序代码之外。 0001c04a: bn 0x1c04a 我不知道为什么？我在调试中暂停这个，堆栈使用情况显示为溢出。现在我无法采取下一步行动。谁能帮助我？非常感谢。 i.MX-RT600 回复： EVK cannot run to main code and stack overflow handed in debug mode 現在已經可以正常工作了, 原來是我下載了SDK_2_16_000_MIMXRT685-AUD-EVK.zip, 但是我的開發板是RT685-EVK, 我重新下載SDK_2_16_000_EVK-MIMXRT685.zip已可以正常工作, 謝謝NXP的支持與協助. ,

EVK は、デバッグ モードでメイン コードとスタック オーバーフローに実行できません まず、RT685 EVKボードを使用します。SDKのサンプルコードをインポートしましたが、コードは問題なくビルドされています。SEGGER J-Linkプローブとしてデバッグしますが、プログラムのフラッシュは問題ありません。しかし、コードは以下のようにハングインしました。 デバッグ情報がないアドレス "0x1c04a" でブレークするか、プログラム コードの外部でブレークします。 0001C04A: B.N 0x1c04a なぜかわかりません。デバッグでこれを一時停止すると、スタック使用量がオーバーフローとして表示されます。今、私は次のステップに進むことができません。誰が私を助けてくれますか?ありがとうございました。 i.MX-RT600 

EVK cannot run to main code and stack overflow handed in debug mode I firstly use RT685 EVK board. I imported the SDK example code, and the code is built ok. I debug as SEGGER J-Link probes, and program flash is no problem. But the code hanged in as below: Break at address "0x1c04a" with no debug information available, or outside of program code. 0001c04a: b.n 0x1c04a I don't know why that? I suspend this in debug, the stack usage is showed as Overflow. Now I cannot take the next step. Who can help me? Thank very much. i.MX-RT600 

BUG Report: endpoint indices used instead of endpoint IDs in JN5189DK6 ZCL OTA code The ZCL codes uses endpoint indices internally (index to psZCL_Common->psZCL_EndPointRecord) and maps between IDs provided on registration via eZCL_SearchForEPIndex and u8ZCL_GetEPIdFromIndex. The current ZCL OTA code mistakenly uses indices where IDs are expected in two locations. The problem this causes is hidden when endpoint IDs are continuous and begin at 1. Details: - SDK Version: 2.6.15 - JN5189DK6/middleware/wireless/zigbee/ZCL/Clusters/OTA/Source/OTA.c // // The u8SourceEndPointId > u8ZCL_GetNumberOfEndpointsRegistered // range check is incorrect and needs to be removed // PUBLIC teZCL_Status eOtaFindCluster( uint8 u8SourceEndPointId, tsZCL_EndPointDefinition **ppsEndPointDefinition, tsZCL_ClusterInstance **ppsClusterInstance, tsOTA_Common **ppsOTACustomDataStructure, bool_t bIsServer) { if(u8SourceEndPointId > u8ZCL_GetNumberOfEndpointsRegistered()) { return(E_ZCL_ERR_EP_RANGE); } // check EP is registered and cluster is present in the send device if(eZCL_SearchForEPentry(u8SourceEndPointId, ppsEndPointDefinition) != E_ZCL_SUCCESS) { return(E_ZCL_ERR_EP_RANGE); } if(eZCL_SearchForClusterEntry(u8SourceEndPointId, OTA_CLUSTER_ID, bIsServer, ppsClusterInstance) != E_ZCL_SUCCESS) { return(E_ZCL_ERR_CLUSTER_NOT_FOUND); } // initialise custom data pointer *ppsOTACustomDataStructure = (tsOTA_Common *)(*ppsClusterInstance)->pvEndPointCustomStructPtr; if(*ppsOTACustomDataStructure==NULL) { return(E_ZCL_ERR_PARAMETER_NULL); } return(E_ZCL_SUCCESS); } // // FIXED // PUBLIC teZCL_Status eOtaFindCluster( uint8 u8SourceEndPointId, tsZCL_EndPointDefinition **ppsEndPointDefinition, tsZCL_ClusterInstance **ppsClusterInstance, tsOTA_Common **ppsOTACustomDataStructure, bool_t bIsServer) { // check EP is registered and cluster is present in the send device if(eZCL_SearchForEPentry(u8SourceEndPointId, ppsEndPointDefinition) != E_ZCL_SUCCESS) { return(E_ZCL_ERR_EP_RANGE); } if(eZCL_SearchForClusterEntry(u8SourceEndPointId, OTA_CLUSTER_ID, bIsServer, ppsClusterInstance) != E_ZCL_SUCCESS) { return(E_ZCL_ERR_CLUSTER_NOT_FOUND); } // initialise custom data pointer *ppsOTACustomDataStructure = (tsOTA_Common *)(*ppsClusterInstance)->pvEndPointCustomStructPtr; if(*ppsOTACustomDataStructure==NULL) { return(E_ZCL_ERR_PARAMETER_NULL); } return(E_ZCL_SUCCESS); } and Re: BUG Report: endpoint indices used instead of endpoint IDs in JN5189DK6 ZCL OTA code Hello, Thank you for your feedback, I will let the responsible team know about this. Regards, Ana Sofia. Re: BUG Report: endpoint indices used instead of endpoint IDs in JN5189DK6 ZCL OTA code Here is the second item. The system says I've run out of time to edit the message, despite it being about 30 seconds: // // The *eOtaTimeUpdate* function expects an endpoint ID, not an index // PUBLIC void vOtaTimerClickCallback(tsZCL_CallBackEvent *psCallBackEvent) { #if (defined(OTA_SERVER) && defined(OTA_PAGE_REQUEST_SUPPORT)) || defined(OTA_CLIENT) int i; uint8 u8NumberOfendpoints; u8NumberOfendpoints = u8ZCL_GetNumberOfEndpointsRegistered(); // find price clusters on each EP - if any for(i=1; i<(u8NumberOfendpoints+1); i++) { // deliver time to any EP-server/client eOtaTimeUpdate(i, TRUE, psCallBackEvent); eOtaTimeUpdate(i, FALSE, psCallBackEvent); } #endif } // // FIXED // PUBLIC void vOtaTimerClickCallback(tsZCL_CallBackEvent *psCallBackEvent) { #if (defined(OTA_SERVER) && defined(OTA_PAGE_REQUEST_SUPPORT)) || defined(OTA_CLIENT) int i; uint8 u8NumberOfendpoints; u8NumberOfendpoints = u8ZCL_GetNumberOfEndpointsRegistered(); // find price clusters on each EP - if any for(i = 0; i < u8NumberOfendpoints; i++) { uint8_t u8EndpointId = u8ZCL_GetEPIdFromIndex(i); // deliver time to any EP-server/client eOtaTimeUpdate(u8EndpointId, TRUE, psCallBackEvent); eOtaTimeUpdate(u8EndpointId, FALSE, psCallBackEvent); } #endif }

バグレポート:JN5189DK6 ZCL OTAコードでエンドポイントIDの代わりにエンドポイントインデックスが使用される ZCL コードは、エンドポイント インデックスを内部的に使用し ( インデックスは psZCL_Common->psZCL_EndPointRecord)、 eZCL_SearchForEPIndex と u8ZCL_GetEPIdFromIndex による登録時に指定された ID 間でマップします。 現在の ZCL OTA コードでは、ID が 2 つの場所で予期されるインデックスが誤って使用されています。これが引き起こす問題は、エンドポイント ID が連続し、1 から始まる場合に隠されます。 細部： - SDK バージョン: 2.6.15 - JN5189DK6/middleware/wireless/zigbee/ZCL/Clusters/OTA/Source/OTA.c (英語) // // The u8SourceEndPointId > u8ZCL_GetNumberOfEndpointsRegistered // range check is incorrect and needs to be removed // PUBLIC teZCL_Status eOtaFindCluster( uint8 u8SourceEndPointId, tsZCL_EndPointDefinition **ppsEndPointDefinition, tsZCL_ClusterInstance **ppsClusterInstance, tsOTA_Common **ppsOTACustomDataStructure, bool_t bIsServer) { if(u8SourceEndPointId > u8ZCL_GetNumberOfEndpointsRegistered()) { return(E_ZCL_ERR_EP_RANGE); } // check EP is registered and cluster is present in the send device if(eZCL_SearchForEPentry(u8SourceEndPointId, ppsEndPointDefinition) != E_ZCL_SUCCESS) { return(E_ZCL_ERR_EP_RANGE); } if(eZCL_SearchForClusterEntry(u8SourceEndPointId, OTA_CLUSTER_ID, bIsServer, ppsClusterInstance) != E_ZCL_SUCCESS) { return(E_ZCL_ERR_CLUSTER_NOT_FOUND); } // initialise custom data pointer *ppsOTACustomDataStructure = (tsOTA_Common *)(*ppsClusterInstance)->pvEndPointCustomStructPtr; if(*ppsOTACustomDataStructure==NULL) { return(E_ZCL_ERR_PARAMETER_NULL); } return(E_ZCL_SUCCESS); } // // FIXED // PUBLIC teZCL_Status eOtaFindCluster( uint8 u8SourceEndPointId, tsZCL_EndPointDefinition **ppsEndPointDefinition, tsZCL_ClusterInstance **ppsClusterInstance, tsOTA_Common **ppsOTACustomDataStructure, bool_t bIsServer) { // check EP is registered and cluster is present in the send device if(eZCL_SearchForEPentry(u8SourceEndPointId, ppsEndPointDefinition) != E_ZCL_SUCCESS) { return(E_ZCL_ERR_EP_RANGE); } if(eZCL_SearchForClusterEntry(u8SourceEndPointId, OTA_CLUSTER_ID, bIsServer, ppsClusterInstance) != E_ZCL_SUCCESS) { return(E_ZCL_ERR_CLUSTER_NOT_FOUND); } // initialise custom data pointer *ppsOTACustomDataStructure = (tsOTA_Common *)(*ppsClusterInstance)->pvEndPointCustomStructPtr; if(*ppsOTACustomDataStructure==NULL) { return(E_ZCL_ERR_PARAMETER_NULL); } return(E_ZCL_SUCCESS); } 及び Re:バグレポート:JN5189DK6 ZCL OTAコードでエンドポイントIDの代わりにエンドポイントインデックスが使用されています これが2番目のアイテムです。システムは、約30秒であるにもかかわらず、メッセージを編集する時間がなくなったと言います。 // // The *eOtaTimeUpdate* function expects an endpoint ID, not an index // PUBLIC void vOtaTimerClickCallback(tsZCL_CallBackEvent *psCallBackEvent) { #if (defined(OTA_SERVER) && defined(OTA_PAGE_REQUEST_SUPPORT)) || defined(OTA_CLIENT) int i; uint8 u8NumberOfendpoints; u8NumberOfendpoints = u8ZCL_GetNumberOfEndpointsRegistered(); // find price clusters on each EP - if any for(i=1; i<(u8NumberOfendpoints+1); i++) { // deliver time to any EP-server/client eOtaTimeUpdate(i, TRUE, psCallBackEvent); eOtaTimeUpdate(i, FALSE, psCallBackEvent); } #endif } // // FIXED // PUBLIC void vOtaTimerClickCallback(tsZCL_CallBackEvent *psCallBackEvent) { #if (defined(OTA_SERVER) && defined(OTA_PAGE_REQUEST_SUPPORT)) || defined(OTA_CLIENT) int i; uint8 u8NumberOfendpoints; u8NumberOfendpoints = u8ZCL_GetNumberOfEndpointsRegistered(); // find price clusters on each EP - if any for(i = 0; i < u8NumberOfendpoints; i++) { uint8_t u8EndpointId = u8ZCL_GetEPIdFromIndex(i); // deliver time to any EP-server/client eOtaTimeUpdate(u8EndpointId, TRUE, psCallBackEvent); eOtaTimeUpdate(u8EndpointId, FALSE, psCallBackEvent); } #endif }

MM9Z1J638擦除EEPROM问题 问候亲爱的专家，我正在尝试使用自制编程器调试 MM9Z1J638 MCU，我查看了数据表并成功读取了设备 ID EEprom 和 PFlash，但是当我尝试擦除 eeprom 时它什么也没做，我正在使用命令 0x12（命令） 0x10（adr 高） 0x0000（地址中+低） 我也尝试了 0x1210（cmd+adrHigh）0x0000 和许多其他选项...正如我在执行此操作之前所看到的，我需要清除 CCIF 寄存器，但我在数据表中找到任何信息，如何使用 bdm 命令来执行此操作，我应该使用什么命令来清除 FSTAT 寄存器以及它位于何处，另外我想知道 FCLKDIV 寄存器的地址是什么 另外我想知道我是否应该将像 0x09 这样的命令作为 2 个字（如 0x0910 0x0000）发送，或者我应该像 0x09 0x10 0x0000 那样执行 我确实需要一些关于此命令（0x09 0x11 0x12 等）的解释提示（启动前需要清除错误的命令）） 提前感谢！ 小型发动机司机 回复：MM9Z1J638擦除EEPROM问题 我自己做的是调试接口+自制发送命令的SW 无论如何，在您的帮助下我已经知道该怎么做了，非常感谢！ 回复：MM9Z1J638擦除EEPROM问题 抱歉，我在创建主题时选择了错误的目录，据我了解，我应该在操作之前写入 FCLKDIV 寄存器并擦除错误，但 FSTAT 寄存器在启动之前是 0x80...所以我该怎么办？我需要直接写入 FCCOB 寄存器吗？还是我可以使用数据表中显示的命令？例如，我想擦除整个 eeprom 以重新编程它，那么我到底该怎么做呢？在向 FCLKDIV 发送 0x00 后，FCLKDIV 设置为 fclkdiv=80，FSTAT=80，因此这意味着 mcu 是空闲的并且没有存储错误，下一步是什么？我只需要发送 0x12 和地址？但它对我来说不起作用，我正在做这样的擦除命令 发送 2 个单词 0x1210(命令 + adr_high) 0x0000（adr_med + adr_low） 我错过了什么？ 谢谢回复

MM9Z1J638 erase EEPROM problem Greetings Dear Experts, I'm trying to debug MM9Z1J638 MCU with a selfmade programmer, i looked in Datasheet and  succesfully read Device ID EEprom and PFlash but when i try to ERASE eeprom it do nothing I'm using comands 0x12 (cmd) 0x10 (adr High) 0x0000 (adr Med+Low) also i tried with 0x1210(cmd+adrHigh) 0x0000 and many other options... as i see before doing this i need to clear CCIF register but i cant find any information in datasheet how i can do it with bdm commands, what commands shall i use to clear FSTAT register and where it is located, also i wonder what is the address of FCLKDIV register And also i wonder shall i send comand like 0x09 as a 2 words like 0x0910 0x0000 or i shall do it like 0x09 0x10 0x0000  I really need some tips in explaination of this command (0x09 0x11 0x12 etc) ((commands that need clearing errors before start)) Thanks in advance! Small Engine Driver Re: MM9Z1J638 erase EEPROM problem my selfmade is debug interface+selfmade SW for sending commands anywaym i already figured out how to do it with you help, thanks a lot! Re: MM9Z1J638 erase EEPROM problem Hi, 1) There are two ways how to program MCU with self made programmer – either via BDM or using bootloader. Of course, bootloader also requires its load via BDM. If you use mass erase command then it is suitable immediately unsecure the mcu by rewriting the security byte in the flash. If it is not done then the MCU is secured after next reset. You can also erase the flash sector by sector. Bootloader is described here: https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Programmer-for-S12Z-microcontroller/m-p/1828519#M19723 https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12Z-MagniV-Serial-Bootloader-Interface/m-p/1522147 https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Simple-Serial-Bootloader-for-S12Z-AN-draft/ta-p/1126452 https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Flash-Corruption/m-p/955528/highlight/true First of all you should read the data sheet to understand how the programming and erasing memory works. 2) If you mean you want to program the data into the EEPROM and FLASH by means your application SW, then it is another story. In both cases it is necessary to switch off the memory window (or shift to the part which is not EW) because it reads flash and it is not allowed to read the flash while it is E/W. My question is. Does the “self made programmer” means either bootloader or debug interface or your application SW? Best regards, Ladislav Re: MM9Z1J638 erase EEPROM problem I chose wrong directory when creating theme i'm sorry, as i understand i shall write FCLKDIV register before operation and erase errors but FSTAT register is 0x80 before start... so what shall i do? and do i need to write directly to FCCOB register or i can use comand just as it presented in datsheet? for example i want to erase entire eeprom to reprog it again, so what exactly i shall do? FCLKDIV is set fclkdiv=80 after sending 0x00 to it, FSTAT= 80 so it means mcu is free and no errors stored, what's next? i just need to send 0x12 and address? but its not work for me, im doing erase comands like this sending 2 words 0x1210(comand + adr_high) 0x0000(adr_med + adr_low) what am i missing? Thanks for reply

BUG 报告：JN5189DK6 ZCL OTA 代码中使用端点索引代替端点 ID ZCL 代码在内部使用端点索引（ psZCL_Common->psZCL_EndPointRecord的索引）并通过eZCL_SearchForEPIndex和u8ZCL_GetEPIdFromIndex在注册时提供的 ID 之间进行映射。 当前的 ZCL OTA 代码错误地使用了在两个位置需要 ID 的索引。当端点 ID 连续且从 1 开始时，由此引起的问题就会被隐藏。 细节： SDK版本：2.6.15 - JN5189DK6/中间件/无线/zigbee/ZCL/Clusters/OTA/Source/OTA.c // // The u8SourceEndPointId > u8ZCL_GetNumberOfEndpointsRegistered // range check is incorrect and needs to be removed // PUBLIC teZCL_Status eOtaFindCluster( uint8 u8SourceEndPointId, tsZCL_EndPointDefinition **ppsEndPointDefinition, tsZCL_ClusterInstance **ppsClusterInstance, tsOTA_Common **ppsOTACustomDataStructure, bool_t bIsServer) { if(u8SourceEndPointId > u8ZCL_GetNumberOfEndpointsRegistered()) { return(E_ZCL_ERR_EP_RANGE); } // check EP is registered and cluster is present in the send device if(eZCL_SearchForEPentry(u8SourceEndPointId, ppsEndPointDefinition) != E_ZCL_SUCCESS) { return(E_ZCL_ERR_EP_RANGE); } if(eZCL_SearchForClusterEntry(u8SourceEndPointId, OTA_CLUSTER_ID, bIsServer, ppsClusterInstance) != E_ZCL_SUCCESS) { return(E_ZCL_ERR_CLUSTER_NOT_FOUND); } // initialise custom data pointer *ppsOTACustomDataStructure = (tsOTA_Common *)(*ppsClusterInstance)->pvEndPointCustomStructPtr; if(*ppsOTACustomDataStructure==NULL) { return(E_ZCL_ERR_PARAMETER_NULL); } return(E_ZCL_SUCCESS); } // // FIXED // PUBLIC teZCL_Status eOtaFindCluster( uint8 u8SourceEndPointId, tsZCL_EndPointDefinition **ppsEndPointDefinition, tsZCL_ClusterInstance **ppsClusterInstance, tsOTA_Common **ppsOTACustomDataStructure, bool_t bIsServer) { // check EP is registered and cluster is present in the send device if(eZCL_SearchForEPentry(u8SourceEndPointId, ppsEndPointDefinition) != E_ZCL_SUCCESS) { return(E_ZCL_ERR_EP_RANGE); } if(eZCL_SearchForClusterEntry(u8SourceEndPointId, OTA_CLUSTER_ID, bIsServer, ppsClusterInstance) != E_ZCL_SUCCESS) { return(E_ZCL_ERR_CLUSTER_NOT_FOUND); } // initialise custom data pointer *ppsOTACustomDataStructure = (tsOTA_Common *)(*ppsClusterInstance)->pvEndPointCustomStructPtr; if(*ppsOTACustomDataStructure==NULL) { return(E_ZCL_ERR_PARAMETER_NULL); } return(E_ZCL_SUCCESS); } 和 回复：BUG 报告：JN5189DK6 ZCL OTA 代码中使用了端点索引而不是端点 ID 这是第二项。系统说我已经没有时间编辑该消息了，尽管时间大约为 30 秒： // // The *eOtaTimeUpdate* function expects an endpoint ID, not an index // PUBLIC void vOtaTimerClickCallback(tsZCL_CallBackEvent *psCallBackEvent) { #if (defined(OTA_SERVER) && defined(OTA_PAGE_REQUEST_SUPPORT)) || defined(OTA_CLIENT) int i; uint8 u8NumberOfendpoints; u8NumberOfendpoints = u8ZCL_GetNumberOfEndpointsRegistered(); // find price clusters on each EP - if any for(i=1; i<(u8NumberOfendpoints+1); i++) { // deliver time to any EP-server/client eOtaTimeUpdate(i, TRUE, psCallBackEvent); eOtaTimeUpdate(i, FALSE, psCallBackEvent); } #endif } // // FIXED // PUBLIC void vOtaTimerClickCallback(tsZCL_CallBackEvent *psCallBackEvent) { #if (defined(OTA_SERVER) && defined(OTA_PAGE_REQUEST_SUPPORT)) || defined(OTA_CLIENT) int i; uint8 u8NumberOfendpoints; u8NumberOfendpoints = u8ZCL_GetNumberOfEndpointsRegistered(); // find price clusters on each EP - if any for(i = 0; i < u8NumberOfendpoints; i++) { uint8_t u8EndpointId = u8ZCL_GetEPIdFromIndex(i); // deliver time to any EP-server/client eOtaTimeUpdate(u8EndpointId, TRUE, psCallBackEvent); eOtaTimeUpdate(u8EndpointId, FALSE, psCallBackEvent); } #endif }

EEPROMの問題MM9Z1J638消去 こんにちは親愛なる専門家、私は自作のプログラマーでMM9Z1J638 MCUをデバッグしようとしています、私はデータシートを見て、正常にデバイスID EEpromとPFlashを読み取ったが、私がEEPROMを消去しようとすると、それは私がコマンドを使用している何もしません 0x12 (cmd) 0x10(ADR高) 0x0000(adr Med + Low) また、0x1210(cmd + adrHigh)0x0000や他の多くのオプションを試しました...これを行う前に見るように、CCIFレジスタをクリアする必要がありますが、データシートに情報を見つけることができませんBDMコマンドでそれを行う方法、FSTATレジスタをクリアするためにどのコマンドを使用し、それがどこにあるのか、また、FCLKDIVレジスタのアドレスは何なのか疑問に思います そしてまた、私は0x0910 0x0000のような2つの単語として0x09のようなコマンドを送るべきか、それとも私はそれをするようにするべきだろうか0x09 0x10 0x0000 私は本当にこのコマンド(0x09 0x11 0x12など)の説明にいくつかのヒントが必要です(((開始前にエラーをクリアする必要があるコマンド)) よろしくお願いいたします！ 小型エンジンドライバー Re:MM9Z1J638消去EEPROMの問題 私の自作は、コマンドを送信するためのデバッグインターフェース+自作のSWです とにかく、私はすでにあなたの助けを借りてそれを行う方法を見つけ出しました、どうもありがとう! Re:MM9Z1J638消去EEPROMの問題 テーマを作成するときに間違ったディレクトリを選択しました申し訳ありませんが、操作前にFCLKDIVレジスタを書き込み、エラーを消去する必要があることを理解していますが、開始前にFSTATレジスタが0x80されています...では、どうすればいいのでしょうか?また、FCCOBレジスタに直接書き込む必要がありますか、それともdatsheetに表示されているようにcomandを使用できますか?たとえば、EEPROM全体を消去して再度再現したいのですが、具体的にどうすればよいでしょうか?FCLKDIVは、0x00を送信した後、fclkdiv = 80に設定されているため、MCUが空いており、エラーが保存されていないことを意味しますが、次は何ですか?0x12と住所を送るだけですか?しかし、それは私にとっては仕事ではありません、私はこのようにコマンドを消去します 2ワードを送る 0x1210(コマンド+adr_high) 0x0000(adr_med+adr_low) 何が足りないのか? 返信ありがとうございます

FS26 reads the FS_STATE register in debug mode and it is always 0x14. There is no description of thi FS26 in debug mode to read FS_STATE register has been 0x14, in the manual does not change the return value description, according to the flowchart in the manual, after power-on should go through the OTP program will enter 01001 Init FS, then you can write the initialization register data stream, but at present due to FS_STATE problems, I can not go to init FS. In the community I found such a help, but unfortunately there is no specific description and solution, the link is as follows: Fs26 failed to initialize using the function Sbc_fs26_initDevice()  Re: FS26 reads the FS_STATE register in debug mode and it is always 0x14. There is no description of hello,Tomas I've successfully identified the cause and entered the normal mode. Thank you for your reply. BRs, zyg Re: FS26 reads the FS_STATE register in debug mode and it is always 0x14. There is no description of Hello, Is your power-up sequence successfully completed and the RSTB pin released? If not, please see below the RSTB Low reason checklist. If necessary, please check regulators output when RSTB low with oscilloscope, please also check if there is OV/UV flag reported. BRs, Tomas

LPC4330 DWT used on Event Recorder for GCOV/UNITY Test Coverage Generation Hi NXP Team, We are trying to use the Event Recorder to produce test coverage results for GCOV/UNITY. This will be executed by using the Keil Simulator. We are setting the EVENT_TIMESTAMP_SOURCE = 0 in EventRecorderConf.h to skip the double declaration of Systick_Timer IRQ Handler. When we do this, the 1st source file to generate the GCOV Test Coverage produces wrong results and followed with the other source files with zero percent test coverage. Debugging inside makes the progress step by step even if we dont put a breakpoint, meaning it stops with Access Violation on 0xE0000001 even pressing the RUN button to finish the test. But if we use the EVENT_TIMESTAMP_SOURCE = 1 in EventRecorderConf.h, we need to exclude any duplicated Systick_Handler IRQ Definition along the code to prevent the compilation error and retain the one in EventRecorder.c. This can finish the test inside debug without breakpoint by pressing the RUN Button. We noticed also the CMSIS File named core_cm4.h v2.10 has no definition of the DWT Structure. While the latest LPCOpen Library has the DWT Definition. Is the DWT feature enabled on LPC4330FBD144 using it together the EventRecorder without any complications? Please advise. Thanks and Good Day, Leo Re: LPC4330 DWT used on Event Recorder for GCOV/UNITY Test Coverage Generation I finally managed to solve the problem by Mapping the DWT locations on UNITY/GCOV Environment. Added address definitions with READ/WRITE Access on .ini file from 0xE0000000 to 0xE000EDFC. The test coverage now appears without linker error on Systick_Handler IRQ with EVENT_TIMESTAMP_SOURCE = 0. Re: LPC4330 DWT used on Event Recorder for GCOV/UNITY Test Coverage Generation Hi Kevin458, I already tried playing with those settings. The DWT is not a component of LPC4330FBD144 but it was a component of CMSIS core_cm4.h file. The release of this CMSIS file dated July 2011 contains no DWT structure originally. But the latest LPCOpen Library has the updated CMSIS that includes this DWT. Which makes me think that DWT feature was not really tested to be compatible with other tools such as UNITY/GCOV. The only thing that I tried so far is to use a preprocessor variable to exclude the definition of Systick_Handler to avoid the linker error which states that it got multiplied. And got the coverage. Anyway, thanks for the input. Thanks and Good Day, Leo Re: LPC4330 DWT used on Event Recorder for GCOV/UNITY Test Coverage Generation The issue likely stems from incorrect configuration of the Event Recorder with EVENT_TIMESTAMP_SOURCE = 0. Verify DWT availability for your LPC4330FBD144. Use EVENT_TIMESTAMP_SOURCE = 1 with proper SysTick handler management. Simplify your test case and use a debugger to pinpoint the issue.

i.MX8MP 过热时的自动开机行为 我正在使用带有 imx8mp 处理器的 congatec SMARC 模块。 为了澄清我们的要求： 当 SMARC 模块上的温度传感器达到 105°C 时，系统关闭。 目前，系统需要手动电源循环才能重新启动。 我想修改这种行为，以便当温度低于触发阈值时系统自动重新启动。 我们发现参考资料表明可以在 SCFW（系统控制器固件）中修改此行为。但是，SCFW 固件不用于 i.MX8MP 处理器。 i.MX8MP的启动顺序如下： BootROM → SPL → BL31（ATF - ARM 可信固件）→ OP-TEE（可选）→ BL33（U-Boot）→ Linux 内核。 根据我们的理解，解决此行为的潜在领域包括： a) 修改 BL31（ATF）。 调整 SNVS（安全非易失性存储）内的设置。 b) 配置 SMARC 模块上的 PMIC PCA9450C 以启用自动开机。 如果 PMIC 配置是正确的路径，您能否提供有关配置 PCA9450C 实现自动开机的文档或详细信息？ 或者，您有更好的解决方案吗？ 评估板 回复：i.MX8MP 过热时的自动开机行为 我最终设置了一个闹钟，并添加了一个服务以在关机前进行设置。因此，每次触发系统断电等时，都会触发警报。总比没有好。 echo +120 > /sys/class/rtc/rtc1/wakealarm   回复：i.MX8MP 过热时的自动开机行为 亲爱的 Marco_Savo， 修改 BL31 不是一个选择。 您的第二个选项是不可能的，因为您必须断言 PMIC_ON_REQ 才能启动开机序列，它没有自动开机。 您可以使用 FPGA 来断言 PMIC_ON_REQ 信号。