How to Unlock Cycle Milestone Series Bryce Harper in MLB The Show 26 If you have been grinding Diamond Dynasty lately, you already know that the community is buzzing about the new 98 OVR Cycle Milestone Series Bryce Harper. This card was dropped to commemorate his historic real-world performance where he hit for the cycle, and honestly, the attributes make it an absolute must-have for anyone looking to anchor their outfield or add some elite left-handed power to their lineup. The catch? He isn't tied to a straightforward program reward path. To get your hands on this Harper card, you need to acquire Chase Pack 16. Because it is a Chase Pack reward, unlocking him takes a bit of strategy, luck, or a healthy stack of Stubs. Depending on how much time or in-game currency you have, here are the four best ways to add him to your squad. 1. Grind the 4th Inning XP Reward Path Wheel If you are running a strict "No Money Spent" (NMS) squad, this is your best active grind method to pull the card entirely for free. Once you finish up the main rewards in the 4th Inning XP Program, the grind does not actually stop. Every chunk of extra XP you accumulate beyond the program's main cap grants you a spin on the repeatable Reward Path Wheel. Chase Pack 16 is sitting right in that wheel’s prize pool, meaning you can keep farming XP and taking shots at pulling the pack without spending a single stub. 2. Buy the The Show 50-Pack Bundle For players who prefer to skip the random wheel spins and have been saving up their hard-earned stubs, you can take a more direct route in the Pack Market. If you purchase the standard The Show 50-Pack Bundle, the game throws in a guaranteed Chase Pack 16 as a bonus. While buying bundles is always a bit of an investment, knowing you are 100% getting the specific Chase Pack containing Harper makes this a much safer bet than buying individual packs. 3. Test Your Luck with Standard The Show Packs You can also just play the game naturally and hope the RNG gods smile on you. Every single standard individual base pack you open carries a small, random percentage chance to upgrade into a Chase Pack 16. The best way to maximize this method without spending currency is to hoard free packs from current content. Make sure to knock out your tasks in the June Countdown Program, the June Spotlight Program, and jump into the Moonshot II Event. All of these modes hand out a ton of free base packs, giving you plenty of free lottery tickets for that Chase Pack upgrade. 4. Buy Directly from the Community Marketplace If you absolutely hate relying on pack luck and just want the card guaranteed right now, head straight over to the Legends & Flashbacks section of the Community Marketplace. You can use your banked Stubs to buy Bryce Harper directly from other players who managed to pull him. Just be prepared to pay a premium. Depending on market fluctuations and daily demand, his price has been hovering heavily around the 364,000 to 404,000 Stubs range. It is a hefty price tag, but it completely removes the guesswork if you have the stubs to spare.

host-to-switch trailer not removed on SJA1110 I am sending ethernet frames via the host processor (Cortex-M7) on a SJA1110. To route them to the specific ports on the switch I am using the host-to-switch header/trailer described in UM11107 under 5.8.2. The frames are received on the correct port however the trailer is not stripped or only partily stripped. For reference here is the same frame once before sending stored in the txBuffer and once after receiving in the rxBuffer of another device: 01 80 c2 00 00 10 68 58 c5 00 11 02 8b 8c 88 39 88 b7 5a 46 00 01 02 06 68 58 c5 00 11 02 04 01 00 06 01 02 12 01 01 14 0e 01 02 11 00 c5 58 68 08 d8 26 c0 cb fd 18 00 00 00 00 ---- 00 04 00 00 00 ====== 01 80 C2 00 00 10 68 58 C5 00 11 02 88 B7 5A 46 00 01 02 06 68 58 C5 00 11 02 04 01 00 06 01 02 12 01 01 14 0E 01 02 11 00 C5 58 68 08 D8 26 C0 CB FD 18 00 00 00 00 ---- 00 04 00 00 00 As you can see the header is removed completly but the trailer (everything after the 4 dashed lines) is not removed (or set to all 0s because atleast 64 bytes are required for the ethernet frame to be valid). Re: host-to-switch trailer not removed on SJA1110 Hello @flxwly , From the provided data, the host-to-switch header seems to be recognized by the switch, because the 4-byte header is removed from the outgoing frame. However, the trailer bytes still appear at the end of the received frame. One important point to check is the TRAILER_POS field in the host-to-switch header. The header bytes in your example are 8b 8c 88 39 Interpreting this according to the host-to-switch header format gives HEADER_TYPE = 0x8B8C, HOST_SWITCH = 1, TRAILER = 1, and TRAILER_POS = 57. However, in the transmitted frame shown in your dump, the 5-byte trailer appears to start at byte offset 59 from the MAC DA field, zero-based. Depending on the exact position counting convention relative to SFD, the expected value may differ by one, but the encoded value 57 does not seem to match the actual trailer position. Therefore, please first check how the TRAILER_POS field is calculated and try setting it to the position corresponding to the actual first byte of the trailer. There is also a second point: the provided test frame is very short. If the 5-byte trailer were stripped, the resulting Ethernet frame would become shorter than the minimum Ethernet frame size without FCS, so padding would need to be added again on egress. To avoid this ambiguity, could you please repeat the test with a longer payload, for example by adding 16 or 32 dummy bytes before the host trailer? This will make it clear whether the trailer is really stripped or not. Please also confirm that the egress port where the second device receives the frame is configured as a normal port. According to the UM, the header and trailer are stripped when the frame egresses a normal port, while the control information is preserved when the frame egresses the host port or a cascaded port. Finally, could you please share how the 5-byte trailer value `00 04 00 00 00` is generated? It would be useful to verify the bit packing of FRAMEID, PRIO, SWITCHID, and DESTPORTS against the format shown in the user manual. Best regards, Pavel Re: host-to-switch trailer not removed on SJA1110 Hello @PavelL, thank you for your reply. The trailer position is correct because I marked the "end" of my frame in the post wrong. It is actually 2 bytes earlier (at byte 57 as you correctly states). Therefore the trailer is also different and now makes sense and corresponds to the sceme in the UM. I can also confirm that on frames where the trailer only comes after atleast 64 bytes the trailer is removed correctly. So this is only a problem for frames shorter than 64 bytes before the trailer is added (which should not exist according to IEEE spec if i remember correct).  Best regards Nepomuk

[S32K388]SPD 1.0.6 パッケージに完全なテスト例が欠けている - レジスタレベルの参照Cのリクエスト NXPサポートチームの皆さん、こんにちは。   「S32K3 バージョン1.0.6のセーフティ・ペリフェラル・ドライバ」をダウンロードしました。   SPD_example_S32K388_M7_0_0プロジェクトをインストールしてS32 Design Studioにインポートしたところ、main.cはほぼ空であることに気づきました   **私の環境:** - S32 Design Studio for S32 プラットフォーム 3.5 - SPD バージョン:1.0.6(SW32K3_SPD_1.0.6_D2512_DesignStudio_updatesite_updated.zip) - ターゲット:S32K388 M7_0   **私が期待していたこと** 以下のレジスタレベルの完全な例をお送りください。 すべてのメモリ（フラッシュ、SRAM、TCM）にECCを適用- FCCU（故障収集・制御装置） - STCU2 (LBIST/MBIST を備えたセルフテスト コントロール ユニット 2) - EIM（エラー注入モジュール） - ERM（エラー報告モジュール） - CMU（クロックモニタユニット） - ロックステップコア- SWT(ソフトウェア監視)   [[email protected]]宛てに送信してください。 または、ダウンロードリンクを提供してください。 よろしくお願いします。   よろしくお願いいたします。 Re: [S32K388] SPD 1.0.6 Package Missing Complete Test Examples - Request for Register-Level Referenc こんにちは、 @xlele さん。 Copilotさんによると:SPDは完全なデモプロジェクトを提供していますが、EB Tresosのみで利用可能で、S32DS IDEsには対応していません。 デモはスタンドアロンの.exeファイルとして配布されています。バージョン。 こちらはS32DS IDEの非公式SPD例です。 https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-BIST-eMCEM-SPD106-v2-0-S32DS365-RTD700/ta-p/2373113 ベアメタルEIM、ERMの例を1つ挙げます。 https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-EIM-ERM-DTCM-SRAM-Baremetal-v3-0-S32DS36/ta-p/2193534 CMU_FCの例を1つ挙げます。 https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-MCAL-MCU-ClockMonitor-v1-0-S32DS36-RTD600/ta-p/2179976 SWTの例はRTDでデフォルトで見つけることができます。 よろしくお願いいたします。 ダニエル

College Football 27: Official Cover Athlete Prediction and Launch Schedule Breakdown The wait is almost over. EA Sports College Football 27 is locked in for an official worldwide launch on Thursday, July 9, 2026. This year is a massive milestone for the franchise. For the first time ever, the series is breaking out of its console-only cage and landing on PC via Steam, the Epic Games Store, and the EA App. PC players can finally join PlayStation 5 and Xbox Series X|S users on the virtual gridiron. EA has officially finalized its cover stars and laid out a staggered early access schedule. If you want to plan your kickoff, here is a complete breakdown of who is on the box, when you can start playing, and what it will cost. Official Cover Athletes Instead of highlighting just one player, EA Sports went with a star-studded, multi-athlete approach to celebrate the modern era of college football across different editions. Standard Edition Cover The standard cover features a powerhouse trio of dominant offensive playmakers who lit up the previous season: Dante Moore – The star quarterback leading the Oregon Ducks. Malachi Toney – Miami’s electrifying wide receiver. Kewan Lacy – The explosive Ole Miss running back. Deluxe Edition Cover The Deluxe Edition expands the squad, grouping the three Standard Edition stars alongside major defensive standouts and a championship coach: Jayden Maiava (USC Quarterback) Colin Simmons (Texas Linebacker) Leonard Moore (Notre Dame Cornerback) Curt Cignetti (Indiana’s national championship-winning head coach) Official Launch Schedule Depending on your pre-order tier or subscription status, there are three distinct windows to jump into the game. The staggered release schedule lets the most dedicated fans get a full week of head-start playtime. Release Date Access Window Requirement / Edition July 2, 2026 7-Day Early Access / 10-Hour Trial EA Sports MVP+ Membership or standard EA Play Trial July 6, 2026 3-Day Early Access Deluxe Edition, MVP Bundle, or EA Play Pro (PC) July 9, 2026 Official Worldwide Launch Standard Edition (All Platforms) Pricing & Edition Breakdown Pre-orders are already live on the official EA Sports storefront. Choosing the right version comes down to how early you want to play and whether you also play Madden. Standard Edition ($69.99): Gives you the base game on the July 9 launch date, plus standard pre-order incentives like Ultimate Team cover athlete items and basic Dynasty coach points. Deluxe Edition ($99.99): Unlocks the game 3 days early on July 6 and includes 4,600 College Football Points to kickstart your Ultimate Team roster. MVP Bundle ($149.99): A massive package built for football purists. It bundles the Deluxe Edition of College Football 27 with the Deluxe Edition of the upcoming Madden NFL 27, giving you early access and premium currency for both titles.

如何从源代码构建 imx-optee-os 并将其集成到 uboot FIT 镜像中？ 我使用的是 i.MX8MP SoC。我从https://github.com/nxp-imx/imx-optee-os.git克隆了 imx-optee-os 源代码，并检出了 lf-6.6.36_2.1.0branch。如何版本 imx-optee-os 并将其软件包到 flash.bin 中图像？ i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: How do I build imx-optee-os from source and integrate it into the uboot FIT image? 你好， 我不太清楚您具体使用的是哪个 BSP 版本，但请参阅 i.MX Linux 用户指南的 4.5.13 节。如何使用 imx-mkimage 构建 imx-boot 镜像，并查找 i.MX 8M EVK 部分（i.MX8M 是系列名称） Linux 文档： https://www.nxp.com/design/design-center/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applications-processors:IMXLINUX i.MX Linux 用户指南： https://www.nxp.com/docs/en/user-guide/UG10163.pdf 此致敬礼/Saludos， 阿尔多。

Question Regarding Critical Section Protection for OTP and NVM Access Services Hi, We previously encountered an issue caused by a background process when modifying the OTP (Secure Debug Password) and Life Cycle (LC) in HSE_B. As a result, we were advised to protect the OTP and LC update operations by using a critical section. In addition, would it also be necessary to protect service requests that access the NVM area, rather than the OTP, such as ImportKey, FormatKeyCatalogs, SmrEntryInstall, and CrEntryInstall, by using a critical section? Re: Question Regarding Critical Section Protection for OTP and NVM Access Services Hi @lukaszadrapa, thank you for your reply. In that case, instead of entering a critical section, would it be sufficient to check the HSE_CONFIG_GPR3 register before accessing the flash to ensure that flash access is available? Re: Question Regarding Critical Section Protection for OTP and NVM Access Services Hi @wodudwo  To have full picture, I recommend to read description in HSE Firmware reference manual rev. 2.7 in section: “14.6.5  Synchronizing flash read/write access between HSE and application core”: https://www.nxp.com/webapp/sd/collateral/1765990353647716033651?version=2.7 There are tables 149, 150 and 151 where you can find details about typical scenarios. In short: if HSE firmware is executing, it’s not possible to program a flash block from which the firmware is running from. In case of S32K344 and FULL_MEM version (just an example) it’s block 3, in case of AB_SWAP it’s block 1. It’s necessary to wait until HSE is in idle state and then do not trigger other HSE services. If HSE is performing flash operation on SYS-IMG (like key catalog formatting, importing a key, writing NVM attribute…) then, in addition, it is not possible to access data flash memory. If HSE is writing OTP data (attribute, life cycle advancing, programming password etc.) it is not possible to access UTEST and also flash block 0 because UTEST and flash block 0 are in the same read partition. And this seems to be the key point if you have a problem with ADKP programming and with life cycle advancing. Please take a look at this post where I described what needs to be relocated from flash block 0: https://community.nxp.com/t5/S32K/S32K324-HSE-Setting-ADKP-Issue/m-p/2369325/highlight/true#M58774 And when talking about synchronization between flash and HSE, notice that the support for synchronization between FLS and CRYPTO modules in RTD was added in version 5.0.0 and higher. Here is a screenshot from 6.0.0: If you use older RTD version, it needs to be handled by users. Notice that this synchronization does not solve the problem with programming OTP attributes to UTEST. The code still needs to be relocated from flash block 0. Regards, Lukas Re: Question Regarding Critical Section Protection for OTP and NVM Access Services It depends on scenario. “In addition, would it also be necessary to protect service requests that access the NVM area, rather than the OTP, such as ImportKey, FormatKeyCatalogs, SmrEntryInstall, and CrEntryInstall, by using a critical section?” For this scenario – no. HSE_CONFIG_GPR3 informs users if read/execute or program/erase is blocked for application by HSE on some flash block. But this is not a protection similar to critical section in your code. Critical section will ensure that there will be no interrupt which could access data flash or which could somehow interfere with the operations. But this has nothing to do with status of HSE_CONFIG_GPR3. Anyway, mentioned services like ImportKey, FormatKeyCatalogs, SmrEntryInstall, and CrEntryInstall are crucial configuration services which should be executed sequentially in controlled environment. It makes sense to use critical section. If it is necessary to handle some important interrupts in the meantime, it’s necessary to ensure that used interrupt resources does not interfere with HSE and flash blocks used by HSE. Re: Question Regarding Critical Section Protection for OTP and NVM Access Services Hi, @lukaszadrapa  Thank you for your explanation. If I understand correctly, checking the HSE_CONFIG_GPR3 register alone is not sufficient, and protection using a critical section is still required. My understanding is that even if an interrupt occurs, checking the HSE_CONFIG_GPR3 register before accessing the flash should prevent the application core and the HSE core from accessing the same flash block simultaneously. If a critical section is not used, are there any other potential issues that could occur besides simultaneous flash access between the application core and the HSE core? Re: Question Regarding Critical Section Protection for OTP and NVM Access Services Conversely, is it also an issue if the application core performs a program/erase operation while HSE is already performing a program/erase operation? - Yes, it is an issue because no more flash operations can run at the same time.   If so, can this situation be prevented by checking not only bits 21:16 but also bits 29:24 of the HSE_CONFIG_GPR3 register before the application core starts the program/erase operation? - Yes. This would help in situation when HSE is already programming the flash and application core want to also start another flash operation.   If this approach is not sufficient to prevent such conflicts, would using a critical section be the recommended solution for protecting these service requests? - When HSE performs mentioned NVM operations (catalog format, key import…), application should not start other flash operations and should not access flash block which is being programmed by HSE. If anything like that is done by the interrupt handlers, yes, critical section would prevent this conflict.   Additionally, the tables do not explicitly describe the case where the application core is executing code from a code flash block while HSE is performing a program/erase operation on the same code flash block. Is this scenario considered safe without any synchronization, or does it also require some form of protection? - Code flash memory is being programmed by HSE only when HSE/SBAF installs/updates/recovers/erases HSE firmware. This is done either out of reset automatically or it is triggered by software. HSE firmware is located it the end of code flash (in FULL_MEM version) or at the end of active and passive block (AB_SWAP version). It is expected that the application starts from lower flash blocks and it also waits until initialization is done and until HSE finishes the initialization (and possible flash operations). So, there’s no risk in this case. If application triggers an update of HSE firmware, it’s up to user to ensure that corresponding flash block is not access during this operation. If protection is required for this scenario, what would be the recommended way to implement it? - As described above – after reset, do not access flash block which contains HSE firmware until initialization is completed. And do not access the flash block when your software initiates HSE firmware update.   Re: Question Regarding Critical Section Protection for OTP and NVM Access Services hi, @lukaszadrapa  Thank you for your explanation. Your answers have been very helpful.  Re: Question Regarding Critical Section Protection for OTP and NVM Access Services Hi, @lukaszadrapa  Thank you for your reply. According to Tables 149, 150, and 151 in the HSE Firmware Reference Manual, which describe synchronization requirements for concurrent flash program/erase operations, the following is stated: No synchronization steps to be followed. It is expected that the M7_0/1 core does not issue any command to HSE which involves program/erase operation when it is programming data flash. Conversely, is it also an issue if the application core performs a program/erase operation while HSE is already performing a program/erase operation? If so, can this situation be prevented by checking not only bits 21:16 but also bits 29:24 of the HSE_CONFIG_GPR3 register before the application core starts the program/erase operation? If this approach is not sufficient to prevent such conflicts, would using a critical section be the recommended solution for protecting these service requests? Additionally, the tables do not explicitly describe the case where the application core is executing code from a code flash block while HSE is performing a program/erase operation on the same code flash block. Is this scenario considered safe without any synchronization, or does it also require some form of protection? If protection is required for this scenario, what would be the recommended way to implement it? Re: Question Regarding Critical Section Protection for OTP and NVM Access Services We are getting back to tables 149, 150 and 151 from HSE firmware reference manual which I mentioned earlier. It's necessary to evaluate the program flow, compare it with scenarios described in the tables and decide if countermeasures are needed or not. Otherwise there could be a risk that HSE will disrupt application core(s) or vice versa.  Regards, Lukas

关于 OTP 和 NVM 访问服务的关键部分保护的问题 您好，我们之前在修改 HSE_B 中的 OTP（安全调试密码）和生命周期 (LC) 时，遇到了由后台进程引起的问题。 因此，我们被建议使用临界区来保护 OTP 和 LC 更新操作。 此外，是否也需要使用临界区来保护访问 NVM 区域（而不是 OTP）的服务请求，例如ImportKey 、 FormatKeyCatalogs 、 SmrEntryInstall和CrEntryInstall ？ Re: Question Regarding Critical Section Protection for OTP and NVM Access Services 嗨@lukaszadrapa ， 感谢您的回复。 在这种情况下，与其进入临界区，不如在访问闪存之前检查 HSE_CONFIG_GPR3 寄存器以确保闪存访问可用，这样是否就足够了？ Re: Question Regarding Critical Section Protection for OTP and NVM Access Services 嗨@wodudwo 为了获得完整的信息，我建议阅读 HSE 固件参考手册 rev. 中的描述。2.7 节： “14.6.5同步 HSE 和应用核心之间的闪存读/写访问： https://www.nxp.com/webapp/sd/collateral/1765990353647716033651?version=2.7 表 149、150 和 151 中提供了典型场景的详细信息。 简而言之：如果 HSE 固件正在执行，则无法对正在运行该固件的闪存块进行编程。以 S32K344 和 FULL_MEM 版本为例（仅举例），它是第 3 个块；以 AB_SWAP 为例，它是第 1 个块。必须等到 HSE 处于 IDLE状态后，才不要触发其他 HSE 服务。 如果 HSE 正在对 SYS-IMG 执行闪存操作（例如密钥目录格式化、导入密钥、写入 NVM 属性等），则此外，也无法访问数据闪存。 如果 HSE 正在写入 OTP 数据（属性、生命周期推进、编程密码等），则无法访问 UTEST 和闪存块 0，因为 UTEST 和闪存块 0 位于同一个读取分区中。如果你在使用 ADKP 编程和生命周期推进方面遇到问题，这似乎就是关键所在。请查看这篇帖子，其中我描述了需要从闪存块 0 迁移的内容： https://community.nxp.com/t5/S32K/S32K324-HSE-Setting-ADKP-Issue/mp/2369325/highlight/true#M58774 谈到闪存和 HSE 之间的同步时，请注意 RTD 中 FLS 和 CRYPTO 模块之间的同步支持是在 5.0.0 及更高版本中添加的。 以下是 6.0.0 版本的屏幕截图： 如果使用较旧的RTD版本，则需要用户自行处理。请注意，这种同步并不能解决将 OTP 属性编程到 UTEST 的问题。代码仍需从闪存块 0 迁移出来。 此致， Lukas Re: Question Regarding Critical Section Protection for OTP and NVM Access Services 这要视具体情况而定。 “此外，是否也需要使用临界区来保护访问 NVM 区域（而不是 OTP）的服务请求，例如ImportKey 、 FormatKeyCatalogs 、 SmrEntryInstall和CrEntryInstall ？” 就这种情况而言——不。HSE_CONFIG_GPR3 通知用户，如果 HSE 阻止了对某些闪存块的读取/执行或编程/擦除操作。但这并不类似于代码中的临界区保护机制。临界区将确保不会发生任何可能访问数据闪存或以任何方式干扰操作的中断。但这与 HSE_CONFIG_GPR3 的状态无关。 总之，提到的 ImportKey、FormatKeyCatalogs、SmrEntryInstall 和 CrEntryInstall 等服务都是至关重要的配置服务，应该在受控环境中按顺序执行。使用临界区是合理的。如果在此期间需要处理一些重要的中断，则必须确保所使用的中断资源不会干扰 HSE 和 HSE 使用的闪存块。 Re: Question Regarding Critical Section Protection for OTP and NVM Access Services 你好， @lukaszadrapa 谢谢你的解释。 如果我理解正确的话，仅仅检查 HSE_CONFIG_GPR3 寄存器是不够的，仍然需要使用临界区进行保护。 我的理解是，即使发生中断，在访问闪存之前检查 HSE_CONFIG_GPR3 寄存器也应该能够防止应用程序内核和 HSE 内核同时访问同一个闪存块。 如果不使用临界区，除了应用程序核心和 HSE 核心之间同时访问闪存之外，还会出现其他潜在问题吗？ Re: Question Regarding Critical Section Protection for OTP and NVM Access Services 反过来，如果应用程序核心在 HSE 已经执行编程/擦除操作的同时执行编程/擦除操作，这是否也是一个问题？ - 是的，这是一个问题，因为不能同时运行更多闪存操作。 如果是这样，是否可以通过在应用程序内核开始编程/擦除操作之前，不仅检查 HSE_CONFIG_GPR3 寄存器的第 21:16 位，而且检查第 29:24 位来防止这种情况发生？ - 是的。这有助于解决 HSE 已经对闪存进行编程，而应用程序核心也想启动另一个闪存操作的情况。 如果这种方法不足以防止此类冲突，那么使用临界区是否是保护这些服务请求的推荐解决方案？ - 当 HSE 执行上述 NVM 操作（目录格式、密钥导入等）时，应用程序不应启动其他闪存操作，也不应访问 HSE 正在编程的闪存块。如果中断处理程序执行了类似的操作，那么临界区可以防止这种冲突。 此外，表格没有明确描述应用程序核心正在执行代码闪存块中的代码，而 HSE 正在对同一个代码闪存块执行编程/擦除操作的情况。 在没有任何同步的情况下，这种方案是否安全？还是也需要某种形式的保护？ - 代码闪存仅在 HSE/SBAF 安装/更新/恢复/擦除 HSE 固件时由 HSE 进行编程。这是通过自动复位实现的，也是由软件触发的。 HSE 固件位于代码闪存的末尾（在 FULL_MEM 版本中）或主动和被动块的末尾（AB_SWAP 版本中）。预计应用程序将从较低的闪存块开始，并且会等待初始化完成，以及 HSE 完成初始化（以及可能的闪存操作）。所以，这种情况没有风险。如果应用程序触发 HSE 固件更新，则用户有责任确保在此操作期间不会访问相应的闪存块。 如果需要针对这种情况采取保护措施，建议采用哪种实施方法？ - 如上所述 - RESET后，在初始化完成之前，请勿访问包含 HSE 固件的闪存块。当您的软件启动 HSE 固件更新时，请勿访问闪存块。 Re: Question Regarding Critical Section Protection for OTP and NVM Access Services 我们现在要回到我之前提到的 HSE 固件参考手册中的表 149、150 和 151。有必要评估程序流程，将其与表格中描述的情况进行比较，并决定是否需要采取应对措施。否则，HSE可能会干扰应用程序核心，反之亦然。 此致， Lukas Re: Question Regarding Critical Section Protection for OTP and NVM Access Services 你好， @lukaszadrapa 感谢您的回复。 根据 HSE 固件参考手册中的表 149、150 和 151（其中描述了并发闪存编程/擦除操作的同步要求），规定如下： 无需遵循任何同步步骤。预计 M7_0/1 内核在对数据闪存进行编程时，不会向 HSE 发出任何涉及编程/擦除操作的命令。 反过来，如果应用程序核心在 HSE 已经执行编程/擦除操作的同时执行编程/擦除操作，这是否也是一个问题？ 如果是这样，是否可以通过在应用程序内核开始编程/擦除操作之前，不仅检查 HSE_CONFIG_GPR3 寄存器的第 21:16 位，而且检查第 29:24 位来防止这种情况发生？ 如果这种方法不足以防止此类冲突，那么使用临界区是否是保护这些服务请求的推荐解决方案？ 此外，表格没有明确描述应用程序核心正在执行代码闪存块中的代码，而 HSE 正在对同一个代码闪存块执行编程/擦除操作的情况。 在没有任何同步的情况下，这种方案是否安全？还是也需要某种形式的保护？ 如果需要针对这种情况采取保护措施，建议采用哪种实施方法？ Re: Question Regarding Critical Section Protection for OTP and NVM Access Services 嗨， @lukaszadrapa 谢谢你的解释。您的回答非常有帮助。

imx-optee-osをソースコードからビルドして、それをuboot FITイメージに統合するにはどうすればよいですか？ 私はi.MX8MP SoCを使用しています。私はhttps://github.com/nxp-imx/imx-optee-os.gitから imx-optee-os のソースコードをクローンし、lf-6.6.36_2.1.0 ブランチをチェックアウトしました。imx-optee-oをどのように構築して、それをflash.binにパッケージ化すればいいのでしょうか画像？ i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: How do I build imx-optee-os from source and integrate it into the uboot FIT image? こんにちは、 どのBSPバージョンを使っているのか正確にはわかりませんが、i.MX Linuxユーザーガイドのセクション4.5.13をぜひご覧くださいimx-mkimageを使ってimx-bootイメージを構築する方法と、i.MX 8M EVKセクション(i.MX8Mがファミリ)を探す Linuxのドキュメント: https://www.nxp.com/design/design-center/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applications-processors:IMXLINUX i.MX Linuxユーザーガイド: https://www.nxp.com/docs/en/user-guide/UG10163.pdf よろしくお願いいたします。 アルド。

OTPおよびNVMアクセスサービスのクリティカルセクション保護に関する質問 こんにちは。以前、HSE_B で OTP (セキュアデバッグパスワード) とライフサイクル (LC) を変更する際に、バックグラウンドプロセスが原因で問題が発生しました。 その結果、OTPおよびLCの更新処理を保護するためにクリティカルセクションを使用するよう助言を受けました。 さらに、 ImportKey、 FormatKeyCatalogs、 SmrEntryInstall、 CrEntryInstallなど、OTPではなくNVM領域にアクセスするサービスリクエストも、クリティカルセクションを使って保護する必要があるのでしょうか? Re: Question Regarding Critical Section Protection for OTP and NVM Access Services こんにちは、 @lukaszadrapa さん。 ご返信よろしくお願いします。 CASE、クリティカルセクションに入る代わりに、フラッシュにアクセスする前にHSE_CONFIG_GPR3レジスタを確認してフラッシュアクセス可能かどうかを確認するだけで十分でしょうか? Re: Question Regarding Critical Section Protection for OTP and NVM Access Services こんにちは、 @wodudwo さん。 全体像を把握するには、HSEファームウェアのリファレンスマニュアルの説明を読むことをお勧めします。2.7節： 「14.6.5HSEとアプリケーションコア間のフラッシュ読み書きアクセスの同期」: https://www.nxp.com/webapp/sd/collateral/1765990353647716033651?version=2.7 表149、150、151には典型的なシナリオの詳細が記載されています。 要するに、HSEファームウェアが実行されている場合、そのファームウェアが実行されているフラッシュブロックをプログラムすることはできません。S32K344 CASE や FULL_MEM CASE (あくまで例ですが) ではブロック3、AB_SWAP CASE ではブロック1です。HSEがアイドル状態になるまで待ち、その後他のHSEサービスを起動しないことが大切です。 HSEがSYS-IMGに対してフラッシュ操作(キーカタログのフォーマット、キーのインポート、NVM属性の書き込みなど)を行っている場合、さらにデータフラッシュメモリへのアクセスは不可能です。 HSEがOTPデータ(属性、ライフサイクル進行、パスワードのプログラミングなど)を書き込んでいる場合、UTESTとフラッシュブロック0の両方にアクセスすることはできません。なぜなら、UTESTとフラッシュブロック0が同じ読み取りパーティション内にあるからです。そして、ADKPプログラミングやライフサイクル進行に問題がある場合、これが重要なポイントとなるようです。フラッシュブロック0から移動する必要があるものについて説明したこちらの投稿をご覧ください。 https://community.nxp.com/t5/S32K/S32K324-HSE-Setting-ADKP-Issue/mp/2369325/highlight/true#M58774 また、フラッシュとHSEの同期について話す際、RTDのFLSとCRYPTOモジュール間の同期サポートがバージョン5.0.0以降に追加されたことに注目してください。 以下はバージョン6.0.0のスクリーンショットです。 古いRTDバージョンを使う場合は、ユーザーが対応する必要があります。この同期では、OTP属性をUTESTにプログラミングする際の問題は解決されないことに注意してください。コードはフラッシュブロック0から移動させる必要がある。 よろしくお願いいたします。 ルーカス Re: Question Regarding Critical Section Protection for OTP and NVM Access Services こんにちは、 @lukaszadrapa ご説明ありがとうございました。 私の理解が正しければ、HSE_CONFIG_GPR3レジスタのチェックだけでは不十分であり、クリティカルセクションを用いた保護が依然として必要となる。 私の理解では、割り込みが発生しても、フラッシュにアクセスする前にHSE_CONFIG_GPR3レジスタを確認することで、アプリケーションコアとHSEコアが同時に同じフラッシュブロックにアクセスするのを防ぐはずです。 クリティカルセクションが使われない場合、アプリケーションコアとHSEコア間の同時フラッシュアクセス以外に起こりうる問題はありますか? Re: Question Regarding Critical Section Protection for OTP and NVM Access Services 状況によります。 「さらに、 ImportKey、 FormatKeyCatalogs、 SmrEntryInstall、 CrEntryInstallなど、OTPではなくNVM領域にアクセスするサービスリクエストも、クリティカルセクションを使って保護する必要があるのでしょうか?」 このシナリオでは、答えはノーです。HSE_CONFIG_GPR3、HSEがフラッシュブロックで読み書き/実行やプログラム/消去をブロックした場合にユーザーに通知します。しかし、これはあなたのコードにおけるクリティカルセクションのような保護機能ではありません。クリティカルセクションは、データフラッシュにアクセスする割り込みや、操作に干渉する割り込みが起きないことを保証します。しかし、これはHSE_CONFIG_GPR3の状態とは何の関係もありません。 いずれにせよ、ImportKey、FormatKeyCatalogs、SmrEntryInstall、CrEntryInstallといったサービスは、管理された環境下で順番に実行する必要のある重要な構成サービスです。クリティカルセクションを使用するのは理にかなっている。その間に重要な割り込みを処理する必要がある場合には、使用される割り込みリソースがHSEおよびHSEで使用されるフラッシュブロックに干渉しないようにする必要があります。 Re: Question Regarding Critical Section Protection for OTP and NVM Access Services 先ほど述べたHSEファームウェアリファレンスマニュアルの表149、150、151に戻ります。プログラムの流れを評価し、表に記載されているシナリオと比較し、対策が必要かどうかを判断する必要があります。そうでなければ、HSEがアプリケーションコアを妨害したり、その逆を妨げるリスクがあります。 よろしくお願いいたします。 ルーカス Re: Question Regarding Critical Section Protection for OTP and NVM Access Services こんにちは、 @lukaszadrapa ご説明ありがとうございました。あなたの回答は大変参考になりました。 Re: Question Regarding Critical Section Protection for OTP and NVM Access Services こんにちは、 @lukaszadrapa ご返信よろしくお願いします。 HSEファームウェアリファレンスマニュアルの表149、150、151によると、同時フラッシュプログラム/消去操作の同期要件を説明しています。 同期手順は不要です。M7_0/1コアは、データフラッシュをプログラムしている際にHSEに対してプログラム/消去操作に関するコマンドを出さないことが期待されています。 逆に、アプリケーションコアがプログラム/消去操作を行っている間にHSEがすでにプログラム/消去操作を行っている場合も問題になるのでしょうか? もしそうなら、アプリケーションコアがプログラム/消去操作を開始する前に、HSE_CONFIG_GPR3レジスタの21:16だけでなく29:24ビットもチェックすることでこの状況を防げますか? この方法ではこのような競合を防ぐのに十分でない場合、これらのサービス要求を保護するための推奨される解決策はクリティカルセクションを使用することでしょうか？ さらに、表はアプリケーションコアがコードフラッシュブロックからコードを実行している間に、HSEが同じコードフラッシュブロックに対してプログラム/消去操作を行う場合を明示的に説明していません。 このシナリオは、同期処理なしでも安全だと考えられるのでしょうか、それとも何らかの保護対策が必要でしょうか？ このシナリオにおいて保護が必要な場合、推奨される実装方法はどのようなものでしょうか？ Re: Question Regarding Critical Section Protection for OTP and NVM Access Services 逆に、アプリケーションコアがプログラム/消去操作を行っている間にHSEがすでにプログラム/消去操作を行っている場合も問題になるのでしょうか? - はい、問題はあります。なぜなら、フラッシュ操作を同時に実行できなくなるからです。 もしそうなら、アプリケーションコアがプログラム/消去操作を開始する前に、HSE_CONFIG_GPR3レジスタの21:16だけでなく29:24ビットもチェックすることでこの状況を防げますか? - はい。これは、HSEがすでにフラッシュをプログラムしていて、アプリケーションコアが別のフラッシュ操作を始めたい場合に役立ちます。 この方法ではこのような競合を防ぐのに十分でない場合、これらのサービス要求を保護するための推奨される解決策はクリティカルセクションを使用することでしょうか？ - HSEが前述のNVM操作(カタログ形式、キーインポートなど)を行う際、アプリケーションは他のフラッシュ操作を開始しず、HSEがプログラムしているフラッシュブロックにもアクセスしてはいけません。割り込みハンドラによってそのような処理が行われる場合、クリティカルセクションによってこの競合は防止されます。 さらに、表はアプリケーションコアがコードフラッシュブロックからコードを実行している間に、HSEが同じコードフラッシュブロックに対してプログラム/消去操作を行う場合を明示的に説明していません。 このシナリオは、同期処理なしでも安全だと考えられるのでしょうか、それとも何らかの保護対策が必要でしょうか？ - コードフラッシュメモリは、HSE/SBAFがHSEファームウェアをインストール/更新/復旧/消去する場合にのみ、HSEによってプログラムされます。これはリセット後に自動的に行われるか、ソフトウェアによってトリガーされます。 HSEファームウェアは、コードフラッシュの末尾（FULL_MEMバージョン）またはアクティブブロックとパッシブブロックの末尾（AB_SWAPバージョン）に配置されます。アプリケーションは下位のフラッシュブロックから開始することが期待されており、初期化が完了し、HSEが初期化(および可能なフラッシュ操作)を完了するまで待ちます。ですので、このケースにはリスクはありません。アプリケーションがHSEファームウェアの更新をトリガーした場合、対応するフラッシュブロックがこの操作中にアクセスされないようにするのはユーザーが確認します。 このシナリオにおいて保護が必要な場合、推奨される実装方法はどのようなものでしょうか？ - 前述の通り – リセット後は、初期化が完了するまでHSEファームウェアを含むフラッシュブロックにアクセスしないでください。また、ソフトウェアがHSEファームウェアアップデートを開始する際にフラッシュブロックにアクセスしないでください。

カレッジフットボール27：公式カバーアスリート予想と発売スケジュール詳細 待ち時間はもうすぐ終わる。EA Sports College Football 27は、2026年7月9日（木）に全世界で正式に発売されることが決定しました。 今年はフランチャイズにとって大きな節目となる年だ。シリーズ史上初めて、コンソール専用という枠を超え、Steam、Epic Games Store、EAアプリを通じてPCにも登場する。PCプレイヤーはついにPlayStation 5やXbox Series X|Sユーザーとバーチャルグリッドアイアンに参加できるようになりました。 EAは正式に表紙スターを確定し、段階的な早期アクセススケジュールを発表しました。キックオフの計画を立てたい場合は、ボックスに誰がいるか、いつプレー開始できるか、そして費用がいくらかを詳細にまとめておきます。 公式カバーアスリート EA Sportsは、特定の選手だけをフィーチャーするのではなく、様々なエディションを通して、スター選手が多数登場する複数のアスリートをフィーチャーすることで、現代のカレッジフットボールを称えるというアプローチを採用した。 通常版カバー 通常版の表紙には、前シーズンに大活躍した、圧倒的な攻撃力を誇る3人のプレイメーカーがフィーチャーされている。 ダンテ・ムーア – オレゴン・ダックスを率いるスタークォーターバック。 マラキ・トニー – マイアミの電撃的なワイドレシーバー。 ケワン・レイシー – オレミス大学の爆発的なランニングバック。 デラックスエディションカバー デラックスエディションでは、スタンダードエディションのスター選手3名に加え、守備陣の主力選手や優勝経験のあるコーチが加わり、チーム構成がさらに充実します。 ジェイデン・マイアバ（南カリフォルニア大学クォーターバック） コリン・シモンズ（テキサス大学ラインバッカー） レナード・ムーア（ノートルダム大学コーナーバック） カート・シグネッティ（インディアナ大学の全米選手権優勝監督） 公式発売スケジュール 予約購入のティアやサブスクリプション状況に応じて、ゲームを開始できる期間は3つに分かれています。段階的な発売スケジュールにより、最も熱心なファンは1週間先行してプレイできる。 リリース日 アクセスウィンドウ 要件／エディション 2026年7月2日 7日間の早期アクセス/10時間トライアル EA Sports MVP+メンバーシップまたは標準のEA Playトライアル 2026年7月6日 3日間の早期アクセス デラックスエディション、MVPバンドル、またはEA Play Pro（PC版） 2026年7月9日 世界同時発売開始 スタンダードエディション(全プラットフォーム) 価格とエディションの内訳 EA Sportsの公式ストアでは、既に予約注文が開始されています。適切なバージョンを選ぶには、いつからプレイしたいか、そしてMaddenもプレイするかどうかが重要になります。 スタンダード版（69.99ドル）：7月9日の発売日に基本ゲームを入手できるほか、Ultimate Teamのカバーアスリートアイテムや基本的なDynastyコーチポイントといった、通常の予約特典も付いてきます。 デラックス版（99.99ドル）：7月6日にゲームを3日早くアンロックでき、Ultimate Teamのロスター作成に役立つ4,600カレッジフットボールポイントが含まれています。 MVPバンドル（149.99ドル）：サッカーの純粋主義者のために作られた巨大なパッケージです。このゲームは、College Football 27のデラックスエディションと、今後発売予定のMadden NFL 27のデラックスエディションをバンドルしており、両タイトルの早期アクセスとプレミアム通貨が提供されます。

Hello World with the Model-Based Design Toolbox — Model. Generate. Drive. 1 Every great build starts with "Hello World" Every engineer remembers their first “Hello World” — that small, satisfying moment when an idea typed on a screen suddenly comes to life on a real machine. This series is a take on that same feeling, only this time the “machine” is a car. It’s a demonstrator that looks and behaves like a real vehicle, showcasing the combined use of tools from both the NXP and MathWorks ecosystems. This demo has been showcased at several events, including most recently at the MathWorks booth during Embedded World 2026 and MathWorks Automotive Conference, where the demo video that accompanies this series was filmed. Think of these articles as a guided tour through how the whole thing comes together, piece by piece. ▶ Watch the demo in action — presented at the MathWorks booth, Embedded World 2026 2 Table of Contents • Every great build starts with Hello World • From a model on a laptop to silicon on the bench • From the steering wheel to every node • And it grew up along the way • Built to be rebuilt — and learned from • A demonstrator, not a blueprint • The article series — one domain at a time 3 From a model on a laptop to silicon on the bench How does a car end up running on NXP silicon, starting from a model on a laptop? That’s where the NXP Model-Based Design Toolbox (MBDT) comes in. It acts as the bridge between the MathWorks ecosystem — Simulink and MATLAB — and NXP’s processors and embedded tools. An application is designed and modeled in Simulink, MBDT generates optimized code for the chosen NXP target, and that code is deployed straight onto the hardware. The main advantage of this approach is what it allows before any board is involved: an application can be validated and tuned in simulation first, and hardware that isn’t physically present can simply be simulated in its place. The results: early issue detection, shorter development cycles, and a faster time to market — backed by a toolchain that has been validated end to end. Figure 1. NXP Model-Based Design Toolbox One Pager 4 From the steering wheel to every node At the heart of the demo is a driver-in-the-loop setup: a physical steering wheel and a set of foot pedals feed signals directly into the simulation, where a virtual car is driven in simulation, into an environment developed through a RoadRunner simulated environment. From there, a clear hierarchy carries every input down to the hardware. The main node — an S32N processor — sits at the center: it communicates with the host PC running the simulation and makes the vehicle-level decisions. It then hands those decisions to a zonal node that acts as a gateway, fanning the signals out to the end nodes that handle each function — the front and rear lights, the front and rear parking sensors, the radar, and the steering rack, and, on the traction side, the battery management system and motor control. The effect is immediate and physical: steering and acceleration in the virtual world set the model on the table moving; shifting into reverse spins the motors up in the right direction; and when an obstacle appears behind the physical car, it stops on its own, with the rear lights turning red across every node — just like a production vehicle. Throughout, a live dashboard built with NXP’s FreeMASTER Lite shows the vehicle state as it happens, from the reverse camera to the parking sensors, blending signals from the virtual world with readings from the physical hardware. Figure 2. Demo architecture — main node (S32N), zonal gateway, and end nodes. 5 And it grew up along the way Behind all of these are the core functions of a real car — lighting, parking sensors, steering rack, motor control, and battery management — spread across roughly ten microcontrollers and processors and sixteen NXP evaluation boards and reference designs. There’s no need to unpack every component here, because each one earns its own dedicated article series later on. What’s worth knowing is how it all grew: this didn’t start as today’s car. It began as a battery management system (BMS), then gained cloud connectivity, then motor control — which evolved into a full traction inverter demo — and from there the remaining vehicle domains, from body and lighting to chassis and parking, were layered on one by one until it became a complete vehicle topology. In other words, existing MathWorks and model-based examples were assembled, domain by domain, into a car. 6 Built to be rebuilt — and learn from Why go to all this trouble? Mostly to document the work, share the thinking behind it, and show how to actually use MBDT. A big part of the appeal is that everything runs on NXP evaluation boards, which means the whole thing can be reproduced. There’s no need to redo a complex custom hardware design before starting; the same boards can be picked up to get going right away. That also makes the demo a hands-on learning platform: a place to explore the model-based workflow by doing one domain at a time. Note: A word on scope — this is a proof of concept that demonstrates the development workflow, not production firmware as it stands today. A great path forward is NXP’s CoreRide, which you can read more about on this page: Software-Defined Vehicle Development: NXP CoreRide Platform — but that part will not be covered in this series. Whether the field is automotive, electrification, industrial automation, or robotics — or simply an interest in model-based development — there should be something here worth taking away. 7 A demonstrator, not a blueprint One last note on how to read all of this. This car is a demonstrator, not a reference design. It was built with the hardware that happened to be on hand, so some of the boards and NXP solutions used aren’t necessarily the optimal fit for a given function — for a specific job, a different microcontroller might serve better. The point was never to say “use exactly these parts.” The point is the steps and the approach: the workflow itself, and how the pieces fit together. With that in mind, the articles below each take a part of this build and show how it’s done. Welcome to “Hello World” with the Model-Based Design Toolbox. 8 The article series — one domain at a time Each part of the demo car gets its own dedicated write-up, grouped into the twelve tracks below. As articles go live, the placeholders will be replaced with links. Bookmark this page — it will keep growing. NXP MBDT — How-To & Introduction What is Model-Based Design Toolbox? How to install Model-Based Design Toolbox? MBDT Setup and How-to run an application Develop an MBDT application workflow Create a new model and configure it for NXP Hardware Create a new configuration project using the S32CT How to MBDT Dio Port/Pins FreeMASTER & FreeMASTER Lite Introduction to FreeMASTER Using FreeMASTER block in Simulink Visualize and control variables in FreeMASTER Create web dashboard with FreeMASTER Lite Parking sensors Overview SW & HW Environment Logic Control (Main model overview) Lights Overview SW & HW Environment Logic Control (Main model overview) Motor Control Overview SW & HW Environment Logic Control Architecture (Main model overview) Battery Management Systems Overview SW & HW Environment Logic Control (Main model overview) Steering Overview SW & HW Environment Logic Control (Main model overview) Radar Overview SW & HW Environment Processing Chain - NXP Radar SDK Main Node Overview SW & HW Environment Logic Control (Main model overview) Zone Node Overview SW & HW Environment Logic Control (Main model overview) Software & Integration Creating virtual vehicle with MathWorks Overview SW & HW Environment Logic Control Creating Virtual Scenes & Scenarios with MathWorks (RoadRunner & Unreal Engine)  Processor-in-the-Loop (PIL) What is next? Export to & Debug generated code to S32 Design Studio IDE Other Guides Getting Started with FRDM-A-S32K312 using Model-Based Design  A1: Interacting with Digital Inputs Outputs on MR-CANHUBK344 A2: Sending data via UART and monitoring signals with FreeMASTER A3: Controlling LED intensity with ADC and PWM A4: Communicating over the CAN Bus   Note: This index is updated as new articles are published.

CLRC663 plus - LPCD Tip & Tricks Prerequisites:  CLRC663 plus Low Power Card Detection 1// Antenna Size  The stronger the coupling between reader and card, the better the detection range.  Ideally, the NFC reader antenna should have a size and form factor similar to that of the target NFC tag antenna. In practice, the reader antenna is typically designed to be slightly larger—by approximately 10% to 20%—to ensure reliable coupling and performance. 2// Antenna Q-factor  Higher Q-factor typically serves higher detection range. The Q-factor should be selected in accordance with the target communication bit rate.(e.g. Q≈30 for 106 kbit/s).  The antenna Q factor is mainly defined by the mechanical design of the antenna itself, as well as by external damping resistors. However, for LPCD-insensitive systems, a zero-ohm damping resistor can be used, and the system should then be evaluated through testing.  3// Target tuning  The CLRC663 should typically be used with the asymmetrical tuning as there is no internal power regulation implemented.  However, in some cases, symmetrical tuning may be beneficial, as it can improve detection range and sensitivity. Care must be taken to ensure that, under varying conditions—such as antenna loading by different NFC tags or the presence of nearby metal, the TVDD current does not exceed the specified maximum limits.   In CLRC663 LPCD operation, detection performance improves with higher TX power. However, this also increases current consumption, so an appropriate trade-off must be determined.   As a starting point, an antenna impedance of approximately Z≈ 50 Ω can be used.   4// Receiver setting (external Rx resistors) Based on the AN11019 (chapter 4.4.1), the peak voltage between RxN and GND (or RxP and GND) shall be in the range of 1.2Vp - 1.7Vp. Generally, higher Rx voltage levels improve detection range. To increase LPCD sensitivity and range, it can be advantageous to operate close to the upper limit of the allowed Rx voltage.   Please note that excessively high RX voltage may lead to immediate false wake-ups. 5//LPCD Settings As a starting point, we recommend using the following settings:   These settings provide robust immunity against false wake-ups and are highly efficient in terms of current consumption. The typical detection range for standard NFC tags is approximately 10 mm to 20 mm or even less in an application where the antenna is placed near a metal environment. Detection performance can be further improved by lowering the threshold settings +0 and -0. If this settings is used, we strongly advice using LPCD_FILTER feature as well. Alternatively, the user can use "high detection range option" + LPCD_FILTER. After using these settings, we recommend running "Endless LPCD" for a while and checking for any false wake-up rates. Note: The LPCD filter feature helps prevent false wake-ups. This is especially important when the threshold is set to +0 and -0. When using thresholds of +0 and −0 it is also recommended to set the "CWMAX" parameter (address 0x2A) to 1b. 5.1// LPCD RF ON time  If the RF on-time is shorter than approximately 20 µs - 30 µs , the primary detuning effect is dominated by the physical design of the NFC tag. For longer RF on-times, the NFC tag becomes energized, and its electrical parameters begin to contribute significantly to the overall detuning. Based on this understanding, a longer RF on-time can help increase LPCD detection range. However, this comes at the cost of higher current consumption. Therefore, it is recommended to compensate by adjusting the RF off-time. See an example below.   5.2// LPCD Charge pump  This function allows the TX power to be increased exclusively during the LPCD RF On time.   This can be beneficial if you want to avoid increasing the power in active mode (e.g., by reducing the tuning impedance) but only increase it during LPCD operation.   By activating the LPCD charge pump, detection performance can be improved, but at the cost of increased current consumption.   If this feature is enabled, it is recommended to verify the LPCD RF ping using an oscilloscope. It may be necessary to increase the RF On time to allow the amplitude to properly settle. Especially for TVDD= 3.3V or lower. 6// Summary Mode  Tuning function Target impedance Q-factor Receiver voltage LPCD Threshold LPCD Filter LPCD Charge -pump RF On time  Standard Asymmetrical  20 Ω - 80 Ω  10 - 30 1.5 Vp +1 and -1 disable disable 10 us High detection range  Asymmetrical /Symmetrical (1) 20 Ω - 50 Ω >25 (2) 1.7 Vp +0 and -0 enable enable/ disable (3)  20 us-100 us Note (1): Symmetrical tuning can only be applied if the TVDD current does not exceed the maximum allowable value after antenna loading caused by a card or metal object. Please ensure that this condition is met. Note (2): If high detection performance is required, the external antenna damping resistors are typically replaced with 0 Ω resistors, resulting in a higher antenna Q-factor. In this case, the user must verify that NFC communication continues to operate reliably. Due to the increased Q-factor, this configuration is typically limited to communication speeds of 106 kbit/s Note (3): Once the charge pump is enabled, the RF On time should be verified and adjusted if necessary. Please also note that the relationship between TX power and detection distance is not linear or unlimited. Beyond a certain point, enabling the charge pump provides only marginal improvements in detection distance.     Please note that the High Detection mode is generally more susceptible to false wake-ups and results in higher current consumption than the standard mode. NFC Frontend Solutions

eIQ ModelRunner on MCUs ModelRunner is a benchmarking tool for running TensorFlow Lite models on NXP microcontrollers. It supports both HTTP and UART communication modes and provides detailed latency profiling for each model layer. The model profiling information is in JSON format and can be uploaded to the upcoming eIQ AI Toolkit and eIQ AI Hub tools for more detailed analysis.  ModelRunner is available on the following MCU devices: FRDM-MCXN947 MCX-N5XX-EVK MCX-N9XX-EVK MIMXRT700-EVK MIMXRT595-EVK MIMXRT685-EVK MIMXRT1060-EVK MIMXRT1170-EVK There are two methods for using ModelRunner: Via an Ethernet connection to the board Via UART using an emulated network connection  - useful for devices without Ethernet like i.MX RT700 The attached guide walks through how to use both methods. A Windows Powershell or Linux prompt should be used for this lab as a normal Windows command prompt will not parse the commands correctly. 

eIQ Neutron NPU Support in Zephyr Zephyr now supports the eIQ Neutron NPU on MCX N and i.MX RT700. This article will describe how to get Zephyr and use the eIQ Neutron NPU libraries and examples.  Some previous experience with eIQ Neutron NPU enablement is assumed, so ensure you're familiar with the eIQ Neutron SDK, converting models for eIQ Neutron NPU, and basic ML concepts by going through the MCX N or i.MX RT700  NPU bare-metal lab guides for VS Code before continuing on below.  Install Software Run the MCUXpresso Installer tool and install three key components: Zephyr Developer Arm GNU Toolchain Zephyr SDK LinkServer Install LinkServer and add LinkServer to the PATH Install VS Code and MCUxpresso VS Code plugin Download Zephyr Open VSCode Go to the MCUXpresso for VSCode plugin and click on Import Repository Go to the Remote tab and select the Zephyr repository. Choose it a directory name and location to download the repository to, and then click on Import. It will take approximately 30 minutes to download the repository. Near the end of the download there will be several prompts in the terminal asking to accept licenses. Type “y” to accept and hit enter. There will be about 10 of these prompts at the end. Open the MCUXpresso Venv Terminal which has a Python virtual environment with all the paths preconfigured that were installed by MCUXpresso Installer. In the terminal that pops up, type “1” to select the default environment. Then navigate to the directory you downloaded Zephyr into Run the following commands to get TensorFlow: west config manifest.project-filter -- +tflite-micro west update Go into the zephyr subdirectory folder cd zephyr Now need to explicitly download the Pull Request (PR) that enables eIQ Neutron. This eventually won’t be necessary when Zephyr 4.5 is released in October, but until then will need to type the following In the command prompt to get it: git remote -v git remote add upstream https://github.com/zephyrproject-rtos/zephyr.git git remote -v   git stash git fetch upstream pull/108834/head:pr-108834 git checkout pr-108834 After this command you should see there’s now a folder at \ \zephyr\samples\boards\nxp\tflm_neutron with example source code. Compile and Run a Zephyr eIQ Neutron NPU example Compile the project with west:  For MCX N: west build -p auto -b frdm_mcxn947/mcxn947/cpu0 samples/boards/nxp/tflm_neutron   For RT700: west build -p auto -b mimxrt700_evk/mimxrt798s/cm33_cpu0 samples/boards/nxp/tflm_neutron Open TeraTerm or other serial terminal program, and connect to the virtual COM port that board enumerated as when you plugged in the USB cable. Use 115200 baud, 1 stop bit, no parity. Flash the resulting code with west flash The serial terminal should show the following: Can debug with west debug  Run your own NPU accelerated ML model in Zephyr Make sure you've gone through the MCX N or i.MX RT700  hands-on labs so you're familiar with the enablement. The same steps for converting a model with the Neutron Converter tool inside eIQ Neutron SDK, updating the eIQ Neutron libraries, modfiying the operator list, and adding a new model are relevant when using Zephyr, but the file locations will be Zephyr specific. Also note that the header file generated by the Neutron Converter tool will need to be updated to match the header of the model.hpp file.  Also note that the README.rst file in the Zephyr Neutron example mentions using eIQ Toolkit but that information is outdated and been superseded by eIQ Neutron SDK.  eIQ Neutron example is at \zephyr\samples\boards\nxp\tflm_neutron Neutron libraries are at \modules\hal\nxp\zephyr\blobs\neutron\ Model data is at \zephyr\samples\boards\nxp\tflm_neutron\src\models\mcxn\model.hpp Labels file is at \zephyr\samples\boards\nxp\tflm_neutron\src\labels.h kTensorArenaSize variable is set in \zephyr\samples\boards\nxp\tflm_neutron\src\main_functions.cpp (line 40) and is set to 60KB by default OpResolver is set in \zephyr\samples\boards\nxp\tflm_neutron\src\main_functions.cpp (line 65) The model is selected in \zephyr\samples\boards\nxp\tflm_neutron\src\main_functions.cpp (line 11) Additional References: Blog post on west which Zephyr uses. Zephyr on FRDM-MCXN947 Zephyr on i.MX RT700 Zephyr TensorFlow Hands-On Training

Automotive Vehicle Comfort Control Using FRDM-A-S32K344 Microcontrollers Overview This article demonstrates the implementation of a vehicle comfort control system using the FRDM-A-S32K344 development platform. The application showcases how embedded peripherals can be used to control multiple vehicle comfort functions, including cabin cooling and electric window operation. The demo operates a DC motor and a stepper motor based on user inputs while providing real-time control through PWM generation and GPIO outputs. The project highlights the interaction between user inputs, control logic, PWM motor control, and stepper motor sequencing commonly found in automotive body electronics and comfort modules. The solution is based on an Application Code Hub example designed for the FRDM-A-S32K344 platform. Vehicle Comfort Control on FRDM-A-S32K344  Learning Objectives This project demonstrates: GPIO-based input handling PWM motor control Direction control techniques Stepper motor sequencing Real-time actuator control Automotive comfort system concepts Multi-actuator control using S32K3 peripherals The example provides a practical introduction to automotive body-control applications involving cooling and window-control systems. System Architecture The application follows a command-and-control architecture:   Plain Text     User Inputs ↓ GPIO Interface ↓ Vehicle Comfort Control Logic ↓ PWM + GPIO Outputs ↓ DC Motor + Stepper Motor Architecture Diagram (Insert Vehicle Comfort Control Architecture Diagram) Figure Caption Figure 1. Vehicle comfort control system architecture. User button inputs are processed by the S32K344 microcontroller. The application determines the desired comfort function and generates either PWM-controlled outputs for the cooling fan or GPIO sequencing signals for the stepper motor representing window movement.  Control Principle The demo operates two independent comfort functions: Cooling System Control A DC motor represents a vehicle cooling fan. The MCU generates PWM signals that regulate: Fan activation Fan speed Cooling-system behavior PWM control allows smooth speed adjustments while minimizing power losses. Window Control System A stepper motor represents an electric window mechanism. The MCU controls the motor through a full-step coil sequencing algorithm. This allows: Upward movement Downward movement Direction control Precise positioning The behavior emulates typical automotive power-window systems. User Input Processing The system uses push-button inputs connected to the FRDM-A-S32K344 board. The button states are continuously monitored through GPIO inputs. Based on the detected command, the application executes the corresponding comfort function. Possible actions include: Increasing fan activity Decreasing fan activity Moving the window upward Moving the window downward The control logic translates user commands into actuator actions in real time. DC Motor Control The DC Motor 2 Click board is used to drive a 5V fan motor. PWM output generated by the S32K344 controls: Motor activation Speed variation As the PWM duty cycle changes, the fan speed changes accordingly. This illustrates a common cooling-system implementation used throughout the automotive industry. Stepper Motor Control The H-Bridge Click board controls a NEMA17 stepper motor using a full-step drive sequence. The MCU energizes the motor coils in a predefined pattern:   Plain Text     A → B → C → D   This enables: Controlled rotation Direction changes Window position simulation The process demonstrates how automotive ECUs control electromechanical comfort systems. Control Behavior The control logic can be represented as a command-response system. Example behavior: User Action System Response Fan Command PWM duty cycle adjusted Window Up Stepper advances forward Window Down Stepper advances reverse No Command Actuators remain idle Control Behavior Diagram (Insert Comfort Control Behavior Diagram) Figure Caption Figure 2. Vehicle comfort control behavior. User commands are translated into specific actuator actions. PWM signals regulate fan speed, while GPIO-driven step sequences determine stepper motor direction and movement. Hardware Setup Required Hardware FRDM-A-S32K344 FRDM-A-S32K344FRDM-A-S32K344 FRDM K64 Click Shield FRDM K64 click shieldFRDM K64 click shield DC Motor 2 Click DC Motor 2 ClickDC Motor 2 Click H-Bridge Click H-Bridge ClickH-Bridge Click 5V Fan Motor 5V Fan Motor5V Fan Motor Stepper Motor NEMA17 Stepper Motor Nema17Stepper Motor Nema17 Full setup: Comfort Full SetupComfort Full Setup This configuration enables simultaneous control of both rotational-speed and positional actuators. Software Environment The example was developed using: S32 Design Studio S32K3 Real-Time Drivers (RTD) Application Code Hub framework The software demonstrates practical usage of GPIO and PWM drivers for actuator control. Implementation Guide Step 1: Import the Project Open S32 Design Studio Import project from Application Code Hub Search for Vehicle Comfort Control example Expected result: Project appears in workspace Step 2: Build the Application Compile the project Check for errors Expected result: Successful build Step 3: Connect Hardware Install: FRDM K64 Click Shield DC Motor 2 Click H-Bridge Click Fan motor NEMA17 stepper motor Verify all wiring before powering the system. Step 4: Flash and Run Program the MCU Start execution Expected result: Application runs continuously Step 5: Functional Validation After startup: Press the control buttons Observe fan operation Observe stepper motor movement Expected result: The system immediately responds to user commands. Comfort System Examples The demonstrated functions correspond to common automotive applications. Cooling Regulation The DC motor represents: Cabin ventilation systems HVAC airflow control Cooling fan operation Electric Window Control The stepper motor represents: Window up/down movement Position control Direction control These systems are examples of comfort-oriented body electronics within modern vehicles. Possible Extensions The application can be enhanced with: Feedback-Based Control Add sensors to provide closed-loop position or speed control. Automatic Comfort Modes Implement predefined comfort profiles. CAN Communication Enable communication with other vehicle ECUs. Diagnostic Functions Add fault detection and actuator monitoring. Position Memory Store and restore window or comfort positions. Conclusion This vehicle comfort control demonstration shows how the S32K344 platform can integrate user inputs, GPIO processing, PWM generation, and electromechanical actuator control into a complete embedded automotive application. By controlling both a DC motor and a stepper motor, the project illustrates the implementation of cooling-system regulation and electric-window operation, providing a practical example of automotive comfort-module design on the S32K3 platform. Comfort ResultComfort Result The course serves as a foundation for the Eat-Sleep-Code-Repeat learning initiative, encouraging a hands-on approach where students continuously learn, develop, test, and improve automotive embedded applications using real hardware and practical examples.

To complement solution how to printf float number in MCUXpresso IDE Hi: In previous topics there are some discussions how to print float number in MCUXpresso IDE and SDK. To try them and summarize the final solution: 1.PRINTF the float number to UART console set below macro in project configuration->C/C++ build ->setting PRINTF_FLOAT_ENABLE=1 such code will work. float test1 = 0.15; PRINTF("%f\r\n",test1); 2.Transform float number to string by sprintf() function. there is one error in SDK user manual, " Ensure Redlib: Use floating point version of printf is selected " during project creation does not work. The default C library Redlib doesn't support floating, so it couldn't work with redlib. The correct solution are: (1)Change link library to NewLib, it's full C library and support float  printf. But notice need include in related c file, or else sprintf(float) doesn't work as expected. (2)Change link library to NewLib Nano, it's compact C library , and need click "enable print float" to enable float function, which actually add " -u _printf_float" link symbol. But notice need include in related c file, or else sprintf(float) doesn't work as expected. So the solution surely add flash & RAM consumption in project, but for i.MXRT series it's not problem. Attach is one example for RT1020 EVK. Re: To complement solution how to printf float number in MCUXpresso IDE Thank you! That solved my problem.  Re: To complement solution how to printf float number in MCUXpresso IDE Hi @daweiyou  Thank you so much for your contribution. The information was pretty helpful and it might be helpful for many people. Thank you again. Best Regards. Pablo Avalos.

Custom S32G399A board: No frames cross switch-facing RGMII bus in either direction Board: Custom S32G399A based module, derived from S32G-VNP-RDB3. PFE_MAC1 connected via RGMII (PE_02–PE_13) to an NXP SJA1110A switch port 2, configured as the DSA CPU port (in-tree sja1105 driver, kernel 6.x BSP43.0). Topology: - PFE_MAC0: SGMII via SerDes1 lane1, Mode 1 - PFE_MAC1: RGMII to SJA1110A port 2 (DSA CPU port) — the port in question - PFE_MAC2: SGMII via SerDes0 lane1 The S32G MACs are configured as follows: +---------+--------------+------------------+ |                    | LANE 0               | LANE 1                        | +---------+--------------+------------------+ | SERDES0    | GMAC (SGMII) | PFE_MAC2 (SGMII)  | | SERDES1      | NOT USED        | PFE_MAC0 (SGMII) | +---------+--------------+------------------+ Full U-Boot hwconfig: hwconfig=pcie0:mode=sgmii,clock=ext,fmhz=100,xpcs_mode=both;pcie1:mode=sgmii,clock=ext,fmhz=100,xpcs_mode=0 pfeng_mode=enable,sgmii,rgmii,sgmii DTS for port@2 (switch side): port@2 { reg = <2>; label = "OBC-1"; ethernet = <&pfe_netif1>; phy-mode = "rgmii"; rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; fixed-link { speed = <1000>; full-duplex; }; }; DTS for pfe_netif1 (MAC side): &pfe_netif1 { phy-mode = "rgmii"; status = "okay"; fixed-link { speed = <1000>; full-duplex; }; }; PFE_MAC1 (pfe1) link state — confirmed up and correctly configured at the Linux/driver level: dmesg at boot: [ 5.264108] pfeng 46000000.pfe: netif name: pfe1 [ 5.274127] pfeng 46000000.pfe: netif(pfe1) linked phyif: 1 [ 5.279692] pfeng 46000000.pfe: netif(pfe1) mode: std [ 5.284853] pfeng 46000000.pfe: netif(pfe1) HIFs: count 1 map 02 [ 6.012884] pfeng 46000000.pfe pfe1 (uninitialized): Subscribe to HIF1 [ 6.019438] pfeng 46000000.pfe pfe1 (uninitialized): Host LLTX disabled [ 6.026270] pfeng 46000000.pfe pfe1 (uninitialized): Enable HIF1 [ 6.032374] pfeng 46000000.pfe pfe1 (uninitialized): setting MAC addr: 00:04:9f:be:ef:01 [ 6.040545] pfeng 46000000.pfe pfe1 (uninitialized): PTP HW addend 0x80000000, max_adj configured to 46566128 ppb [ 6.060939] pfeng 46000000.pfe pfe1 (uninitialized): Registered PTP HW clock successfully on EMAC1 [ 6.070441] pfeng 46000000.pfe pfe1: registered [ 6.207482] pfeng 46000000.pfe pfe1: configuring for fixed/rgmii link mode [ 6.214306] pfeng 46000000.pfe pfe1: Set TX clock to 125000000Hz [ 6.220158] pfeng 46000000.pfe pfe1: Link is Up - 1Gbps/Full - flow control off [ 5.257995] pfeng 46000000.pfe: EMAC0 interface mode: 4 [ 5.290707] pfeng 46000000.pfe: EMAC1 interface mode: 9 [ 5.323320] pfeng 46000000.pfe: EMAC2 interface mode: 4 [ 5.354571] pfeng 46000000.pfe: Interface selected: EMAC0: 0x4 EMAC1: 0x9 EMAC2: 0x4 [ 5.382609] pfeng 46000000.pfe: TX clock on EMAC0 for interface sgmii installed [ 5.390050] pfeng 46000000.pfe: RX clock on EMAC0 for interface sgmii installed [ 5.404998] pfeng 46000000.pfe: TX clock on EMAC1 for interface rgmii installed [ 5.419918] pfeng 46000000.pfe: Defer enabling of RX clock on EMAC1 for interface rgmii (ret: -5) [ 5.434235] pfeng 46000000.pfe: TX clock on EMAC2 for interface sgmii installed [ 5.448374] pfeng 46000000.pfe: RX clock on EMAC2 for interface sgmii installed [ 5.667058] pfeng 46000000.pfe: EMAC timestamp external mode bitmap: 0 [ 5.998447] pfeng 46000000.pfe pfe0 (uninitialized): Registered PTP HW clock successfully on EMAC0 [ 6.060939] pfeng 46000000.pfe pfe1 (uninitialized): Registered PTP HW clock successfully on EMAC1 [ 6.130296] pfeng 46000000.pfe pfe2 (uninitialized): Registered PTP HW clock successfully on EMAC2 [ 6.215040] pfeng 46000000.pfe: RX clock on EMAC1 for interface rgmii installed Live DTB confirms the kernel matches the source DTS: # cat /proc/device-tree/soc/pfe@46000000/ethernet@11/phy-mode rgmii ip a output: 6: pfe1: mtu 1536 qdisc mq state UP group default qlen 1000 link/ether 00:04:9f:be:ef:01 brd ff:ff:ff:ff:ff:ff inet6 fe80::204:9fff:febe:ef01/64 scope link All SJA1110 DSA slave ports correctly enumerated. This confirms the sja1105 DSA driver bound successfully to pfe1 as the CPU port/DSA master and parsed the static config without error. Clock tree: both TX and RX RGMII clocks enabled and attached to the correct consumer: # cat /sys/kernel/debug/clk/clk_summary | grep pfe1 pfe1_tx_mii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id pfe1_rx_mii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id pfe1_tx_rmii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id pfe1_rx_rmii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id pfe1_tx_rgmii 1 1 0 125000000 0 0 50000 Y ethernet@11 tx_rgmii pfe1_rx_rgmii 1 1 0 125000000 0 0 50000 Y ethernet@11 rx_rgmii pfe1_tx_sgmii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id pfe1_rx_sgmii 0 0 0 125000000 0 0 50000 Y deviceless no_connection_id So pfe1 is UP, LOWER_UP, correctly bound to the SJA1110 as DSA master, running in RGMII mode with both clocks enabled — this rules out pfe1 being down, unbound, or misconfigured at the Linux/driver level. The open question is specifically whether frames actually cross the physical RGMII pins between PFE_MAC1 and SJA1110 port 2. Issue: No traffic appears to cross the RGMII bus between PFE_MAC1 and SJA1110 port 2 in either direction, despite everything on both sides of that bus being independently up: Test 1 — S32G -> switch direction Setup: ip addr add 192.168.1.100/24 dev EPS-100bt1-9 ethtool -S pfe1 | grep '^ p02_' > before tcpdump -i pfe1 -e -nn -c 20 > capture.txt & arping -c 10 -I EPS-100bt1-9 192.168.1.6 ethtool -S pfe1 | grep '^ p02_' > after # arping -c 10 -I EPS-100bt1-9 192.168.1.6 ARPING 192.168.1.6 from 192.168.1.100 EPS-100bt1-9 Sent 10 probes (10 broadcast(s)) Received 0 response(s) $ cat capture.txt tcpdump: verbose output suppressed, use -v[v]... for full protocol decode listening on pfe1, link-type NULL (BSD loopback), snapshot length 262144 bytes 18:08:36.352535 AF Unknown (4294967295), length 64: 0x0000: ffff 0004 9fbe ef01 dadb 0c09 0806 0001 ................ 0x0010: 0800 0604 0001 0004 9fbe ef01 c0a8 0164 ...............d 0x0020: ffff ffff ffff c0a8 0106 0000 0000 0000 ................ 0x0030: 0000 0000 0000 0000 0000 0000 ............ [... 9 more identical ARP frames, all correctly DSA-tagged (dadb 0c09) and well-formed, plus one unrelated IPv6 background frame interleaved ...] # diff before after --- before +++ after @@ -1,4 +1,4 @@ - p02_: 1 + p02_: 0 p02_n_runt: 0 p02_n_soferr: 0 p02_n_alignerr: 0 # grep n_rxfrm before after before: p02_n_rxfrm: 0 after: p02_n_rxfrm: 0 Test 2 — switch -> S32G direction Setup Partner board is a separate SJA1105 switch based board. # ping -c 10 -I t1-6 192.168.1.100 (run on a separate SJA1105/1110-family switch board connected to our port 9 / 100BASE-T1 / EPS-100bt1-9) # diff before after (ethtool -S EPS-100bt1-9) - n_rxfrm: 0 + n_rxfrm: 9 <- port 9 physically received 9 frames from the wire # diff before after - p02_n_txfrm: 0 + p02_n_txfrm: 9 <- switch fabric forwarded all 9 toward the CPU port # tcpdump -i pfe1 -e -nn -c 20 (same window) listening on pfe1, link-type NULL (BSD loopback), snapshot length 262144 bytes [-- nothing captured --] Port 9 received 9 real frames; the fabric forwarded all 9 toward port 2 — but nothing arrived at pfe1. So the SJA1110's own fabric counters show all 9 frames successfully forwarded from port 9 to port 2's egress. But tcpdump -i pfe1 -e -nn on the S32G during this exact test shows NOTHING received. So the DSA/software layer on the S32G side believes it's sending (case 1). The switch's internal fabric believes it's sending toward the CPU port (case 2). Neither side has any confirmation that the other actually received anything across the physical RGMII bus. Every layer adjacent to this bus works individually; the bus itself has no confirmed successful crossing in either direction. What's been ruled out so far: - pfeng_mode / hwconfig (xpcs_mode) — confirmed correct; EMAC1 mode is RGMII (0x9), not SGMII (it was previously misconfigured as SGMII due to xpcs_mode=both on SerDes1 forcing PFE_MAC1's XPCS into SGMII; corrected to xpcs_mode=0 since PFE_MAC0 alone only needs XPCS0) - PFE_MAC1 TX/RX clock enablement — confirmed enabled at the correct rate (125MHz) in clk_summary - DSA tagging and CPU port binding — confirmed working (port netdevs exist, frames get tagged with the correct destination port in the DSA header) - SJA1110 internal fabric/forwarding — confirmed working between two other ports (9 and 2) using real external traffic - BASE-T1 link partner — confirmed passing real frames into the switch (port 9 n_rxfrm increments from genuine wire traffic) What hasn't been ruled out / open questions: - Whether 1000 Mbps RGMII with zero internal delay on both MAC and switch sides (rx/tx-internal-delay-ps=0, plain "rgmii" not "rgmii-id") is compatible without delay added by board trace length — have not yet tried forcing the link down to 100 Mbps as a timing-margin test 1. Is rx/tx-internal-delay-ps=0 on both ends at 1000 Mbps RGMII expected to work, or does this combination typically require delay compensation unless the PCB explicitly accounts for it? 2. Am I missing any other configuration? Happy to share full register dumps, if required. Appreciate any pointers before we probe the PE_02-13 bus with a logic analyzer (limited probe access due to board layout, so it is not so convenient currently. Thanks. Re: Custom S32G399A board: No frames cross switch-facing RGMII bus in either direction Hi @Joey_z @db16122 I am attaching the relevant sections of the schematics here. The connection flow is as follows: We use PE_02 to PE_13 on the S32G3 chip shown in s32g3_pfe_mac1_connections.png for the PFE_MAC1. They go to a board to board connector (shown in Board_to_board_connector.png) that routes these signals to  a different board that has the switch. The switch connections are shown in SJA1110_A.png and SJA1110_B.png. So the connection is PE_xx pins -> board connectors -> switch (SJA1110) Please let me know if you have any questions. I have also raised a support ticket ( #00990408) with the same details.  Re: Custom S32G399A board: No frames cross switch-facing RGMII bus in either direction Hi,pcentauri92 Thank you for your reply. Please provide me with the schematic diagrams related to your ETH, particularly the ones for PFE_MCA1 and SJA1110 sections. You can create an internal support system case. In the information description, @Joey, then provide your schematic diagram information. Refer to this website: https://support.nxp.com BR Joey Re: Custom S32G399A board: No frames cross switch-facing RGMII bus in either direction Hi @Joey_z , Thank you for the response. The module in question here is a custom design that uses the S32G399A chip along with the NXP SJA1110A ethernet switch. We based this design on the S32G-VNP-RDB3 development platform but we made quite a few changes from the base design. The PFE_MAC1 using RGMII is one of those changes.  I am also attaching the dts file override where we change the PFE_MAC1 mode and pinmux here. PFE_MAC1 mode configuration: /* pfe_mdio1 is already disabled in the base config in s32gxxxa-rdb.dtsi */ &pfe_mdio1 { /* occupied by GMAC0 */ status = "disabled"; }; /* * pfe_netif1 = PFE_MAC1 — management port to Switch-A port 2. * Overrides the base "sgmii" stub in s32gxxxa-rdb.dtsi. * Plain "rgmii" (no -id/-txid) since both MAC and switch add zero delay. * No phy-handle: the link partner is the SJA1110A switch, described as a * fixed-link on switch port@2. MDIO is not needed for link management here. */ &pfe_netif1 { phy-mode = "rgmii"; status = "okay"; fixed-link { speed = <1000>; full-duplex; }; }; PFE_MAC1 pinmux: /* * PFE_MAC1 RGMII pinmux — management port to Switch-A. * * All RX pad SSS values confirmed from S32G3 IOMUX spreadsheet. * TX path: output pads only, no IMCR needed. * RX path: input pads + IMCR registers to route pads into PFE_MAC1. * * Note: PE_07 (TXD3) uses FUNC3, not FUNC2. Similarly PE_08 (RX_CLK) output uses FUNC3; its IMCR (CR#859) uses FUNC2. */ pfe1rgmii_pins: pfe1rgmii_pins { /* TX outputs: PE_02=TX_CLK, PE_03=TX_EN, PE_04=TXD0, PE_05=TXD1, PE_06=TXD2 PE_07 (TXD3) */ pfe1rgmii_grp0 { pinmux = , /* PE_02: PFE_MAC1_TX_CLK */ , /* PE_03: PFE_MAC1_TX_EN */ , /* PE_04: PFE_MAC1_TXD0 */ , /* PE_05: PFE_MAC1_TXD1 */ , /* PE_06: PFE_MAC1_TXD2 */ ; /* PE_07: PFE_MAC1_TXD3 */ output-enable; slew-rate = ; }; /* RX inputs — pads set to FUNC0 (input mode); routing into PFE_MAC1 is handled by the IMCR entries in pfe1rgmii_grp2 below. NXP input mux pattern: pad=FUNC0 + IMCR=FUNC2 */ pfe1rgmii_grp1 { pinmux = , /* PE_08: input */ , /* PE_09: input */ , /* PE_10: input */ , /* PE_11: input */ , /* PE_12: input */ ; /* PE_13: input */ input-enable; slew-rate = ; }; /* IMCR input mux — selects which pad drives each PFE_MAC1 RX signal. CR#866 routes PE_02 (TX_CLK pad) back into PFE_MAC1_TX_CLK_I; required even for RGMII TX because the MAC samples its own TX_CLK internally. All entries at FUNC2 per S32G3 IOMUX spreadsheet. */ pfe1rgmii_grp2 { pinmux = , /* CR#866: PFE_MAC1_TX_CLK_I ← PE_02 */ , /* CR#859: PFE_MAC1_RX_CLK_I ← PE_08 */ , /* CR#865: PFE_MAC1_RXDV_I ← PE_09 */ , /* CR#861: PFE_MAC1_RXD_I[0] ← PE_10 */ , /* CR#862: PFE_MAC1_RXD_I[1] ← PE_11 */ , /* CR#863: PFE_MAC1_RXD_I[2] ← PE_12 */ ; /* CR#864: PFE_MAC1_RXD_I[3] ← PE_13 */ }; }; Please let me know if you need any other information.    Re: Custom S32G399A board: No frames cross switch-facing RGMII bus in either direction any schematics sharing from hardware side for RGMII bus between PFE_MAC1 and SJA1110 port 2 ? Re: Custom S32G399A board: No frames cross switch-facing RGMII bus in either direction Hi，pcentauri92 Thank you for your detail information According to my understanding, there seems to be a problem with the communication when using PFE_MAC1 RGMAII and Port 2 of SJA1110A on your development board. Is that correct? The default configuration of S32G-VNP-RDB3 is that PFE_MAC0/1 operates in SGMII mode and is connected to SJA1110. On your development board, why did you consider using RGMII mode? It is recommended to modify the corresponding software configuration. BR Joey

Debug Flash Script Overriding "Protect Internal Flash Memory Area" Settings Hi, We are currently testing an application jump from App1 to App2 on the FRDM-S32K344. Our application layout is: App1 Start Address: 0x00400000 App2 Start Address: 0x00500000 For debugging, we are using separate debug configurations with flash memory protection enabled. When debugging App1, the memory protection range is configured as: 0x00500000 to 0x005FFFFF (to protect App2) When debugging App2, the memory protection range is configured as: 0x00400000 to 0x004FFFFF (to protect App1) However, during programming through the debug configuration, we observe that the protected flash region is still being erased, even though the memory protection range has been configured. Could anyone clarify the following? Is the Flash Programmer expected to honor the configured memory protection ranges during erase/program operations? Is there any additional configuration required to prevent the protected flash region from being erased? Has anyone successfully used memory protection to preserve another application while programming only one application on the FRDM-S32K344? Logs and LD files are attached for your ref. we are using on board PE debugger Any guidance or recommendations would be greatly appreciated. Thank you. Re: Debug Flash Script Overriding "Protect Internal Flash Memory Area" Settings Hi @Avinpat123  I did quick test in the same version of S32 Design Studio to be sure it is working. I used the same setup – one application forced to 0x40_0000 while 0x50_0000 area is configured to be preserved and second application forced to 0x50_0000 while 0x40_0000 area is configured to be preserved: Here are the logs which shows that this configuration is taken into account: And I can see in the memory that the content is really preserved, so it works as expected. I  saw in your screenshots that you configured the address range but the “Preserve this range” check box is not enabled. Isn’t that the problem? Regards, Lukas Re: Debug Flash Script Overriding "Protect Internal Flash Memory Area" Settings Hi @ lukaszadrapa  Thanks for the reply yes as you told check box was the issue now it is working fine

S32K3 ADC 外部チャネルの利用 こんにちは。NXPチーム S32K3 ADCの外部チャネルの使い方 . Re: S32K3 ADC Use of external channels こんにちは、 @VaneBさん これに関して、追加の質問があります。 もし私のデザインにマルチマックスがなくても、例えばセンサ1にADC1_X[0]、センサ2にADC1_X[1]、そしてADC1_Xセンサ3にだけ使いたい場合は、MAピンをGPIO出力ピンなど他の用途で再利用してLEDを駆動することは可能でしょうか? 私のデザインはs32k344をベースにしています Re: S32K3 ADC Use of external channels NPXチームの皆様、こんにちは。 このトピックに関連して、以下の図のようなSCHを実装することが可能かどうか確認していただけますか? サポートありがとうございます。 Re: S32K3 ADC Use of external channels @VaneB ご協力いただき、誠にありがとうございました。 Re: S32K3 ADC Use of external channels こんにちは@Niuyanlin 各ADCは外部アナログ多重化器の8チャネル中1チャネルを選択するために使う3つの外部デコード信号(MA)を提供し、最大4つのマルチプレクサを設置して32の外部チャネルを接続できます。つまり、これら4つのマルチプレクサは同じMA信号を共有します。 ADCは変換対象の現在のチャネルに基づき、これらの外部アナログ多重化器を制御するよう自動設定します。マスクレジスタのビットに応じて、対応する「X」ピンがサンプリングされ、その結果が「MA」と「X」の組み合わせに対応する場所に格納されます。 当社の開発ボードには外部アナログ多重化装置が設計されていないため、そのような例は実装されていません。 Re: S32K3 ADC Use of external channels こんにちは。ヴェインB あなたのプロンプトによると、RTDで外部チャネルADCを使った例が見つかりません。もし対応するルーティンがあれば、ぜひ送っていただけると嬉しいです。どうもありがとうございます。 Re: S32K3 ADC Use of external channels こんにちは@Niuyanlin RTDで役立つかもしれないADCの実装例が見つかります。 BR VaneB

MBDT中的CAN总线处理 我正在使用 NXP 的 MBDT for S32K344 来配置 FlexCAN0。我想了解 CAN 消息处理的哪些部分由 NXP 模块/工具箱管理，哪些部分需要由应用程序处理。 仲裁和缓冲区处理是否由驱动程序/工具箱管理？例如：如果我先发送 0x18FEF111，那么 0x18FEEF00 都不会出现在总线上。但如果先发送 0x18FEEF00，则两者都会被发送。当两者同时触发信号时，只会显示其中一个。 那么，在同时发送多个帧时，是否需要为每个消息 ID 分配专用的发送硬件对象？ MBDT 或 SDK 是否处理消息优先级，并在未收到 ACK 时自动重试？ 如果高优先级 ID 失败（例如，没有收到 ACK），是否会阻塞其他消息？我们如何检测并从中恢复？ 为了避免阻塞或消息丢失，模型中是否需要手动管理缓冲区分配或传输时序？ 在 MBDT 中配置多个 Tx 消息 ID 的最佳方法是什么？使用动态缓冲区。 请明确哪些是内部处理的，哪些是我们需要在应用程序中处理的。 示例模型 Re: CAN Bus Handling in MBDT 你好@SorinIBancila ， 我遇到了需要发送的帧数超过可用 HTH 硬件对象数量的情况。由于 S32CT 无法利用 CanIf 发送缓冲实现，您能否推荐一种基于 Simulink 的缓冲解决方案来解决此问题？ 谢谢，此致敬礼！ 桑德什 Re: CAN Bus Handling in MBDT 你好， 32 个 Can Hw 对象数量并非限制。根据你所使用的MCU型号，你还可以进一步提高这个限制。您可以修改 Can Hw Object Count 的数量，但如果您输入的数字过大，S32CT 将报错。 顺祝商祺！ 索林·班奇拉 Re: CAN Bus Handling in MBDT 明白了！如果我需要发送超过 32 条消息，是否应该创建额外的发送硬件对象？另外，在 S32K3 中使用 S32CT，单个 CAN 收发器或控制器下最多可以配置多少个硬件对象？ 想了解在限制条件下，如何以最佳方式构建大型消息集的 HOH。 Re: CAN Bus Handling in MBDT 你好， 你认为一次需要发送多少条信息？ 我已在 S32K358 HVBMS 参考设计上测试了以下场景： 使用单个 TX 硬件对象，并将Can 硬件对象计数设置为 32（以允许缓冲区中最多 32 条消息）。 在 Simulink 中，我向消息缓冲区填充了 32 条消息，随着缓冲区填充的进行，消息优先级也随之增加，以验证仲裁过程。 结果： 正如预期的那样，由于消息缓冲区尚未完全填充，因此发送的第一批消息优先级较低。大约在第 6 条消息时，缓冲区已满，我们可以看到优先级较高的消息会先发送。 由于你想使用单个收发器，因此实际上不可能同时发送所有消息。 顺祝商祺！ 索林·班奇拉 Re: CAN Bus Handling in MBDT 索林，你好 感谢您的意见！ 我想说明在使用动态缓冲区时，在 MBDT 中配置多个 Tx 消息 ID 的最佳方法。就我而言，该控制器用于电动汽车应用，采用基于 J1939 的 CAN 设置，涉及数百个循环消息。 在 S32CT 中为每条消息创建单独的硬件对象似乎既不可扩展也不实用。我希望使用单个 Tx 硬件对象来动态处理多个消息，并通过一个 CAN 接口同时传输它们。 请问针对这种使用场景，推荐的配置或最佳实践是什么？另外，请推荐一些我需要参考的文档，以便了解 MBDT 中配置设置的工作原理和相关函数。 Re: CAN Bus Handling in MBDT 你好， 首先，我想指出的是，S32K3xx 的 MBDT 是基于 S32K3 RTD 的版本。外围设备的配置是在 S32 配置工具中完成的，以便您可以灵活地进行所需的设置。因此，要检查 NXP 的 MBDT S32K3xx 是否支持某个功能，您可以检查外设（在 S32K3 RTD 中）使用的源代码及其在 S32 配置工具中的可用设置。 在工具箱中，您可以在此处找到 FlexCAN 外设的实现： {toolboxRoot}/src/S32K3_RTD/SW32K3_S32M27x_RTD_R21-11_6.0.0/eclipse/plugins/Can_43_FLEXCAN_TS_T40D34M60I0R0/ 笔记！根据您使用的 MBDT S32K3 版本不同，S32K3 RTD 的名称可能会有所不同。 你问题的答案是基于我的经验，可能并不完全准确。 1、2 和 5：该工具箱不处理任何仲裁，但我不太确定 SDK 中有哪些选项可用于此目的。在你的示例中，你创建了另一个CanHardwareObject并使用它来发送第二条消息，但这种方法可能难以管理。第二个解决方案可能是增加Can Hw 对象计数，以允许缓冲区中存在更多消息。 3：S32K3 的 MBDT 不处理任何消息优先级。据我所知，FlexCAN 控制器负责重试发送消息，直到收到 ACK 为止，同时将消息阻塞在缓冲区中。 4. 检测消息是否已发送的一种方法是使用硬件中断回调中的CanIf_TxConfirmation中断来标记消息已发送。如果指定的 PDU 没有触发信号中断，则表示该消息未发送。此外，还有一个中断（ CAN_ControllerBusOff ）可用，当满足 CAN 总线关闭的条件时，该中断会产生触发信号。在 S32 配置工具中，有一个选项可以从总线关闭状态自动恢复。 如有任何疑问，请随时回复。 此致， 索林·班奇拉