Inquiry Regarding Firmware Integrity Verification After Bootloader Flashing and Porting Functionalit Dear NXP Support Team, I am currently working on a project involving the S32K146 microcontroller and the S32 Design Studio (S32DS) development environment. My question concerns two topics: After the Bootloader has successfully flashed the firmware, I would like to know if there is a way to verify the integrity of the firmware to ensure that it has been correctly written without any corruption. Could you provide guidance on any available methods or tools for achieving this firmware integrity verification? I am also attempting to port an existing MPC5606 project to the S32K146. Specifically, the original MPC5606 project uses the following code for section manipulation:#pragma push #pragma force_active on #pragma section_sconst_type "_bblk_entry" "_bblk_entry" extern __asm void __start(); const uint32_t bblk_entry_addr = (uint32_t)__start; /*vcus*/ #pragma pop         I would like to know how to implement similar functionality in the S32K146 environment. Could you provide guidance on how to achieve this in the S32K146? Thank you for your time and assistance. I look forward to your response.   Best regards, ChandlerX Re: Inquiry Regarding Firmware Integrity Verification After Bootloader Flashing and Porting Function Hi VaneB, I wanted to express my gratitude for the information you provided. It has been extremely helpful to me. Thank you so much for your support! Best regards, ChandlerX Re: Inquiry Regarding Firmware Integrity Verification After Bootloader Flashing and Porting Function Hi @ChandlerX  1. Please refer to the following link where this topic has been discussed, as it may be helpful to you: Secure boot implementation for boot loader as well as application image security 2. To port the code from the MPC5606 to the S32K146, you will need to adjust it for the GCC compiler used in the S32K146 environment. Unlike the MPC5606, GCC does not use pragmas for section manipulation but instead relies on __attribute__((section(".user_section"))). For further guidance, please refer to the following links: Common Function Attributes HOWTO: Place custom data into flash memory BR, VaneB

当启用 HAB 时，如何使用 U-Boot 启动 Linux 内核？ 我正在使用 i.MX8M Nano。 我已经阅读了 uboot-imx 文档和其他相关材料，现在我能够在启用安全启动和加密启动的情况下启动 U-Boot。 现在，我正在尝试手动加载预构建的内核和 DTB 并使用 booti 命令启动。但是，我遇到了以下错误： 我怀疑该错误是由于内核映像未签名造成的。 u-boot=> fatload mmc 2:1 ${loadaddr} Image 28013056 bytes read in 144 ms (185.5 MiB/s) u-boot=> fatload mmc 2:1 ${fdt_addr} imx8mn-ddr3l-evk.dtb 40155 bytes read in 9 ms (4.3 MiB/s) u-boot=> booti ${loadaddr} - ${fdt_addr} Authenticate image from DDR location 0x40400000... bad magic magic=0xff length=0xffff version=0xff bad length magic=0xff length=0xffff version=0xff Bad version magic=0xff length=0xffff version=0xff Error: Invalid IVT structure Authenticate Image Fail, Please check 当启用 HAB 时，如何使用 U-Boot 启动 Linux 内核？ 如果需要签名，我应该如何对内核进行签名？ 此外，早期指南中描述的方法似乎假设了一个独立的环境。 如何在 Yocto 中生成与 HAB 兼容的图像？ 顺祝商祺！ 回复：当启用 HAB 时，如何使用 U-Boot 启动 Linux 内核？ 已解决。 原因是没有配置 bootargs。

S32 Design studio for ARM 2.2 License extend Hi,     I will use S32 Design studio for ARM 2.2 , pls help me, tks. Item Description S32 Design Studio for ARM v2.2 Activation Code： 067C-DFBC-9C46-C280 Re: S32 Design studio for ARM 2.2 License extend Hi,  your S32DS license has been extended. 

ブートローダのフラッシュおよびポーティング機能後のファームウェアの完全性検証に関するお問い合わせ NXPサポートチームの皆様へ 現在、S32K146マイコンと開発環境S32 Design Studio(S32DS)のプロジェクトに取り組んでいます。私の質問は2つのトピックに関するものです。 ブートローダーがファームウェアを正常にフラッシュした後、ファームウェアの整合性を確認して、ファームウェアが破損せずに正しく書き込まれていることを確認する方法があるかどうかを知りたいのですが。このファームウェアの整合性検証を実現するために利用可能な方法やツールについて、ガイダンスを提供していただけますか? また、既存のMPC5606プロジェクトをS32K146に移植しようとしています。具体的には、元の MPC5606 プロジェクトでは、セクション操作に次のコードを使用します #pragma。 #pragma force_active オン #pragma section_sconst_type 「_bblk_entry」「_bblk_entry」 extern __asm void __start(); 定数 uint32_t bblk_entry_addr = (uint32_t)__start;/*VCUS*/ #pragma ポップ S32K146環境で同様の機能を実装する方法を知りたいです。これをS32K146で達成するためのガイダンスを提供していただけますか? お時間を割いていただき、ありがとうございました。皆様のご回答をお待ちしております。   よろしくお願いいたします チャンドラーX Re: ブートローダのフラッシュ後のファームウェアの整合性検証とポーティング機能に関するお問い合わせ こんにちはベーンB、 皆様からご提供いただいた情報に感謝の意を表したいと思います。それは私にとって非常に役に立ちました。応援いただき、誠にありがとうございます! よろしくお願いいたします チャンドラーX

How can I configure my device to connect using 802.11n at 2.4GHz 40MHz? I am currently using mlanutl and setting 'bandcfg 31', but I am unable to connect using 802.11n at 2.4GHz 40MHz. To connect at 802.11n 2.4GHz 40MHz, is it necessary to enable 'bit5: AC 2.4G' as mentioned in the 'Usage' section of 'bandcfg'? Also, what does 'AC 2.4G' mean? Re: How can I configure my device to connect using 802.11n at 2.4GHz 40MHz? Dear @mkawa , Band width control or limitation is not implemented on STA side. The better way is to set in on AP or router side.  [Note] It is worthing noticing that disconnection maybe occur if you set only 40M band width to be permitted due to hostapd mechanism. Because hostapd will switch from 40M to 20M when signals quality is bad. For 802.11n, this is regular setting: ...... ht_capab=[HT40+][SHORT-GI-20][SHORT-GI-40] ...... So it is not recommended that you try this! Thanks1 Regards, weidong

如何配置我的设备以使用 2.4GHz 40MHz 的 802.11n 进行连接？ 我目前正在使用 mlanutl 并设置“bandcfg 31”，但无法使用 2.4GHz 40MHz 的 802.11n 进行连接。 要以 802.11n 2.4GHz 40MHz 进行连接，是否需要启用“bandcfg”的“使用”部分中提到的“bit5：AC 2.4G”？ 另外，“AC 2.4G”是什么意思？

GPU stress test in imx8qxp Hi  NXP, How to stress the GPU in imx8qxp, Can you please guide me. Provide sample code for gpu stress test. Re: GPU stress test in imx8qxp Hi @Rita_Wang , Thank you! Re: GPU stress test in imx8qxp Benchmark Tests: /usr/bin/glmark2-es2-wayland Re: GPU stress test in imx8qxp Hi , I found that glmark2 utility is used to stress the gpu, and I just enabled it in the board. glmark2-es2 , glmark-es2-drm , glmark-es2 -wayland , these 3 utilities showing. Among these which should I prefer and can you please provide the commands needed. Re: GPU stress test in imx8qxp We have the GPU sdk that include several examples for stress the GPU on the Linux BSP, also it includes a benchmark for the testing, you can check the hands on I attach to you. The method is the same. Re: GPU stress test in imx8qxp Hi @Rita_Wang , BSP version is imx-5.10.72-2.2.0 . Re: GPU stress test in imx8qxp I will confirm it for you, which version BSP are you using?

imx8qxp での GPU ストレステスト こんにちはNXPの、 imx8qxpでGPUに負荷をかける方法、ガイドしていただけますか。GPU ストレス テストのサンプル コードを提供します。 Re: imx8qxp での GPU ストレステスト こんにちは @Rita_Wang 、 ありがとうございます！ Re: imx8qxp での GPU ストレステスト ベンチマークテスト: /usr/bin/glmark2-es2-ウェイランド Re: imx8qxp での GPU ストレステスト こんにちは glmark2ユーティリティがGPUにストレスを与えるために使用されていることを発見し、ボードで有効にしました。glmark2-es2 , glmark-es2-drm , glmark-es2 -wayland , これらの3つのユーティリティを示しています。これらの中で、私が好むべきであり、必要なコマンドを提供していただけますか。 Re: imx8qxp での GPU ストレステスト 私たちは、Linux BSP上のGPUにストレスを与えるためのいくつかの例を含むGPU SDKを持っています、また、それはテストのためのベンチマークを含んでいます、あなたは私があなたに添付するハンズオンをチェックすることができます。方法は同じです。 Re: imx8qxp での GPU ストレステスト こんにちは @Rita_Wang 、 BSP のバージョンは imx-5.10.72-2.2.0 です。 Re: imx8qxp での GPU ストレステスト 確認します、どのバージョンのBSPを使用していますか?

C Compiler error Hi， I am using the S32G3 development board to port rtos, there is a problem with the compilation, see the picture below, how do I choose the Libraries support, and if I want to solve the problem of "cannot read spec file 'nano.specs'",I What should I do? S32G-VNP-RDB3  Re: C Compiler error Hi @jiajun,  Thank you for contacting NXP Support! I have reviewed your issues with the S32G example, and it seems that you met with the same issues that are described on the following community thread: unable to build Uart_Example_S32G274A_M7 - NXP Community Please have a look to that thread and tell me if you have questions. 

imx8qxp 中的 GPU 压力测试 你好，恩智浦， 如何在 imx8qxp 中强调 GPU，您能指导我吗？提供gpu压力测试的示例代码。 回复：imx8qxp 中的 GPU 压力测试 你好@Rita_Wang ， 谢谢你！ 回复：imx8qxp 中的 GPU 压力测试 基准测试： /usr/bin/glmark2-es2-wayland 回复：imx8qxp 中的 GPU 压力测试 你好 ， 我发现 glmark2 实用程序用于强调 gpu，我刚刚在主板上启用了它。glmark2-es2 ， glmark-es2-drm ， glmark-es2 -wayland ，显示这 3 个实用程序。其中我应该选择哪一个？您能否提供所需的命令？ 回复：imx8qxp 中的 GPU 压力测试 我们有 GPU sdk，其中包含几个用于在 Linux BSP 上强调 GPU 的示例，还包括一个测试基准，您可以检查我附给您的实践。方法是一样的。 回复：imx8qxp 中的 GPU 压力测试 你好@Rita_Wang ， BSP版本是imx-5.10.72-2.2.0。 回复：imx8qxp 中的 GPU 压力测试 我帮您确认一下，您使用的是哪个版本的BSP？

[imx8mp] use FLEXCAN2 controller by M7 Hello everyone, I am new here and I got my hands on an imx8mp µC. On the µC I want to run an application which needs two CANs. For this µC are CAN demo implementations available, which I am able to run on my Hardware. To run one of this examples on FLEXCAN2 instead of FLEXCAN1 the board configuration has to change. In particular I added the PIN and Clock config for FLEXCAN2. Currently the initialization for FLEXCAN1 is running fine, but the initialization of FLEXCAN2 is stuck while disabling the FLEXCAN Module.  Within the Demo Code is a init for an specific GPIO pin. /* GPIO5_IO05 is used to control CAN1_STBY which is ebaled active high */ gpio_pin_config_t config = {kGPIO_DigitalOutput, 1, kGPIO_NoIntmode}; GPIO_PinInit(GPIO5, 5U, &config); I do not set an GPIO for CAN2 and I think there is my issue. Does anyone know where I can find the information which GPIO I have to use for CAN2? Thanks for your help in advance. Greetings schwammal i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: [imx8mp] use FLEXCAN2 controller by M7 Hi Aldo, thanks for this information. From the Files you have shared I assume, that I have to set the MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 to high to switch for CAN2. The initialization is still not working properly, but I will talk to my colleagues about it bevor posting an update. Best regards schwammal Re: [imx8mp] use FLEXCAN2 controller by M7 Hello, it is actually a bit difficult to use FlexCAN2 on the EVK, as the pins used for this one are shared with PDM and also there is a switch that need to be enabled in order for it to actually be selected. So, it is not enough to just mux the FlexCAN correctly but to set this switch as well, to see an example of such implementation one could refer to the Linux Device tree: https://github.com/nxp-imx/linux-imx/blob/lf-6.6.y/arch/arm64/boot/dts/freescale/imx8mp-evk.dts#L422 https://github.com/nxp-imx/linux-imx/blob/lf-6.6.y/arch/arm64/boot/dts/freescale/imx8mp-evk.dts#L1077 https://github.com/nxp-imx/linux-imx/blob/lf-6.6.y/arch/arm64/boot/dts/freescale/imx8mp-evk.dts#L1090 Best regards/Saludos, Aldo.

Problems with elf File generated by MCUXpresso Good afternoon,  due to problems with the on board debug probe on the FRDM-K66 board and problems of this board with Segger J-Link Plus, I want to use Segger's Ozone and generate the elf file with MCUXPresso.  After Debug->Start Debug Session -> Download and Reset Program the program should start executing the function main(). The corresponding map file shows that main() starts at 0x428 in the program memory. extract from frdmk66f_lwip_tcpecho_bm.map .text.main 0x00000428 0x240 ./source/lwip_tcpecho_bm.o 0x00000428 main In Ozone at the disassembly window everything looks alright but the code line in the file scope window does not match to the reset conditions. If I understand elf files correctly, the C-code and the corresponding executabble code are linked together. Here, the executable code starts at the right position but is not linked to the corresponding c-code which would be the first non comment or signal declaration line in main(). Thanks in advance for your help Christof Abt Re: Problems with elf File generated by MCUXpresso Hello, I am glad to hear that.  Any new issues, welcome to create a new post. BRs, Celeste Re: Problems with elf File generated by MCUXpresso Hello all,  I have just found out a working designflow with the FRDM-K66F evaluation board. The on board debugger often dies when the board is connected to a Windows 10 computer. I think it is a problem with the software on the additional microcontroller on the board.  I connected a SEEGER J-link and the connection was established but afterwards the whole system stalled. Yesterday I updated the MCUXpresso IDE to version 24.12.148 and this combination of an external debugger, the FRDM-K66F and the MCUXpresso seems to work.  My problem is solved! Thanks for your support Re: Problems with elf File generated by MCUXpresso Hello @ChristofAbt , Thanks for your post. We don't have Ozone on our side, so I'm unable to replicate your issue in the exactly same way. I used the on-board debugger to debug the axf file generated by MCUXPresso and didn't encounter any problems. In the .map file: .text.main 0x000005fc 0x188 ./source/lwip_tcpecho_bm.o 0x000005fc main Through the disassembly in the following way. You can see from the following picture that there is no problem.   You mentioned that your ELF file was generated by MCUXpresso. Could you please tell me how exactly you generated it? BRs, Celeste Re: Problems with elf File generated by MCUXpresso Sorry, I have forgotten to add the screenshot

PN7642 MCUXpresso SDK v02.15.00 example import Hello!  I`m using MCUXpresso IDE v11.9.1 [Build 2170] [2024-04-19]. After  PN7642 MCUXpresso SDK v02.15.00 installation I`m trying to import example from SDK but I cannot complete example import because of error that is shown after example selection  There was no such problem with previous SDK version. What can be the reason and how to fix it?  Thanks in advance. Artem Re: PN7642 MCUXpresso SDK v02.15.00 example import Thank you! Now all is OK. Re: PN7642 MCUXpresso SDK v02.15.00 example import Hello @ArtemPN, Hope you are doing well. Please, unzip the SDK package by right clicking the file in the Installed SDKs window > Unzip archive: After this, try importing a project from the SDK. Please, let me know your findings. Regards, Eduardo.

Reason for disable of clock gate before setting the module clock Hi all, I noticed that void BOARD_BootClockRUN(void) disables clock gates before configuring the module clocks in the SDK. Could someone explain the reason? For example, uart module Best regards, Doris Re: Reason for disable of clock gate before setting the module clock Hi @MCW  Thank you for your interest and my apologies for the delayed respose! The main reason is to safely change the  clock mux settings for a clock. Take for example the LPUART clock figure you attached: Yes, LPUART clocks  are shut down, but after that the mux settings for LPUART clocks are changed. This is my interpretation according to section 14.6.1.7 Clock Switching Multiplexers of the RT1060 RM, there are some asynchronous muxes, that could cause undersired clock glitches.  Also the BOARD_BootClockRUN(void) is auto generated by the Config Tool's Clock Tool,  if a clock is disabled in the Clocks tool diagram, it is expected that will be disabled on the generated code.  I hope this could help you! Diego

Setting S32K312 PLL then system will reset Hi All, The customer setting S32K312 PLL then system will reset, attached file is the customer sample code. could you give me some comments? thanks. FUNC(void, SYSDAL_APPL_CODE) SysDal_DriverInitZero(void) {     OsIf_Init(NULL_PTR);     /* Initialise MCU Driver */ #if (MCU_PRECOMPILE_SUPPORT == STD_ON)     Mcu_Init(NULL_PTR); #else     Mcu_Init( &Mcu_Config ); #endif     /* Set the CPU Clock to the PLL */ #if (MCU_INIT_CLOCK == STD_ON)     Mcu_InitClock(McuClockSettingConfig_HighPerf);  // only do this setting, system will reset every one second.  #endif #if(MCU_NO_PLL == STD_OFF)     /* Wait until the PLL is locked */     while (MCU_PLL_LOCKED != Mcu_GetPllStatus()); //include this setting, system will reset one time only.     /* Activate the PLL Clock */     Mcu_DistributePllClock(); //include this setting, system will reset one time only. #endif/*MCU_NO_PLL == STD_OFF*/     /* Initialize PORT */     Port_Init( &Port_Config );     /* Set the MCU to RUN mode */     Mcu_SetMode(McuModeSettingConf_Run); } Main Loop     for (;;) {                 (void)Dio_FlipChannel((Dio_ChannelType)DioConf_DioChannel_View1);     } Re: Setting S32K312 PLL then system will reset Please refer to the discussion in HSE PLL configuration. Re: Setting S32K312 PLL then system will reset Hi Robin Thank for your reply, the system reset problem is fixed. One more question, S32K3xx_DCF_clients.xlxs mentions HSE_CLK_MODE_AND_GSKT_CTRL register can set to 1x then HSE clock can set up to 120MHz, but how to change register setting? Because I can't find HSE_CLK_MODE_AND_GSKT_CTRL register in reference manual, I have found related register is HSE_CLK_MODE_OPTION, but that is read only register. Thanks. Re: Setting S32K312 PLL then system will reset Hi Please check if it is related to the reasons mentioned in the following discussion: If I don't give s32k312 delay, the CAN stop during operation I checked your Clock_Ip_PBcfg.c, and it seems to be caused by it: { AIPS_SLOW_CLK, 4U, { 0U, } }, { HSE_CLK, 1U, { 0U, } }, Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

IMX93 - AHAB セキュアブート - SRKテーブル NXPの専門家の皆さん、こんにちは。 私はIMX93プロセッサでAHAB SecureBootを勉強しており、証明書を生成するためにCSTツールを使用しています。 多くの例は、4つのリーフ(SRKn、1から4までのn)を持つPKIツリーの生成を示しています。 生成後、SRK_TableとSRK_TableFuseを生成しなければなりません。 SRK_Tableは画像に追加され、SRK_TableFuseをeFuseにフラッシュする必要があります。 CST ToolはSRK_TableFuseを16ワードとして生成しますが、リファレンスマニュアルには16個のヒューズ(Yが0から15までのOES_SRKHy)がありますが、そのうちのいくつかは予約されています。 これらのeFuse(8から15までのヒューズ)もフラッシュできますか? さらに、ターゲットに対して 1 つの証明書のみを含む SRK テーブルを生成できますか? どうもありがとうございます！ 日時:IMX93 - AHABセキュアブート - SRKテーブル git の例では、証明書は sha384 で生成されています。

iMX8DX SCU reset when booting with M4 powered up Hi ! I am working on an application for the cortex M4 on my board. I'm dealing with a Colibri iMX8DX v1.0 E mounted on a Toradex Aster v1.1 B on which I flashed a Linux embedded v7.1 Minimal. I rerouted the debug console of the Cortex M4 to the UARTB (or UART0) because the 144 and 146 SODIMM pins that would be connected to the tightly coupled UART of the M4 were not connected on the Aster Card. Following this, I was able to run some examples from the MCUXpresso SDK and see their result on my debug console. Now, when I try to boot Linux after launching the m4boot_0 command in U-Boot, the kernel almost finishes its initialization before reset with "Reset cause: SCFW fault reset". Just so I avoid any weird interference with badly controlled pins, the firmware I am currently attempting to make work alongside Linux is the looped Hello World demo from the MCUXpresso SDK. The boot log is attached to this message. I have no idea what causes this error, any tips would be so welcome. i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Re: iMX8DX SCU reset when booting with M4 powered up Thanks for your response @Manuel_Salas , I just found the problem, actually. I was getting desperate because this behavior kept happening despite putting a simpler program in, attempting multiple device trees and overlays... The problem appears to be the BSP I was using, I read somewhere a few minutes ago that version 7.1.0 had trouble dealing with the m4 and flashing the version 6.8 instead fixed it all. Best regards, Tom Re: iMX8DX SCU reset when booting with M4 powered up Hello @Sselas  I hope you are doing very well. Sometimes this happens when core M4 is trying to use a peripheral that Cortex A is also trying to use with Linux, Please be sure that you are not using the same peripheral in both sides, or change your Linux Device tree to avoid it. Best regards, Salas.

IMX93 - AHAB SecureBoot - SRK TABLE Hello NXP experts, I am studying AHAB SecureBoot on IMX93 processor, and I am using CST tool in order to generate certifcates. A lot of example shows a PKI tree generation with 4 leafs (SRKn, n from 1 to 4). After the generation, I have to generate the SRK_Table and the SRK_TableFuse. The SRK_Table is appended on the image, and after I have to flash SRK_TableFuse into eFuse. CST Tool generates SRK_TableFuse as 16 words, but on the reference manual I have 16 fuse (OES_SRKHy with Y from 0 to 15), but some of them are RESERVED, can I flash also these eFuses (fuse from 8 to 15)? More over, Can I generate a SRK Table with only one certificate for my target? Thanks a lot! Re: IMX93 - AHAB SecureBoot - SRK TABLE In the example from git, the certificates were generated with sha384! Re: IMX93 - AHAB SecureBoot - SRK TABLE Hello @il_ciancio  can I flash also these eFuses (fuse from 8 to 15)? -> No, please have a reference 9x_secure_boot for i.MX93 Can I generate a SRK Table with only one certificate for my target? -> In AHAB, it requires always 4 SRKs. Regards Harvey Re: IMX93 - AHAB SecureBoot - SRK TABLE Hello,  about the SRK table to be fused, i have found an error during the generation. The correct command with CST tools for IMX9 is showed in: uboot-imx/doc/imx/ahab/introduction_ahab.txt at lf_v2024.04 · nxp-imx/uboot-imx In i.MX 8ULP/9x, the expected SRK HASH is of 256 bit. $ cd ../crts/ $ ../linux64/bin/srktool -a -d sha256 -s sha384. Why is there -s sha384  (-s, --sign_digest) ?

IMX93 - AHAB 安全启动 - SRK 表 您好，恩智浦专家， 我正在研究 IMX93 处理器上的 AHAB SecureBoot，并且正在使用 CST 工具来生成证书。 许多示例展示了具有 4 个叶子（SRKn，n 从 1 到 4）的 PKI 树生成。 生成之后，我必须生成 SRK_Table 和 SRK_TableFuse。 SRK_Table 附加在图像上，之后我必须将 SRK_TableFuse 刷入 eFuse。 CST 工具生成 SRK_TableFuse 为 16 个字，但在参考手册中我有 16 个保险丝（OES_SRKHy，Y 从 0 到 15），但其中一些是保留的， 我也可以刷新这些 eFuse（保险丝从 8 到 15）吗？ 此外，我可以为我的目标生成仅包含一个证书的 SRK 表吗？ 多谢！ 回复：IMX93 - AHAB 安全启动 - SRK 表 在 git 的示例中，证书是使用 sha384 生成的！

PF3000 SWの電流制限動作 親愛なるコミュニティの皆様へ PF3000が内蔵されている装置の使用を検討しています。データシートによると、SW2は短絡時に電流制限があるとされていますが、その具体的な動作を完全には理解していません。 例えば、2秒OFFと0.1秒ONを繰り返すのか、それとも短絡が解消されるまで完全に出力を停止するのか。 さらに、短絡が発生した後、電流制限はどのくらい持続しますか? よろしくお願いいたします キノシタ